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Commit e47b14af00b4f4c982d10296f2d5dd678d320dc7

Authored by Alice Guo
Committed by Ye Li
1 parent ff0854ff80
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22580-3: imx8mm-evk: config: fix mtdparts and drop CONFIG_MTD_DEVICE 

remove space from mtdparts definition and remove
"#define CONFIG_MTD_DEVICE" to make source code can be copiled correctly

Signed-off-by: Alice Guo <alice.guo@nxp.com>
(cherry picked from commit c01b869d5b9dc8cff340c9b911d8df9d2aa257dd)

Showing 1 changed file with 1 additions and 2 deletions Inline Diff

include/configs/imx8mm_evk.h
Diff comments   View file @ e47b14a
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 #ifndef __IMX8MM_EVK_H 6 #ifndef __IMX8MM_EVK_H
7 #define __IMX8MM_EVK_H 7 #define __IMX8MM_EVK_H
8 8
9 #include <linux/sizes.h> 9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 11
12 #include "imx_env.h" 12 #include "imx_env.h"
13 13
14 #ifdef CONFIG_SECURE_BOOT 14 #ifdef CONFIG_SECURE_BOOT
15 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ 15 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */
16 #endif 16 #endif
17 17
18 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 18 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
19 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 19 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
20 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 20 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
22 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 22 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
23 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) 23 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
24 24
25 #ifdef CONFIG_SPL_BUILD 25 #ifdef CONFIG_SPL_BUILD
26 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 26 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
27 #define CONFIG_SPL_WATCHDOG_SUPPORT 27 #define CONFIG_SPL_WATCHDOG_SUPPORT
28 #define CONFIG_SPL_POWER_SUPPORT 28 #define CONFIG_SPL_POWER_SUPPORT
29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
30 #define CONFIG_SPL_I2C_SUPPORT 30 #define CONFIG_SPL_I2C_SUPPORT
31 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 31 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
32 #define CONFIG_SPL_STACK 0x91fff0 32 #define CONFIG_SPL_STACK 0x91fff0
33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT
34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT
35 #define CONFIG_SPL_GPIO_SUPPORT 35 #define CONFIG_SPL_GPIO_SUPPORT
36 #define CONFIG_SPL_BSS_START_ADDR 0x00910000 36 #define CONFIG_SPL_BSS_START_ADDR 0x00910000
37 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 37 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
38 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 38 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
39 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 39 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
40 #define CONFIG_SYS_ICACHE_OFF 40 #define CONFIG_SYS_ICACHE_OFF
41 #define CONFIG_SYS_DCACHE_OFF 41 #define CONFIG_SYS_DCACHE_OFF
42 42
43 #define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 43 #define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
44 44
45 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 45 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
46 46
47 #undef CONFIG_DM_MMC 47 #undef CONFIG_DM_MMC
48 #undef CONFIG_DM_PMIC 48 #undef CONFIG_DM_PMIC
49 #undef CONFIG_DM_PMIC_PFUZE100 49 #undef CONFIG_DM_PMIC_PFUZE100
50 50
51 #define CONFIG_POWER 51 #define CONFIG_POWER
52 #define CONFIG_POWER_I2C 52 #define CONFIG_POWER_I2C
53 #define CONFIG_POWER_BD71837 53 #define CONFIG_POWER_BD71837
54 54
55 #define CONFIG_SYS_I2C 55 #define CONFIG_SYS_I2C
56 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 56 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
57 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 57 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
58 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 58 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
59 59
60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
61 61
62 #if defined(CONFIG_NAND_BOOT) 62 #if defined(CONFIG_NAND_BOOT)
63 #define CONFIG_SPL_NAND_SUPPORT 63 #define CONFIG_SPL_NAND_SUPPORT
64 #define CONFIG_SPL_DMA_SUPPORT 64 #define CONFIG_SPL_DMA_SUPPORT
65 #define CONFIG_SPL_NAND_MXS 65 #define CONFIG_SPL_NAND_MXS
66 #define CONFIG_SPL_NAND_BASE 66 #define CONFIG_SPL_NAND_BASE
67 #define CONFIG_SPL_NAND_IDENT 67 #define CONFIG_SPL_NAND_IDENT
68 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ 68 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
69 69
70 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ 70 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
71 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ 71 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
72 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) 72 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
73 #endif 73 #endif
74 74
75 #endif 75 #endif
76 76
77 #define CONFIG_CMD_READ 77 #define CONFIG_CMD_READ
78 #define CONFIG_SERIAL_TAG 78 #define CONFIG_SERIAL_TAG
79 #define CONFIG_FASTBOOT_USB_DEV 0 79 #define CONFIG_FASTBOOT_USB_DEV 0
80 80
81 #define CONFIG_REMAKE_ELF 81 #define CONFIG_REMAKE_ELF
82 82
83 #define CONFIG_BOARD_EARLY_INIT_F 83 #define CONFIG_BOARD_EARLY_INIT_F
84 #define CONFIG_BOARD_LATE_INIT 84 #define CONFIG_BOARD_LATE_INIT
85 85
86 #undef CONFIG_CMD_EXPORTENV 86 #undef CONFIG_CMD_EXPORTENV
87 #undef CONFIG_CMD_IMPORTENV 87 #undef CONFIG_CMD_IMPORTENV
88 #undef CONFIG_CMD_IMLS 88 #undef CONFIG_CMD_IMLS
89 89
90 #undef CONFIG_CMD_CRC32 90 #undef CONFIG_CMD_CRC32
91 #undef CONFIG_BOOTM_NETBSD 91 #undef CONFIG_BOOTM_NETBSD
92 92
93 /* ENET Config */ 93 /* ENET Config */
94 /* ENET1 */ 94 /* ENET1 */
95 #if defined(CONFIG_CMD_NET) 95 #if defined(CONFIG_CMD_NET)
96 #define CONFIG_CMD_PING 96 #define CONFIG_CMD_PING
97 #define CONFIG_CMD_DHCP 97 #define CONFIG_CMD_DHCP
98 #define CONFIG_CMD_MII 98 #define CONFIG_CMD_MII
99 #define CONFIG_MII 99 #define CONFIG_MII
100 #define CONFIG_ETHPRIME "FEC" 100 #define CONFIG_ETHPRIME "FEC"
101 101
102 #define CONFIG_FEC_MXC 102 #define CONFIG_FEC_MXC
103 #define CONFIG_FEC_XCV_TYPE RGMII 103 #define CONFIG_FEC_XCV_TYPE RGMII
104 #define CONFIG_FEC_MXC_PHYADDR 0 104 #define CONFIG_FEC_MXC_PHYADDR 0
105 #define FEC_QUIRK_ENET_MAC 105 #define FEC_QUIRK_ENET_MAC
106 106
107 #define CONFIG_PHY_GIGE 107 #define CONFIG_PHY_GIGE
108 #define IMX_FEC_BASE 0x30BE0000 108 #define IMX_FEC_BASE 0x30BE0000
109 109
110 #define CONFIG_PHYLIB 110 #define CONFIG_PHYLIB
111 #define CONFIG_PHY_ATHEROS 111 #define CONFIG_PHY_ATHEROS
112 #endif 112 #endif
113 113
114 #ifdef CONFIG_NAND_BOOT 114 #ifdef CONFIG_NAND_BOOT
115 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " 115 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
116 #endif 116 #endif
117 117
118 /* 118 /*
119 * Another approach is add the clocks for inmates into clks_init_on 119 * Another approach is add the clocks for inmates into clks_init_on
120 * in clk-imx8mm.c, then clk_ingore_unused could be removed. 120 * in clk-imx8mm.c, then clk_ingore_unused could be removed.
121 */ 121 */
122 #define JAILHOUSE_ENV \ 122 #define JAILHOUSE_ENV \
123 "jh_clk= \0 " \ 123 "jh_clk= \0 " \
124 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \ 124 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \
125 "setenv jh_clk clk_ignore_unused; " \ 125 "setenv jh_clk clk_ignore_unused; " \
126 "if run loadimage; then " \ 126 "if run loadimage; then " \
127 "run mmcboot; " \ 127 "run mmcboot; " \
128 "else run jh_netboot; fi; \0" \ 128 "else run jh_netboot; fi; \0" \
129 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " 129 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
130 130
131 131
132 #define CONFIG_MFG_ENV_SETTINGS \ 132 #define CONFIG_MFG_ENV_SETTINGS \
133 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 133 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
134 "initrd_addr=0x43800000\0" \ 134 "initrd_addr=0x43800000\0" \
135 "initrd_high=0xffffffffffffffff\0" \ 135 "initrd_high=0xffffffffffffffff\0" \
136 "emmc_dev=2\0"\ 136 "emmc_dev=2\0"\
137 "sd_dev=1\0" \ 137 "sd_dev=1\0" \
138 138
139 /* Initial environment variables */ 139 /* Initial environment variables */
140 #if defined(CONFIG_NAND_BOOT) 140 #if defined(CONFIG_NAND_BOOT)
141 #define CONFIG_EXTRA_ENV_SETTINGS \ 141 #define CONFIG_EXTRA_ENV_SETTINGS \
142 CONFIG_MFG_ENV_SETTINGS \ 142 CONFIG_MFG_ENV_SETTINGS \
143 "fdt_addr=0x43000000\0" \ 143 "fdt_addr=0x43000000\0" \
144 "fdt_high=0xffffffffffffffff\0" \ 144 "fdt_high=0xffffffffffffffff\0" \
145 "mtdparts=" MFG_NAND_PARTITION "\0" \ 145 "mtdparts=" MFG_NAND_PARTITION "\0" \
146 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ 146 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
147 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \ 147 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \
148 "root=ubi0:nandrootfs rootfstype=ubifs " \ 148 "root=ubi0:nandrootfs rootfstype=ubifs " \
149 MFG_NAND_PARTITION \ 149 MFG_NAND_PARTITION \
150 "\0" \ 150 "\0" \
151 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ 151 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
152 "nand read ${fdt_addr} 0x7000000 0x100000;"\ 152 "nand read ${fdt_addr} 0x7000000 0x100000;"\
153 "booti ${loadaddr} - ${fdt_addr}" 153 "booti ${loadaddr} - ${fdt_addr}"
154 154
155 #else 155 #else
156 #define CONFIG_EXTRA_ENV_SETTINGS \ 156 #define CONFIG_EXTRA_ENV_SETTINGS \
157 CONFIG_MFG_ENV_SETTINGS \ 157 CONFIG_MFG_ENV_SETTINGS \
158 JAILHOUSE_ENV \ 158 JAILHOUSE_ENV \
159 "script=boot.scr\0" \ 159 "script=boot.scr\0" \
160 "image=Image\0" \ 160 "image=Image\0" \
161 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ 161 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
162 "fdt_addr=0x43000000\0" \ 162 "fdt_addr=0x43000000\0" \
163 "fdt_high=0xffffffffffffffff\0" \ 163 "fdt_high=0xffffffffffffffff\0" \
164 "boot_fdt=try\0" \ 164 "boot_fdt=try\0" \
165 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 165 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
166 "initrd_addr=0x43800000\0" \ 166 "initrd_addr=0x43800000\0" \
167 "initrd_high=0xffffffffffffffff\0" \ 167 "initrd_high=0xffffffffffffffff\0" \
168 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 168 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
169 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 169 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
170 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 170 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
171 "mmcautodetect=yes\0" \ 171 "mmcautodetect=yes\0" \
172 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ 172 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
173 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 173 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
174 "bootscript=echo Running bootscript from mmc ...; " \ 174 "bootscript=echo Running bootscript from mmc ...; " \
175 "source\0" \ 175 "source\0" \
176 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 176 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
177 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 177 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
178 "mmcboot=echo Booting from mmc ...; " \ 178 "mmcboot=echo Booting from mmc ...; " \
179 "run mmcargs; " \ 179 "run mmcargs; " \
180 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 180 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
181 "if run loadfdt; then " \ 181 "if run loadfdt; then " \
182 "booti ${loadaddr} - ${fdt_addr}; " \ 182 "booti ${loadaddr} - ${fdt_addr}; " \
183 "else " \ 183 "else " \
184 "echo WARN: Cannot load the DT; " \ 184 "echo WARN: Cannot load the DT; " \
185 "fi; " \ 185 "fi; " \
186 "else " \ 186 "else " \
187 "echo wait for boot; " \ 187 "echo wait for boot; " \
188 "fi;\0" \ 188 "fi;\0" \
189 "netargs=setenv bootargs ${jh_clk} console=${console} " \ 189 "netargs=setenv bootargs ${jh_clk} console=${console} " \
190 "root=/dev/nfs " \ 190 "root=/dev/nfs " \
191 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 191 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
192 "netboot=echo Booting from net ...; " \ 192 "netboot=echo Booting from net ...; " \
193 "run netargs; " \ 193 "run netargs; " \
194 "if test ${ip_dyn} = yes; then " \ 194 "if test ${ip_dyn} = yes; then " \
195 "setenv get_cmd dhcp; " \ 195 "setenv get_cmd dhcp; " \
196 "else " \ 196 "else " \
197 "setenv get_cmd tftp; " \ 197 "setenv get_cmd tftp; " \
198 "fi; " \ 198 "fi; " \
199 "${get_cmd} ${loadaddr} ${image}; " \ 199 "${get_cmd} ${loadaddr} ${image}; " \
200 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 200 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
201 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 201 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
202 "booti ${loadaddr} - ${fdt_addr}; " \ 202 "booti ${loadaddr} - ${fdt_addr}; " \
203 "else " \ 203 "else " \
204 "echo WARN: Cannot load the DT; " \ 204 "echo WARN: Cannot load the DT; " \
205 "fi; " \ 205 "fi; " \
206 "else " \ 206 "else " \
207 "booti; " \ 207 "booti; " \
208 "fi;\0" 208 "fi;\0"
209 209
210 #define CONFIG_BOOTCOMMAND \ 210 #define CONFIG_BOOTCOMMAND \
211 "mmc dev ${mmcdev}; if mmc rescan; then " \ 211 "mmc dev ${mmcdev}; if mmc rescan; then " \
212 "if run loadbootscript; then " \ 212 "if run loadbootscript; then " \
213 "run bootscript; " \ 213 "run bootscript; " \
214 "else " \ 214 "else " \
215 "if run loadimage; then " \ 215 "if run loadimage; then " \
216 "run mmcboot; " \ 216 "run mmcboot; " \
217 "else run netboot; " \ 217 "else run netboot; " \
218 "fi; " \ 218 "fi; " \
219 "fi; " \ 219 "fi; " \
220 "else booti ${loadaddr} - ${fdt_addr}; fi" 220 "else booti ${loadaddr} - ${fdt_addr}; fi"
221 #endif 221 #endif
222 222
223 /* Link Definitions */ 223 /* Link Definitions */
224 #define CONFIG_LOADADDR 0x40480000 224 #define CONFIG_LOADADDR 0x40480000
225 225
226 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 226 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
227 227
228 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 228 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
229 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
230 #define CONFIG_SYS_INIT_SP_OFFSET \ 230 #define CONFIG_SYS_INIT_SP_OFFSET \
231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
232 #define CONFIG_SYS_INIT_SP_ADDR \ 232 #define CONFIG_SYS_INIT_SP_ADDR \
233 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 233 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
234 234
235 #define CONFIG_ENV_OVERWRITE 235 #define CONFIG_ENV_OVERWRITE
236 #if defined(CONFIG_ENV_IS_IN_MMC) 236 #if defined(CONFIG_ENV_IS_IN_MMC)
237 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 237 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
238 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) 238 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
239 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 239 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
240 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 240 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
241 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 241 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
242 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 242 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
243 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 243 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
244 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 244 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
245 #elif defined(CONFIG_ENV_IS_IN_NAND) 245 #elif defined(CONFIG_ENV_IS_IN_NAND)
246 #define CONFIG_ENV_OFFSET (60 << 20) 246 #define CONFIG_ENV_OFFSET (60 << 20)
247 #endif 247 #endif
248 #define CONFIG_ENV_SIZE 0x1000 248 #define CONFIG_ENV_SIZE 0x1000
249 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 249 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
250 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 250 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
251 251
252 /* Size of malloc() pool */ 252 /* Size of malloc() pool */
253 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) 253 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
254 254
255 #define CONFIG_SYS_SDRAM_BASE 0x40000000 255 #define CONFIG_SYS_SDRAM_BASE 0x40000000
256 #define PHYS_SDRAM 0x40000000 256 #define PHYS_SDRAM 0x40000000
257 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ 257 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
258 258
259 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 259 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
260 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 260 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
261 (PHYS_SDRAM_SIZE >> 1)) 261 (PHYS_SDRAM_SIZE >> 1))
262 262
263 #define CONFIG_BAUDRATE 115200 263 #define CONFIG_BAUDRATE 115200
264 264
265 #define CONFIG_MXC_UART 265 #define CONFIG_MXC_UART
266 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR 266 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
267 267
268 /* Monitor Command Prompt */ 268 /* Monitor Command Prompt */
269 #undef CONFIG_SYS_PROMPT 269 #undef CONFIG_SYS_PROMPT
270 #define CONFIG_SYS_PROMPT "u-boot=> " 270 #define CONFIG_SYS_PROMPT "u-boot=> "
271 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 271 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
272 #define CONFIG_SYS_CBSIZE 2048 272 #define CONFIG_SYS_CBSIZE 2048
273 #define CONFIG_SYS_MAXARGS 64 273 #define CONFIG_SYS_MAXARGS 64
274 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 274 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
276 sizeof(CONFIG_SYS_PROMPT) + 16) 276 sizeof(CONFIG_SYS_PROMPT) + 16)
277 277
278 #define CONFIG_IMX_BOOTAUX 278 #define CONFIG_IMX_BOOTAUX
279 279
280 /* USDHC */ 280 /* USDHC */
281 #define CONFIG_CMD_MMC 281 #define CONFIG_CMD_MMC
282 #define CONFIG_FSL_ESDHC 282 #define CONFIG_FSL_ESDHC
283 #define CONFIG_FSL_USDHC 283 #define CONFIG_FSL_USDHC
284 284
285 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK 285 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
286 #define CONFIG_SYS_FSL_USDHC_NUM 1 286 #define CONFIG_SYS_FSL_USDHC_NUM 1
287 #else 287 #else
288 #define CONFIG_SYS_FSL_USDHC_NUM 2 288 #define CONFIG_SYS_FSL_USDHC_NUM 2
289 #endif 289 #endif
290 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 290 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
291 291
292 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 292 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
293 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 293 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
294 294
295 #ifdef CONFIG_FSL_FSPI 295 #ifdef CONFIG_FSL_FSPI
296 #define FSL_FSPI_FLASH_SIZE SZ_32M 296 #define FSL_FSPI_FLASH_SIZE SZ_32M
297 #define FSL_FSPI_FLASH_NUM 1 297 #define FSL_FSPI_FLASH_NUM 1
298 #define FSPI0_BASE_ADDR 0x30bb0000 298 #define FSPI0_BASE_ADDR 0x30bb0000
299 #define FSPI0_AMBA_BASE 0x0 299 #define FSPI0_AMBA_BASE 0x0
300 #define CONFIG_FSPI_QUAD_SUPPORT 300 #define CONFIG_FSPI_QUAD_SUPPORT
301 301
302 #define CONFIG_SYS_FSL_FSPI_AHB 302 #define CONFIG_SYS_FSL_FSPI_AHB
303 #endif 303 #endif
304 304
305 #ifdef CONFIG_NAND_MXS 305 #ifdef CONFIG_NAND_MXS
306 #define CONFIG_CMD_NAND_TRIMFFS 306 #define CONFIG_CMD_NAND_TRIMFFS
307 307
308 /* NAND stuff */ 308 /* NAND stuff */
309 #define CONFIG_SYS_MAX_NAND_DEVICE 1 309 #define CONFIG_SYS_MAX_NAND_DEVICE 1
310 #define CONFIG_SYS_NAND_BASE 0x20000000 310 #define CONFIG_SYS_NAND_BASE 0x20000000
311 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 311 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
312 #define CONFIG_SYS_NAND_ONFI_DETECTION 312 #define CONFIG_SYS_NAND_ONFI_DETECTION
313 313
314 #ifdef CONFIG_CMD_UBI 314 #ifdef CONFIG_CMD_UBI
315 #define CONFIG_MTD_DEVICE
316 #endif 315 #endif
317 #endif /* CONFIG_NAND_MXS */ 316 #endif /* CONFIG_NAND_MXS */
318 317
319 318
320 #define CONFIG_MXC_GPIO 319 #define CONFIG_MXC_GPIO
321 320
322 #define CONFIG_MXC_OCOTP 321 #define CONFIG_MXC_OCOTP
323 #define CONFIG_CMD_FUSE 322 #define CONFIG_CMD_FUSE
324 323
325 #ifndef CONFIG_DM_I2C 324 #ifndef CONFIG_DM_I2C
326 #define CONFIG_SYS_I2C 325 #define CONFIG_SYS_I2C
327 #endif 326 #endif
328 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 327 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
329 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 328 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
330 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 329 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
331 #define CONFIG_SYS_I2C_SPEED 100000 330 #define CONFIG_SYS_I2C_SPEED 100000
332 331
333 /* USB configs */ 332 /* USB configs */
334 #ifndef CONFIG_SPL_BUILD 333 #ifndef CONFIG_SPL_BUILD
335 #define CONFIG_CMD_USB 334 #define CONFIG_CMD_USB
336 #define CONFIG_USB_STORAGE 335 #define CONFIG_USB_STORAGE
337 #define CONFIG_USBD_HS 336 #define CONFIG_USBD_HS
338 337
339 #define CONFIG_CMD_USB_MASS_STORAGE 338 #define CONFIG_CMD_USB_MASS_STORAGE
340 #define CONFIG_USB_GADGET_MASS_STORAGE 339 #define CONFIG_USB_GADGET_MASS_STORAGE
341 #define CONFIG_USB_FUNCTION_MASS_STORAGE 340 #define CONFIG_USB_FUNCTION_MASS_STORAGE
342 341
343 #endif 342 #endif
344 343
345 #define CONFIG_USB_GADGET_VBUS_DRAW 2 344 #define CONFIG_USB_GADGET_VBUS_DRAW 2
346 345
347 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 346 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
348 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 347 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
349 348
350 #ifdef CONFIG_VIDEO 349 #ifdef CONFIG_VIDEO
351 #define CONFIG_VIDEO_MXS 350 #define CONFIG_VIDEO_MXS
352 #define CONFIG_VIDEO_LOGO 351 #define CONFIG_VIDEO_LOGO
353 #define CONFIG_SPLASH_SCREEN 352 #define CONFIG_SPLASH_SCREEN
354 #define CONFIG_SPLASH_SCREEN_ALIGN 353 #define CONFIG_SPLASH_SCREEN_ALIGN
355 #define CONFIG_CMD_BMP 354 #define CONFIG_CMD_BMP
356 #define CONFIG_BMP_16BPP 355 #define CONFIG_BMP_16BPP
357 #define CONFIG_VIDEO_BMP_RLE8 356 #define CONFIG_VIDEO_BMP_RLE8
358 #define CONFIG_VIDEO_BMP_LOGO 357 #define CONFIG_VIDEO_BMP_LOGO
359 #define CONFIG_IMX_VIDEO_SKIP 358 #define CONFIG_IMX_VIDEO_SKIP
360 #define CONFIG_RM67191 359 #define CONFIG_RM67191
361 #endif 360 #endif
362 361
363 #define CONFIG_OF_SYSTEM_SETUP 362 #define CONFIG_OF_SYSTEM_SETUP
364 363
365 #if defined(CONFIG_ANDROID_SUPPORT) 364 #if defined(CONFIG_ANDROID_SUPPORT)
366 #include "imx8mm_evk_android.h" 365 #include "imx8mm_evk_android.h"
367 #endif 366 #endif
368 #endif 367 #endif
369 368