Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit e5336ae19bce8086f2c9b2028e167d8afd90d173

Authored by Eric Lee
1 parent f3001a034d
Exists in smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga

Make changes to hardware revision 00F0: Replace Ethernet PHY by RTL8211FD-CG

Showing 2 changed files with 3 additions and 3 deletions Inline Diff

arch/arm/dts/fsl-smarcimx8mq.dts
Diff comments   View file @ e5336ae
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 /dts-v1/; 16 /dts-v1/;
17 17
18 /* First 128KB is for PSCI ATF. */ 18 /* First 128KB is for PSCI ATF. */
19 /memreserve/ 0x40000000 0x00020000; 19 /memreserve/ 0x40000000 0x00020000;
20 20
21 #include "fsl-imx8mq.dtsi" 21 #include "fsl-imx8mq.dtsi"
22 22
23 / { 23 / {
24 model = "Embedian SMARC-iMX8M Computer on Module"; 24 model = "Embedian SMARC-iMX8M Computer on Module";
25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; 25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
26 26
27 regulators { 27 regulators {
28 compatible = "simple-bus"; 28 compatible = "simple-bus";
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 31
32 reg_usdhc2_vmmc: usdhc2_vmmc { 32 reg_usdhc2_vmmc: usdhc2_vmmc {
33 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3"; 34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>; 35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38 enable-active-high; 38 enable-active-high;
39 }; 39 };
40 }; 40 };
41 41
42 backlight: backlight { 42 backlight: backlight {
43 compatible = "pwm-backlight"; 43 compatible = "pwm-backlight";
44 pwms = <&pwm1 0 1000000 0>; 44 pwms = <&pwm1 0 1000000 0>;
45 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 45 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
46 10 11 12 13 14 15 16 17 18 19 46 10 11 12 13 14 15 16 17 18 19
47 20 21 22 23 24 25 26 27 28 29 47 20 21 22 23 24 25 26 27 28 29
48 30 31 32 33 34 35 36 37 38 39 48 30 31 32 33 34 35 36 37 38 39
49 40 41 42 43 44 45 46 47 48 49 49 40 41 42 43 44 45 46 47 48 49
50 50 51 52 53 54 55 56 57 58 59 50 50 51 52 53 54 55 56 57 58 59
51 60 61 62 63 64 65 66 67 68 69 51 60 61 62 63 64 65 66 67 68 69
52 70 71 72 73 74 75 76 77 78 79 52 70 71 72 73 74 75 76 77 78 79
53 80 81 82 83 84 85 86 87 88 89 53 80 81 82 83 84 85 86 87 88 89
54 90 91 92 93 94 95 96 97 98 99 54 90 91 92 93 94 95 96 97 98 99
55 100>; 55 100>;
56 default-brightness-level = <80>; 56 default-brightness-level = <80>;
57 status = "disabled"; 57 status = "disabled";
58 }; 58 };
59 }; 59 };
60 60
61 &iomuxc { 61 &iomuxc {
62 pinctrl-names = "default"; 62 pinctrl-names = "default";
63 63
64 smarc-imx8mq { 64 smarc-imx8mq {
65 pinctrl_fec1: fec1grp { 65 pinctrl_fec1: fec1grp {
66 fsl,pins = < 66 fsl,pins = <
67 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 67 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
68 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 68 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
69 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 69 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
70 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 70 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
71 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 71 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
72 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 72 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
73 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 73 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
74 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 74 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
75 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 75 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
76 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 76 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
77 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 77 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
78 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 78 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
79 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 79 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
80 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 80 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
81 >; 81 >;
82 }; 82 };
83 83
84 pinctrl_i2c1: i2c1grp { 84 pinctrl_i2c1: i2c1grp {
85 fsl,pins = < 85 fsl,pins = <
86 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 86 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
87 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 87 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
88 >; 88 >;
89 }; 89 };
90 90
91 pinctrl_i2c2: i2c2grp { 91 pinctrl_i2c2: i2c2grp {
92 fsl,pins = < 92 fsl,pins = <
93 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 93 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
94 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 94 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
95 >; 95 >;
96 }; 96 };
97 97
98 pinctrl_i2c3: i2c3grp { 98 pinctrl_i2c3: i2c3grp {
99 fsl,pins = < 99 fsl,pins = <
100 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 100 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
101 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 101 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
102 >; 102 >;
103 }; 103 };
104 104
105 pinctrl_i2c4: i2c4grp { 105 pinctrl_i2c4: i2c4grp {
106 fsl,pins = < 106 fsl,pins = <
107 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f 107 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
108 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f 108 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
109 >; 109 >;
110 }; 110 };
111 111
112 112
113 pinctrl_pcie0: pcie0grp { 113 pinctrl_pcie0: pcie0grp {
114 fsl,pins = < 114 fsl,pins = <
115 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 115 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
116 >; 116 >;
117 }; 117 };
118 118
119 pinctrl_pcie1: pcie1grp { 119 pinctrl_pcie1: pcie1grp {
120 fsl,pins = < 120 fsl,pins = <
121 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 121 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
122 >; 122 >;
123 }; 123 };
124 124
125 pinctrl_pwm1: pwm1grp { 125 pinctrl_pwm1: pwm1grp {
126 fsl,pins = < 126 fsl,pins = <
127 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 127 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
128 >; 128 >;
129 }; 129 };
130 130
131 pinctrl_qspi: qspigrp { 131 pinctrl_qspi: qspigrp {
132 fsl,pins = < 132 fsl,pins = <
133 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 133 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
134 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 134 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
135 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 135 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82
136 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 136 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
137 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 137 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
138 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 138 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
139 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 139 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
140 140
141 >; 141 >;
142 }; 142 };
143 143
144 pinctrl_uart1: uart1grp { 144 pinctrl_uart1: uart1grp {
145 fsl,pins = < 145 fsl,pins = <
146 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 146 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
147 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 147 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
148 >; 148 >;
149 }; 149 };
150 150
151 pinctrl_uart2: uart2grp { 151 pinctrl_uart2: uart2grp {
152 fsl,pins = < 152 fsl,pins = <
153 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 153 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79
154 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 154 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79
155 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */ 155 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */
156 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */ 156 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */
157 >; 157 >;
158 }; 158 };
159 159
160 pinctrl_uart3: uart3grp { 160 pinctrl_uart3: uart3grp {
161 fsl,pins = < 161 fsl,pins = <
162 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 162 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
163 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 163 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
164 >; 164 >;
165 }; 165 };
166 166
167 pinctrl_uart4: uart4grp { 167 pinctrl_uart4: uart4grp {
168 fsl,pins = < 168 fsl,pins = <
169 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79 169 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79
170 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79 170 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79
171 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */ 171 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */
172 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */ 172 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */
173 >; 173 >;
174 }; 174 };
175 175
176 pinctrl_usdhc1: usdhc1grp { 176 pinctrl_usdhc1: usdhc1grp {
177 fsl,pins = < 177 fsl,pins = <
178 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 178 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
179 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 179 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
180 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 180 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
181 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 181 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
182 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 182 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
183 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 183 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
184 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 184 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
185 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 185 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
186 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 186 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
187 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 187 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
188 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 188 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
189 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 189 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
190 >; 190 >;
191 }; 191 };
192 192
193 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 193 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
194 fsl,pins = < 194 fsl,pins = <
195 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 195 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
196 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 196 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
197 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 197 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
198 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 198 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
199 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 199 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
200 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 200 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
201 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 201 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
202 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 202 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
203 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 203 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
204 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 204 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
205 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 205 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
206 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 206 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
207 >; 207 >;
208 }; 208 };
209 209
210 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 210 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
211 fsl,pins = < 211 fsl,pins = <
212 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 212 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
213 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 213 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
214 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 214 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
215 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 215 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
216 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 216 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
217 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 217 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
218 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 218 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
219 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 219 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
220 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 220 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
221 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 221 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
222 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 222 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
223 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 223 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
224 >; 224 >;
225 }; 225 };
226 226
227 pinctrl_usdhc2_gpio: usdhc2grpgpio { 227 pinctrl_usdhc2_gpio: usdhc2grpgpio {
228 fsl,pins = < 228 fsl,pins = <
229 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 229 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41
230 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 230 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
231 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 231 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
232 >; 232 >;
233 }; 233 };
234 234
235 pinctrl_usdhc2: usdhc2grp { 235 pinctrl_usdhc2: usdhc2grp {
236 fsl,pins = < 236 fsl,pins = <
237 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 237 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
238 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 238 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
239 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 239 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
240 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 240 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
241 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 241 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
242 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 242 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
243 >; 243 >;
244 }; 244 };
245 245
246 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 246 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
247 fsl,pins = < 247 fsl,pins = <
248 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 248 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
249 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 249 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
250 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 250 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
251 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 251 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
252 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 252 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
253 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 253 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
254 >; 254 >;
255 }; 255 };
256 256
257 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 257 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
258 fsl,pins = < 258 fsl,pins = <
259 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 259 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
260 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 260 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
261 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 261 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
262 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 262 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
263 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 263 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
264 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 264 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
265 >; 265 >;
266 }; 266 };
267 267
268 pinctrl_sai2: sai2grp { 268 pinctrl_sai2: sai2grp {
269 fsl,pins = < 269 fsl,pins = <
270 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 270 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
271 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 271 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
272 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 272 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
273 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 273 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
274 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 274 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
275 >; 275 >;
276 }; 276 };
277 277
278 pinctrl_wdog: wdoggrp { 278 pinctrl_wdog: wdoggrp {
279 fsl,pins = < 279 fsl,pins = <
280 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 280 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
281 >; 281 >;
282 }; 282 };
283 }; 283 };
284 }; 284 };
285 285
286 &fec1 { 286 &fec1 {
287 pinctrl-names = "default"; 287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_fec1>; 288 pinctrl-0 = <&pinctrl_fec1>;
289 phy-mode = "rgmii-id"; 289 phy-mode = "rgmii-id";
290 phy-handle = <&ethphy0>; 290 phy-handle = <&ethphy0>;
291 fsl,magic-packet; 291 fsl,magic-packet;
292 interrupt-parent = <&gpio1>; 292 interrupt-parent = <&gpio1>;
293 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 293 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
294 status = "okay"; 294 status = "okay";
295 295
296 mdio { 296 mdio {
297 #address-cells = <1>; 297 #address-cells = <1>;
298 #size-cells = <0>; 298 #size-cells = <0>;
299 299
300 ethphy0: ethernet-phy@0 { 300 ethphy0: ethernet-phy@0 {
301 compatible = "ethernet-phy-ieee802.3-c22"; 301 compatible = "ethernet-phy-ieee802.3-c22";
302 reg = <6>; 302 reg = <1>;
303 at803x,led-act-blind-workaround; 303 at803x,led-act-blind-workaround;
304 at803x,eee-disabled; 304 at803x,eee-disabled;
305 }; 305 };
306 }; 306 };
307 }; 307 };
308 308
309 &i2c1 { 309 &i2c1 {
310 clock-frequency = <100000>; 310 clock-frequency = <100000>;
311 pinctrl-names = "default"; 311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c1>; 312 pinctrl-0 = <&pinctrl_i2c1>;
313 status = "okay"; 313 status = "okay";
314 314
315 pmic: pfuze100@08 { 315 pmic: pfuze100@08 {
316 compatible = "fsl,pfuze100"; 316 compatible = "fsl,pfuze100";
317 reg = <0x08>; 317 reg = <0x08>;
318 318
319 regulators { 319 regulators {
320 sw1a_reg: sw1ab { 320 sw1a_reg: sw1ab {
321 regulator-min-microvolt = <300000>; 321 regulator-min-microvolt = <300000>;
322 regulator-max-microvolt = <1875000>; 322 regulator-max-microvolt = <1875000>;
323 regulator-always-on; 323 regulator-always-on;
324 }; 324 };
325 325
326 sw1c_reg: sw1c { 326 sw1c_reg: sw1c {
327 regulator-min-microvolt = <300000>; 327 regulator-min-microvolt = <300000>;
328 regulator-max-microvolt = <1875000>; 328 regulator-max-microvolt = <1875000>;
329 regulator-always-on; 329 regulator-always-on;
330 }; 330 };
331 331
332 sw2_reg: sw2 { 332 sw2_reg: sw2 {
333 regulator-min-microvolt = <800000>; 333 regulator-min-microvolt = <800000>;
334 regulator-max-microvolt = <3300000>; 334 regulator-max-microvolt = <3300000>;
335 regulator-always-on; 335 regulator-always-on;
336 }; 336 };
337 337
338 sw3a_reg: sw3ab { 338 sw3a_reg: sw3ab {
339 regulator-min-microvolt = <400000>; 339 regulator-min-microvolt = <400000>;
340 regulator-max-microvolt = <1975000>; 340 regulator-max-microvolt = <1975000>;
341 regulator-always-on; 341 regulator-always-on;
342 }; 342 };
343 343
344 sw4_reg: sw4 { 344 sw4_reg: sw4 {
345 regulator-min-microvolt = <800000>; 345 regulator-min-microvolt = <800000>;
346 regulator-max-microvolt = <3300000>; 346 regulator-max-microvolt = <3300000>;
347 regulator-always-on; 347 regulator-always-on;
348 }; 348 };
349 349
350 swbst_reg: swbst { 350 swbst_reg: swbst {
351 regulator-min-microvolt = <5000000>; 351 regulator-min-microvolt = <5000000>;
352 regulator-max-microvolt = <5150000>; 352 regulator-max-microvolt = <5150000>;
353 }; 353 };
354 354
355 snvs_reg: vsnvs { 355 snvs_reg: vsnvs {
356 regulator-min-microvolt = <1000000>; 356 regulator-min-microvolt = <1000000>;
357 regulator-max-microvolt = <3000000>; 357 regulator-max-microvolt = <3000000>;
358 regulator-always-on; 358 regulator-always-on;
359 }; 359 };
360 360
361 vref_reg: vrefddr { 361 vref_reg: vrefddr {
362 regulator-always-on; 362 regulator-always-on;
363 }; 363 };
364 364
365 vgen1_reg: vgen1 { 365 vgen1_reg: vgen1 {
366 regulator-min-microvolt = <800000>; 366 regulator-min-microvolt = <800000>;
367 regulator-max-microvolt = <1550000>; 367 regulator-max-microvolt = <1550000>;
368 }; 368 };
369 369
370 vgen2_reg: vgen2 { 370 vgen2_reg: vgen2 {
371 regulator-min-microvolt = <800000>; 371 regulator-min-microvolt = <800000>;
372 regulator-max-microvolt = <1550000>; 372 regulator-max-microvolt = <1550000>;
373 regulator-always-on; 373 regulator-always-on;
374 }; 374 };
375 375
376 vgen3_reg: vgen3 { 376 vgen3_reg: vgen3 {
377 regulator-min-microvolt = <1800000>; 377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <3300000>; 378 regulator-max-microvolt = <3300000>;
379 regulator-always-on; 379 regulator-always-on;
380 }; 380 };
381 381
382 vgen4_reg: vgen4 { 382 vgen4_reg: vgen4 {
383 regulator-min-microvolt = <1800000>; 383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <3300000>; 384 regulator-max-microvolt = <3300000>;
385 regulator-always-on; 385 regulator-always-on;
386 }; 386 };
387 387
388 vgen5_reg: vgen5 { 388 vgen5_reg: vgen5 {
389 regulator-min-microvolt = <1800000>; 389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <3300000>; 390 regulator-max-microvolt = <3300000>;
391 regulator-always-on; 391 regulator-always-on;
392 }; 392 };
393 393
394 vgen6_reg: vgen6 { 394 vgen6_reg: vgen6 {
395 regulator-min-microvolt = <1800000>; 395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <3300000>; 396 regulator-max-microvolt = <3300000>;
397 }; 397 };
398 }; 398 };
399 }; 399 };
400 400
401 s35390a: s35390a@30 { 401 s35390a: s35390a@30 {
402 compatible = "s35390a"; 402 compatible = "s35390a";
403 reg = <0x30>; 403 reg = <0x30>;
404 }; 404 };
405 405
406 cape_eeprom0: cape_eeprom@57 { 406 cape_eeprom0: cape_eeprom@57 {
407 compatible = "at,24c256"; 407 compatible = "at,24c256";
408 reg = <0x57>; 408 reg = <0x57>;
409 }; 409 };
410 }; 410 };
411 411
412 &i2c2 { 412 &i2c2 {
413 clock-frequency = <100000>; 413 clock-frequency = <100000>;
414 pinctrl-names = "default"; 414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_i2c2>; 415 pinctrl-0 = <&pinctrl_i2c2>;
416 status = "okay"; 416 status = "okay";
417 417
418 baseboard_eeprom: baseboard_eeprom@50 { 418 baseboard_eeprom: baseboard_eeprom@50 {
419 compatible = "at,24c256"; 419 compatible = "at,24c256";
420 reg = <0x50>; 420 reg = <0x50>;
421 }; 421 };
422 422
423 dsi_lvds_bridge: sn65dsi84@2c { 423 dsi_lvds_bridge: sn65dsi84@2c {
424 status = "disabled"; 424 status = "disabled";
425 reg = <0x2c>; 425 reg = <0x2c>;
426 compatible = "ti,sn65dsi84"; 426 compatible = "ti,sn65dsi84";
427 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 427 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
428 interrupt-parent = <&gpio4>; 428 interrupt-parent = <&gpio4>;
429 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 429 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
430 430
431 /* AUO G070VW01 7-inch 800x480 LVDS Display */ 431 /* AUO G070VW01 7-inch 800x480 LVDS Display */
432 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 432 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
433 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 433 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
434 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 434 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
435 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 435 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
436 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 436 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
437 0x3C 0x3D 0x3E 0xE0 0x0D>; 437 0x3C 0x3D 0x3E 0xE0 0x0D>;
438 438
439 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 439 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
440 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 440 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
441 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 441 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
442 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 442 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
443 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 443 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
444 0x00 0x00 0x00 0x01 0x01>; 444 0x00 0x00 0x00 0x01 0x01>;
445 445
446 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ 446 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
447 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 447 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
448 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 448 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
449 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 449 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
450 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 450 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
451 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 451 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
452 0x3C 0x3D 0x3E 0xE0 0x0D>; 452 0x3C 0x3D 0x3E 0xE0 0x0D>;
453 453
454 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 454 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
455 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 455 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
456 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 456 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
457 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 457 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
458 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 458 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
459 0x00 0x00 0x00 0x01 0x01>;*/ 459 0x00 0x00 0x00 0x01 0x01>;*/
460 460
461 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ 461 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
462 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 462 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
463 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 463 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
464 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 464 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
465 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 465 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
466 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 466 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
467 0x3C 0x3D 0x3E 0xE0 0x0D>; 467 0x3C 0x3D 0x3E 0xE0 0x0D>;
468 468
469 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 469 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
470 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 470 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
471 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 471 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
472 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 472 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
473 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 473 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
474 0x00 0x00 0x00 0x01 0x01>;*/ 474 0x00 0x00 0x00 0x01 0x01>;*/
475 }; 475 };
476 }; 476 };
477 477
478 &i2c3 { 478 &i2c3 {
479 clock-frequency = <100000>; 479 clock-frequency = <100000>;
480 pinctrl-names = "default"; 480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_i2c3>; 481 pinctrl-0 = <&pinctrl_i2c3>;
482 status = "okay"; 482 status = "okay";
483 }; 483 };
484 484
485 &i2c4 { 485 &i2c4 {
486 clock-frequency = <100000>; 486 clock-frequency = <100000>;
487 pinctrl-names = "default"; 487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_i2c4>; 488 pinctrl-0 = <&pinctrl_i2c4>;
489 status = "okay"; 489 status = "okay";
490 }; 490 };
491 491
492 &pcie0{ 492 &pcie0{
493 pinctrl-names = "default"; 493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_pcie0>; 494 pinctrl-0 = <&pinctrl_pcie0>;
495 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; 495 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
496 status = "okay"; 496 status = "okay";
497 }; 497 };
498 498
499 &pcie1{ 499 &pcie1{
500 pinctrl-names = "default"; 500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_pcie1>; 501 pinctrl-0 = <&pinctrl_pcie1>;
502 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 502 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
503 status = "okay"; 503 status = "okay";
504 }; 504 };
505 505
506 &pwm1 { 506 &pwm1 {
507 pinctrl-names = "default"; 507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_pwm1>; 508 pinctrl-0 = <&pinctrl_pwm1>;
509 status = "okay"; 509 status = "okay";
510 }; 510 };
511 511
512 &uart1 { /* console */ 512 &uart1 { /* console */
513 pinctrl-names = "default"; 513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_uart1>; 514 pinctrl-0 = <&pinctrl_uart1>;
515 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; 515 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
516 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 516 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
517 status = "okay"; 517 status = "okay";
518 }; 518 };
519 519
520 &lcdif { 520 &lcdif {
521 status = "okay"; 521 status = "okay";
522 disp-dev = "mipi_dsi_northwest"; 522 disp-dev = "mipi_dsi_northwest";
523 display = <&display0>; 523 display = <&display0>;
524 524
525 display0: display@0 { 525 display0: display@0 {
526 bits-per-pixel = <24>; 526 bits-per-pixel = <24>;
527 bus-width = <24>; 527 bus-width = <24>;
528 528
529 display-timings { 529 display-timings {
530 native-mode = <&timing0>; 530 native-mode = <&timing0>;
531 timing0: timing0 { 531 timing0: timing0 {
532 clock-frequency = <9200000>; 532 clock-frequency = <9200000>;
533 hactive = <480>; 533 hactive = <480>;
534 vactive = <272>; 534 vactive = <272>;
535 hfront-porch = <8>; 535 hfront-porch = <8>;
536 hback-porch = <4>; 536 hback-porch = <4>;
537 hsync-len = <41>; 537 hsync-len = <41>;
538 vback-porch = <2>; 538 vback-porch = <2>;
539 vfront-porch = <4>; 539 vfront-porch = <4>;
540 vsync-len = <10>; 540 vsync-len = <10>;
541 541
542 hsync-active = <0>; 542 hsync-active = <0>;
543 vsync-active = <0>; 543 vsync-active = <0>;
544 de-active = <1>; 544 de-active = <1>;
545 pixelclk-active = <0>; 545 pixelclk-active = <0>;
546 }; 546 };
547 }; 547 };
548 }; 548 };
549 port@0 { 549 port@0 {
550 lcdif_mipi_dsi: mipi-dsi-endpoint { 550 lcdif_mipi_dsi: mipi-dsi-endpoint {
551 remote-endpoint = <&mipi_dsi_in>; 551 remote-endpoint = <&mipi_dsi_in>;
552 }; 552 };
553 }; 553 };
554 }; 554 };
555 555
556 &qspi { 556 &qspi {
557 pinctrl-names = "default"; 557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_qspi>; 558 pinctrl-0 = <&pinctrl_qspi>;
559 status = "okay"; 559 status = "okay";
560 }; 560 };
561 561
562 &mipi_dsi { 562 &mipi_dsi {
563 reset = <&src>; 563 reset = <&src>;
564 mux-sel = <&gpr>; /* lcdif or dcss */ 564 mux-sel = <&gpr>; /* lcdif or dcss */
565 status = "okay"; 565 status = "okay";
566 566
567 port@1 { 567 port@1 {
568 mipi_dsi_in: endpoint { 568 mipi_dsi_in: endpoint {
569 remote-endpoint = <&lcdif_mipi_dsi>; 569 remote-endpoint = <&lcdif_mipi_dsi>;
570 }; 570 };
571 }; 571 };
572 }; 572 };
573 573
574 &uart2 { 574 &uart2 {
575 pinctrl-names = "default"; 575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_uart2>; 576 pinctrl-0 = <&pinctrl_uart2>;
577 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>; 577 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
578 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 578 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
579 fsl,uart-has-rtscts; 579 fsl,uart-has-rtscts;
580 status = "okay"; 580 status = "okay";
581 }; 581 };
582 582
583 &uart3 { 583 &uart3 {
584 pinctrl-names = "default"; 584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_uart3>; 585 pinctrl-0 = <&pinctrl_uart3>;
586 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; 586 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
587 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 587 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
588 status = "okay"; 588 status = "okay";
589 }; 589 };
590 590
591 &uart4 { 591 &uart4 {
592 pinctrl-names = "default"; 592 pinctrl-names = "default";
593 pinctrl-0 = <&pinctrl_uart4>; 593 pinctrl-0 = <&pinctrl_uart4>;
594 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>; 594 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
595 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 595 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
596 fsl,uart-has-rtscts; 596 fsl,uart-has-rtscts;
597 status = "okay"; 597 status = "okay";
598 }; 598 };
599 599
600 &usdhc1 { 600 &usdhc1 {
601 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
602 pinctrl-0 = <&pinctrl_usdhc1>; 602 pinctrl-0 = <&pinctrl_usdhc1>;
603 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 603 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
604 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 604 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
605 bus-width = <8>; 605 bus-width = <8>;
606 non-removable; 606 non-removable;
607 status = "okay"; 607 status = "okay";
608 }; 608 };
609 609
610 &usdhc2 { 610 &usdhc2 {
611 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 611 pinctrl-names = "default", "state_100mhz", "state_200mhz";
612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
615 bus-width = <4>; 615 bus-width = <4>;
616 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 616 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
617 vmmc-supply = <&reg_usdhc2_vmmc>; 617 vmmc-supply = <&reg_usdhc2_vmmc>;
618 status = "okay"; 618 status = "okay";
619 }; 619 };
620 620
621 &usb3_phy0 { 621 &usb3_phy0 {
622 status = "okay"; 622 status = "okay";
623 }; 623 };
624 624
625 &usb3_0 { 625 &usb3_0 {
626 status = "okay"; 626 status = "okay";
627 }; 627 };
628 628
629 &usb_dwc3_0 { 629 &usb_dwc3_0 {
630 status = "okay"; 630 status = "okay";
631 dr_mode = "peripheral"; 631 dr_mode = "peripheral";
632 }; 632 };
633 633
634 &usb3_phy1 { 634 &usb3_phy1 {
635 status = "okay"; 635 status = "okay";
636 }; 636 };
637 637
638 &usb3_1 { 638 &usb3_1 {
639 status = "disabled"; 639 status = "disabled";
640 }; 640 };
641 641
642 &usb_dwc3_1 { 642 &usb_dwc3_1 {
643 status = "okay"; 643 status = "okay";
644 dr_mode = "host"; 644 dr_mode = "host";
645 }; 645 };
646 646
647 &sai2 { 647 &sai2 {
648 pinctrl-names = "default"; 648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_sai2>; 649 pinctrl-0 = <&pinctrl_sai2>;
650 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, 650 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
651 <&clk IMX8MQ_AUDIO_PLL1>, 651 <&clk IMX8MQ_AUDIO_PLL1>,
652 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, 652 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
653 <&clk IMX8MQ_CLK_SAI2_DIV>; 653 <&clk IMX8MQ_CLK_SAI2_DIV>;
654 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 654 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
655 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; 655 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
656 status = "okay"; 656 status = "okay";
657 }; 657 };
658 658
659 &gpu { 659 &gpu {
660 status = "okay"; 660 status = "okay";
661 }; 661 };
662 662
663 &vpu { 663 &vpu {
664 status = "okay"; 664 status = "okay";
665 }; 665 };
666 666
667 &wdog1 { 667 &wdog1 {
668 pinctrl-names = "default"; 668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_wdog>; 669 pinctrl-0 = <&pinctrl_wdog>;
670 fsl,ext-reset-output; 670 fsl,ext-reset-output;
671 status = "okay"; 671 status = "okay";
672 }; 672 };
673 673
include/configs/smarcimx8mq.h
Diff comments   View file @ e5336ae
1 /* 1 /*
2 * Copyright 2017-2018 NXP 2 * Copyright 2017-2018 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __SMARCIMX8MQ_H 7 #ifndef __SMARCIMX8MQ_H
8 #define __SMARCIMX8MQ_H 8 #define __SMARCIMX8MQ_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include "imx_env.h" 12 #include "imx_env.h"
13 13
14 #ifdef CONFIG_SECURE_BOOT 14 #ifdef CONFIG_SECURE_BOOT
15 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ 15 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */
16 #endif 16 #endif
17 17
18 #define CONFIG_SPL_TEXT_BASE 0x7E1000 18 #define CONFIG_SPL_TEXT_BASE 0x7E1000
19 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 19 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 20 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
24 24
25 #ifdef CONFIG_SPL_BUILD 25 #ifdef CONFIG_SPL_BUILD
26 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 26 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
27 #define CONFIG_SPL_WATCHDOG_SUPPORT 27 #define CONFIG_SPL_WATCHDOG_SUPPORT
28 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 28 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
29 #define CONFIG_SPL_POWER_SUPPORT 29 #define CONFIG_SPL_POWER_SUPPORT
30 #define CONFIG_SPL_I2C_SUPPORT 30 #define CONFIG_SPL_I2C_SUPPORT
31 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 31 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
32 #define CONFIG_SPL_STACK 0x187FF0 32 #define CONFIG_SPL_STACK 0x187FF0
33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT
34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT
35 #define CONFIG_SPL_SERIAL_SUPPORT 35 #define CONFIG_SPL_SERIAL_SUPPORT
36 #define CONFIG_SPL_GPIO_SUPPORT 36 #define CONFIG_SPL_GPIO_SUPPORT
37 #define CONFIG_SPL_MMC_SUPPORT 37 #define CONFIG_SPL_MMC_SUPPORT
38 #define CONFIG_SPL_BSS_START_ADDR 0x00180000 38 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
39 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 39 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
40 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 40 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
41 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 41 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
42 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 42 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
43 #define CONFIG_SYS_ICACHE_OFF 43 #define CONFIG_SYS_ICACHE_OFF
44 #define CONFIG_SYS_DCACHE_OFF 44 #define CONFIG_SYS_DCACHE_OFF
45 45
46 #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 46 #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
47 47
48 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 48 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
49 49
50 #undef CONFIG_DM_MMC 50 #undef CONFIG_DM_MMC
51 #undef CONFIG_DM_PMIC 51 #undef CONFIG_DM_PMIC
52 #undef CONFIG_DM_PMIC_PFUZE100 52 #undef CONFIG_DM_PMIC_PFUZE100
53 53
54 #define CONFIG_SYS_I2C 54 #define CONFIG_SYS_I2C
55 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 55 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
56 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 56 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
57 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 57 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
58 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 58 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
59 59
60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
61 61
62 #define CONFIG_POWER 62 #define CONFIG_POWER
63 #define CONFIG_POWER_I2C 63 #define CONFIG_POWER_I2C
64 #define CONFIG_POWER_PFUZE100 64 #define CONFIG_POWER_PFUZE100
65 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 65 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
66 #endif 66 #endif
67 67
68 #define CONFIG_REMAKE_ELF 68 #define CONFIG_REMAKE_ELF
69 69
70 #define CONFIG_BOARD_EARLY_INIT_F 70 #define CONFIG_BOARD_EARLY_INIT_F
71 #define CONFIG_BOARD_POSTCLK_INIT 71 #define CONFIG_BOARD_POSTCLK_INIT
72 #define CONFIG_BOARD_LATE_INIT 72 #define CONFIG_BOARD_LATE_INIT
73 73
74 /* Flat Device Tree Definitions */ 74 /* Flat Device Tree Definitions */
75 #define CONFIG_OF_BOARD_SETUP 75 #define CONFIG_OF_BOARD_SETUP
76 76
77 #undef CONFIG_CMD_EXPORTENV 77 #undef CONFIG_CMD_EXPORTENV
78 #undef CONFIG_CMD_IMLS 78 #undef CONFIG_CMD_IMLS
79 79
80 #undef CONFIG_CMD_CRC32 80 #undef CONFIG_CMD_CRC32
81 #undef CONFIG_BOOTM_NETBSD 81 #undef CONFIG_BOOTM_NETBSD
82 82
83 /* ENET Config */ 83 /* ENET Config */
84 /* ENET1 */ 84 /* ENET1 */
85 #if defined(CONFIG_CMD_NET) 85 #if defined(CONFIG_CMD_NET)
86 #define CONFIG_CMD_PING 86 #define CONFIG_CMD_PING
87 #define CONFIG_CMD_DHCP 87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_MII 88 #define CONFIG_CMD_MII
89 #define CONFIG_MII 89 #define CONFIG_MII
90 #define CONFIG_ETHPRIME "FEC" 90 #define CONFIG_ETHPRIME "FEC"
91 91
92 #define CONFIG_FEC_MXC 92 #define CONFIG_FEC_MXC
93 #define CONFIG_FEC_XCV_TYPE RGMII 93 #define CONFIG_FEC_XCV_TYPE RGMII
94 #define CONFIG_FEC_MXC_PHYADDR 6 94 #define CONFIG_FEC_MXC_PHYADDR 1
95 #define FEC_QUIRK_ENET_MAC 95 #define FEC_QUIRK_ENET_MAC
96 96
97 #define CONFIG_PHY_GIGE 97 #define CONFIG_PHY_GIGE
98 #define IMX_FEC_BASE 0x30BE0000 98 #define IMX_FEC_BASE 0x30BE0000
99 99
100 #define CONFIG_PHYLIB 100 #define CONFIG_PHYLIB
101 #define CONFIG_PHY_ATHEROS 101 #define CONFIG_PHY_REALTEK
102 #endif 102 #endif
103 103
104 /* 104 /*
105 * Another approach is add the clocks for inmates into clks_init_on 105 * Another approach is add the clocks for inmates into clks_init_on
106 * in clk-imx8mq.c, then clk_ingore_unused could be removed. 106 * in clk-imx8mq.c, then clk_ingore_unused could be removed.
107 */ 107 */
108 #define JAILHOUSE_ENV \ 108 #define JAILHOUSE_ENV \
109 "jh_clk= \0 " \ 109 "jh_clk= \0 " \
110 "jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \ 110 "jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \
111 "setenv jh_clk clk_ignore_unused; " \ 111 "setenv jh_clk clk_ignore_unused; " \
112 "if run loadimage; then " \ 112 "if run loadimage; then " \
113 "run mmcboot; " \ 113 "run mmcboot; " \
114 "else run jh_netboot; fi; \0" \ 114 "else run jh_netboot; fi; \0" \
115 "jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " 115 "jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
116 116
117 #define CONFIG_MFG_ENV_SETTINGS \ 117 #define CONFIG_MFG_ENV_SETTINGS \
118 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 118 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
119 "initrd_addr=0x43800000\0" \ 119 "initrd_addr=0x43800000\0" \
120 "initrd_high=0xffffffffffffffff\0" \ 120 "initrd_high=0xffffffffffffffff\0" \
121 "emmc_dev=0\0"\ 121 "emmc_dev=0\0"\
122 "sd_dev=1\0" \ 122 "sd_dev=1\0" \
123 123
124 /* Initial environment variables */ 124 /* Initial environment variables */
125 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 #define CONFIG_EXTRA_ENV_SETTINGS \
126 CONFIG_MFG_ENV_SETTINGS \ 126 CONFIG_MFG_ENV_SETTINGS \
127 JAILHOUSE_ENV \ 127 JAILHOUSE_ENV \
128 "script=boot.scr\0" \ 128 "script=boot.scr\0" \
129 "image=Image\0" \ 129 "image=Image\0" \
130 "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ 130 "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
131 "fdt_addr=0x43000000\0" \ 131 "fdt_addr=0x43000000\0" \
132 "fdt_high=0xffffffffffffffff\0" \ 132 "fdt_high=0xffffffffffffffff\0" \
133 "boot_fdt=try\0" \ 133 "boot_fdt=try\0" \
134 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 134 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
135 "initrd_addr=0x43800000\0" \ 135 "initrd_addr=0x43800000\0" \
136 "initrd_high=0xffffffffffffffff\0" \ 136 "initrd_high=0xffffffffffffffff\0" \
137 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 137 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
138 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 138 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
139 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 139 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
140 "usbroot=/dev/sda2 rootwait ro\0" \ 140 "usbroot=/dev/sda2 rootwait ro\0" \
141 "mmcrootfstype=ext4 rootwait\0" \ 141 "mmcrootfstype=ext4 rootwait\0" \
142 "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ 142 "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
143 "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \ 143 "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \
144 "mmcautodetect=yes\0" \ 144 "mmcautodetect=yes\0" \
145 "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ 145 "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
146 "env import -t $loadaddr $filesize\0" \ 146 "env import -t $loadaddr $filesize\0" \
147 "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \ 147 "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \
148 "env import -t $loadaddr $filesize\0" \ 148 "env import -t $loadaddr $filesize\0" \
149 "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ 149 "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
150 "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \ 150 "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \
151 "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ 151 "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
152 "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \ 152 "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \
153 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 153 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
154 "bootscript=echo Running bootscript from mmc ...; " \ 154 "bootscript=echo Running bootscript from mmc ...; " \
155 "source\0" \ 155 "source\0" \
156 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 156 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
157 "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \ 157 "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \
158 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ 158 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
159 "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \ 159 "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \
160 "mmcboot=echo Booting from mmc ...; " \ 160 "mmcboot=echo Booting from mmc ...; " \
161 "run mmcargs; " \ 161 "run mmcargs; " \
162 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 162 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
163 "if run loadfdt; then " \ 163 "if run loadfdt; then " \
164 "booti ${loadaddr} - ${fdt_addr}; " \ 164 "booti ${loadaddr} - ${fdt_addr}; " \
165 "else " \ 165 "else " \
166 "echo WARN: Cannot load the DT; " \ 166 "echo WARN: Cannot load the DT; " \
167 "fi; " \ 167 "fi; " \
168 "else " \ 168 "else " \
169 "echo wait for boot; " \ 169 "echo wait for boot; " \
170 "fi;\0" \ 170 "fi;\0" \
171 "usbboot=echo Booting from USB ...; " \ 171 "usbboot=echo Booting from USB ...; " \
172 "run usbargs; " \ 172 "run usbargs; " \
173 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 173 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
174 "if run loadusbfdt; then " \ 174 "if run loadusbfdt; then " \
175 "booti ${loadaddr} - ${fdt_addr}; " \ 175 "booti ${loadaddr} - ${fdt_addr}; " \
176 "else " \ 176 "else " \
177 "echo WARN: Cannot load the DT; " \ 177 "echo WARN: Cannot load the DT; " \
178 "fi; " \ 178 "fi; " \
179 "else " \ 179 "else " \
180 "echo wait for boot; " \ 180 "echo wait for boot; " \
181 "fi;\0" \ 181 "fi;\0" \
182 "netargs=setenv bootargs ${jh_clk} console=${console} " \ 182 "netargs=setenv bootargs ${jh_clk} console=${console} " \
183 "root=/dev/nfs " \ 183 "root=/dev/nfs " \
184 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 184 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
185 "netboot=echo Booting from net ...; " \ 185 "netboot=echo Booting from net ...; " \
186 "run netargs; " \ 186 "run netargs; " \
187 "if test ${ip_dyn} = yes; then " \ 187 "if test ${ip_dyn} = yes; then " \
188 "setenv get_cmd dhcp; " \ 188 "setenv get_cmd dhcp; " \
189 "else " \ 189 "else " \
190 "setenv get_cmd tftp; " \ 190 "setenv get_cmd tftp; " \
191 "fi; " \ 191 "fi; " \
192 "${get_cmd} ${loadaddr} ${image}; " \ 192 "${get_cmd} ${loadaddr} ${image}; " \
193 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 193 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
194 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 194 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
195 "booti ${loadaddr} - ${fdt_addr}; " \ 195 "booti ${loadaddr} - ${fdt_addr}; " \
196 "else " \ 196 "else " \
197 "echo WARN: Cannot load the DT; " \ 197 "echo WARN: Cannot load the DT; " \
198 "fi; " \ 198 "fi; " \
199 "else " \ 199 "else " \
200 "booti; " \ 200 "booti; " \
201 "fi;\0" 201 "fi;\0"
202 202
203 #define CONFIG_BOOTCOMMAND \ 203 #define CONFIG_BOOTCOMMAND \
204 "mmc dev ${mmcdev}; if mmc rescan; then " \ 204 "mmc dev ${mmcdev}; if mmc rescan; then " \
205 "echo Checking for: uEnv.txt ...; " \ 205 "echo Checking for: uEnv.txt ...; " \
206 "if test -e mmc ${bootpart} /uEnv.txt; then " \ 206 "if test -e mmc ${bootpart} /uEnv.txt; then " \
207 "if run loadbootenv; then " \ 207 "if run loadbootenv; then " \
208 "echo Loaded environment from uEnv.txt;" \ 208 "echo Loaded environment from uEnv.txt;" \
209 "run importbootenv;" \ 209 "run importbootenv;" \
210 "fi;" \ 210 "fi;" \
211 "echo Checking if uenvcmd is set ...;" \ 211 "echo Checking if uenvcmd is set ...;" \
212 "if test -n ${uenvcmd}; then " \ 212 "if test -n ${uenvcmd}; then " \
213 "echo Running uenvcmd ...;" \ 213 "echo Running uenvcmd ...;" \
214 "run uenvcmd;" \ 214 "run uenvcmd;" \
215 "fi;" \ 215 "fi;" \
216 "fi; " \ 216 "fi; " \
217 "if run loadimage; then " \ 217 "if run loadimage; then " \
218 "run mmcboot; " \ 218 "run mmcboot; " \
219 "else run netboot; " \ 219 "else run netboot; " \
220 "fi; " \ 220 "fi; " \
221 "booti ${loadaddr} - ${fdt_addr}; fi;" 221 "booti ${loadaddr} - ${fdt_addr}; fi;"
222 222
223 /* Link Definitions */ 223 /* Link Definitions */
224 #define CONFIG_LOADADDR 0x40480000 224 #define CONFIG_LOADADDR 0x40480000
225 225
226 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 226 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
227 227
228 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 228 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
229 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
230 #define CONFIG_SYS_INIT_SP_OFFSET \ 230 #define CONFIG_SYS_INIT_SP_OFFSET \
231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
232 #define CONFIG_SYS_INIT_SP_ADDR \ 232 #define CONFIG_SYS_INIT_SP_ADDR \
233 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 233 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
234 234
235 #define CONFIG_ENV_OVERWRITE 235 #define CONFIG_ENV_OVERWRITE
236 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 236 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
237 #define CONFIG_ENV_SIZE 0x1000 237 #define CONFIG_ENV_SIZE 0x1000
238 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 238 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
239 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 239 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
240 240
241 /* Size of malloc() pool */ 241 /* Size of malloc() pool */
242 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) 242 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
243 243
244 #define CONFIG_SYS_SDRAM_BASE 0x40000000 244 #define CONFIG_SYS_SDRAM_BASE 0x40000000
245 #define PHYS_SDRAM 0x40000000 245 #define PHYS_SDRAM 0x40000000
246 #ifdef CONFIG_2GB_LPDDR4 246 #ifdef CONFIG_2GB_LPDDR4
247 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ 247 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
248 #else 248 #else
249 #define PHYS_SDRAM_SIZE 0x100000000 /* 4GB DDR */ 249 #define PHYS_SDRAM_SIZE 0x100000000 /* 4GB DDR */
250 #endif 250 #endif
251 #define CONFIG_NR_DRAM_BANKS 1 251 #define CONFIG_NR_DRAM_BANKS 1
252 252
253 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 253 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
254 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) 254 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
255 255
256 #define CONFIG_BAUDRATE 115200 256 #define CONFIG_BAUDRATE 115200
257 257
258 #define CONFIG_MXC_UART 258 #define CONFIG_MXC_UART
259 259
260 #ifdef CONFIG_CONSOLE_SER0 260 #ifdef CONFIG_CONSOLE_SER0
261 #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR 261 #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
262 #define CONSOLE_DEV "ttymxc3" 262 #define CONSOLE_DEV "ttymxc3"
263 #endif 263 #endif
264 264
265 #ifdef CONFIG_CONSOLE_SER1 265 #ifdef CONFIG_CONSOLE_SER1
266 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR 266 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
267 #define CONSOLE_DEV "ttymxc2" 267 #define CONSOLE_DEV "ttymxc2"
268 #endif 268 #endif
269 269
270 #ifdef CONFIG_CONSOLE_SER2 270 #ifdef CONFIG_CONSOLE_SER2
271 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR 271 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
272 #define CONSOLE_DEV "ttymxc1" 272 #define CONSOLE_DEV "ttymxc1"
273 #endif 273 #endif
274 274
275 #ifdef CONFIG_CONSOLE_SER3 275 #ifdef CONFIG_CONSOLE_SER3
276 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 276 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
277 #define CONSOLE_DEV "ttymxc0" 277 #define CONSOLE_DEV "ttymxc0"
278 #endif 278 #endif
279 279
280 /* Monitor Command Prompt */ 280 /* Monitor Command Prompt */
281 #undef CONFIG_SYS_PROMPT 281 #undef CONFIG_SYS_PROMPT
282 #define CONFIG_SYS_PROMPT "u-boot$ " 282 #define CONFIG_SYS_PROMPT "u-boot$ "
283 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 283 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
284 #define CONFIG_SYS_CBSIZE 2048 284 #define CONFIG_SYS_CBSIZE 2048
285 #define CONFIG_SYS_MAXARGS 64 285 #define CONFIG_SYS_MAXARGS 64
286 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 286 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
287 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 287 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
288 sizeof(CONFIG_SYS_PROMPT) + 16) 288 sizeof(CONFIG_SYS_PROMPT) + 16)
289 289
290 #define CONFIG_IMX_BOOTAUX 290 #define CONFIG_IMX_BOOTAUX
291 291
292 #define CONFIG_CMD_MMC 292 #define CONFIG_CMD_MMC
293 #define CONFIG_FSL_ESDHC 293 #define CONFIG_FSL_ESDHC
294 #define CONFIG_FSL_USDHC 294 #define CONFIG_FSL_USDHC
295 295
296 #define CONFIG_SYS_FSL_USDHC_NUM 2 296 #define CONFIG_SYS_FSL_USDHC_NUM 2
297 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 297 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
298 298
299 #define CONFIG_CMD_PART 299 #define CONFIG_CMD_PART
300 #define CONFIG_CMD_FS_GENERIC 300 #define CONFIG_CMD_FS_GENERIC
301 301
302 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 302 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
303 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 303 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
304 304
305 #define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ 305 #define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
306 #ifdef CONFIG_FSL_QSPI 306 #ifdef CONFIG_FSL_QSPI
307 #define CONFIG_CMD_SF 307 #define CONFIG_CMD_SF
308 #define CONFIG_SPI_FLASH 308 #define CONFIG_SPI_FLASH
309 #define CONFIG_SPI_FLASH_STMICRO 309 #define CONFIG_SPI_FLASH_STMICRO
310 #define CONFIG_SPI_FLASH_BAR 310 #define CONFIG_SPI_FLASH_BAR
311 #define CONFIG_SF_DEFAULT_BUS 0 311 #define CONFIG_SF_DEFAULT_BUS 0
312 #define CONFIG_SF_DEFAULT_CS 0 312 #define CONFIG_SF_DEFAULT_CS 0
313 #define CONFIG_SF_DEFAULT_SPEED 40000000 313 #define CONFIG_SF_DEFAULT_SPEED 40000000
314 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 314 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
315 315
316 #define FSL_QSPI_FLASH_SIZE (SZ_32M) 316 #define FSL_QSPI_FLASH_SIZE (SZ_32M)
317 #define FSL_QSPI_FLASH_NUM 1 317 #define FSL_QSPI_FLASH_NUM 1
318 #endif 318 #endif
319 319
320 #define CONFIG_MXC_GPIO 320 #define CONFIG_MXC_GPIO
321 321
322 #define CONFIG_MXC_OCOTP 322 #define CONFIG_MXC_OCOTP
323 #define CONFIG_CMD_FUSE 323 #define CONFIG_CMD_FUSE
324 324
325 /* I2C Configs */ 325 /* I2C Configs */
326 #define CONFIG_SYS_I2C_SPEED 100000 326 #define CONFIG_SYS_I2C_SPEED 100000
327 327
328 /* USB configs */ 328 /* USB configs */
329 #ifndef CONFIG_SPL_BUILD 329 #ifndef CONFIG_SPL_BUILD
330 #define CONFIG_HAS_FSL_XHCI_USB 330 #define CONFIG_HAS_FSL_XHCI_USB
331 331
332 #ifdef CONFIG_HAS_FSL_XHCI_USB 332 #ifdef CONFIG_HAS_FSL_XHCI_USB
333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
334 #endif 334 #endif
335 335
336 #define CONFIG_CMD_USB 336 #define CONFIG_CMD_USB
337 #define CONFIG_USB_STORAGE 337 #define CONFIG_USB_STORAGE
338 338
339 #define CONFIG_USBD_HS 339 #define CONFIG_USBD_HS
340 340
341 #define CONFIG_CMD_USB_MASS_STORAGE 341 #define CONFIG_CMD_USB_MASS_STORAGE
342 #define CONFIG_USB_GADGET_MASS_STORAGE 342 #define CONFIG_USB_GADGET_MASS_STORAGE
343 #define CONFIG_USB_FUNCTION_MASS_STORAGE 343 #define CONFIG_USB_FUNCTION_MASS_STORAGE
344 344
345 #define CONFIG_CMD_READ 345 #define CONFIG_CMD_READ
346 #endif 346 #endif
347 347
348 #define CONFIG_SERIAL_TAG 348 #define CONFIG_SERIAL_TAG
349 #define CONFIG_FASTBOOT_USB_DEV 0 349 #define CONFIG_FASTBOOT_USB_DEV 0
350 350
351 351
352 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 352 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
353 353
354 #define CONFIG_USBD_HS 354 #define CONFIG_USBD_HS
355 #define CONFIG_USB_GADGET_VBUS_DRAW 2 355 #define CONFIG_USB_GADGET_VBUS_DRAW 2
356 356
357 #define CONFIG_OF_SYSTEM_SETUP 357 #define CONFIG_OF_SYSTEM_SETUP
358 358
359 /* Framebuffer */ 359 /* Framebuffer */
360 #ifdef CONFIG_VIDEO 360 #ifdef CONFIG_VIDEO
361 #define CONFIG_VIDEO_IMXDCSS 361 #define CONFIG_VIDEO_IMXDCSS
362 #define CONFIG_VIDEO_BMP_RLE8 362 #define CONFIG_VIDEO_BMP_RLE8
363 #define CONFIG_SPLASH_SCREEN 363 #define CONFIG_SPLASH_SCREEN
364 #define CONFIG_SPLASH_SCREEN_ALIGN 364 #define CONFIG_SPLASH_SCREEN_ALIGN
365 #define CONFIG_BMP_16BPP 365 #define CONFIG_BMP_16BPP
366 #define CONFIG_VIDEO_LOGO 366 #define CONFIG_VIDEO_LOGO
367 #define CONFIG_VIDEO_BMP_LOGO 367 #define CONFIG_VIDEO_BMP_LOGO
368 #define CONFIG_IMX_VIDEO_SKIP 368 #define CONFIG_IMX_VIDEO_SKIP
369 #endif 369 #endif
370 370
371 #if defined(CONFIG_ANDROID_SUPPORT) 371 #if defined(CONFIG_ANDROID_SUPPORT)
372 #include "smarcimx8mq_android.h" 372 #include "smarcimx8mq_android.h"
373 #elif defined (CONFIG_ANDROID_THINGS_SUPPORT) 373 #elif defined (CONFIG_ANDROID_THINGS_SUPPORT)
374 #include "smarcimx8mq_androidthings.h" 374 #include "smarcimx8mq_androidthings.h"
375 #endif 375 #endif
376 #endif 376 #endif
377 377