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Commit e7eb277dced570f177d75d56f40219d9dc599ed1

Authored by Fabio Estevam
Committed by Stefano Babic
1 parent 612f2dc026
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mx6boards: Fix error handling in board_mmc_init() 

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Eric Benard <eric@eukrea.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 1 changed file with 6 additions and 4 deletions Inline Diff

board/embest/mx6boards/mx6boards.c
Diff comments   View file @ e7eb277
1 /* 1 /*
2 * Copyright (C) 2014 Eukréa Electromatique 2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com> 3 * Author: Eric Bénard <eric@eukrea.com>
4 * Fabio Estevam <fabio.estevam@freescale.com> 4 * Fabio Estevam <fabio.estevam@freescale.com>
5 * Jon Nettleton <jon.nettleton@gmail.com> 5 * Jon Nettleton <jon.nettleton@gmail.com>
6 * 6 *
7 * based on sabresd.c which is : 7 * based on sabresd.c which is :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc. 8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * and on hummingboard.c which is : 9 * and on hummingboard.c which is :
10 * Copyright (C) 2013 SolidRun ltd. 10 * Copyright (C) 2013 SolidRun ltd.
11 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>. 11 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
12 * 12 *
13 * SPDX-License-Identifier: GPL-2.0+ 13 * SPDX-License-Identifier: GPL-2.0+
14 */ 14 */
15 15
16 #include <asm/arch/clock.h> 16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/imx-regs.h> 18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h> 19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h> 20 #include <asm/arch/mx6-pins.h>
21 #include <asm/errno.h> 21 #include <asm/errno.h>
22 #include <asm/gpio.h> 22 #include <asm/gpio.h>
23 #include <asm/imx-common/iomux-v3.h> 23 #include <asm/imx-common/iomux-v3.h>
24 #include <asm/imx-common/boot_mode.h> 24 #include <asm/imx-common/boot_mode.h>
25 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/imx-common/mxc_i2c.h>
26 #include <asm/imx-common/spi.h> 26 #include <asm/imx-common/spi.h>
27 #include <asm/imx-common/video.h> 27 #include <asm/imx-common/video.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 #include <mmc.h> 29 #include <mmc.h>
30 #include <fsl_esdhc.h> 30 #include <fsl_esdhc.h>
31 #include <miiphy.h> 31 #include <miiphy.h>
32 #include <netdev.h> 32 #include <netdev.h>
33 #include <asm/arch/mxc_hdmi.h> 33 #include <asm/arch/mxc_hdmi.h>
34 #include <asm/arch/crm_regs.h> 34 #include <asm/arch/crm_regs.h>
35 #include <linux/fb.h> 35 #include <linux/fb.h>
36 #include <ipu_pixfmt.h> 36 #include <ipu_pixfmt.h>
37 #include <asm/io.h> 37 #include <asm/io.h>
38 #include <asm/arch/sys_proto.h> 38 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR; 39 DECLARE_GLOBAL_DATA_PTR;
40 40
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 44
45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 48
49 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ 49 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ 50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
51 PAD_CTL_HYS) 51 PAD_CTL_HYS)
52 52
53 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 53 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
55 55
56 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ 56 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
58 58
59 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ 59 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
61 61
62 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 62 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
64 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 64 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
65 65
66 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 66 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 67 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
68 68
69 static int board_type = -1; 69 static int board_type = -1;
70 #define BOARD_IS_MARSBOARD 0 70 #define BOARD_IS_MARSBOARD 0
71 #define BOARD_IS_RIOTBOARD 1 71 #define BOARD_IS_RIOTBOARD 1
72 72
73 int dram_init(void) 73 int dram_init(void)
74 { 74 {
75 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 75 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
76 76
77 return 0; 77 return 0;
78 } 78 }
79 79
80 static iomux_v3_cfg_t const uart2_pads[] = { 80 static iomux_v3_cfg_t const uart2_pads[] = {
81 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 81 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 82 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 }; 83 };
84 84
85 static void setup_iomux_uart(void) 85 static void setup_iomux_uart(void)
86 { 86 {
87 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 87 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
88 } 88 }
89 89
90 iomux_v3_cfg_t const enet_pads[] = { 90 iomux_v3_cfg_t const enet_pads[] = {
91 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 92 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 /* GPIO16 -> AR8035 25MHz */ 93 /* GPIO16 -> AR8035 25MHz */
94 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 94 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
95 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), 95 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
96 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 96 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 97 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 101 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
102 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), 102 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
103 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 104 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
105 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 105 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
106 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 108 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
109 /* AR8035 PHY Reset */ 109 /* AR8035 PHY Reset */
110 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 110 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
111 /* AR8035 PHY Interrupt */ 111 /* AR8035 PHY Interrupt */
112 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL), 112 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 }; 113 };
114 114
115 static void setup_iomux_enet(void) 115 static void setup_iomux_enet(void)
116 { 116 {
117 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 117 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
118 118
119 /* Reset AR8035 PHY */ 119 /* Reset AR8035 PHY */
120 gpio_direction_output(IMX_GPIO_NR(3, 31) , 0); 120 gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
121 mdelay(2); 121 mdelay(2);
122 gpio_set_value(IMX_GPIO_NR(3, 31), 1); 122 gpio_set_value(IMX_GPIO_NR(3, 31), 1);
123 } 123 }
124 124
125 int mx6_rgmii_rework(struct phy_device *phydev) 125 int mx6_rgmii_rework(struct phy_device *phydev)
126 { 126 {
127 /* from linux/arch/arm/mach-imx/mach-imx6q.c : 127 /* from linux/arch/arm/mach-imx/mach-imx6q.c :
128 * Ar803x phy SmartEEE feature cause link status generates glitch, 128 * Ar803x phy SmartEEE feature cause link status generates glitch,
129 * which cause ethernet link down/up issue, so disable SmartEEE 129 * which cause ethernet link down/up issue, so disable SmartEEE
130 */ 130 */
131 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 131 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
132 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); 132 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
133 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); 133 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
134 134
135 return 0; 135 return 0;
136 } 136 }
137 137
138 int board_phy_config(struct phy_device *phydev) 138 int board_phy_config(struct phy_device *phydev)
139 { 139 {
140 mx6_rgmii_rework(phydev); 140 mx6_rgmii_rework(phydev);
141 141
142 if (phydev->drv->config) 142 if (phydev->drv->config)
143 phydev->drv->config(phydev); 143 phydev->drv->config(phydev);
144 144
145 return 0; 145 return 0;
146 } 146 }
147 147
148 iomux_v3_cfg_t const usdhc2_pads[] = { 148 iomux_v3_cfg_t const usdhc2_pads[] = {
149 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), 149 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
150 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 155 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
156 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 156 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
157 }; 157 };
158 158
159 iomux_v3_cfg_t const usdhc3_pads[] = { 159 iomux_v3_cfg_t const usdhc3_pads[] = {
160 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), 160 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
161 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 163 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 }; 166 };
167 167
168 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = { 168 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
169 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 169 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
170 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 170 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
171 }; 171 };
172 172
173 iomux_v3_cfg_t const usdhc4_pads[] = { 173 iomux_v3_cfg_t const usdhc4_pads[] = {
174 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), 174 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
175 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 175 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 176 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 177 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 178 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 179 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 /* eMMC RST */ 180 /* eMMC RST */
181 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 181 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 }; 182 };
183 183
184 #ifdef CONFIG_FSL_ESDHC 184 #ifdef CONFIG_FSL_ESDHC
185 struct fsl_esdhc_cfg usdhc_cfg[3] = { 185 struct fsl_esdhc_cfg usdhc_cfg[3] = {
186 {USDHC2_BASE_ADDR}, 186 {USDHC2_BASE_ADDR},
187 {USDHC3_BASE_ADDR}, 187 {USDHC3_BASE_ADDR},
188 {USDHC4_BASE_ADDR}, 188 {USDHC4_BASE_ADDR},
189 }; 189 };
190 190
191 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 191 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
192 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0) 192 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
193 193
194 int board_mmc_getcd(struct mmc *mmc) 194 int board_mmc_getcd(struct mmc *mmc)
195 { 195 {
196 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 196 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
197 int ret = 0; 197 int ret = 0;
198 198
199 switch (cfg->esdhc_base) { 199 switch (cfg->esdhc_base) {
200 case USDHC2_BASE_ADDR: 200 case USDHC2_BASE_ADDR:
201 ret = !gpio_get_value(USDHC2_CD_GPIO); 201 ret = !gpio_get_value(USDHC2_CD_GPIO);
202 break; 202 break;
203 case USDHC3_BASE_ADDR: 203 case USDHC3_BASE_ADDR:
204 if (board_type == BOARD_IS_RIOTBOARD) 204 if (board_type == BOARD_IS_RIOTBOARD)
205 ret = !gpio_get_value(USDHC3_CD_GPIO); 205 ret = !gpio_get_value(USDHC3_CD_GPIO);
206 else if (board_type == BOARD_IS_MARSBOARD) 206 else if (board_type == BOARD_IS_MARSBOARD)
207 ret = 1; /* eMMC/uSDHC3 is always present */ 207 ret = 1; /* eMMC/uSDHC3 is always present */
208 break; 208 break;
209 case USDHC4_BASE_ADDR: 209 case USDHC4_BASE_ADDR:
210 ret = 1; /* eMMC/uSDHC4 is always present */ 210 ret = 1; /* eMMC/uSDHC4 is always present */
211 break; 211 break;
212 } 212 }
213 213
214 return ret; 214 return ret;
215 } 215 }
216 216
217 int board_mmc_init(bd_t *bis) 217 int board_mmc_init(bd_t *bis)
218 { 218 {
219 s32 status = 0; 219 int ret;
220 int i; 220 int i;
221 221
222 /* 222 /*
223 * According to the board_mmc_init() the following map is done: 223 * According to the board_mmc_init() the following map is done:
224 * (U-boot device node) (Physical Port) 224 * (U-boot device node) (Physical Port)
225 * ** RiOTboard : 225 * ** RiOTboard :
226 * mmc0 SDCard slot (bottom) 226 * mmc0 SDCard slot (bottom)
227 * mmc1 uSDCard slot (top) 227 * mmc1 uSDCard slot (top)
228 * mmc2 eMMC 228 * mmc2 eMMC
229 * ** MarSBoard : 229 * ** MarSBoard :
230 * mmc0 uSDCard slot (bottom) 230 * mmc0 uSDCard slot (bottom)
231 * mmc1 eMMC 231 * mmc1 eMMC
232 */ 232 */
233 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 233 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
234 switch (i) { 234 switch (i) {
235 case 0: 235 case 0:
236 imx_iomux_v3_setup_multiple_pads( 236 imx_iomux_v3_setup_multiple_pads(
237 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 237 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
238 gpio_direction_input(USDHC2_CD_GPIO); 238 gpio_direction_input(USDHC2_CD_GPIO);
239 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 239 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
240 usdhc_cfg[0].max_bus_width = 4; 240 usdhc_cfg[0].max_bus_width = 4;
241 break; 241 break;
242 case 1: 242 case 1:
243 imx_iomux_v3_setup_multiple_pads( 243 imx_iomux_v3_setup_multiple_pads(
244 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 244 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
245 if (board_type == BOARD_IS_RIOTBOARD) { 245 if (board_type == BOARD_IS_RIOTBOARD) {
246 imx_iomux_v3_setup_multiple_pads( 246 imx_iomux_v3_setup_multiple_pads(
247 riotboard_usdhc3_pads, 247 riotboard_usdhc3_pads,
248 ARRAY_SIZE(riotboard_usdhc3_pads)); 248 ARRAY_SIZE(riotboard_usdhc3_pads));
249 gpio_direction_input(USDHC3_CD_GPIO); 249 gpio_direction_input(USDHC3_CD_GPIO);
250 } else { 250 } else {
251 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); 251 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
252 udelay(250); 252 udelay(250);
253 gpio_set_value(IMX_GPIO_NR(7, 8), 1); 253 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
254 } 254 }
255 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 255 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
256 usdhc_cfg[1].max_bus_width = 4; 256 usdhc_cfg[1].max_bus_width = 4;
257 break; 257 break;
258 case 2: 258 case 2:
259 imx_iomux_v3_setup_multiple_pads( 259 imx_iomux_v3_setup_multiple_pads(
260 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 260 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
261 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 261 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
262 usdhc_cfg[2].max_bus_width = 4; 262 usdhc_cfg[2].max_bus_width = 4;
263 gpio_direction_output(IMX_GPIO_NR(6, 8) , 0); 263 gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
264 udelay(250); 264 udelay(250);
265 gpio_set_value(IMX_GPIO_NR(6, 8), 1); 265 gpio_set_value(IMX_GPIO_NR(6, 8), 1);
266 break; 266 break;
267 default: 267 default:
268 printf("Warning: you configured more USDHC controllers" 268 printf("Warning: you configured more USDHC controllers"
269 "(%d) then supported by the board (%d)\n", 269 "(%d) then supported by the board (%d)\n",
270 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 270 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
271 return status; 271 return -EINVAL;
272 } 272 }
273 273
274 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 274 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
275 if (ret)
276 return ret;
275 } 277 }
276 278
277 return status; 279 return 0;
278 } 280 }
279 #endif 281 #endif
280 282
281 #ifdef CONFIG_MXC_SPI 283 #ifdef CONFIG_MXC_SPI
282 iomux_v3_cfg_t const ecspi1_pads[] = { 284 iomux_v3_cfg_t const ecspi1_pads[] = {
283 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 285 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
284 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 286 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
285 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 287 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
286 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 288 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
287 }; 289 };
288 290
289 int board_spi_cs_gpio(unsigned bus, unsigned cs) 291 int board_spi_cs_gpio(unsigned bus, unsigned cs)
290 { 292 {
291 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; 293 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
292 } 294 }
293 295
294 static void setup_spi(void) 296 static void setup_spi(void)
295 { 297 {
296 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 298 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
297 } 299 }
298 #endif 300 #endif
299 301
300 struct i2c_pads_info i2c_pad_info1 = { 302 struct i2c_pads_info i2c_pad_info1 = {
301 .scl = { 303 .scl = {
302 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL 304 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
303 | MUX_PAD_CTRL(I2C_PAD_CTRL), 305 | MUX_PAD_CTRL(I2C_PAD_CTRL),
304 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 306 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
305 | MUX_PAD_CTRL(I2C_PAD_CTRL), 307 | MUX_PAD_CTRL(I2C_PAD_CTRL),
306 .gp = IMX_GPIO_NR(5, 27) 308 .gp = IMX_GPIO_NR(5, 27)
307 }, 309 },
308 .sda = { 310 .sda = {
309 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA 311 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
310 | MUX_PAD_CTRL(I2C_PAD_CTRL), 312 | MUX_PAD_CTRL(I2C_PAD_CTRL),
311 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 313 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
312 | MUX_PAD_CTRL(I2C_PAD_CTRL), 314 | MUX_PAD_CTRL(I2C_PAD_CTRL),
313 .gp = IMX_GPIO_NR(5, 26) 315 .gp = IMX_GPIO_NR(5, 26)
314 } 316 }
315 }; 317 };
316 318
317 struct i2c_pads_info i2c_pad_info2 = { 319 struct i2c_pads_info i2c_pad_info2 = {
318 .scl = { 320 .scl = {
319 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL 321 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
320 | MUX_PAD_CTRL(I2C_PAD_CTRL), 322 | MUX_PAD_CTRL(I2C_PAD_CTRL),
321 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 323 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
322 | MUX_PAD_CTRL(I2C_PAD_CTRL), 324 | MUX_PAD_CTRL(I2C_PAD_CTRL),
323 .gp = IMX_GPIO_NR(4, 12) 325 .gp = IMX_GPIO_NR(4, 12)
324 }, 326 },
325 .sda = { 327 .sda = {
326 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA 328 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
327 | MUX_PAD_CTRL(I2C_PAD_CTRL), 329 | MUX_PAD_CTRL(I2C_PAD_CTRL),
328 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 330 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
329 | MUX_PAD_CTRL(I2C_PAD_CTRL), 331 | MUX_PAD_CTRL(I2C_PAD_CTRL),
330 .gp = IMX_GPIO_NR(4, 13) 332 .gp = IMX_GPIO_NR(4, 13)
331 } 333 }
332 }; 334 };
333 335
334 struct i2c_pads_info i2c_pad_info3 = { 336 struct i2c_pads_info i2c_pad_info3 = {
335 .scl = { 337 .scl = {
336 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL 338 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
337 | MUX_PAD_CTRL(I2C_PAD_CTRL), 339 | MUX_PAD_CTRL(I2C_PAD_CTRL),
338 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 340 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
339 | MUX_PAD_CTRL(I2C_PAD_CTRL), 341 | MUX_PAD_CTRL(I2C_PAD_CTRL),
340 .gp = IMX_GPIO_NR(1, 5) 342 .gp = IMX_GPIO_NR(1, 5)
341 }, 343 },
342 .sda = { 344 .sda = {
343 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA 345 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
344 | MUX_PAD_CTRL(I2C_PAD_CTRL), 346 | MUX_PAD_CTRL(I2C_PAD_CTRL),
345 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 347 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
346 | MUX_PAD_CTRL(I2C_PAD_CTRL), 348 | MUX_PAD_CTRL(I2C_PAD_CTRL),
347 .gp = IMX_GPIO_NR(1, 6) 349 .gp = IMX_GPIO_NR(1, 6)
348 } 350 }
349 }; 351 };
350 352
351 iomux_v3_cfg_t const tft_pads_riot[] = { 353 iomux_v3_cfg_t const tft_pads_riot[] = {
352 /* LCD_PWR_EN */ 354 /* LCD_PWR_EN */
353 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 355 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
354 /* TOUCH_INT */ 356 /* TOUCH_INT */
355 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 357 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
356 /* LED_PWR_EN */ 358 /* LED_PWR_EN */
357 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 359 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
358 /* BL LEVEL */ 360 /* BL LEVEL */
359 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 361 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
360 }; 362 };
361 363
362 iomux_v3_cfg_t const tft_pads_mars[] = { 364 iomux_v3_cfg_t const tft_pads_mars[] = {
363 /* LCD_PWR_EN */ 365 /* LCD_PWR_EN */
364 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 366 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
365 /* TOUCH_INT */ 367 /* TOUCH_INT */
366 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 368 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
367 /* LED_PWR_EN */ 369 /* LED_PWR_EN */
368 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 370 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
369 /* BL LEVEL (PWM4) */ 371 /* BL LEVEL (PWM4) */
370 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 372 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
371 }; 373 };
372 374
373 #if defined(CONFIG_VIDEO_IPUV3) 375 #if defined(CONFIG_VIDEO_IPUV3)
374 376
375 static void enable_lvds(struct display_info_t const *dev) 377 static void enable_lvds(struct display_info_t const *dev)
376 { 378 {
377 struct iomuxc *iomux = (struct iomuxc *) 379 struct iomuxc *iomux = (struct iomuxc *)
378 IOMUXC_BASE_ADDR; 380 IOMUXC_BASE_ADDR;
379 setbits_le32(&iomux->gpr[2], 381 setbits_le32(&iomux->gpr[2],
380 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT); 382 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
381 /* set backlight level to ON */ 383 /* set backlight level to ON */
382 if (board_type == BOARD_IS_RIOTBOARD) 384 if (board_type == BOARD_IS_RIOTBOARD)
383 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1); 385 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
384 else if (board_type == BOARD_IS_MARSBOARD) 386 else if (board_type == BOARD_IS_MARSBOARD)
385 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1); 387 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
386 } 388 }
387 389
388 static void disable_lvds(struct display_info_t const *dev) 390 static void disable_lvds(struct display_info_t const *dev)
389 { 391 {
390 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 392 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
391 393
392 /* set backlight level to OFF */ 394 /* set backlight level to OFF */
393 if (board_type == BOARD_IS_RIOTBOARD) 395 if (board_type == BOARD_IS_RIOTBOARD)
394 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); 396 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
395 else if (board_type == BOARD_IS_MARSBOARD) 397 else if (board_type == BOARD_IS_MARSBOARD)
396 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); 398 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
397 399
398 clrbits_le32(&iomux->gpr[2], 400 clrbits_le32(&iomux->gpr[2],
399 IOMUXC_GPR2_LVDS_CH0_MODE_MASK); 401 IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
400 } 402 }
401 403
402 static void do_enable_hdmi(struct display_info_t const *dev) 404 static void do_enable_hdmi(struct display_info_t const *dev)
403 { 405 {
404 disable_lvds(dev); 406 disable_lvds(dev);
405 imx_enable_hdmi_phy(); 407 imx_enable_hdmi_phy();
406 } 408 }
407 409
408 static int detect_i2c(struct display_info_t const *dev) 410 static int detect_i2c(struct display_info_t const *dev)
409 { 411 {
410 return (0 == i2c_set_bus_num(dev->bus)) && 412 return (0 == i2c_set_bus_num(dev->bus)) &&
411 (0 == i2c_probe(dev->addr)); 413 (0 == i2c_probe(dev->addr));
412 } 414 }
413 415
414 struct display_info_t const displays[] = {{ 416 struct display_info_t const displays[] = {{
415 .bus = -1, 417 .bus = -1,
416 .addr = 0, 418 .addr = 0,
417 .pixfmt = IPU_PIX_FMT_RGB24, 419 .pixfmt = IPU_PIX_FMT_RGB24,
418 .detect = detect_hdmi, 420 .detect = detect_hdmi,
419 .enable = do_enable_hdmi, 421 .enable = do_enable_hdmi,
420 .mode = { 422 .mode = {
421 .name = "HDMI", 423 .name = "HDMI",
422 .refresh = 60, 424 .refresh = 60,
423 .xres = 1024, 425 .xres = 1024,
424 .yres = 768, 426 .yres = 768,
425 .pixclock = 15385, 427 .pixclock = 15385,
426 .left_margin = 220, 428 .left_margin = 220,
427 .right_margin = 40, 429 .right_margin = 40,
428 .upper_margin = 21, 430 .upper_margin = 21,
429 .lower_margin = 7, 431 .lower_margin = 7,
430 .hsync_len = 60, 432 .hsync_len = 60,
431 .vsync_len = 10, 433 .vsync_len = 10,
432 .sync = FB_SYNC_EXT, 434 .sync = FB_SYNC_EXT,
433 .vmode = FB_VMODE_NONINTERLACED 435 .vmode = FB_VMODE_NONINTERLACED
434 } }, { 436 } }, {
435 .bus = 2, 437 .bus = 2,
436 .addr = 0x1, 438 .addr = 0x1,
437 .pixfmt = IPU_PIX_FMT_LVDS666, 439 .pixfmt = IPU_PIX_FMT_LVDS666,
438 .detect = detect_i2c, 440 .detect = detect_i2c,
439 .enable = enable_lvds, 441 .enable = enable_lvds,
440 .mode = { 442 .mode = {
441 .name = "LCD8000-97C", 443 .name = "LCD8000-97C",
442 .refresh = 60, 444 .refresh = 60,
443 .xres = 1024, 445 .xres = 1024,
444 .yres = 768, 446 .yres = 768,
445 .pixclock = 15385, 447 .pixclock = 15385,
446 .left_margin = 100, 448 .left_margin = 100,
447 .right_margin = 200, 449 .right_margin = 200,
448 .upper_margin = 10, 450 .upper_margin = 10,
449 .lower_margin = 20, 451 .lower_margin = 20,
450 .hsync_len = 20, 452 .hsync_len = 20,
451 .vsync_len = 8, 453 .vsync_len = 8,
452 .sync = FB_SYNC_EXT, 454 .sync = FB_SYNC_EXT,
453 .vmode = FB_VMODE_NONINTERLACED 455 .vmode = FB_VMODE_NONINTERLACED
454 } } }; 456 } } };
455 size_t display_count = ARRAY_SIZE(displays); 457 size_t display_count = ARRAY_SIZE(displays);
456 458
457 static void setup_display(void) 459 static void setup_display(void)
458 { 460 {
459 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 461 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
460 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 462 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
461 int reg; 463 int reg;
462 464
463 enable_ipu_clock(); 465 enable_ipu_clock();
464 imx_setup_hdmi(); 466 imx_setup_hdmi();
465 467
466 /* Turn on LDB0, IPU,IPU DI0 clocks */ 468 /* Turn on LDB0, IPU,IPU DI0 clocks */
467 setbits_le32(&mxc_ccm->CCGR3, 469 setbits_le32(&mxc_ccm->CCGR3,
468 MXC_CCM_CCGR3_LDB_DI0_MASK); 470 MXC_CCM_CCGR3_LDB_DI0_MASK);
469 471
470 /* set LDB0 clk select to 011/011 */ 472 /* set LDB0 clk select to 011/011 */
471 clrsetbits_le32(&mxc_ccm->cs2cdr, 473 clrsetbits_le32(&mxc_ccm->cs2cdr,
472 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, 474 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
473 (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); 475 (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
474 476
475 setbits_le32(&mxc_ccm->cscmr2, 477 setbits_le32(&mxc_ccm->cscmr2,
476 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); 478 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
477 479
478 setbits_le32(&mxc_ccm->chsccdr, 480 setbits_le32(&mxc_ccm->chsccdr,
479 (CHSCCDR_CLK_SEL_LDB_DI0 481 (CHSCCDR_CLK_SEL_LDB_DI0
480 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); 482 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
481 483
482 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 484 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
483 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 485 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
484 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 486 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
485 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 487 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
486 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 488 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
487 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 489 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
488 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 490 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
489 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 491 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
490 writel(reg, &iomux->gpr[2]); 492 writel(reg, &iomux->gpr[2]);
491 493
492 clrsetbits_le32(&iomux->gpr[3], 494 clrsetbits_le32(&iomux->gpr[3],
493 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | 495 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
494 IOMUXC_GPR3_HDMI_MUX_CTL_MASK, 496 IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
495 IOMUXC_GPR3_MUX_SRC_IPU1_DI0 497 IOMUXC_GPR3_MUX_SRC_IPU1_DI0
496 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 498 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
497 } 499 }
498 #endif /* CONFIG_VIDEO_IPUV3 */ 500 #endif /* CONFIG_VIDEO_IPUV3 */
499 501
500 /* 502 /*
501 * Do not overwrite the console 503 * Do not overwrite the console
502 * Use always serial for U-Boot console 504 * Use always serial for U-Boot console
503 */ 505 */
504 int overwrite_console(void) 506 int overwrite_console(void)
505 { 507 {
506 return 1; 508 return 1;
507 } 509 }
508 510
509 int board_eth_init(bd_t *bis) 511 int board_eth_init(bd_t *bis)
510 { 512 {
511 setup_iomux_enet(); 513 setup_iomux_enet();
512 514
513 return cpu_eth_init(bis); 515 return cpu_eth_init(bis);
514 } 516 }
515 517
516 int board_early_init_f(void) 518 int board_early_init_f(void)
517 { 519 {
518 u32 cputype = cpu_type(get_cpu_rev()); 520 u32 cputype = cpu_type(get_cpu_rev());
519 521
520 switch (cputype) { 522 switch (cputype) {
521 case MXC_CPU_MX6SOLO: 523 case MXC_CPU_MX6SOLO:
522 board_type = BOARD_IS_RIOTBOARD; 524 board_type = BOARD_IS_RIOTBOARD;
523 break; 525 break;
524 case MXC_CPU_MX6D: 526 case MXC_CPU_MX6D:
525 board_type = BOARD_IS_MARSBOARD; 527 board_type = BOARD_IS_MARSBOARD;
526 break; 528 break;
527 } 529 }
528 530
529 setup_iomux_uart(); 531 setup_iomux_uart();
530 532
531 if (board_type == BOARD_IS_RIOTBOARD) 533 if (board_type == BOARD_IS_RIOTBOARD)
532 imx_iomux_v3_setup_multiple_pads( 534 imx_iomux_v3_setup_multiple_pads(
533 tft_pads_riot, ARRAY_SIZE(tft_pads_riot)); 535 tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
534 else if (board_type == BOARD_IS_MARSBOARD) 536 else if (board_type == BOARD_IS_MARSBOARD)
535 imx_iomux_v3_setup_multiple_pads( 537 imx_iomux_v3_setup_multiple_pads(
536 tft_pads_mars, ARRAY_SIZE(tft_pads_mars)); 538 tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
537 #if defined(CONFIG_VIDEO_IPUV3) 539 #if defined(CONFIG_VIDEO_IPUV3)
538 /* power ON LCD */ 540 /* power ON LCD */
539 gpio_direction_output(IMX_GPIO_NR(1, 29) , 1); 541 gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
540 /* touch interrupt is an input */ 542 /* touch interrupt is an input */
541 gpio_direction_input(IMX_GPIO_NR(6, 14)); 543 gpio_direction_input(IMX_GPIO_NR(6, 14));
542 /* power ON backlight */ 544 /* power ON backlight */
543 gpio_direction_output(IMX_GPIO_NR(6, 15) , 1); 545 gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
544 /* set backlight level to off */ 546 /* set backlight level to off */
545 if (board_type == BOARD_IS_RIOTBOARD) 547 if (board_type == BOARD_IS_RIOTBOARD)
546 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); 548 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
547 else if (board_type == BOARD_IS_MARSBOARD) 549 else if (board_type == BOARD_IS_MARSBOARD)
548 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); 550 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
549 setup_display(); 551 setup_display();
550 #endif 552 #endif
551 553
552 return 0; 554 return 0;
553 } 555 }
554 556
555 int board_init(void) 557 int board_init(void)
556 { 558 {
557 /* address of boot parameters */ 559 /* address of boot parameters */
558 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 560 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
559 /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */ 561 /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
560 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 562 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
561 /* i2c2 : HDMI EDID */ 563 /* i2c2 : HDMI EDID */
562 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 564 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
563 /* i2c3 : LVDS, Expansion connector */ 565 /* i2c3 : LVDS, Expansion connector */
564 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); 566 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
565 #ifdef CONFIG_MXC_SPI 567 #ifdef CONFIG_MXC_SPI
566 setup_spi(); 568 setup_spi();
567 #endif 569 #endif
568 return 0; 570 return 0;
569 } 571 }
570 572
571 #ifdef CONFIG_CMD_BMODE 573 #ifdef CONFIG_CMD_BMODE
572 static const struct boot_mode riotboard_boot_modes[] = { 574 static const struct boot_mode riotboard_boot_modes[] = {
573 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 575 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
574 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 576 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
575 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 577 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
576 {NULL, 0}, 578 {NULL, 0},
577 }; 579 };
578 static const struct boot_mode marsboard_boot_modes[] = { 580 static const struct boot_mode marsboard_boot_modes[] = {
579 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 581 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
580 {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 582 {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
581 {NULL, 0}, 583 {NULL, 0},
582 }; 584 };
583 #endif 585 #endif
584 586
585 int board_late_init(void) 587 int board_late_init(void)
586 { 588 {
587 #ifdef CONFIG_CMD_BMODE 589 #ifdef CONFIG_CMD_BMODE
588 if (board_type == BOARD_IS_RIOTBOARD) 590 if (board_type == BOARD_IS_RIOTBOARD)
589 add_board_boot_modes(riotboard_boot_modes); 591 add_board_boot_modes(riotboard_boot_modes);
590 else if (board_type == BOARD_IS_RIOTBOARD) 592 else if (board_type == BOARD_IS_RIOTBOARD)
591 add_board_boot_modes(marsboard_boot_modes); 593 add_board_boot_modes(marsboard_boot_modes);
592 #endif 594 #endif
593 595
594 return 0; 596 return 0;
595 } 597 }
596 598
597 int checkboard(void) 599 int checkboard(void)
598 { 600 {
599 puts("Board: "); 601 puts("Board: ");
600 if (board_type == BOARD_IS_MARSBOARD) 602 if (board_type == BOARD_IS_MARSBOARD)
601 puts("MarSBoard\n"); 603 puts("MarSBoard\n");
602 else if (board_type == BOARD_IS_RIOTBOARD) 604 else if (board_type == BOARD_IS_RIOTBOARD)
603 puts("RIoTboard\n"); 605 puts("RIoTboard\n");
604 else 606 else
605 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev())); 607 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
606 608
607 return 0; 609 return 0;
608 } 610 }
609 611