Eric Lee / smarc-uboot

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/*

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/*

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* URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.

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* URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.

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*

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*

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* Interrupt support is added. Now, it has been tested

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* Interrupt support is added. Now, it has been tested

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* on ULI1575 chip and works well with USB keyboard.

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* on ULI1575 chip and works well with USB keyboard.

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*

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*

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* Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>

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* Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>

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*

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*

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* Gary Jennejohn, DENX Software Engineering <gj@denx.de>

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* Gary Jennejohn, DENX Software Engineering <gj@denx.de>

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*

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*

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* Note: Much of this code has been derived from Linux 2.4

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* Note: Much of this code has been derived from Linux 2.4

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*

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*

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* ebenard@eukrea.com - based on s3c24x0's driver

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* ebenard@eukrea.com - based on s3c24x0's driver

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*

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*

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* See file CREDITS for list of people who contributed to this

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* See file CREDITS for list of people who contributed to this

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* project.

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* project.

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*

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*

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* This program is free software; you can redistribute it and/or

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* This program is free software; you can redistribute it and/or

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* modify it under the terms of the GNU General Public License as

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* modify it under the terms of the GNU General Public License as

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* published by the Free Software Foundation; either version 2 of

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* published by the Free Software Foundation; either version 2 of

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* the License, or (at your option) any later version.

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* the License, or (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

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* MA 02111-1307 USA

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* MA 02111-1307 USA

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*

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*

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*/

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*/

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/*

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/*

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* IMPORTANT NOTES

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* IMPORTANT NOTES

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* 1 - Read doc/README.generic_usb_ohci

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* 1 - Read doc/README.generic_usb_ohci

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* 2 - this driver is intended for use with USB Mass Storage Devices

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* 2 - this driver is intended for use with USB Mass Storage Devices

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* (BBB) and USB keyboard. There is NO support for Isochronous pipes!

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* (BBB) and USB keyboard. There is NO support for Isochronous pipes!

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* 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG

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* 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG

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* to activate workaround for bug #41 or this driver will NOT work!

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* to activate workaround for bug #41 or this driver will NOT work!

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*/

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*/

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#include <common.h>

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#include <common.h>

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#ifdef CONFIG_USB_OHCI_NEW

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#ifdef CONFIG_USB_OHCI_NEW

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#include <asm/byteorder.h>

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#include <asm/byteorder.h>

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#if defined(CONFIG_PCI_OHCI)

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#if defined(CONFIG_PCI_OHCI)

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# include <pci.h>

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# include <pci.h>

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#endif

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#endif

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#include <malloc.h>

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#include <malloc.h>

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#include <usb.h>

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#include <usb.h>

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#include "usb_ohci.h"

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#include "usb_ohci.h"

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#ifdef CONFIG_AT91RM9200

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#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */

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#endif

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#if defined(CONFIG_ARM920T) || \

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#if defined(CONFIG_ARM920T) || \

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defined(CONFIG_S3C2400) || \

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defined(CONFIG_S3C2400) || \

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defined(CONFIG_S3C2410) || \

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defined(CONFIG_S3C2410) || \

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defined(CONFIG_440EP) || \

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defined(CONFIG_440EP) || \

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defined(CONFIG_PCI_OHCI) || \

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defined(CONFIG_PCI_OHCI) || \

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defined(CONFIG_MPC5200)

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defined(CONFIG_MPC5200)

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# define OHCI_USE_NPS /* force NoPowerSwitching mode */

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# define OHCI_USE_NPS /* force NoPowerSwitching mode */

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#endif

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#endif

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#undef OHCI_VERBOSE_DEBUG /* not always helpful */

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#undef OHCI_VERBOSE_DEBUG /* not always helpful */

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#undef DEBUG

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#undef DEBUG

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#undef SHOW_INFO

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#undef SHOW_INFO

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#undef OHCI_FILL_TRACE

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#undef OHCI_FILL_TRACE

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/* For initializing controller (mask in an HCFS mode too) */

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/* For initializing controller (mask in an HCFS mode too) */

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#define OHCI_CONTROL_INIT \

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#define OHCI_CONTROL_INIT \

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(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE

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(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE

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/*

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/*

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* e.g. PCI controllers need this

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* e.g. PCI controllers need this

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*/

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*/

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#ifdef CFG_OHCI_SWAP_REG_ACCESS

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#ifdef CFG_OHCI_SWAP_REG_ACCESS

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# define readl(a) __swap_32(*((vu_long *)(a)))

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# define readl(a) __swap_32(*((vu_long *)(a)))

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# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))

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# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))

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#else

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#else

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# define readl(a) (*((vu_long *)(a)))

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# define readl(a) (*((vu_long *)(a)))

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# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))

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# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))

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#endif /* CFG_OHCI_SWAP_REG_ACCESS */

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#endif /* CFG_OHCI_SWAP_REG_ACCESS */

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#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })

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#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })

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#ifdef CONFIG_PCI_OHCI

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#ifdef CONFIG_PCI_OHCI

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static struct pci_device_id ohci_pci_ids[] = {

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static struct pci_device_id ohci_pci_ids[] = {

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{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */

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{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */

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{0x1033, 0x0035}, /* NEC PCI OHCI module ids */

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{0x1033, 0x0035}, /* NEC PCI OHCI module ids */

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/* Please add supported PCI OHCI controller ids here */

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/* Please add supported PCI OHCI controller ids here */

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{0, 0}

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{0, 0}

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};

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};

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#endif

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#endif

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#ifdef DEBUG

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#ifdef DEBUG

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#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)

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#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)

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#else

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#else

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#define dbg(format, arg...) do {} while(0)

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#define dbg(format, arg...) do {} while(0)

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#endif /* DEBUG */

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#endif /* DEBUG */

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#define err(format, arg...) printf("ERROR: " format "\n", ## arg)

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#define err(format, arg...) printf("ERROR: " format "\n", ## arg)

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#undef SHOW_INFO

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#undef SHOW_INFO

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#ifdef SHOW_INFO

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#ifdef SHOW_INFO

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#define info(format, arg...) printf("INFO: " format "\n", ## arg)

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#define info(format, arg...) printf("INFO: " format "\n", ## arg)

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#else

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#else

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#define info(format, arg...) do {} while(0)

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#define info(format, arg...) do {} while(0)

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#endif

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#endif

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#ifdef CFG_OHCI_BE_CONTROLLER

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#ifdef CFG_OHCI_BE_CONTROLLER

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# define m16_swap(x) cpu_to_be16(x)

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# define m16_swap(x) cpu_to_be16(x)

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# define m32_swap(x) cpu_to_be32(x)

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# define m32_swap(x) cpu_to_be32(x)

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#else

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#else

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# define m16_swap(x) cpu_to_le16(x)

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# define m16_swap(x) cpu_to_le16(x)

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# define m32_swap(x) cpu_to_le32(x)

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# define m32_swap(x) cpu_to_le32(x)

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#endif /* CFG_OHCI_BE_CONTROLLER */

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#endif /* CFG_OHCI_BE_CONTROLLER */

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/* global ohci_t */

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/* global ohci_t */

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static ohci_t gohci;

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static ohci_t gohci;

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/* this must be aligned to a 256 byte boundary */

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/* this must be aligned to a 256 byte boundary */

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struct ohci_hcca ghcca[1];

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struct ohci_hcca ghcca[1];

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/* a pointer to the aligned storage */

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/* a pointer to the aligned storage */

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struct ohci_hcca *phcca;

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struct ohci_hcca *phcca;

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/* this allocates EDs for all possible endpoints */

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/* this allocates EDs for all possible endpoints */

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struct ohci_device ohci_dev;

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struct ohci_device ohci_dev;

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/* RHSC flag */

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/* RHSC flag */

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int got_rhsc;

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int got_rhsc;

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/* device which was disconnected */

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/* device which was disconnected */

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struct usb_device *devgone;

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struct usb_device *devgone;

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139

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/*-------------------------------------------------------------------------*/

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/*-------------------------------------------------------------------------*/

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/* AMD-756 (D2 rev) reports corrupt register contents in some cases.

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/* AMD-756 (D2 rev) reports corrupt register contents in some cases.

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* The erratum (#4) description is incorrect. AMD's workaround waits

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* The erratum (#4) description is incorrect. AMD's workaround waits

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* till some bits (mostly reserved) are clear; ok for all revs.

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* till some bits (mostly reserved) are clear; ok for all revs.

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*/

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*/

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#define OHCI_QUIRK_AMD756 0xabcd

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#define OHCI_QUIRK_AMD756 0xabcd

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#define read_roothub(hc, register, mask) ({ \

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#define read_roothub(hc, register, mask) ({ \

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u32 temp = readl (&hc->regs->roothub.register); \

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u32 temp = readl (&hc->regs->roothub.register); \

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if (hc->flags & OHCI_QUIRK_AMD756) \

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if (hc->flags & OHCI_QUIRK_AMD756) \

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while (temp & mask) \

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while (temp & mask) \

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temp = readl (&hc->regs->roothub.register); \

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temp = readl (&hc->regs->roothub.register); \

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temp; })

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temp; })

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static u32 roothub_a (struct ohci *hc)

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static u32 roothub_a (struct ohci *hc)

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{ return read_roothub (hc, a, 0xfc0fe000); }

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{ return read_roothub (hc, a, 0xfc0fe000); }

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static inline u32 roothub_b (struct ohci *hc)

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static inline u32 roothub_b (struct ohci *hc)

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{ return readl (&hc->regs->roothub.b); }

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{ return readl (&hc->regs->roothub.b); }

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static inline u32 roothub_status (struct ohci *hc)

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static inline u32 roothub_status (struct ohci *hc)

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{ return readl (&hc->regs->roothub.status); }

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{ return readl (&hc->regs->roothub.status); }

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static u32 roothub_portstatus (struct ohci *hc, int i)

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static u32 roothub_portstatus (struct ohci *hc, int i)

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{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }

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{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }

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/* forward declaration */

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/* forward declaration */

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static int hc_interrupt (void);

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static int hc_interrupt (void);

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static void

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static void

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td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,

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td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,

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int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);

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int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);

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168

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/*-------------------------------------------------------------------------*

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/*-------------------------------------------------------------------------*

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* URB support functions

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* URB support functions

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*-------------------------------------------------------------------------*/

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*-------------------------------------------------------------------------*/

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/* free HCD-private data associated with this URB */

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/* free HCD-private data associated with this URB */

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static void urb_free_priv (urb_priv_t * urb)

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static void urb_free_priv (urb_priv_t * urb)

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{

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{

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int i;

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int i;

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int last;

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int last;

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struct td * td;

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struct td * td;

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180

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last = urb->length - 1;

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last = urb->length - 1;

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if (last >= 0) {

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if (last >= 0) {

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for (i = 0; i <= last; i++) {

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for (i = 0; i <= last; i++) {

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td = urb->td[i];

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td = urb->td[i];

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if (td) {

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if (td) {

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td->usb_dev = NULL;

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td->usb_dev = NULL;

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urb->td[i] = NULL;

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urb->td[i] = NULL;

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}

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}

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}

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}

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}

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}

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free(urb);

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free(urb);

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}

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}

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/*-------------------------------------------------------------------------*/

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/*-------------------------------------------------------------------------*/

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#ifdef DEBUG

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#ifdef DEBUG

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static int sohci_get_current_frame_number (struct usb_device * dev);

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static int sohci_get_current_frame_number (struct usb_device * dev);

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/* debug| print the main components of an URB

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/* debug| print the main components of an URB

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* small: 0) header + data packets 1) just header */

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* small: 0) header + data packets 1) just header */

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static void pkt_print (urb_priv_t *purb, struct usb_device * dev,

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static void pkt_print (urb_priv_t *purb, struct usb_device * dev,

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unsigned long pipe, void * buffer,

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unsigned long pipe, void * buffer,

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int transfer_len, struct devrequest * setup, char * str, int small)

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int transfer_len, struct devrequest * setup, char * str, int small)

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{

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{

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dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",

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dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",

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str,

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str,

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sohci_get_current_frame_number (dev),

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sohci_get_current_frame_number (dev),

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usb_pipedevice (pipe),

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usb_pipedevice (pipe),

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usb_pipeendpoint (pipe),

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usb_pipeendpoint (pipe),

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usb_pipeout (pipe)? 'O': 'I',

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usb_pipeout (pipe)? 'O': 'I',

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usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):

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usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):

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(usb_pipecontrol (pipe)? "CTRL": "BULK"),

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(usb_pipecontrol (pipe)? "CTRL": "BULK"),

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(purb ? purb->actual_length : 0),

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(purb ? purb->actual_length : 0),

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transfer_len, dev->status);

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transfer_len, dev->status);

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#ifdef OHCI_VERBOSE_DEBUG

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#ifdef OHCI_VERBOSE_DEBUG

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if (!small) {

217

if (!small) {

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int i, len;

218

int i, len;

215

219

216

if (usb_pipecontrol (pipe)) {

220

if (usb_pipecontrol (pipe)) {

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printf (__FILE__ ": cmd(8):");

221

printf (__FILE__ ": cmd(8):");

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for (i = 0; i < 8 ; i++)

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for (i = 0; i < 8 ; i++)

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printf (" %02x", ((__u8 *) setup) [i]);

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printf (" %02x", ((__u8 *) setup) [i]);

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printf ("\n");

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printf ("\n");

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}

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}

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if (transfer_len > 0 && buffer) {

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if (transfer_len > 0 && buffer) {

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printf (__FILE__ ": data(%d/%d):",

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printf (__FILE__ ": data(%d/%d):",

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(purb ? purb->actual_length : 0),

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(purb ? purb->actual_length : 0),

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transfer_len);

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transfer_len);

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len = usb_pipeout (pipe)?

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len = usb_pipeout (pipe)?

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transfer_len:

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transfer_len:

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(purb ? purb->actual_length : 0);

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(purb ? purb->actual_length : 0);

229

for (i = 0; i < 16 && i < len; i++)

233

for (i = 0; i < 16 && i < len; i++)

230

printf (" %02x", ((__u8 *) buffer) [i]);

234

printf (" %02x", ((__u8 *) buffer) [i]);

231

printf ("%s\n", i < len? "...": "");

235

printf ("%s\n", i < len? "...": "");

232

}

236

}

233

}

237

}

234

#endif

238

#endif

235

}

239

}

236

240

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/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/

241

/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/

238

void ep_print_int_eds (ohci_t *ohci, char * str) {

242

void ep_print_int_eds (ohci_t *ohci, char * str) {

239

int i, j;

243

int i, j;

240

__u32 * ed_p;

244

__u32 * ed_p;

241

for (i= 0; i < 32; i++) {

245

for (i= 0; i < 32; i++) {

242

j = 5;

246

j = 5;

243

ed_p = &(ohci->hcca->int_table [i]);

247

ed_p = &(ohci->hcca->int_table [i]);

244

if (*ed_p == 0)

248

if (*ed_p == 0)

245

continue;

249

continue;

246

printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);

250

printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);

247

while (*ed_p != 0 && j--) {

251

while (*ed_p != 0 && j--) {

248

ed_t *ed = (ed_t *)m32_swap(ed_p);

252

ed_t *ed = (ed_t *)m32_swap(ed_p);

249

printf (" ed: %4x;", ed->hwINFO);

253

printf (" ed: %4x;", ed->hwINFO);

250

ed_p = &ed->hwNextED;

254

ed_p = &ed->hwNextED;

251

}

255

}

252

printf ("\n");

256

printf ("\n");

253

}

257

}

254

}

258

}

255

259

256

static void ohci_dump_intr_mask (char *label, __u32 mask)

260

static void ohci_dump_intr_mask (char *label, __u32 mask)

257

{

261

{

258

dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",

262

dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",

259

label,

263

label,

260

mask,

264

mask,

261

(mask & OHCI_INTR_MIE) ? " MIE" : "",

265

(mask & OHCI_INTR_MIE) ? " MIE" : "",

262

(mask & OHCI_INTR_OC) ? " OC" : "",

266

(mask & OHCI_INTR_OC) ? " OC" : "",

263

(mask & OHCI_INTR_RHSC) ? " RHSC" : "",

267

(mask & OHCI_INTR_RHSC) ? " RHSC" : "",

264

(mask & OHCI_INTR_FNO) ? " FNO" : "",

268

(mask & OHCI_INTR_FNO) ? " FNO" : "",

265

(mask & OHCI_INTR_UE) ? " UE" : "",

269

(mask & OHCI_INTR_UE) ? " UE" : "",

266

(mask & OHCI_INTR_RD) ? " RD" : "",

270

(mask & OHCI_INTR_RD) ? " RD" : "",

267

(mask & OHCI_INTR_SF) ? " SF" : "",

271

(mask & OHCI_INTR_SF) ? " SF" : "",

268

(mask & OHCI_INTR_WDH) ? " WDH" : "",

272

(mask & OHCI_INTR_WDH) ? " WDH" : "",

269

(mask & OHCI_INTR_SO) ? " SO" : ""

273

(mask & OHCI_INTR_SO) ? " SO" : ""

270

);

274

);

271

}

275

}

272

276

273

static void maybe_print_eds (char *label, __u32 value)

277

static void maybe_print_eds (char *label, __u32 value)

274

{

278

{

275

ed_t *edp = (ed_t *)value;

279

ed_t *edp = (ed_t *)value;

276

280

277

if (value) {

281

if (value) {

278

dbg ("%s %08x", label, value);

282

dbg ("%s %08x", label, value);

279

dbg ("%08x", edp->hwINFO);

283

dbg ("%08x", edp->hwINFO);

280

dbg ("%08x", edp->hwTailP);

284

dbg ("%08x", edp->hwTailP);

281

dbg ("%08x", edp->hwHeadP);

285

dbg ("%08x", edp->hwHeadP);

282

dbg ("%08x", edp->hwNextED);

286

dbg ("%08x", edp->hwNextED);

283

}

287

}

284

}

288

}

285

289

286

static char * hcfs2string (int state)

290

static char * hcfs2string (int state)

287

{

291

{

288

switch (state) {

292

switch (state) {

289

case OHCI_USB_RESET: return "reset";

293

case OHCI_USB_RESET: return "reset";

290

case OHCI_USB_RESUME: return "resume";

294

case OHCI_USB_RESUME: return "resume";

291

case OHCI_USB_OPER: return "operational";

295

case OHCI_USB_OPER: return "operational";

292

case OHCI_USB_SUSPEND: return "suspend";

296

case OHCI_USB_SUSPEND: return "suspend";

293

}

297

}

294

return "?";

298

return "?";

295

}

299

}

296

300

297

/* dump control and status registers */

301

/* dump control and status registers */

298

static void ohci_dump_status (ohci_t *controller)

302

static void ohci_dump_status (ohci_t *controller)

299

{

303

{

300

struct ohci_regs *regs = controller->regs;

304

struct ohci_regs *regs = controller->regs;

301

__u32 temp;

305

__u32 temp;

302

306

303

temp = readl (&regs->revision) & 0xff;

307

temp = readl (&regs->revision) & 0xff;

304

if (temp != 0x10)

308

if (temp != 0x10)

305

dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));

309

dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));

306

310

307

temp = readl (&regs->control);

311

temp = readl (&regs->control);

308

dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,

312

dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,

309

(temp & OHCI_CTRL_RWE) ? " RWE" : "",

313

(temp & OHCI_CTRL_RWE) ? " RWE" : "",

310

(temp & OHCI_CTRL_RWC) ? " RWC" : "",

314

(temp & OHCI_CTRL_RWC) ? " RWC" : "",

311

(temp & OHCI_CTRL_IR) ? " IR" : "",

315

(temp & OHCI_CTRL_IR) ? " IR" : "",

312

hcfs2string (temp & OHCI_CTRL_HCFS),

316

hcfs2string (temp & OHCI_CTRL_HCFS),

313

(temp & OHCI_CTRL_BLE) ? " BLE" : "",

317

(temp & OHCI_CTRL_BLE) ? " BLE" : "",

314

(temp & OHCI_CTRL_CLE) ? " CLE" : "",

318

(temp & OHCI_CTRL_CLE) ? " CLE" : "",

315

(temp & OHCI_CTRL_IE) ? " IE" : "",

319

(temp & OHCI_CTRL_IE) ? " IE" : "",

316

(temp & OHCI_CTRL_PLE) ? " PLE" : "",

320

(temp & OHCI_CTRL_PLE) ? " PLE" : "",

317

temp & OHCI_CTRL_CBSR

321

temp & OHCI_CTRL_CBSR

318

);

322

);

319

323

320

temp = readl (&regs->cmdstatus);

324

temp = readl (&regs->cmdstatus);

321

dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,

325

dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,

322

(temp & OHCI_SOC) >> 16,

326

(temp & OHCI_SOC) >> 16,

323

(temp & OHCI_OCR) ? " OCR" : "",

327

(temp & OHCI_OCR) ? " OCR" : "",

324

(temp & OHCI_BLF) ? " BLF" : "",

328

(temp & OHCI_BLF) ? " BLF" : "",

325

(temp & OHCI_CLF) ? " CLF" : "",

329

(temp & OHCI_CLF) ? " CLF" : "",

326

(temp & OHCI_HCR) ? " HCR" : ""

330

(temp & OHCI_HCR) ? " HCR" : ""

327

);

331

);

328

332

329

ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));

333

ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));

330

ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));

334

ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));

331

335

332

maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));

336

maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));

333

337

334

maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));

338

maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));

335

maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));

339

maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));

336

340

337

maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));

341

maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));

338

maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));

342

maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));

339

343

340

maybe_print_eds ("donehead", readl (&regs->donehead));

344

maybe_print_eds ("donehead", readl (&regs->donehead));

341

}

345

}

342

346

343

static void ohci_dump_roothub (ohci_t *controller, int verbose)

347

static void ohci_dump_roothub (ohci_t *controller, int verbose)

344

{

348

{

345

__u32 temp, ndp, i;

349

__u32 temp, ndp, i;

346

350

347

temp = roothub_a (controller);

351

temp = roothub_a (controller);

348

ndp = (temp & RH_A_NDP);

352

ndp = (temp & RH_A_NDP);

349

#ifdef CONFIG_AT91C_PQFP_UHPBUG

353

#ifdef CONFIG_AT91C_PQFP_UHPBUG

350

ndp = (ndp == 2) ? 1:0;

354

ndp = (ndp == 2) ? 1:0;

351

#endif

355

#endif

352

if (verbose) {

356

if (verbose) {

353

dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,

357

dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,

354

((temp & RH_A_POTPGT) >> 24) & 0xff,

358

((temp & RH_A_POTPGT) >> 24) & 0xff,

355

(temp & RH_A_NOCP) ? " NOCP" : "",

359

(temp & RH_A_NOCP) ? " NOCP" : "",

356

(temp & RH_A_OCPM) ? " OCPM" : "",

360

(temp & RH_A_OCPM) ? " OCPM" : "",

357

(temp & RH_A_DT) ? " DT" : "",

361

(temp & RH_A_DT) ? " DT" : "",

358

(temp & RH_A_NPS) ? " NPS" : "",

362

(temp & RH_A_NPS) ? " NPS" : "",

359

(temp & RH_A_PSM) ? " PSM" : "",

363

(temp & RH_A_PSM) ? " PSM" : "",

360

ndp

364

ndp

361

);

365

);

362

temp = roothub_b (controller);

366

temp = roothub_b (controller);

363

dbg ("roothub.b: %08x PPCM=%04x DR=%04x",

367

dbg ("roothub.b: %08x PPCM=%04x DR=%04x",

364

temp,

368

temp,

365

(temp & RH_B_PPCM) >> 16,

369

(temp & RH_B_PPCM) >> 16,

366

(temp & RH_B_DR)

370

(temp & RH_B_DR)

367

);

371

);

368

temp = roothub_status (controller);

372

temp = roothub_status (controller);

369

dbg ("roothub.status: %08x%s%s%s%s%s%s",

373

dbg ("roothub.status: %08x%s%s%s%s%s%s",

370

temp,

374

temp,

371

(temp & RH_HS_CRWE) ? " CRWE" : "",

375

(temp & RH_HS_CRWE) ? " CRWE" : "",

372

(temp & RH_HS_OCIC) ? " OCIC" : "",

376

(temp & RH_HS_OCIC) ? " OCIC" : "",

373

(temp & RH_HS_LPSC) ? " LPSC" : "",

377

(temp & RH_HS_LPSC) ? " LPSC" : "",

374

(temp & RH_HS_DRWE) ? " DRWE" : "",

378

(temp & RH_HS_DRWE) ? " DRWE" : "",

375

(temp & RH_HS_OCI) ? " OCI" : "",

379

(temp & RH_HS_OCI) ? " OCI" : "",

376

(temp & RH_HS_LPS) ? " LPS" : ""

380

(temp & RH_HS_LPS) ? " LPS" : ""

377

);

381

);

378

}

382

}

379

383

380

for (i = 0; i < ndp; i++) {

384

for (i = 0; i < ndp; i++) {

381

temp = roothub_portstatus (controller, i);

385

temp = roothub_portstatus (controller, i);

382

dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",

386

dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",

383

i,

387

i,

384

temp,

388

temp,

385

(temp & RH_PS_PRSC) ? " PRSC" : "",

389

(temp & RH_PS_PRSC) ? " PRSC" : "",

386

(temp & RH_PS_OCIC) ? " OCIC" : "",

390

(temp & RH_PS_OCIC) ? " OCIC" : "",

387

(temp & RH_PS_PSSC) ? " PSSC" : "",

391

(temp & RH_PS_PSSC) ? " PSSC" : "",

388

(temp & RH_PS_PESC) ? " PESC" : "",

392

(temp & RH_PS_PESC) ? " PESC" : "",

389

(temp & RH_PS_CSC) ? " CSC" : "",

393

(temp & RH_PS_CSC) ? " CSC" : "",

390

394

391

(temp & RH_PS_LSDA) ? " LSDA" : "",

395

(temp & RH_PS_LSDA) ? " LSDA" : "",

392

(temp & RH_PS_PPS) ? " PPS" : "",

396

(temp & RH_PS_PPS) ? " PPS" : "",

393

(temp & RH_PS_PRS) ? " PRS" : "",

397

(temp & RH_PS_PRS) ? " PRS" : "",

394

(temp & RH_PS_POCI) ? " POCI" : "",

398

(temp & RH_PS_POCI) ? " POCI" : "",

395

(temp & RH_PS_PSS) ? " PSS" : "",

399

(temp & RH_PS_PSS) ? " PSS" : "",

396

400

397

(temp & RH_PS_PES) ? " PES" : "",

401

(temp & RH_PS_PES) ? " PES" : "",

398

(temp & RH_PS_CCS) ? " CCS" : ""

402

(temp & RH_PS_CCS) ? " CCS" : ""

399

);

403

);

400

}

404

}

401

}

405

}

402

406

403

static void ohci_dump (ohci_t *controller, int verbose)

407

static void ohci_dump (ohci_t *controller, int verbose)

404

{

408

{

405

dbg ("OHCI controller usb-%s state", controller->slot_name);

409

dbg ("OHCI controller usb-%s state", controller->slot_name);

406

410

407

/* dumps some of the state we know about */

411

/* dumps some of the state we know about */

408

ohci_dump_status (controller);

412

ohci_dump_status (controller);

409

if (verbose)

413

if (verbose)

410

ep_print_int_eds (controller, "hcca");

414

ep_print_int_eds (controller, "hcca");

411

dbg ("hcca frame #%04x", controller->hcca->frame_no);

415

dbg ("hcca frame #%04x", controller->hcca->frame_no);

412

ohci_dump_roothub (controller, 1);

416

ohci_dump_roothub (controller, 1);

413

417

414

#endif /* DEBUG */

418

#endif /* DEBUG */

415

419

416

/*-------------------------------------------------------------------------*

420

/*-------------------------------------------------------------------------*

417

* Interface functions (URB)

421

* Interface functions (URB)

418

*-------------------------------------------------------------------------*/

422

*-------------------------------------------------------------------------*/

419

423

420

/* get a transfer request */

424

/* get a transfer request */

421

425

422

int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)

426

int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)

423

{

427

{

424

ohci_t *ohci;

428

ohci_t *ohci;

425

ed_t * ed;

429

ed_t * ed;

426

urb_priv_t *purb_priv = urb;

430

urb_priv_t *purb_priv = urb;

427

int i, size = 0;

431

int i, size = 0;

428

struct usb_device *dev = urb->dev;

432

struct usb_device *dev = urb->dev;

429

unsigned long pipe = urb->pipe;

433

unsigned long pipe = urb->pipe;

430

void *buffer = urb->transfer_buffer;

434

void *buffer = urb->transfer_buffer;

431

int transfer_len = urb->transfer_buffer_length;

435

int transfer_len = urb->transfer_buffer_length;

432

int interval = urb->interval;

436

int interval = urb->interval;

433

437

434

ohci = &gohci;

438

ohci = &gohci;

435

439

436

/* when controller's hung, permit only roothub cleanup attempts

440

/* when controller's hung, permit only roothub cleanup attempts

437

* such as powering down ports */

441

* such as powering down ports */

438

if (ohci->disabled) {

442

if (ohci->disabled) {

439

err("sohci_submit_job: EPIPE");

443

err("sohci_submit_job: EPIPE");

440

return -1;

444

return -1;

441

}

445

}

442

446

443

/* we're about to begin a new transaction here so mark the URB unfinished */

447

/* we're about to begin a new transaction here so mark the URB unfinished */

444

urb->finished = 0;

448

urb->finished = 0;

445

449

446

/* every endpoint has a ed, locate and fill it */

450

/* every endpoint has a ed, locate and fill it */

447

if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {

451

if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {

448

err("sohci_submit_job: ENOMEM");

452

err("sohci_submit_job: ENOMEM");

449

return -1;

453

return -1;

450

}

454

}

451

455

452

/* for the private part of the URB we need the number of TDs (size) */

456

/* for the private part of the URB we need the number of TDs (size) */

453

switch (usb_pipetype (pipe)) {

457

switch (usb_pipetype (pipe)) {

454

case PIPE_BULK: /* one TD for every 4096 Byte */

458

case PIPE_BULK: /* one TD for every 4096 Byte */

455

size = (transfer_len - 1) / 4096 + 1;

459

size = (transfer_len - 1) / 4096 + 1;

456

break;

460

break;

457

case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */

461

case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */

458

size = (transfer_len == 0)? 2:

462

size = (transfer_len == 0)? 2:

459

(transfer_len - 1) / 4096 + 3;

463

(transfer_len - 1) / 4096 + 3;

460

break;

464

break;

461

case PIPE_INTERRUPT: /* 1 TD */

465

case PIPE_INTERRUPT: /* 1 TD */

462

size = 1;

466

size = 1;

463

break;

467

break;

464

}

468

}

465

469

466

ed->purb = urb;

470

ed->purb = urb;

467

471

468

if (size >= (N_URB_TD - 1)) {

472

if (size >= (N_URB_TD - 1)) {

469

err("need %d TDs, only have %d", size, N_URB_TD);

473

err("need %d TDs, only have %d", size, N_URB_TD);

470

return -1;

474

return -1;

471

}

475

}

472

purb_priv->pipe = pipe;

476

purb_priv->pipe = pipe;

473

477

474

/* fill the private part of the URB */

478

/* fill the private part of the URB */

475

purb_priv->length = size;

479

purb_priv->length = size;

476

purb_priv->ed = ed;

480

purb_priv->ed = ed;

477

purb_priv->actual_length = 0;

481

purb_priv->actual_length = 0;

478

482

479

/* allocate the TDs */

483

/* allocate the TDs */

480

/* note that td[0] was allocated in ep_add_ed */

484

/* note that td[0] was allocated in ep_add_ed */

481

for (i = 0; i < size; i++) {

485

for (i = 0; i < size; i++) {

482

purb_priv->td[i] = td_alloc (dev);

486

purb_priv->td[i] = td_alloc (dev);

483

if (!purb_priv->td[i]) {

487

if (!purb_priv->td[i]) {

484

purb_priv->length = i;

488

purb_priv->length = i;

485

urb_free_priv (purb_priv);

489

urb_free_priv (purb_priv);

486

err("sohci_submit_job: ENOMEM");

490

err("sohci_submit_job: ENOMEM");

487

return -1;

491

return -1;

488

}

492

}

489

}

493

}

490

494

491

if (ed->state == ED_NEW || (ed->state & ED_DEL)) {

495

if (ed->state == ED_NEW || (ed->state & ED_DEL)) {

492

urb_free_priv (purb_priv);

496

urb_free_priv (purb_priv);

493

err("sohci_submit_job: EINVAL");

497

err("sohci_submit_job: EINVAL");

494

return -1;

498

return -1;

495

}

499

}

496

500

497

/* link the ed into a chain if is not already */

501

/* link the ed into a chain if is not already */

498

if (ed->state != ED_OPER)

502

if (ed->state != ED_OPER)

499

ep_link (ohci, ed);

503

ep_link (ohci, ed);

500

504

501

/* fill the TDs and link it to the ed */

505

/* fill the TDs and link it to the ed */

502

td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);

506

td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);

503

507

504

return 0;

508

return 0;

505

}

509

}

506

510

507

static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)

511

static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)

508

{

512

{

509

struct ohci_regs *regs = hc->regs;

513

struct ohci_regs *regs = hc->regs;

510

514

511

switch (usb_pipetype (urb->pipe)) {

515

switch (usb_pipetype (urb->pipe)) {

512

case PIPE_INTERRUPT:

516

case PIPE_INTERRUPT:

513

/* implicitly requeued */

517

/* implicitly requeued */

514

if (urb->dev->irq_handle &&

518

if (urb->dev->irq_handle &&

515

(urb->dev->irq_act_len = urb->actual_length)) {

519

(urb->dev->irq_act_len = urb->actual_length)) {

516

writel (OHCI_INTR_WDH, &regs->intrenable);

520

writel (OHCI_INTR_WDH, &regs->intrenable);

517

readl (&regs->intrenable); /* PCI posting flush */

521

readl (&regs->intrenable); /* PCI posting flush */

518

urb->dev->irq_handle(urb->dev);

522

urb->dev->irq_handle(urb->dev);

519

writel (OHCI_INTR_WDH, &regs->intrdisable);

523

writel (OHCI_INTR_WDH, &regs->intrdisable);

520

readl (&regs->intrdisable); /* PCI posting flush */

524

readl (&regs->intrdisable); /* PCI posting flush */

521

}

525

}

522

urb->actual_length = 0;

526

urb->actual_length = 0;

523

td_submit_job (

527

td_submit_job (

524

urb->dev,

528

urb->dev,

525

urb->pipe,

529

urb->pipe,

526

urb->transfer_buffer,

530

urb->transfer_buffer,

527

urb->transfer_buffer_length,

531

urb->transfer_buffer_length,

528

NULL,

532

NULL,

529

urb,

533

urb,

530

urb->interval);

534

urb->interval);

531

break;

535

break;

532

case PIPE_CONTROL:

536

case PIPE_CONTROL:

533

case PIPE_BULK:

537

case PIPE_BULK:

534

break;

538

break;

535

default:

539

default:

536

return 0;

540

return 0;

537

}

541

}

538

return 1;

542

return 1;

539

}

543

}

540

544

541

/*-------------------------------------------------------------------------*/

545

/*-------------------------------------------------------------------------*/

542

546

543

#ifdef DEBUG

547

#ifdef DEBUG

544

/* tell us the current USB frame number */

548

/* tell us the current USB frame number */

545

549

546

static int sohci_get_current_frame_number (struct usb_device *usb_dev)

550

static int sohci_get_current_frame_number (struct usb_device *usb_dev)

547

{

551

{

548

ohci_t *ohci = &gohci;

552

ohci_t *ohci = &gohci;

549

553

550

return m16_swap (ohci->hcca->frame_no);

554

return m16_swap (ohci->hcca->frame_no);

551

}

555

}

552

#endif

556

#endif

553

557

554

/*-------------------------------------------------------------------------*

558

/*-------------------------------------------------------------------------*

555

* ED handling functions

559

* ED handling functions

556

*-------------------------------------------------------------------------*/

560

*-------------------------------------------------------------------------*/

557

561

558

/* search for the right branch to insert an interrupt ed into the int tree

562

/* search for the right branch to insert an interrupt ed into the int tree

559

* do some load ballancing;

563

* do some load ballancing;

560

* returns the branch and

564

* returns the branch and

561

* sets the interval to interval = 2^integer (ld (interval)) */

565

* sets the interval to interval = 2^integer (ld (interval)) */

562

566

563

static int ep_int_ballance (ohci_t * ohci, int interval, int load)

567

static int ep_int_ballance (ohci_t * ohci, int interval, int load)

564

{

568

{

565

int i, branch = 0;

569

int i, branch = 0;

566

570

567

/* search for the least loaded interrupt endpoint

571

/* search for the least loaded interrupt endpoint

568

* branch of all 32 branches

572

* branch of all 32 branches

569

*/

573

*/

570

for (i = 0; i < 32; i++)

574

for (i = 0; i < 32; i++)

571

if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])

575

if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])

572

branch = i;

576

branch = i;

573

577

574

branch = branch % interval;

578

branch = branch % interval;

575

for (i = branch; i < 32; i += interval)

579

for (i = branch; i < 32; i += interval)

576

ohci->ohci_int_load [i] += load;

580

ohci->ohci_int_load [i] += load;

577

581

578

return branch;

582

return branch;

579

}

583

}

580

584

581

/*-------------------------------------------------------------------------*/

585

/*-------------------------------------------------------------------------*/

582

586

583

/* 2^int( ld (inter)) */

587

/* 2^int( ld (inter)) */

584

588

585

static int ep_2_n_interval (int inter)

589

static int ep_2_n_interval (int inter)

586

{

590

{

587

int i;

591

int i;

588

for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);

592

for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);

589

return 1 << i;

593

return 1 << i;

590

}

594

}

591

595

592

/*-------------------------------------------------------------------------*/

596

/*-------------------------------------------------------------------------*/

593

597

594

/* the int tree is a binary tree

598

/* the int tree is a binary tree

595

* in order to process it sequentially the indexes of the branches have to be mapped

599

* in order to process it sequentially the indexes of the branches have to be mapped

596

* the mapping reverses the bits of a word of num_bits length */

600

* the mapping reverses the bits of a word of num_bits length */

597

601

598

static int ep_rev (int num_bits, int word)

602

static int ep_rev (int num_bits, int word)

599

{

603

{

600

int i, wout = 0;

604

int i, wout = 0;

601

605

602

for (i = 0; i < num_bits; i++)

606

for (i = 0; i < num_bits; i++)

603

wout |= (((word >> i) & 1) << (num_bits - i - 1));

607

wout |= (((word >> i) & 1) << (num_bits - i - 1));

604

return wout;

608

return wout;

605

}

609

}

606

610

607

/*-------------------------------------------------------------------------*

611

/*-------------------------------------------------------------------------*

608

* ED handling functions

612

* ED handling functions

609

*-------------------------------------------------------------------------*/

613

*-------------------------------------------------------------------------*/

610

614

611

/* link an ed into one of the HC chains */

615

/* link an ed into one of the HC chains */

612

616

613

static int ep_link (ohci_t *ohci, ed_t *edi)

617

static int ep_link (ohci_t *ohci, ed_t *edi)

614

{

618

{

615

volatile ed_t *ed = edi;

619

volatile ed_t *ed = edi;

616

int int_branch;

620

int int_branch;

617

int i;

621

int i;

618

int inter;

622

int inter;

619

int interval;

623

int interval;

620

int load;

624

int load;

621

__u32 * ed_p;

625

__u32 * ed_p;

622

626

623

ed->state = ED_OPER;

627

ed->state = ED_OPER;

624

ed->int_interval = 0;

628

ed->int_interval = 0;

625

629

626

switch (ed->type) {

630

switch (ed->type) {

627

case PIPE_CONTROL:

631

case PIPE_CONTROL:

628

ed->hwNextED = 0;

632

ed->hwNextED = 0;

629

if (ohci->ed_controltail == NULL) {

633

if (ohci->ed_controltail == NULL) {

630

writel (ed, &ohci->regs->ed_controlhead);

634

writel (ed, &ohci->regs->ed_controlhead);

631

} else {

635

} else {

632

ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);

636

ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);

633

}

637

}

634

ed->ed_prev = ohci->ed_controltail;

638

ed->ed_prev = ohci->ed_controltail;

635

if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&

639

if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&

636

!ohci->ed_rm_list[1] && !ohci->sleeping) {

640

!ohci->ed_rm_list[1] && !ohci->sleeping) {

637

ohci->hc_control |= OHCI_CTRL_CLE;

641

ohci->hc_control |= OHCI_CTRL_CLE;

638

writel (ohci->hc_control, &ohci->regs->control);

642

writel (ohci->hc_control, &ohci->regs->control);

639

}

643

}

640

ohci->ed_controltail = edi;

644

ohci->ed_controltail = edi;

641

break;

645

break;

642

646

643

case PIPE_BULK:

647

case PIPE_BULK:

644

ed->hwNextED = 0;

648

ed->hwNextED = 0;

645

if (ohci->ed_bulktail == NULL) {

649

if (ohci->ed_bulktail == NULL) {

646

writel (ed, &ohci->regs->ed_bulkhead);

650

writel (ed, &ohci->regs->ed_bulkhead);

647

} else {

651

} else {

648

ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);

652

ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);

649

}

653

}

650

ed->ed_prev = ohci->ed_bulktail;

654

ed->ed_prev = ohci->ed_bulktail;

651

if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&

655

if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&

652

!ohci->ed_rm_list[1] && !ohci->sleeping) {

656

!ohci->ed_rm_list[1] && !ohci->sleeping) {

653

ohci->hc_control |= OHCI_CTRL_BLE;

657

ohci->hc_control |= OHCI_CTRL_BLE;

654

writel (ohci->hc_control, &ohci->regs->control);

658

writel (ohci->hc_control, &ohci->regs->control);

655

}

659

}

656

ohci->ed_bulktail = edi;

660

ohci->ed_bulktail = edi;

657

break;

661

break;

658

662

659

case PIPE_INTERRUPT:

663

case PIPE_INTERRUPT:

660

load = ed->int_load;

664

load = ed->int_load;

661

interval = ep_2_n_interval (ed->int_period);

665

interval = ep_2_n_interval (ed->int_period);

662

ed->int_interval = interval;

666

ed->int_interval = interval;

663

int_branch = ep_int_ballance (ohci, interval, load);

667

int_branch = ep_int_ballance (ohci, interval, load);

664

ed->int_branch = int_branch;

668

ed->int_branch = int_branch;

665

669

666

for (i = 0; i < ep_rev (6, interval); i += inter) {

670

for (i = 0; i < ep_rev (6, interval); i += inter) {

667

inter = 1;

671

inter = 1;

668

for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);

672

for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);

669

(*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);

673

(*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);

670

ed_p = &(((ed_t *)ed_p)->hwNextED))

674

ed_p = &(((ed_t *)ed_p)->hwNextED))

671

inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);

675

inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);

672

ed->hwNextED = *ed_p;

676

ed->hwNextED = *ed_p;

673

*ed_p = m32_swap((unsigned long)ed);

677

*ed_p = m32_swap((unsigned long)ed);

674

}

678

}

675

break;

679

break;

676

}

680

}

677

return 0;

681

return 0;

678

}

682

}

679

683

680

/*-------------------------------------------------------------------------*/

684

/*-------------------------------------------------------------------------*/

681

685

682

/* scan the periodic table to find and unlink this ED */

686

/* scan the periodic table to find and unlink this ED */

683

static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,

687

static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,

684

unsigned index, unsigned period)

688

unsigned index, unsigned period)

685

{

689

{

686

for (; index < NUM_INTS; index += period) {

690

for (; index < NUM_INTS; index += period) {

687

__u32 *ed_p = &ohci->hcca->int_table [index];

691

__u32 *ed_p = &ohci->hcca->int_table [index];

688

692

689

/* ED might have been unlinked through another path */

693

/* ED might have been unlinked through another path */

690

while (*ed_p != 0) {

694

while (*ed_p != 0) {

691

if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {

695

if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {

692

*ed_p = ed->hwNextED;

696

*ed_p = ed->hwNextED;

693

break;

697

break;

694

}

698

}

695

ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);

699

ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);

696

}

700

}

697

}

701

}

698

}

702

}

699

703

700

/* unlink an ed from one of the HC chains.

704

/* unlink an ed from one of the HC chains.

701

* just the link to the ed is unlinked.

705

* just the link to the ed is unlinked.

702

* the link from the ed still points to another operational ed or 0

706

* the link from the ed still points to another operational ed or 0

703

* so the HC can eventually finish the processing of the unlinked ed */

707

* so the HC can eventually finish the processing of the unlinked ed */

704

708

705

static int ep_unlink (ohci_t *ohci, ed_t *edi)

709

static int ep_unlink (ohci_t *ohci, ed_t *edi)

706

{

710

{

707

volatile ed_t *ed = edi;

711

volatile ed_t *ed = edi;

708

int i;

712

int i;

709

713

710

ed->hwINFO |= m32_swap (OHCI_ED_SKIP);

714

ed->hwINFO |= m32_swap (OHCI_ED_SKIP);

711

715

712

switch (ed->type) {

716

switch (ed->type) {

713

case PIPE_CONTROL:

717

case PIPE_CONTROL:

714

if (ed->ed_prev == NULL) {

718

if (ed->ed_prev == NULL) {

715

if (!ed->hwNextED) {

719

if (!ed->hwNextED) {

716

ohci->hc_control &= ~OHCI_CTRL_CLE;

720

ohci->hc_control &= ~OHCI_CTRL_CLE;

717

writel (ohci->hc_control, &ohci->regs->control);

721

writel (ohci->hc_control, &ohci->regs->control);

718

}

722

}

719

writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);

723

writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);

720

} else {

724

} else {

721

ed->ed_prev->hwNextED = ed->hwNextED;

725

ed->ed_prev->hwNextED = ed->hwNextED;

722

}

726

}

723

if (ohci->ed_controltail == ed) {

727

if (ohci->ed_controltail == ed) {

724

ohci->ed_controltail = ed->ed_prev;

728

ohci->ed_controltail = ed->ed_prev;

725

} else {

729

} else {

726

((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;

730

((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;

727

}

731

}

728

break;

732

break;

729

733

730

case PIPE_BULK:

734

case PIPE_BULK:

731

if (ed->ed_prev == NULL) {

735

if (ed->ed_prev == NULL) {

732

if (!ed->hwNextED) {

736

if (!ed->hwNextED) {

733

ohci->hc_control &= ~OHCI_CTRL_BLE;

737

ohci->hc_control &= ~OHCI_CTRL_BLE;

734

writel (ohci->hc_control, &ohci->regs->control);

738

writel (ohci->hc_control, &ohci->regs->control);

735

}

739

}

736

writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);

740

writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);

737

} else {

741

} else {

738

ed->ed_prev->hwNextED = ed->hwNextED;

742

ed->ed_prev->hwNextED = ed->hwNextED;

739

}

743

}

740

if (ohci->ed_bulktail == ed) {

744

if (ohci->ed_bulktail == ed) {

741

ohci->ed_bulktail = ed->ed_prev;

745

ohci->ed_bulktail = ed->ed_prev;

742

} else {

746

} else {

743

((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;

747

((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;

744

}

748

}

745

break;

749

break;

746

750

747

case PIPE_INTERRUPT:

751

case PIPE_INTERRUPT:

748

periodic_unlink (ohci, ed, 0, 1);

752

periodic_unlink (ohci, ed, 0, 1);

749

for (i = ed->int_branch; i < 32; i += ed->int_interval)

753

for (i = ed->int_branch; i < 32; i += ed->int_interval)

750

ohci->ohci_int_load[i] -= ed->int_load;

754

ohci->ohci_int_load[i] -= ed->int_load;

751

break;

755

break;

752

}

756

}

753

ed->state = ED_UNLINK;

757

ed->state = ED_UNLINK;

754

return 0;

758

return 0;

755

}

759

}

756

760

757

/*-------------------------------------------------------------------------*/

761

/*-------------------------------------------------------------------------*/

758

762

759

/* add/reinit an endpoint; this should be done once at the

763

/* add/reinit an endpoint; this should be done once at the

760

* usb_set_configuration command, but the USB stack is a little bit

764

* usb_set_configuration command, but the USB stack is a little bit

761

* stateless so we do it at every transaction if the state of the ed

765

* stateless so we do it at every transaction if the state of the ed

762

* is ED_NEW then a dummy td is added and the state is changed to

766

* is ED_NEW then a dummy td is added and the state is changed to

763

* ED_UNLINK in all other cases the state is left unchanged the ed

767

* ED_UNLINK in all other cases the state is left unchanged the ed

764

* info fields are setted anyway even though most of them should not

768

* info fields are setted anyway even though most of them should not

765

* change

769

* change

766

*/

770

*/

767

static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,

771

static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,

768

int interval, int load)

772

int interval, int load)

769

{

773

{

770

td_t *td;

774

td_t *td;

771

ed_t *ed_ret;

775

ed_t *ed_ret;

772

volatile ed_t *ed;

776

volatile ed_t *ed;

773

777

774

ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |

778

ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |

775

(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];

779

(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];

776

780

777

if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {

781

if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {

778

err("ep_add_ed: pending delete");

782

err("ep_add_ed: pending delete");

779

/* pending delete request */

783

/* pending delete request */

780

return NULL;

784

return NULL;

781

}

785

}

782

786

783

if (ed->state == ED_NEW) {

787

if (ed->state == ED_NEW) {

784

ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */

788

ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */

785

/* dummy td; end of td list for ed */

789

/* dummy td; end of td list for ed */

786

td = td_alloc (usb_dev);

790

td = td_alloc (usb_dev);

787

ed->hwTailP = m32_swap ((unsigned long)td);

791

ed->hwTailP = m32_swap ((unsigned long)td);

788

ed->hwHeadP = ed->hwTailP;

792

ed->hwHeadP = ed->hwTailP;

789

ed->state = ED_UNLINK;

793

ed->state = ED_UNLINK;

790

ed->type = usb_pipetype (pipe);

794

ed->type = usb_pipetype (pipe);

791

ohci_dev.ed_cnt++;

795

ohci_dev.ed_cnt++;

792

}

796

}

793

797

794

ed->hwINFO = m32_swap (usb_pipedevice (pipe)

798

ed->hwINFO = m32_swap (usb_pipedevice (pipe)

795

| usb_pipeendpoint (pipe) << 7

799

| usb_pipeendpoint (pipe) << 7

796

| (usb_pipeisoc (pipe)? 0x8000: 0)

800

| (usb_pipeisoc (pipe)? 0x8000: 0)

797

| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))

801

| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))

798

| usb_pipeslow (pipe) << 13

802

| usb_pipeslow (pipe) << 13

799

| usb_maxpacket (usb_dev, pipe) << 16);

803

| usb_maxpacket (usb_dev, pipe) << 16);

800

804

801

if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {

805

if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {

802

ed->int_period = interval;

806

ed->int_period = interval;

803

ed->int_load = load;

807

ed->int_load = load;

804

}

808

}

805

809

806

return ed_ret;

810

return ed_ret;

807

}

811

}

808

812

809

/*-------------------------------------------------------------------------*

813

/*-------------------------------------------------------------------------*

810

* TD handling functions

814

* TD handling functions

811

*-------------------------------------------------------------------------*/

815

*-------------------------------------------------------------------------*/

812

816

813

/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */

817

/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */

814

818

815

static void td_fill (ohci_t *ohci, unsigned int info,

819

static void td_fill (ohci_t *ohci, unsigned int info,

816

void *data, int len,

820

void *data, int len,

817

struct usb_device *dev, int index, urb_priv_t *urb_priv)

821

struct usb_device *dev, int index, urb_priv_t *urb_priv)

818

{

822

{

819

volatile td_t *td, *td_pt;

823

volatile td_t *td, *td_pt;

820

#ifdef OHCI_FILL_TRACE

824

#ifdef OHCI_FILL_TRACE

821

int i;

825

int i;

822

#endif

826

#endif

823

827

824

if (index > urb_priv->length) {

828

if (index > urb_priv->length) {

825

err("index > length");

829

err("index > length");

826

return;

830

return;

827

}

831

}

828

/* use this td as the next dummy */

832

/* use this td as the next dummy */

829

td_pt = urb_priv->td [index];

833

td_pt = urb_priv->td [index];

830

td_pt->hwNextTD = 0;

834

td_pt->hwNextTD = 0;

831

835

832

/* fill the old dummy TD */

836

/* fill the old dummy TD */

833

td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);

837

td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);

834

838

835

td->ed = urb_priv->ed;

839

td->ed = urb_priv->ed;

836

td->next_dl_td = NULL;

840

td->next_dl_td = NULL;

837

td->index = index;

841

td->index = index;

838

td->data = (__u32)data;

842

td->data = (__u32)data;

839

#ifdef OHCI_FILL_TRACE

843

#ifdef OHCI_FILL_TRACE

840

if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {

844

if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {

841

for (i = 0; i < len; i++)

845

for (i = 0; i < len; i++)

842

printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);

846

printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);

843

printf("\n");

847

printf("\n");

844

}

848

}

845

#endif

849

#endif

846

if (!len)

850

if (!len)

847

data = 0;

851

data = 0;

848

852

849

td->hwINFO = m32_swap (info);

853

td->hwINFO = m32_swap (info);

850

td->hwCBP = m32_swap ((unsigned long)data);

854

td->hwCBP = m32_swap ((unsigned long)data);

851

if (data)

855

if (data)

852

td->hwBE = m32_swap ((unsigned long)(data + len - 1));

856

td->hwBE = m32_swap ((unsigned long)(data + len - 1));

853

else

857

else

854

td->hwBE = 0;

858

td->hwBE = 0;

855

td->hwNextTD = m32_swap ((unsigned long)td_pt);

859

td->hwNextTD = m32_swap ((unsigned long)td_pt);

856

860

857

/* append to queue */

861

/* append to queue */

858

td->ed->hwTailP = td->hwNextTD;

862

td->ed->hwTailP = td->hwNextTD;

859

}

863

}

860

864

861

/*-------------------------------------------------------------------------*/

865

/*-------------------------------------------------------------------------*/

862

866

863

/* prepare all TDs of a transfer */

867

/* prepare all TDs of a transfer */

864

868

865

static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,

869

static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,

866

int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)

870

int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)

867

{

871

{

868

ohci_t *ohci = &gohci;

872

ohci_t *ohci = &gohci;

869

int data_len = transfer_len;

873

int data_len = transfer_len;

870

void *data;

874

void *data;

871

int cnt = 0;

875

int cnt = 0;

872

__u32 info = 0;

876

__u32 info = 0;

873

unsigned int toggle = 0;

877

unsigned int toggle = 0;

874

878

875

/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */

879

/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */

876

if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {

880

if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {

877

toggle = TD_T_TOGGLE;

881

toggle = TD_T_TOGGLE;

878

} else {

882

} else {

879

toggle = TD_T_DATA0;

883

toggle = TD_T_DATA0;

880

usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);

884

usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);

881

}

885

}

882

urb->td_cnt = 0;

886

urb->td_cnt = 0;

883

if (data_len)

887

if (data_len)

884

data = buffer;

888

data = buffer;

885

else

889

else

886

data = 0;

890

data = 0;

887

891

888

switch (usb_pipetype (pipe)) {

892

switch (usb_pipetype (pipe)) {

889

case PIPE_BULK:

893

case PIPE_BULK:

890

info = usb_pipeout (pipe)?

894

info = usb_pipeout (pipe)?

891

TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;

895

TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;

892

while(data_len > 4096) {

896

while(data_len > 4096) {

893

td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);

897

td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);

894

data += 4096; data_len -= 4096; cnt++;

898

data += 4096; data_len -= 4096; cnt++;

895

}

899

}

896

info = usb_pipeout (pipe)?

900

info = usb_pipeout (pipe)?

897

TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;

901

TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;

898

td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);

902

td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);

899

cnt++;

903

cnt++;

900

904

901

if (!ohci->sleeping)

905

if (!ohci->sleeping)

902

writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */

906

writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */

903

break;

907

break;

904

908

905

case PIPE_CONTROL:

909

case PIPE_CONTROL:

906

info = TD_CC | TD_DP_SETUP | TD_T_DATA0;

910

info = TD_CC | TD_DP_SETUP | TD_T_DATA0;

907

td_fill (ohci, info, setup, 8, dev, cnt++, urb);

911

td_fill (ohci, info, setup, 8, dev, cnt++, urb);

908

if (data_len > 0) {

912

if (data_len > 0) {

909

info = usb_pipeout (pipe)?

913

info = usb_pipeout (pipe)?

910

914

911

/* NOTE: mishandles transfers >8K, some >4K */

915

/* NOTE: mishandles transfers >8K, some >4K */

912

td_fill (ohci, info, data, data_len, dev, cnt++, urb);

916

td_fill (ohci, info, data, data_len, dev, cnt++, urb);

913

}

917

}

914

info = usb_pipeout (pipe)?

918

info = usb_pipeout (pipe)?

915

TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;

919

TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;

916

td_fill (ohci, info, data, 0, dev, cnt++, urb);

920

td_fill (ohci, info, data, 0, dev, cnt++, urb);

917

if (!ohci->sleeping)

921

if (!ohci->sleeping)

918

writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */

922

writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */

919

break;

923

break;

920

924

921

case PIPE_INTERRUPT:

925

case PIPE_INTERRUPT:

922

info = usb_pipeout (urb->pipe)?

926

info = usb_pipeout (urb->pipe)?

923

TD_CC | TD_DP_OUT | toggle:

927

TD_CC | TD_DP_OUT | toggle:

924

TD_CC | TD_R | TD_DP_IN | toggle;

928

TD_CC | TD_R | TD_DP_IN | toggle;

925

td_fill (ohci, info, data, data_len, dev, cnt++, urb);

929

td_fill (ohci, info, data, data_len, dev, cnt++, urb);

926

break;

930

break;

927

}

931

}

928

if (urb->length != cnt)

932

if (urb->length != cnt)

929

dbg("TD LENGTH %d != CNT %d", urb->length, cnt);

933

dbg("TD LENGTH %d != CNT %d", urb->length, cnt);

930

}

934

}

931

935

932

/*-------------------------------------------------------------------------*

936

/*-------------------------------------------------------------------------*

933

* Done List handling functions

937

* Done List handling functions

934

*-------------------------------------------------------------------------*/

938

*-------------------------------------------------------------------------*/

935

939

936

/* calculate the transfer length and update the urb */

940

/* calculate the transfer length and update the urb */

937

941

938

static void dl_transfer_length(td_t * td)

942

static void dl_transfer_length(td_t * td)

939

{

943

{

940

__u32 tdINFO, tdBE, tdCBP;

944

__u32 tdINFO, tdBE, tdCBP;

941

urb_priv_t *lurb_priv = td->ed->purb;

945

urb_priv_t *lurb_priv = td->ed->purb;

942

946

943

tdINFO = m32_swap (td->hwINFO);

947

tdINFO = m32_swap (td->hwINFO);

944

tdBE = m32_swap (td->hwBE);

948

tdBE = m32_swap (td->hwBE);

945

tdCBP = m32_swap (td->hwCBP);

949

tdCBP = m32_swap (td->hwCBP);

946

950

947

if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&

951

if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&

948

((td->index == 0) || (td->index == lurb_priv->length - 1)))) {

952

((td->index == 0) || (td->index == lurb_priv->length - 1)))) {

949

if (tdBE != 0) {

953

if (tdBE != 0) {

950

if (td->hwCBP == 0)

954

if (td->hwCBP == 0)

951

lurb_priv->actual_length += tdBE - td->data + 1;

955

lurb_priv->actual_length += tdBE - td->data + 1;

952

else

956

else

953

lurb_priv->actual_length += tdCBP - td->data;

957

lurb_priv->actual_length += tdCBP - td->data;

954

}

958

}

955

}

959

}

956

}

960

}

957

961

958

/*-------------------------------------------------------------------------*/

962

/*-------------------------------------------------------------------------*/

959

963

960

/* replies to the request have to be on a FIFO basis so

964

/* replies to the request have to be on a FIFO basis so

961

* we reverse the reversed done-list */

965

* we reverse the reversed done-list */

962

966

963

static td_t * dl_reverse_done_list (ohci_t *ohci)

967

static td_t * dl_reverse_done_list (ohci_t *ohci)

964

{

968

{

965

__u32 td_list_hc;

969

__u32 td_list_hc;

966

td_t *td_rev = NULL;

970

td_t *td_rev = NULL;

967

td_t *td_list = NULL;

971

td_t *td_list = NULL;

968

urb_priv_t *lurb_priv = NULL;

972

urb_priv_t *lurb_priv = NULL;

969

973

970

td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;

974

td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;

971

ohci->hcca->done_head = 0;

975

ohci->hcca->done_head = 0;

972

976

973

while (td_list_hc) {

977

while (td_list_hc) {

974

td_list = (td_t *)td_list_hc;

978

td_list = (td_t *)td_list_hc;

975

979

976

if (TD_CC_GET (m32_swap (td_list->hwINFO))) {

980

if (TD_CC_GET (m32_swap (td_list->hwINFO))) {

977

lurb_priv = td_list->ed->purb;

981

lurb_priv = td_list->ed->purb;

978

dbg(" USB-error/status: %x : %p",

982

dbg(" USB-error/status: %x : %p",

979

TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);

983

TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);

980

if (td_list->ed->hwHeadP & m32_swap (0x1)) {

984

if (td_list->ed->hwHeadP & m32_swap (0x1)) {

981

if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {

985

if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {

982

td_list->ed->hwHeadP =

986

td_list->ed->hwHeadP =

983

(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |

987

(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |

984

(td_list->ed->hwHeadP & m32_swap (0x2));

988

(td_list->ed->hwHeadP & m32_swap (0x2));

985

lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;

989

lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;

986

} else

990

} else

987

td_list->ed->hwHeadP &= m32_swap (0xfffffff2);

991

td_list->ed->hwHeadP &= m32_swap (0xfffffff2);

988

}

992

}

989

#ifdef CONFIG_MPC5200

993

#ifdef CONFIG_MPC5200

990

td_list->hwNextTD = 0;

994

td_list->hwNextTD = 0;

991

#endif

995

#endif

992

}

996

}

993

997

994

td_list->next_dl_td = td_rev;

998

td_list->next_dl_td = td_rev;

995

td_rev = td_list;

999

td_rev = td_list;

996

td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;

1000

td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;

997

}

1001

}

998

return td_list;

1002

return td_list;

999

}

1003

}

1000

1004

1001

/*-------------------------------------------------------------------------*/

1005

/*-------------------------------------------------------------------------*/

1002

1006

1003

/* td done list */

1007

/* td done list */

1004

static int dl_done_list (ohci_t *ohci, td_t *td_list)

1008

static int dl_done_list (ohci_t *ohci, td_t *td_list)

1005

{

1009

{

1006

td_t *td_list_next = NULL;

1010

td_t *td_list_next = NULL;

1007

ed_t *ed;

1011

ed_t *ed;

1008

int cc = 0;

1012

int cc = 0;

1009

int stat = 0;

1013

int stat = 0;

1010

/* urb_t *urb; */

1014

/* urb_t *urb; */

1011

urb_priv_t *lurb_priv;

1015

urb_priv_t *lurb_priv;

1012

__u32 tdINFO, edHeadP, edTailP;

1016

__u32 tdINFO, edHeadP, edTailP;

1013

1017

1014

while (td_list) {

1018

while (td_list) {

1015

td_list_next = td_list->next_dl_td;

1019

td_list_next = td_list->next_dl_td;

1016

1020

1017

tdINFO = m32_swap (td_list->hwINFO);

1021

tdINFO = m32_swap (td_list->hwINFO);

1018

1022

1019

ed = td_list->ed;

1023

ed = td_list->ed;

1020

lurb_priv = ed->purb;

1024

lurb_priv = ed->purb;

1021

1025

1022

dl_transfer_length(td_list);

1026

dl_transfer_length(td_list);

1023

1027

1024

/* error code of transfer */

1028

/* error code of transfer */

1025

cc = TD_CC_GET (tdINFO);

1029

cc = TD_CC_GET (tdINFO);

1026

if (cc != 0) {

1030

if (cc != 0) {

1027

dbg("ConditionCode %#x", cc);

1031

dbg("ConditionCode %#x", cc);

1028

stat = cc_to_error[cc];

1032

stat = cc_to_error[cc];

1029

}

1033

}

1030

1034

1031

/* see if this done list makes for all TD's of current URB,

1035

/* see if this done list makes for all TD's of current URB,

1032

* and mark the URB finished if so */

1036

* and mark the URB finished if so */

1033

if (++(lurb_priv->td_cnt) == lurb_priv->length) {

1037

if (++(lurb_priv->td_cnt) == lurb_priv->length) {

1034

#if 1

1038

#if 1

1035

if ((ed->state & (ED_OPER | ED_UNLINK)) &&

1039

if ((ed->state & (ED_OPER | ED_UNLINK)) &&

1036

(lurb_priv->state != URB_DEL))

1040

(lurb_priv->state != URB_DEL))

1037

#else

1041

#else

1038

if ((ed->state & (ED_OPER | ED_UNLINK)))

1042

if ((ed->state & (ED_OPER | ED_UNLINK)))

1039

#endif

1043

#endif

1040

lurb_priv->finished = sohci_return_job(ohci,

1044

lurb_priv->finished = sohci_return_job(ohci,

1041

lurb_priv);

1045

lurb_priv);

1042

else

1046

else

1043

dbg("dl_done_list: strange.., ED state %x, ed->state\n");

1047

dbg("dl_done_list: strange.., ED state %x, ed->state\n");

1044

} else

1048

} else

1045

dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,

1049

dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,

1046

lurb_priv->length);

1050

lurb_priv->length);

1047

if (ed->state != ED_NEW &&

1051

if (ed->state != ED_NEW &&

1048

(usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {

1052

(usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {

1049

edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;

1053

edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;

1050

edTailP = m32_swap (ed->hwTailP);

1054

edTailP = m32_swap (ed->hwTailP);

1051

1055

1052

/* unlink eds if they are not busy */

1056

/* unlink eds if they are not busy */

1053

if ((edHeadP == edTailP) && (ed->state == ED_OPER))

1057

if ((edHeadP == edTailP) && (ed->state == ED_OPER))

1054

ep_unlink (ohci, ed);

1058

ep_unlink (ohci, ed);

1055

}

1059

}

1056

1060

1057

td_list = td_list_next;

1061

td_list = td_list_next;

1058

}

1062

}

1059

return stat;

1063

return stat;

1060

}

1064

}

1061

1065

1062

/*-------------------------------------------------------------------------*

1066

/*-------------------------------------------------------------------------*

1063

* Virtual Root Hub

1067

* Virtual Root Hub

1064

*-------------------------------------------------------------------------*/

1068

*-------------------------------------------------------------------------*/

1065

1069

1066

/* Device descriptor */

1070

/* Device descriptor */

1067

static __u8 root_hub_dev_des[] =

1071

static __u8 root_hub_dev_des[] =

1068

{

1072

{

1069

0x12, /* __u8 bLength; */

1073

0x12, /* __u8 bLength; */

1070

0x01, /* __u8 bDescriptorType; Device */

1074

0x01, /* __u8 bDescriptorType; Device */

1071

0x10, /* __u16 bcdUSB; v1.1 */

1075

0x10, /* __u16 bcdUSB; v1.1 */

1072

0x01,

1076

0x01,

1073

0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */

1077

0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */

1074

0x00, /* __u8 bDeviceSubClass; */

1078

0x00, /* __u8 bDeviceSubClass; */

1075

0x00, /* __u8 bDeviceProtocol; */

1079

0x00, /* __u8 bDeviceProtocol; */

1076

0x08, /* __u8 bMaxPacketSize0; 8 Bytes */

1080

0x08, /* __u8 bMaxPacketSize0; 8 Bytes */

1077

0x00, /* __u16 idVendor; */

1081

0x00, /* __u16 idVendor; */

1078

0x00,

1082

0x00,

1079

0x00, /* __u16 idProduct; */

1083

0x00, /* __u16 idProduct; */

1080

0x00,

1084

0x00,

1081

0x00, /* __u16 bcdDevice; */

1085

0x00, /* __u16 bcdDevice; */

1082

0x00,

1086

0x00,

1083

0x00, /* __u8 iManufacturer; */

1087

0x00, /* __u8 iManufacturer; */

1084

0x01, /* __u8 iProduct; */

1088

0x01, /* __u8 iProduct; */

1085

0x00, /* __u8 iSerialNumber; */

1089

0x00, /* __u8 iSerialNumber; */

1086

0x01 /* __u8 bNumConfigurations; */

1090

0x01 /* __u8 bNumConfigurations; */

1087

};

1091

};

1088

1092

1089

/* Configuration descriptor */

1093

/* Configuration descriptor */

1090

static __u8 root_hub_config_des[] =

1094

static __u8 root_hub_config_des[] =

1091

{

1095

{

1092

0x09, /* __u8 bLength; */

1096

0x09, /* __u8 bLength; */

1093

0x02, /* __u8 bDescriptorType; Configuration */

1097

0x02, /* __u8 bDescriptorType; Configuration */

1094

0x19, /* __u16 wTotalLength; */

1098

0x19, /* __u16 wTotalLength; */

1095

0x00,

1099

0x00,

1096

0x01, /* __u8 bNumInterfaces; */

1100

0x01, /* __u8 bNumInterfaces; */

1097

0x01, /* __u8 bConfigurationValue; */

1101

0x01, /* __u8 bConfigurationValue; */

1098

0x00, /* __u8 iConfiguration; */

1102

0x00, /* __u8 iConfiguration; */

1099

0x40, /* __u8 bmAttributes;

1103

0x40, /* __u8 bmAttributes;

1100

Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */

1104

Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */

1101

0x00, /* __u8 MaxPower; */

1105

0x00, /* __u8 MaxPower; */

1102

1106

1103

/* interface */

1107

/* interface */

1104

0x09, /* __u8 if_bLength; */

1108

0x09, /* __u8 if_bLength; */

1105

0x04, /* __u8 if_bDescriptorType; Interface */

1109

0x04, /* __u8 if_bDescriptorType; Interface */

1106

0x00, /* __u8 if_bInterfaceNumber; */

1110

0x00, /* __u8 if_bInterfaceNumber; */

1107

0x00, /* __u8 if_bAlternateSetting; */

1111

0x00, /* __u8 if_bAlternateSetting; */

1108

0x01, /* __u8 if_bNumEndpoints; */

1112

0x01, /* __u8 if_bNumEndpoints; */

1109

0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */

1113

0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */

1110

0x00, /* __u8 if_bInterfaceSubClass; */

1114

0x00, /* __u8 if_bInterfaceSubClass; */

1111

0x00, /* __u8 if_bInterfaceProtocol; */

1115

0x00, /* __u8 if_bInterfaceProtocol; */

1112

0x00, /* __u8 if_iInterface; */

1116

0x00, /* __u8 if_iInterface; */

1113

1117

1114

/* endpoint */

1118

/* endpoint */

1115

0x07, /* __u8 ep_bLength; */

1119

0x07, /* __u8 ep_bLength; */

1116

0x05, /* __u8 ep_bDescriptorType; Endpoint */

1120

0x05, /* __u8 ep_bDescriptorType; Endpoint */

1117

0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */

1121

0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */

1118

0x03, /* __u8 ep_bmAttributes; Interrupt */

1122

0x03, /* __u8 ep_bmAttributes; Interrupt */

1119

0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */

1123

0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */

1120

0x00,

1124

0x00,

1121

0xff /* __u8 ep_bInterval; 255 ms */

1125

0xff /* __u8 ep_bInterval; 255 ms */

1122

};

1126

};

1123

1127

1124

static unsigned char root_hub_str_index0[] =

1128

static unsigned char root_hub_str_index0[] =

1125

{

1129

{

1126

0x04, /* __u8 bLength; */

1130

0x04, /* __u8 bLength; */

1127

0x03, /* __u8 bDescriptorType; String-descriptor */

1131

0x03, /* __u8 bDescriptorType; String-descriptor */

1128

0x09, /* __u8 lang ID */

1132

0x09, /* __u8 lang ID */

1129

0x04, /* __u8 lang ID */

1133

0x04, /* __u8 lang ID */

1130

};

1134

};

1131

1135

1132

static unsigned char root_hub_str_index1[] =

1136

static unsigned char root_hub_str_index1[] =

1133

{

1137

{

1134

28, /* __u8 bLength; */

1138

28, /* __u8 bLength; */

1135

0x03, /* __u8 bDescriptorType; String-descriptor */

1139

0x03, /* __u8 bDescriptorType; String-descriptor */

1136

'O', /* __u8 Unicode */

1140

'O', /* __u8 Unicode */

1137

0, /* __u8 Unicode */

1141

0, /* __u8 Unicode */

1138

'H', /* __u8 Unicode */

1142

'H', /* __u8 Unicode */

1139

0, /* __u8 Unicode */

1143

0, /* __u8 Unicode */

1140

'C', /* __u8 Unicode */

1144

'C', /* __u8 Unicode */

1141

0, /* __u8 Unicode */

1145

0, /* __u8 Unicode */

1142

'I', /* __u8 Unicode */

1146

'I', /* __u8 Unicode */

1143

0, /* __u8 Unicode */

1147

0, /* __u8 Unicode */

1144

' ', /* __u8 Unicode */

1148

' ', /* __u8 Unicode */

1145

0, /* __u8 Unicode */

1149

0, /* __u8 Unicode */

1146

'R', /* __u8 Unicode */

1150

'R', /* __u8 Unicode */

1147

0, /* __u8 Unicode */

1151

0, /* __u8 Unicode */

1148

'o', /* __u8 Unicode */

1152

'o', /* __u8 Unicode */

1149

0, /* __u8 Unicode */

1153

0, /* __u8 Unicode */

1150

'o', /* __u8 Unicode */

1154

'o', /* __u8 Unicode */

1151

0, /* __u8 Unicode */

1155

0, /* __u8 Unicode */

1152

't', /* __u8 Unicode */

1156

't', /* __u8 Unicode */

1153

0, /* __u8 Unicode */

1157

0, /* __u8 Unicode */

1154

' ', /* __u8 Unicode */

1158

' ', /* __u8 Unicode */

1155

0, /* __u8 Unicode */

1159

0, /* __u8 Unicode */

1156

'H', /* __u8 Unicode */

1160

'H', /* __u8 Unicode */

1157

0, /* __u8 Unicode */

1161

0, /* __u8 Unicode */

1158

'u', /* __u8 Unicode */

1162

'u', /* __u8 Unicode */

1159

0, /* __u8 Unicode */

1163

0, /* __u8 Unicode */

1160

'b', /* __u8 Unicode */

1164

'b', /* __u8 Unicode */

1161

0, /* __u8 Unicode */

1165

0, /* __u8 Unicode */

1162

};

1166

};

1163

1167

1164

/* Hub class-specific descriptor is constructed dynamically */

1168

/* Hub class-specific descriptor is constructed dynamically */

1165

1169

1166

/*-------------------------------------------------------------------------*/

1170

/*-------------------------------------------------------------------------*/

1167

1171

1168

#define OK(x) len = (x); break

1172

#define OK(x) len = (x); break

1169

#ifdef DEBUG

1173

#ifdef DEBUG

1170

#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}

1174

#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}

1171

#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}

1175

#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}

1172

#else

1176

#else

1173

#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)

1177

#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)

1174

#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])

1178

#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])

1175

#endif

1179

#endif

1176

#define RD_RH_STAT roothub_status(&gohci)

1180

#define RD_RH_STAT roothub_status(&gohci)

1177

#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)

1181

#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)

1178

1182

1179

/* request to virtual root hub */

1183

/* request to virtual root hub */

1180

1184

1181

int rh_check_port_status(ohci_t *controller)

1185

int rh_check_port_status(ohci_t *controller)

1182

{

1186

{

1183

__u32 temp, ndp, i;

1187

__u32 temp, ndp, i;

1184

int res;

1188

int res;

1185

1189

1186

res = -1;

1190

res = -1;

1187

temp = roothub_a (controller);

1191

temp = roothub_a (controller);

1188

ndp = (temp & RH_A_NDP);

1192

ndp = (temp & RH_A_NDP);

1189

#ifdef CONFIG_AT91C_PQFP_UHPBUG

1193

#ifdef CONFIG_AT91C_PQFP_UHPBUG

1190

ndp = (ndp == 2) ? 1:0;

1194

ndp = (ndp == 2) ? 1:0;

1191

#endif

1195

#endif

1192

for (i = 0; i < ndp; i++) {

1196

for (i = 0; i < ndp; i++) {

1193

temp = roothub_portstatus (controller, i);

1197

temp = roothub_portstatus (controller, i);

1194

/* check for a device disconnect */

1198

/* check for a device disconnect */

1195

if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==

1199

if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==

1196

(RH_PS_PESC | RH_PS_CSC)) &&

1200

(RH_PS_PESC | RH_PS_CSC)) &&

1197

((temp & RH_PS_CCS) == 0)) {

1201

((temp & RH_PS_CCS) == 0)) {

1198

res = i;

1202

res = i;

1199

break;

1203

break;

1200

}

1204

}

1201

}

1205

}

1202

return res;

1206

return res;

1203

}

1207

}

1204

1208

1205

static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,

1209

static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,

1206

void *buffer, int transfer_len, struct devrequest *cmd)

1210

void *buffer, int transfer_len, struct devrequest *cmd)

1207

{

1211

{

1208

void * data = buffer;

1212

void * data = buffer;

1209

int leni = transfer_len;

1213

int leni = transfer_len;

1210

int len = 0;

1214

int len = 0;

1211

int stat = 0;

1215

int stat = 0;

1212

__u32 datab[4];

1216

__u32 datab[4];

1213

__u8 *data_buf = (__u8 *)datab;

1217

__u8 *data_buf = (__u8 *)datab;

1214

__u16 bmRType_bReq;

1218

__u16 bmRType_bReq;

1215

__u16 wValue;

1219

__u16 wValue;

1216

__u16 wIndex;

1220

__u16 wIndex;

1217

__u16 wLength;

1221

__u16 wLength;

1218

1222

1219

#ifdef DEBUG

1223

#ifdef DEBUG

1220

pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));

1224

pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));

1221

#else

1225

#else

1222

wait_ms(1);

1226

wait_ms(1);

1223

#endif

1227

#endif

1224

if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {

1228

if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {

1225

info("Root-Hub submit IRQ: NOT implemented");

1229

info("Root-Hub submit IRQ: NOT implemented");

1226

return 0;

1230

return 0;

1227

}

1231

}

1228

1232

1229

bmRType_bReq = cmd->requesttype | (cmd->request << 8);

1233

bmRType_bReq = cmd->requesttype | (cmd->request << 8);

1230

wValue = cpu_to_le16 (cmd->value);

1234

wValue = cpu_to_le16 (cmd->value);

1231

wIndex = cpu_to_le16 (cmd->index);

1235

wIndex = cpu_to_le16 (cmd->index);

1232

wLength = cpu_to_le16 (cmd->length);

1236

wLength = cpu_to_le16 (cmd->length);

1233

1237

1234

info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",

1238

info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",

1235

dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);

1239

dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);

1236

1240

1237

switch (bmRType_bReq) {

1241

switch (bmRType_bReq) {

1238

/* Request Destination:

1242

/* Request Destination:

1239

without flags: Device,

1243

without flags: Device,

1240

RH_INTERFACE: interface,

1244

RH_INTERFACE: interface,

1241

RH_ENDPOINT: endpoint,

1245

RH_ENDPOINT: endpoint,

1242

RH_CLASS means HUB here,

1246

RH_CLASS means HUB here,

1243

RH_OTHER | RH_CLASS almost ever means HUB_PORT here

1247

RH_OTHER | RH_CLASS almost ever means HUB_PORT here

1244

*/

1248

*/

1245

1249

1246

case RH_GET_STATUS:

1250

case RH_GET_STATUS:

1247

*(__u16 *) data_buf = cpu_to_le16 (1); OK (2);

1251

*(__u16 *) data_buf = cpu_to_le16 (1); OK (2);

1248

case RH_GET_STATUS | RH_INTERFACE:

1252

case RH_GET_STATUS | RH_INTERFACE:

1249

*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);

1253

*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);

1250

case RH_GET_STATUS | RH_ENDPOINT:

1254

case RH_GET_STATUS | RH_ENDPOINT:

1251

*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);

1255

*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);

1252

case RH_GET_STATUS | RH_CLASS:

1256

case RH_GET_STATUS | RH_CLASS:

1253

*(__u32 *) data_buf = cpu_to_le32 (

1257

*(__u32 *) data_buf = cpu_to_le32 (

1254

RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));

1258

RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));

1255

OK (4);

1259

OK (4);

1256

case RH_GET_STATUS | RH_OTHER | RH_CLASS:

1260

case RH_GET_STATUS | RH_OTHER | RH_CLASS:

1257

*(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);

1261

*(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);

1258

1262

1259

case RH_CLEAR_FEATURE | RH_ENDPOINT:

1263

case RH_CLEAR_FEATURE | RH_ENDPOINT:

1260

switch (wValue) {

1264

switch (wValue) {

1261

case (RH_ENDPOINT_STALL): OK (0);

1265

case (RH_ENDPOINT_STALL): OK (0);

1262

}

1266

}

1263

break;

1267

break;

1264

1268

1265

case RH_CLEAR_FEATURE | RH_CLASS:

1269

case RH_CLEAR_FEATURE | RH_CLASS:

1266

switch (wValue) {

1270

switch (wValue) {

1267

case RH_C_HUB_LOCAL_POWER:

1271

case RH_C_HUB_LOCAL_POWER:

1268

OK(0);

1272

OK(0);

1269

case (RH_C_HUB_OVER_CURRENT):

1273

case (RH_C_HUB_OVER_CURRENT):

1270

WR_RH_STAT(RH_HS_OCIC); OK (0);

1274

WR_RH_STAT(RH_HS_OCIC); OK (0);

1271

}

1275

}

1272

break;

1276

break;

1273

1277

1274

case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:

1278

case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:

1275

switch (wValue) {

1279

switch (wValue) {

1276

case (RH_PORT_ENABLE):

1280

case (RH_PORT_ENABLE):

1277

WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);

1281

WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);

1278

case (RH_PORT_SUSPEND):

1282

case (RH_PORT_SUSPEND):

1279

WR_RH_PORTSTAT (RH_PS_POCI); OK (0);

1283

WR_RH_PORTSTAT (RH_PS_POCI); OK (0);

1280

case (RH_PORT_POWER):

1284

case (RH_PORT_POWER):

1281

WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);

1285

WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);

1282

case (RH_C_PORT_CONNECTION):

1286

case (RH_C_PORT_CONNECTION):

1283

WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);

1287

WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);

1284

case (RH_C_PORT_ENABLE):

1288

case (RH_C_PORT_ENABLE):

1285

WR_RH_PORTSTAT (RH_PS_PESC); OK (0);

1289

WR_RH_PORTSTAT (RH_PS_PESC); OK (0);

1286

case (RH_C_PORT_SUSPEND):

1290

case (RH_C_PORT_SUSPEND):

1287

WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);

1291

WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);

1288

case (RH_C_PORT_OVER_CURRENT):

1292

case (RH_C_PORT_OVER_CURRENT):

1289

WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);

1293

WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);

1290

case (RH_C_PORT_RESET):

1294

case (RH_C_PORT_RESET):

1291

WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);

1295

WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);

1292

}

1296

}

1293

break;

1297

break;

1294

1298

1295

case RH_SET_FEATURE | RH_OTHER | RH_CLASS:

1299

case RH_SET_FEATURE | RH_OTHER | RH_CLASS:

1296

switch (wValue) {

1300

switch (wValue) {

1297

case (RH_PORT_SUSPEND):

1301

case (RH_PORT_SUSPEND):

1298

WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);

1302

WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);

1299

case (RH_PORT_RESET): /* BUG IN HUP CODE *********/

1303

case (RH_PORT_RESET): /* BUG IN HUP CODE *********/

1300

if (RD_RH_PORTSTAT & RH_PS_CCS)

1304

if (RD_RH_PORTSTAT & RH_PS_CCS)

1301

WR_RH_PORTSTAT (RH_PS_PRS);

1305

WR_RH_PORTSTAT (RH_PS_PRS);

1302

OK (0);

1306

OK (0);

1303

case (RH_PORT_POWER):

1307

case (RH_PORT_POWER):

1304

WR_RH_PORTSTAT (RH_PS_PPS );

1308

WR_RH_PORTSTAT (RH_PS_PPS );

1305

wait_ms(100);

1309

wait_ms(100);

1306

OK (0);

1310

OK (0);

1307

case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/

1311

case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/

1308

if (RD_RH_PORTSTAT & RH_PS_CCS)

1312

if (RD_RH_PORTSTAT & RH_PS_CCS)

1309

WR_RH_PORTSTAT (RH_PS_PES );

1313

WR_RH_PORTSTAT (RH_PS_PES );

1310

OK (0);

1314

OK (0);

1311

}

1315

}

1312

break;

1316

break;

1313

1317

1314

case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);

1318

case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);

1315

1319

1316

case RH_GET_DESCRIPTOR:

1320

case RH_GET_DESCRIPTOR:

1317

switch ((wValue & 0xff00) >> 8) {

1321

switch ((wValue & 0xff00) >> 8) {

1318

case (0x01): /* device descriptor */

1322

case (0x01): /* device descriptor */

1319

len = min_t(unsigned int,

1323

len = min_t(unsigned int,

1320

leni,

1324

leni,

1321

min_t(unsigned int,

1325

min_t(unsigned int,

1322

sizeof (root_hub_dev_des),

1326

sizeof (root_hub_dev_des),

1323

wLength));

1327

wLength));

1324

data_buf = root_hub_dev_des; OK(len);

1328

data_buf = root_hub_dev_des; OK(len);

1325

case (0x02): /* configuration descriptor */

1329

case (0x02): /* configuration descriptor */

1326

len = min_t(unsigned int,

1330

len = min_t(unsigned int,

1327

leni,

1331

leni,

1328

min_t(unsigned int,

1332

min_t(unsigned int,

1329

sizeof (root_hub_config_des),

1333

sizeof (root_hub_config_des),

1330

wLength));

1334

wLength));

1331

data_buf = root_hub_config_des; OK(len);

1335

data_buf = root_hub_config_des; OK(len);

1332

case (0x03): /* string descriptors */

1336

case (0x03): /* string descriptors */

1333

if(wValue==0x0300) {

1337

if(wValue==0x0300) {

1334

len = min_t(unsigned int,

1338

len = min_t(unsigned int,

1335

leni,

1339

leni,

1336

min_t(unsigned int,

1340

min_t(unsigned int,

1337

sizeof (root_hub_str_index0),

1341

sizeof (root_hub_str_index0),

1338

wLength));

1342

wLength));

1339

data_buf = root_hub_str_index0;

1343

data_buf = root_hub_str_index0;

1340

OK(len);

1344

OK(len);

1341

}

1345

}

1342

if(wValue==0x0301) {

1346

if(wValue==0x0301) {

1343

len = min_t(unsigned int,

1347

len = min_t(unsigned int,

1344

leni,

1348

leni,

1345

min_t(unsigned int,

1349

min_t(unsigned int,

1346

sizeof (root_hub_str_index1),

1350

sizeof (root_hub_str_index1),

1347

wLength));

1351

wLength));

1348

data_buf = root_hub_str_index1;

1352

data_buf = root_hub_str_index1;

1349

OK(len);

1353

OK(len);

1350

}

1354

}

1351

default:

1355

default:

1352

stat = USB_ST_STALLED;

1356

stat = USB_ST_STALLED;

1353

}

1357

}

1354

break;

1358

break;

1355

1359

1356

case RH_GET_DESCRIPTOR | RH_CLASS:

1360

case RH_GET_DESCRIPTOR | RH_CLASS:

1357

{

1361

{

1358

__u32 temp = roothub_a (&gohci);

1362

__u32 temp = roothub_a (&gohci);

1359

1363

1360

data_buf [0] = 9; /* min length; */

1364

data_buf [0] = 9; /* min length; */

1361

data_buf [1] = 0x29;

1365

data_buf [1] = 0x29;

1362

data_buf [2] = temp & RH_A_NDP;

1366

data_buf [2] = temp & RH_A_NDP;

1363

#ifdef CONFIG_AT91C_PQFP_UHPBUG

1367

#ifdef CONFIG_AT91C_PQFP_UHPBUG

1364

data_buf [2] = (data_buf [2] == 2) ? 1:0;

1368

data_buf [2] = (data_buf [2] == 2) ? 1:0;

1365

#endif

1369

#endif

1366

data_buf [3] = 0;

1370

data_buf [3] = 0;

1367

if (temp & RH_A_PSM) /* per-port power switching? */

1371

if (temp & RH_A_PSM) /* per-port power switching? */

1368

data_buf [3] |= 0x1;

1372

data_buf [3] |= 0x1;

1369

if (temp & RH_A_NOCP) /* no overcurrent reporting? */

1373

if (temp & RH_A_NOCP) /* no overcurrent reporting? */

1370

data_buf [3] |= 0x10;

1374

data_buf [3] |= 0x10;

1371

else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */

1375

else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */

1372

data_buf [3] |= 0x8;

1376

data_buf [3] |= 0x8;

1373

1377

1374

/* corresponds to data_buf[4-7] */

1378

/* corresponds to data_buf[4-7] */

1375

datab [1] = 0;

1379

datab [1] = 0;

1376

data_buf [5] = (temp & RH_A_POTPGT) >> 24;

1380

data_buf [5] = (temp & RH_A_POTPGT) >> 24;

1377

temp = roothub_b (&gohci);

1381

temp = roothub_b (&gohci);

1378

data_buf [7] = temp & RH_B_DR;

1382

data_buf [7] = temp & RH_B_DR;

1379

if (data_buf [2] < 7) {

1383

if (data_buf [2] < 7) {

1380

data_buf [8] = 0xff;

1384

data_buf [8] = 0xff;

1381

} else {

1385

} else {

1382

data_buf [0] += 2;

1386

data_buf [0] += 2;

1383

data_buf [8] = (temp & RH_B_DR) >> 8;

1387

data_buf [8] = (temp & RH_B_DR) >> 8;

1384

data_buf [10] = data_buf [9] = 0xff;

1388

data_buf [10] = data_buf [9] = 0xff;

1385

}

1389

}

1386

1390

1387

len = min_t(unsigned int, leni,

1391

len = min_t(unsigned int, leni,

1388

min_t(unsigned int, data_buf [0], wLength));

1392

min_t(unsigned int, data_buf [0], wLength));

1389

OK (len);

1393

OK (len);

1390

}

1394

}

1391

1395

1392

case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);

1396

case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);

1393

1397

1394

case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);

1398

case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);

1395

1399

1396

default:

1400

default:

1397

dbg ("unsupported root hub command");

1401

dbg ("unsupported root hub command");

1398

stat = USB_ST_STALLED;

1402

stat = USB_ST_STALLED;

1399

}

1403

}

1400

1404

1401

#ifdef DEBUG

1405

#ifdef DEBUG

1402

ohci_dump_roothub (&gohci, 1);

1406

ohci_dump_roothub (&gohci, 1);

1403

#else

1407

#else

1404

wait_ms(1);

1408

wait_ms(1);

1405

#endif

1409

#endif

1406

1410

1407

len = min_t(int, len, leni);

1411

len = min_t(int, len, leni);

1408

if (data != data_buf)

1412

if (data != data_buf)

1409

memcpy (data, data_buf, len);

1413

memcpy (data, data_buf, len);

1410

dev->act_len = len;

1414

dev->act_len = len;

1411

dev->status = stat;

1415

dev->status = stat;

1412

1416

1413

#ifdef DEBUG

1417

#ifdef DEBUG

1414

pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);

1418

pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);

1415

#else

1419

#else

1416

wait_ms(1);

1420

wait_ms(1);

1417

#endif

1421

#endif

1418

1422

1419

return stat;

1423

return stat;

1420

}

1424

}

1421

1425

1422

/*-------------------------------------------------------------------------*/

1426

/*-------------------------------------------------------------------------*/

1423

1427

1424

/* common code for handling submit messages - used for all but root hub */

1428

/* common code for handling submit messages - used for all but root hub */

1425

/* accesses. */

1429

/* accesses. */

1426

int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1430

int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1427

int transfer_len, struct devrequest *setup, int interval)

1431

int transfer_len, struct devrequest *setup, int interval)

1428

{

1432

{

1429

int stat = 0;

1433

int stat = 0;

1430

int maxsize = usb_maxpacket(dev, pipe);

1434

int maxsize = usb_maxpacket(dev, pipe);

1431

int timeout;

1435

int timeout;

1432

urb_priv_t *urb;

1436

urb_priv_t *urb;

1433

1437

1434

urb = malloc(sizeof(urb_priv_t));

1438

urb = malloc(sizeof(urb_priv_t));

1435

memset(urb, 0, sizeof(urb_priv_t));

1439

memset(urb, 0, sizeof(urb_priv_t));

1436

1440

1437

urb->dev = dev;

1441

urb->dev = dev;

1438

urb->pipe = pipe;

1442

urb->pipe = pipe;

1439

urb->transfer_buffer = buffer;

1443

urb->transfer_buffer = buffer;

1440

urb->transfer_buffer_length = transfer_len;

1444

urb->transfer_buffer_length = transfer_len;

1441

urb->interval = interval;

1445

urb->interval = interval;

1442

1446

1443

/* device pulled? Shortcut the action. */

1447

/* device pulled? Shortcut the action. */

1444

if (devgone == dev) {

1448

if (devgone == dev) {

1445

dev->status = USB_ST_CRC_ERR;

1449

dev->status = USB_ST_CRC_ERR;

1446

return 0;

1450

return 0;

1447

}

1451

}

1448

1452

1449

#ifdef DEBUG

1453

#ifdef DEBUG

1450

urb->actual_length = 0;

1454

urb->actual_length = 0;

1451

pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));

1455

pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));

1452

#else

1456

#else

1453

wait_ms(1);

1457

wait_ms(1);

1454

#endif

1458

#endif

1455

if (!maxsize) {

1459

if (!maxsize) {

1456

err("submit_common_message: pipesize for pipe %lx is zero",

1460

err("submit_common_message: pipesize for pipe %lx is zero",

1457

pipe);

1461

pipe);

1458

return -1;

1462

return -1;

1459

}

1463

}

1460

1464

1461

if (sohci_submit_job(urb, setup) < 0) {

1465

if (sohci_submit_job(urb, setup) < 0) {

1462

err("sohci_submit_job failed");

1466

err("sohci_submit_job failed");

1463

return -1;

1467

return -1;

1464

}

1468

}

1465

1469

1466

#if 0

1470

#if 0

1467

wait_ms(10);

1471

wait_ms(10);

1468

/* ohci_dump_status(&gohci); */

1472

/* ohci_dump_status(&gohci); */

1469

#endif

1473

#endif

1470

1474

1471

/* allow more time for a BULK device to react - some are slow */

1475

/* allow more time for a BULK device to react - some are slow */

1472

#define BULK_TO 5000 /* timeout in milliseconds */

1476

#define BULK_TO 5000 /* timeout in milliseconds */

1473

if (usb_pipetype (pipe) == PIPE_BULK)

1477

if (usb_pipetype (pipe) == PIPE_BULK)

1474

timeout = BULK_TO;

1478

timeout = BULK_TO;

1475

else

1479

else

1476

timeout = 100;

1480

timeout = 100;

1477

1481

1478

/* wait for it to complete */

1482

/* wait for it to complete */

1479

for (;;) {

1483

for (;;) {

1480

/* check whether the controller is done */

1484

/* check whether the controller is done */

1481

stat = hc_interrupt();

1485

stat = hc_interrupt();

1482

if (stat < 0) {

1486

if (stat < 0) {

1483

stat = USB_ST_CRC_ERR;

1487

stat = USB_ST_CRC_ERR;

1484

break;

1488

break;

1485

}

1489

}

1486

1490

1487

/* NOTE: since we are not interrupt driven in U-Boot and always

1491

/* NOTE: since we are not interrupt driven in U-Boot and always

1488

* handle only one URB at a time, we cannot assume the

1492

* handle only one URB at a time, we cannot assume the

1489

* transaction finished on the first successful return from

1493

* transaction finished on the first successful return from

1490

* hc_interrupt().. unless the flag for current URB is set,

1494

* hc_interrupt().. unless the flag for current URB is set,

1491

* meaning that all TD's to/from device got actually

1495

* meaning that all TD's to/from device got actually

1492

* transferred and processed. If the current URB is not

1496

* transferred and processed. If the current URB is not

1493

* finished we need to re-iterate this loop so as

1497

* finished we need to re-iterate this loop so as

1494

* hc_interrupt() gets called again as there needs to be some

1498

* hc_interrupt() gets called again as there needs to be some

1495

* more TD's to process still */

1499

* more TD's to process still */

1496

if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {

1500

if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {

1497

/* 0xff is returned for an SF-interrupt */

1501

/* 0xff is returned for an SF-interrupt */

1498

break;

1502

break;

1499

}

1503

}

1500

1504

1501

if (--timeout) {

1505

if (--timeout) {

1502

wait_ms(1);

1506

wait_ms(1);

1503

if (!urb->finished)

1507

if (!urb->finished)

1504

dbg("\%");

1508

dbg("\%");

1505

1509

1506

} else {

1510

} else {

1507

err("CTL:TIMEOUT ");

1511

err("CTL:TIMEOUT ");

1508

dbg("submit_common_msg: TO status %x\n", stat);

1512

dbg("submit_common_msg: TO status %x\n", stat);

1509

urb->finished = 1;

1513

urb->finished = 1;

1510

stat = USB_ST_CRC_ERR;

1514

stat = USB_ST_CRC_ERR;

1511

break;

1515

break;

1512

}

1516

}

1513

}

1517

}

1514

1518

1515

dev->status = stat;

1519

dev->status = stat;

1516

dev->act_len = transfer_len;

1520

dev->act_len = transfer_len;

1517

1521

1518

#ifdef DEBUG

1522

#ifdef DEBUG

1519

pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));

1523

pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));

1520

#else

1524

#else

1521

wait_ms(1);

1525

wait_ms(1);

1522

#endif

1526

#endif

1523

1527

1524

/* free TDs in urb_priv */

1528

/* free TDs in urb_priv */

1525

if (usb_pipetype (pipe) != PIPE_INTERRUPT)

1529

if (usb_pipetype (pipe) != PIPE_INTERRUPT)

1526

urb_free_priv (urb);

1530

urb_free_priv (urb);

1527

return 0;

1531

return 0;

1528

}

1532

}

1529

1533

1530

/* submit routines called from usb.c */

1534

/* submit routines called from usb.c */

1531

int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1535

int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1532

int transfer_len)

1536

int transfer_len)

1533

{

1537

{

1534

info("submit_bulk_msg");

1538

info("submit_bulk_msg");

1535

return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);

1539

return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);

1536

}

1540

}

1537

1541

1538

int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1542

int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1539

int transfer_len, struct devrequest *setup)

1543

int transfer_len, struct devrequest *setup)

1540

{

1544

{

1541

int maxsize = usb_maxpacket(dev, pipe);

1545

int maxsize = usb_maxpacket(dev, pipe);

1542

1546

1543

info("submit_control_msg");

1547

info("submit_control_msg");

1544

#ifdef DEBUG

1548

#ifdef DEBUG

1545

pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));

1549

pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));

1546

#else

1550

#else

1547

wait_ms(1);

1551

wait_ms(1);

1548

#endif

1552

#endif

1549

if (!maxsize) {

1553

if (!maxsize) {

1550

err("submit_control_message: pipesize for pipe %lx is zero",

1554

err("submit_control_message: pipesize for pipe %lx is zero",

1551

pipe);

1555

pipe);

1552

return -1;

1556

return -1;

1553

}

1557

}

1554

if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {

1558

if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {

1555

gohci.rh.dev = dev;

1559

gohci.rh.dev = dev;

1556

/* root hub - redirect */

1560

/* root hub - redirect */

1557

return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,

1561

return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,

1558

setup);

1562

setup);

1559

}

1563

}

1560

1564

1561

return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);

1565

return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);

1562

}

1566

}

1563

1567

1564

int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1568

int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

1565

int transfer_len, int interval)

1569

int transfer_len, int interval)

1566

{

1570

{

1567

info("submit_int_msg");

1571

info("submit_int_msg");

1568

return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,

1572

return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,

1569

interval);

1573

interval);

1570

}

1574

}

1571

1575

1572

/*-------------------------------------------------------------------------*

1576

/*-------------------------------------------------------------------------*

1573

* HC functions

1577

* HC functions

1574

*-------------------------------------------------------------------------*/

1578

*-------------------------------------------------------------------------*/

1575

1579

1576

/* reset the HC and BUS */

1580

/* reset the HC and BUS */

1577

1581

1578

static int hc_reset (ohci_t *ohci)

1582

static int hc_reset (ohci_t *ohci)

1579

{

1583

{

1580

int timeout = 30;

1584

int timeout = 30;

1581

int smm_timeout = 50; /* 0,5 sec */

1585

int smm_timeout = 50; /* 0,5 sec */

1582

1586

1583

dbg("%s\n", __FUNCTION__);

1587

dbg("%s\n", __FUNCTION__);

1584

1588

1585

if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */

1589

if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */

1586

writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */

1590

writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */

1587

info("USB HC TakeOver from SMM");

1591

info("USB HC TakeOver from SMM");

1588

while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {

1592

while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {

1589

wait_ms (10);

1593

wait_ms (10);

1590

if (--smm_timeout == 0) {

1594

if (--smm_timeout == 0) {

1591

err("USB HC TakeOver failed!");

1595

err("USB HC TakeOver failed!");

1592

return -1;

1596

return -1;

1593

}

1597

}

1594

}

1598

}

1595

}

1599

}

1596

1600

1597

/* Disable HC interrupts */

1601

/* Disable HC interrupts */

1598

writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);

1602

writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);

1599

1603

1600

dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",

1604

dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",

1601

ohci->slot_name,

1605

ohci->slot_name,

1602

readl(&ohci->regs->control));

1606

readl(&ohci->regs->control));

1603

1607

1604

/* Reset USB (needed by some controllers) */

1608

/* Reset USB (needed by some controllers) */

1605

ohci->hc_control = 0;

1609

ohci->hc_control = 0;

1606

writel (ohci->hc_control, &ohci->regs->control);

1610

writel (ohci->hc_control, &ohci->regs->control);

1607

1611

1608

/* HC Reset requires max 10 us delay */

1612

/* HC Reset requires max 10 us delay */

1609

writel (OHCI_HCR, &ohci->regs->cmdstatus);

1613

writel (OHCI_HCR, &ohci->regs->cmdstatus);

1610

while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {

1614

while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {

1611

if (--timeout == 0) {

1615

if (--timeout == 0) {

1612

err("USB HC reset timed out!");

1616

err("USB HC reset timed out!");

1613

return -1;

1617

return -1;

1614

}

1618

}

1615

udelay (1);

1619

udelay (1);

1616

}

1620

}

1617

return 0;

1621

return 0;

1618

}

1622

}

1619

1623

1620

/*-------------------------------------------------------------------------*/

1624

/*-------------------------------------------------------------------------*/

1621

1625

1622

/* Start an OHCI controller, set the BUS operational

1626

/* Start an OHCI controller, set the BUS operational

1623

* enable interrupts

1627

* enable interrupts

1624

* connect the virtual root hub */

1628

* connect the virtual root hub */

1625

1629

1626

static int hc_start (ohci_t * ohci)

1630

static int hc_start (ohci_t * ohci)

1627

{

1631

{

1628

__u32 mask;

1632

__u32 mask;

1629

unsigned int fminterval;

1633

unsigned int fminterval;

1630

1634

1631

ohci->disabled = 1;

1635

ohci->disabled = 1;

1632

1636

1633

/* Tell the controller where the control and bulk lists are

1637

/* Tell the controller where the control and bulk lists are

1634

* The lists are empty now. */

1638

* The lists are empty now. */

1635

1639

1636

writel (0, &ohci->regs->ed_controlhead);

1640

writel (0, &ohci->regs->ed_controlhead);

1637

writel (0, &ohci->regs->ed_bulkhead);

1641

writel (0, &ohci->regs->ed_bulkhead);

1638

1642

1639

writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */

1643

writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */

1640

1644

1641

fminterval = 0x2edf;

1645

fminterval = 0x2edf;

1642

writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);

1646

writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);

1643

fminterval |= ((((fminterval - 210) * 6) / 7) << 16);

1647

fminterval |= ((((fminterval - 210) * 6) / 7) << 16);

1644

writel (fminterval, &ohci->regs->fminterval);

1648

writel (fminterval, &ohci->regs->fminterval);

1645

writel (0x628, &ohci->regs->lsthresh);

1649

writel (0x628, &ohci->regs->lsthresh);

1646

1650

1647

/* start controller operations */

1651

/* start controller operations */

1648

ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;

1652

ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;

1649

ohci->disabled = 0;

1653

ohci->disabled = 0;

1650

writel (ohci->hc_control, &ohci->regs->control);

1654

writel (ohci->hc_control, &ohci->regs->control);

1651

1655

1652

/* disable all interrupts */

1656

/* disable all interrupts */

1653

mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |

1657

mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |

1654

OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |

1658

OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |

1655

OHCI_INTR_OC | OHCI_INTR_MIE);

1659

OHCI_INTR_OC | OHCI_INTR_MIE);

1656

writel (mask, &ohci->regs->intrdisable);

1660

writel (mask, &ohci->regs->intrdisable);

1657

/* clear all interrupts */

1661

/* clear all interrupts */

1658

mask &= ~OHCI_INTR_MIE;

1662

mask &= ~OHCI_INTR_MIE;

1659

writel (mask, &ohci->regs->intrstatus);

1663

writel (mask, &ohci->regs->intrstatus);

1660

/* Choose the interrupts we care about now - but w/o MIE */

1664

/* Choose the interrupts we care about now - but w/o MIE */

1661

mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;

1665

mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;

1662

writel (mask, &ohci->regs->intrenable);

1666

writel (mask, &ohci->regs->intrenable);

1663

1667

1664

#ifdef OHCI_USE_NPS

1668

#ifdef OHCI_USE_NPS

1665

/* required for AMD-756 and some Mac platforms */

1669

/* required for AMD-756 and some Mac platforms */

1666

writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,

1670

writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,

1667

&ohci->regs->roothub.a);

1671

&ohci->regs->roothub.a);

1668

writel (RH_HS_LPSC, &ohci->regs->roothub.status);

1672

writel (RH_HS_LPSC, &ohci->regs->roothub.status);

1669

#endif /* OHCI_USE_NPS */

1673

#endif /* OHCI_USE_NPS */

1670

1674

1671

#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})

1675

#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})

1672

/* POTPGT delay is bits 24-31, in 2 ms units. */

1676

/* POTPGT delay is bits 24-31, in 2 ms units. */

1673

mdelay ((roothub_a (ohci) >> 23) & 0x1fe);

1677

mdelay ((roothub_a (ohci) >> 23) & 0x1fe);

1674

1678

1675

/* connect the virtual root hub */

1679

/* connect the virtual root hub */

1676

ohci->rh.devnum = 0;

1680

ohci->rh.devnum = 0;

1677

1681

1678

return 0;

1682

return 0;

1679

}

1683

}

1680

1684

1681

/*-------------------------------------------------------------------------*/

1685

/*-------------------------------------------------------------------------*/

1682

1686

1683

/* Poll USB interrupt. */

1687

/* Poll USB interrupt. */

1684

void usb_event_poll(void)

1688

void usb_event_poll(void)

1685

{

1689

{

1686

hc_interrupt();

1690

hc_interrupt();

1687

}

1691

}

1688

1692

1689

/* an interrupt happens */

1693

/* an interrupt happens */

1690

1694

1691

static int hc_interrupt (void)

1695

static int hc_interrupt (void)

1692

{

1696

{

1693

ohci_t *ohci = &gohci;

1697

ohci_t *ohci = &gohci;

1694

struct ohci_regs *regs = ohci->regs;

1698

struct ohci_regs *regs = ohci->regs;

1695

int ints;

1699

int ints;

1696

int stat = -1;

1700

int stat = -1;

1697

1701

1698

if ((ohci->hcca->done_head != 0) &&

1702

if ((ohci->hcca->done_head != 0) &&

1699

!(m32_swap (ohci->hcca->done_head) & 0x01)) {

1703

!(m32_swap (ohci->hcca->done_head) & 0x01)) {

1700

ints = OHCI_INTR_WDH;

1704

ints = OHCI_INTR_WDH;

1701

} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {

1705

} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {

1702

ohci->disabled++;

1706

ohci->disabled++;

1703

err ("%s device removed!", ohci->slot_name);

1707

err ("%s device removed!", ohci->slot_name);

1704

return -1;

1708

return -1;

1705

} else if ((ints &= readl (&regs->intrenable)) == 0) {

1709

} else if ((ints &= readl (&regs->intrenable)) == 0) {

1706

dbg("hc_interrupt: returning..\n");

1710

dbg("hc_interrupt: returning..\n");

1707

return 0xff;

1711

return 0xff;

1708

}

1712

}

1709

1713

1710

/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */

1714

/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */

1711

1715

1712

if (ints & OHCI_INTR_RHSC) {

1716

if (ints & OHCI_INTR_RHSC) {

1713

got_rhsc = 1;

1717

got_rhsc = 1;

1714

stat = 0xff;

1718

stat = 0xff;

1715

}

1719

}

1716

1720

1717

if (ints & OHCI_INTR_UE) {

1721

if (ints & OHCI_INTR_UE) {

1718

ohci->disabled++;

1722

ohci->disabled++;

1719

err ("OHCI Unrecoverable Error, controller usb-%s disabled",

1723

err ("OHCI Unrecoverable Error, controller usb-%s disabled",

1720

ohci->slot_name);

1724

ohci->slot_name);

1721

/* e.g. due to PCI Master/Target Abort */

1725

/* e.g. due to PCI Master/Target Abort */

1722

1726

1723

#ifdef DEBUG

1727

#ifdef DEBUG

1724

ohci_dump (ohci, 1);

1728

ohci_dump (ohci, 1);

1725

#else

1729

#else

1726

wait_ms(1);

1730

wait_ms(1);

1727

#endif

1731

#endif

1728

/* FIXME: be optimistic, hope that bug won't repeat often. */

1732

/* FIXME: be optimistic, hope that bug won't repeat often. */

1729

/* Make some non-interrupt context restart the controller. */

1733

/* Make some non-interrupt context restart the controller. */

1730

/* Count and limit the retries though; either hardware or */

1734

/* Count and limit the retries though; either hardware or */

1731

/* software errors can go forever... */

1735

/* software errors can go forever... */

1732

hc_reset (ohci);

1736

hc_reset (ohci);

1733

return -1;

1737

return -1;

1734

}

1738

}

1735

1739

1736

if (ints & OHCI_INTR_WDH) {

1740

if (ints & OHCI_INTR_WDH) {

1737

wait_ms(1);

1741

wait_ms(1);

1738

writel (OHCI_INTR_WDH, &regs->intrdisable);

1742

writel (OHCI_INTR_WDH, &regs->intrdisable);

1739

(void)readl (&regs->intrdisable); /* flush */

1743

(void)readl (&regs->intrdisable); /* flush */

1740

stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));

1744

stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));

1741

writel (OHCI_INTR_WDH, &regs->intrenable);

1745

writel (OHCI_INTR_WDH, &regs->intrenable);

1742

(void)readl (&regs->intrdisable); /* flush */

1746

(void)readl (&regs->intrdisable); /* flush */

1743

}

1747

}

1744

1748

1745

if (ints & OHCI_INTR_SO) {

1749

if (ints & OHCI_INTR_SO) {

1746

dbg("USB Schedule overrun\n");

1750

dbg("USB Schedule overrun\n");

1747

writel (OHCI_INTR_SO, &regs->intrenable);

1751

writel (OHCI_INTR_SO, &regs->intrenable);

1748

stat = -1;

1752

stat = -1;

1749

}

1753

}

1750

1754

1751

/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */

1755

/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */

1752

if (ints & OHCI_INTR_SF) {

1756

if (ints & OHCI_INTR_SF) {

1753

unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;

1757

unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;

1754

wait_ms(1);

1758

wait_ms(1);

1755

writel (OHCI_INTR_SF, &regs->intrdisable);

1759

writel (OHCI_INTR_SF, &regs->intrdisable);

1756

if (ohci->ed_rm_list[frame] != NULL)

1760

if (ohci->ed_rm_list[frame] != NULL)

1757

writel (OHCI_INTR_SF, &regs->intrenable);

1761

writel (OHCI_INTR_SF, &regs->intrenable);

1758

stat = 0xff;

1762

stat = 0xff;

1759

}

1763

}

1760

1764

1761

writel (ints, &regs->intrstatus);

1765

writel (ints, &regs->intrstatus);

1762

return stat;

1766

return stat;

1763

}

1767

}

1764

1768

1765

/*-------------------------------------------------------------------------*/

1769

/*-------------------------------------------------------------------------*/

1766

1770

1767

/*-------------------------------------------------------------------------*/

1771

/*-------------------------------------------------------------------------*/

1768

1772

1769

/* De-allocate all resources.. */

1773

/* De-allocate all resources.. */

1770

1774

1771

static void hc_release_ohci (ohci_t *ohci)

1775

static void hc_release_ohci (ohci_t *ohci)

1772

{

1776

{

1773

dbg ("USB HC release ohci usb-%s", ohci->slot_name);

1777

dbg ("USB HC release ohci usb-%s", ohci->slot_name);

1774

1778

1775

if (!ohci->disabled)

1779

if (!ohci->disabled)

1776

hc_reset (ohci);

1780

hc_reset (ohci);

1777

}

1781

}

1778

1782

1779

/*-------------------------------------------------------------------------*/

1783

/*-------------------------------------------------------------------------*/

1780

1784

1781

/*

1785

/*

1782

* low level initalisation routine, called from usb.c

1786

* low level initalisation routine, called from usb.c

1783

*/

1787

*/

1784

static char ohci_inited = 0;

1788

static char ohci_inited = 0;

1785

1789

1786

int usb_lowlevel_init(void)

1790

int usb_lowlevel_init(void)

1787

{

1791

{

1788

#ifdef CONFIG_PCI_OHCI

1792

#ifdef CONFIG_PCI_OHCI

1789

pci_dev_t pdev;

1793

pci_dev_t pdev;

1790

#endif

1794

#endif

1791

1795

1792

#ifdef CFG_USB_OHCI_CPU_INIT

1796

#ifdef CFG_USB_OHCI_CPU_INIT

1793

/* cpu dependant init */

1797

/* cpu dependant init */

1794

if(usb_cpu_init())

1798

if(usb_cpu_init())

1795

return -1;

1799

return -1;

1796

#endif

1800

#endif

1797

1801

1798

#ifdef CFG_USB_OHCI_BOARD_INIT

1802

#ifdef CFG_USB_OHCI_BOARD_INIT

1799

/* board dependant init */

1803

/* board dependant init */

1800

if(usb_board_init())

1804

if(usb_board_init())

1801

return -1;

1805

return -1;

1802

#endif

1806

#endif

1803

memset (&gohci, 0, sizeof (ohci_t));

1807

memset (&gohci, 0, sizeof (ohci_t));

1804

1808

1805

/* align the storage */

1809

/* align the storage */

1806

if ((__u32)&ghcca[0] & 0xff) {

1810

if ((__u32)&ghcca[0] & 0xff) {

1807

err("HCCA not aligned!!");

1811

err("HCCA not aligned!!");

1808

return -1;

1812

return -1;

1809

}

1813

}

1810

phcca = &ghcca[0];

1814

phcca = &ghcca[0];

1811

info("aligned ghcca %p", phcca);

1815

info("aligned ghcca %p", phcca);

1812

memset(&ohci_dev, 0, sizeof(struct ohci_device));

1816

memset(&ohci_dev, 0, sizeof(struct ohci_device));

1813

if ((__u32)&ohci_dev.ed[0] & 0x7) {

1817

if ((__u32)&ohci_dev.ed[0] & 0x7) {

1814

err("EDs not aligned!!");

1818

err("EDs not aligned!!");

1815

return -1;

1819

return -1;

1816

}

1820

}

1817

memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));

1821

memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));

1818

if ((__u32)gtd & 0x7) {

1822

if ((__u32)gtd & 0x7) {

1819

err("TDs not aligned!!");

1823

err("TDs not aligned!!");

1820

return -1;

1824

return -1;

1821

}

1825

}

1822

ptd = gtd;

1826

ptd = gtd;

1823

gohci.hcca = phcca;

1827

gohci.hcca = phcca;

1824

memset (phcca, 0, sizeof (struct ohci_hcca));

1828

memset (phcca, 0, sizeof (struct ohci_hcca));

1825

1829

1826

gohci.disabled = 1;

1830

gohci.disabled = 1;

1827

gohci.sleeping = 0;

1831

gohci.sleeping = 0;

1828

gohci.irq = -1;

1832

gohci.irq = -1;

1829

#ifdef CONFIG_PCI_OHCI

1833

#ifdef CONFIG_PCI_OHCI

1830

pdev = pci_find_devices(ohci_pci_ids, 0);

1834

pdev = pci_find_devices(ohci_pci_ids, 0);

1831

1835

1832

if (pdev != -1) {

1836

if (pdev != -1) {

1833

u16 vid, did;

1837

u16 vid, did;

1834

u32 base;

1838

u32 base;

1835

pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);

1839

pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);

1836

pci_read_config_word(pdev, PCI_DEVICE_ID, &did);

1840

pci_read_config_word(pdev, PCI_DEVICE_ID, &did);

1837

printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",

1841

printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",

1838

vid, did, (pdev >> 16) & 0xff,

1842

vid, did, (pdev >> 16) & 0xff,

1839

(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);

1843

(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);

1840

pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);

1844

pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);

1841

printf("OHCI regs address 0x%08x\n", base);

1845

printf("OHCI regs address 0x%08x\n", base);

1842

gohci.regs = (struct ohci_regs *)base;

1846

gohci.regs = (struct ohci_regs *)base;

1843

} else

1847

} else

1844

return -1;

1848

return -1;

1845

#else

1849

#else

1846

gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;

1850

gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;

1847

#endif

1851

#endif

1848

1852

1849

gohci.flags = 0;

1853

gohci.flags = 0;

1850

gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;

1854

gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;

1851

1855

1852

if (hc_reset (&gohci) < 0) {

1856

if (hc_reset (&gohci) < 0) {

1853

hc_release_ohci (&gohci);

1857

hc_release_ohci (&gohci);

1854

err ("can't reset usb-%s", gohci.slot_name);

1858

err ("can't reset usb-%s", gohci.slot_name);

1855

#ifdef CFG_USB_OHCI_BOARD_INIT

1859

#ifdef CFG_USB_OHCI_BOARD_INIT

1856

/* board dependant cleanup */

1860

/* board dependant cleanup */

1857

usb_board_init_fail();

1861

usb_board_init_fail();

1858

#endif

1862

#endif

1859

1863

1860

#ifdef CFG_USB_OHCI_CPU_INIT

1864

#ifdef CFG_USB_OHCI_CPU_INIT

1861

/* cpu dependant cleanup */

1865

/* cpu dependant cleanup */

1862

usb_cpu_init_fail();

1866

usb_cpu_init_fail();

1863

#endif

1867

#endif

1864

return -1;

1868

return -1;

1865

}

1869

}

1866

1870

1867

/* FIXME this is a second HC reset; why?? */

1871

/* FIXME this is a second HC reset; why?? */

1868

/* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);

1872

/* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);

1869

wait_ms(10); */

1873

wait_ms(10); */

1870

if (hc_start (&gohci) < 0) {

1874

if (hc_start (&gohci) < 0) {

1871

err ("can't start usb-%s", gohci.slot_name);

1875

err ("can't start usb-%s", gohci.slot_name);

1872

hc_release_ohci (&gohci);

1876

hc_release_ohci (&gohci);

1873

/* Initialization failed */

1877

/* Initialization failed */

1874

#ifdef CFG_USB_OHCI_BOARD_INIT

1878

#ifdef CFG_USB_OHCI_BOARD_INIT

1875

/* board dependant cleanup */

1879

/* board dependant cleanup */

1876

usb_board_stop();

1880

usb_board_stop();

1877

#endif

1881

#endif

1878

1882

1879

#ifdef CFG_USB_OHCI_CPU_INIT

1883

#ifdef CFG_USB_OHCI_CPU_INIT

1880

/* cpu dependant cleanup */

1884

/* cpu dependant cleanup */

1881

usb_cpu_stop();

1885

usb_cpu_stop();

1882

#endif

1886

#endif

1883

return -1;

1887

return -1;

1884

}

1888

}

1885

1889

1886

#ifdef DEBUG

1890

#ifdef DEBUG

1887

ohci_dump (&gohci, 1);

1891

ohci_dump (&gohci, 1);

1888

#else

1892

#else

1889

wait_ms(1);

1893

wait_ms(1);

1890

#endif

1894

#endif

1891

ohci_inited = 1;

1895

ohci_inited = 1;

1892

return 0;

1896

return 0;

1893

}

1897

}

1894

1898

1895

int usb_lowlevel_stop(void)

1899

int usb_lowlevel_stop(void)

1896

{

1900

{

1897

/* this gets called really early - before the controller has */

1901

/* this gets called really early - before the controller has */

1898

/* even been initialized! */

1902

/* even been initialized! */

1899

if (!ohci_inited)

1903

if (!ohci_inited)

1900

return 0;

1904

return 0;

1901

/* TODO release any interrupts, etc. */

1905

/* TODO release any interrupts, etc. */

1902

/* call hc_release_ohci() here ? */

1906

/* call hc_release_ohci() here ? */

1903

hc_reset (&gohci);

1907

hc_reset (&gohci);

1904

1908

1905

#ifdef CFG_USB_OHCI_BOARD_INIT

1909

#ifdef CFG_USB_OHCI_BOARD_INIT

1906

/* board dependant cleanup */

1910

/* board dependant cleanup */

1907

if(usb_board_stop())

1911

if(usb_board_stop())

1908

return -1;

1912

return -1;

1909

#endif

1913

#endif

1910

1914

1911

#ifdef CFG_USB_OHCI_CPU_INIT

1915

#ifdef CFG_USB_OHCI_CPU_INIT

1912

/* cpu dependant cleanup */

1916

/* cpu dependant cleanup */

1913

if(usb_cpu_stop())

1917

if(usb_cpu_stop())

1914

return -1;

1918

return -1;

1915

#endif

1919

#endif

1916

1920

1917

return 0;

1921

return 0;

1918

}

1922

}

1919

#endif /* CONFIG_USB_OHCI_NEW */

1923

#endif /* CONFIG_USB_OHCI_NEW */

1920

1924

GITLAB

Fix build problems with mp2usb board

 /*
  * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
  *
  * Interrupt support is added. Now, it has been tested
  * on ULI1575 chip and works well with USB keyboard.
  *
  * (C) Copyright 2007
  * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
  *
  * (C) Copyright 2003
  * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  *
  * Note: Much of this code has been derived from Linux 2.4
  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  * (C) Copyright 2000-2002 David Brownell
  *
  * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  * ebenard@eukrea.com - based on s3c24x0's driver
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
  */
 /*
  * IMPORTANT NOTES
  * 1 - Read doc/README.generic_usb_ohci
  * 2 - this driver is intended for use with USB Mass Storage Devices
  *     (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  *     to activate workaround for bug #41 or this driver will NOT work!
  */
 #include <common.h>
 #ifdef CONFIG_USB_OHCI_NEW
 #include <asm/byteorder.h>
 #if defined(CONFIG_PCI_OHCI)
 # include <pci.h>
 #endif
 #include <malloc.h>
 #include <usb.h>
 #include "usb_ohci.h"
+#ifdef CONFIG_AT91RM9200
+#include <asm/arch/hardware.h>	/* needed for AT91_USB_HOST_BASE */
+#endif
 #if defined(CONFIG_ARM920T) || \
     defined(CONFIG_S3C2400) || \
     defined(CONFIG_S3C2410) || \
     defined(CONFIG_440EP) || \
     defined(CONFIG_PCI_OHCI) || \
     defined(CONFIG_MPC5200)
 # define OHCI_USE_NPS		/* force NoPowerSwitching mode */
 #endif
 #undef OHCI_VERBOSE_DEBUG	/* not always helpful */
 #undef DEBUG
 #undef SHOW_INFO
 #undef OHCI_FILL_TRACE
 /* For initializing controller (mask in an HCFS mode too) */
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 /*
  * e.g. PCI controllers need this
  */
 #ifdef CFG_OHCI_SWAP_REG_ACCESS
 # define readl(a) __swap_32(*((vu_long *)(a)))
 # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
 #else
 # define readl(a) (*((vu_long *)(a)))
 # define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 #ifdef CONFIG_PCI_OHCI
 static struct pci_device_id ohci_pci_ids[] = {
 	{0x10b9, 0x5237},	/* ULI1575 PCI OHCI module ids */
 	{0x1033, 0x0035},	/* NEC PCI OHCI module ids */
 	/* Please add supported PCI OHCI controller ids here */
 	{0, 0}
 };
 #endif
 #ifdef DEBUG
 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
 #else
 #define dbg(format, arg...) do {} while(0)
 #endif /* DEBUG */
 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
 #undef SHOW_INFO
 #ifdef SHOW_INFO
 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
 #else
 #define info(format, arg...) do {} while(0)
 #endif
 #ifdef CFG_OHCI_BE_CONTROLLER
 # define m16_swap(x) cpu_to_be16(x)
 # define m32_swap(x) cpu_to_be32(x)
 #else
 # define m16_swap(x) cpu_to_le16(x)
 # define m32_swap(x) cpu_to_le32(x)
 #endif /* CFG_OHCI_BE_CONTROLLER */
 /* global ohci_t */
 static ohci_t gohci;
 /* this must be aligned to a 256 byte boundary */
 struct ohci_hcca ghcca[1];
 /* a pointer to the aligned storage */
 struct ohci_hcca *phcca;
 /* this allocates EDs for all possible endpoints */
 struct ohci_device ohci_dev;
 /* RHSC flag */
 int got_rhsc;
 /* device which was disconnected */
 struct usb_device *devgone;
 /*-------------------------------------------------------------------------*/
 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  * The erratum (#4) description is incorrect.  AMD's workaround waits
  * till some bits (mostly reserved) are clear; ok for all revs.
  */
 #define OHCI_QUIRK_AMD756 0xabcd
 #define read_roothub(hc, register, mask) ({ \
 	u32 temp = readl (&hc->regs->roothub.register); \
 	if (hc->flags & OHCI_QUIRK_AMD756) \
 		while (temp & mask) \
 			temp = readl (&hc->regs->roothub.register); \
 	temp; })
 static u32 roothub_a (struct ohci *hc)
 	{ return read_roothub (hc, a, 0xfc0fe000); }
 static inline u32 roothub_b (struct ohci *hc)
 	{ return readl (&hc->regs->roothub.b); }
 static inline u32 roothub_status (struct ohci *hc)
 	{ return readl (&hc->regs->roothub.status); }
 static u32 roothub_portstatus (struct ohci *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
 /* forward declaration */
 static int hc_interrupt (void);
 static void
 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
 	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
 /*-------------------------------------------------------------------------*
  * URB support functions
  *-------------------------------------------------------------------------*/
 /* free HCD-private data associated with this URB */
 static void urb_free_priv (urb_priv_t * urb)
 {
 	int		i;
 	int		last;
 	struct td	* td;
 	last = urb->length - 1;
 	if (last >= 0) {
 		for (i = 0; i <= last; i++) {
 			td = urb->td[i];
 			if (td) {
 				td->usb_dev = NULL;
 				urb->td[i] = NULL;
 			}
 		}
 	}
 	free(urb);
 }
 /*-------------------------------------------------------------------------*/
 #ifdef DEBUG
 static int sohci_get_current_frame_number (struct usb_device * dev);
 /* debug| print the main components of an URB
  * small: 0) header + data packets 1) just header */
 static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
 	unsigned long pipe, void * buffer,
 	int transfer_len, struct devrequest * setup, char * str, int small)
 {
 	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
 			str,
 			sohci_get_current_frame_number (dev),
 			usb_pipedevice (pipe),
 			usb_pipeendpoint (pipe),
 			usb_pipeout (pipe)? 'O': 'I',
 			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
 				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
 			(purb ? purb->actual_length : 0),
 			transfer_len, dev->status);
 #ifdef	OHCI_VERBOSE_DEBUG
 	if (!small) {
 		int i, len;
 		if (usb_pipecontrol (pipe)) {
 			printf (__FILE__ ": cmd(8):");
 			for (i = 0; i < 8 ; i++)
 				printf (" %02x", ((__u8 *) setup) [i]);
 			printf ("\n");
 		}
 		if (transfer_len > 0 && buffer) {
 			printf (__FILE__ ": data(%d/%d):",
 				(purb ? purb->actual_length : 0),
 				transfer_len);
 			len = usb_pipeout (pipe)?
 					transfer_len:
 					(purb ? purb->actual_length : 0);
 			for (i = 0; i < 16 && i < len; i++)
 				printf (" %02x", ((__u8 *) buffer) [i]);
 			printf ("%s\n", i < len? "...": "");
 		}
 	}
 #endif
 }
 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
 void ep_print_int_eds (ohci_t *ohci, char * str) {
 	int i, j;
 	 __u32 * ed_p;
 	for (i= 0; i < 32; i++) {
 		j = 5;
 		ed_p = &(ohci->hcca->int_table [i]);
 		if (*ed_p == 0)
 		    continue;
 		printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
 		while (*ed_p != 0 && j--) {
 			ed_t *ed = (ed_t *)m32_swap(ed_p);
 			printf (" ed: %4x;", ed->hwINFO);
 			ed_p = &ed->hwNextED;
 		}
 		printf ("\n");
 	}
 }
 static void ohci_dump_intr_mask (char *label, __u32 mask)
 {
 	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
 		label,
 		mask,
 		(mask & OHCI_INTR_MIE) ? " MIE" : "",
 		(mask & OHCI_INTR_OC) ? " OC" : "",
 		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
 		(mask & OHCI_INTR_FNO) ? " FNO" : "",
 		(mask & OHCI_INTR_UE) ? " UE" : "",
 		(mask & OHCI_INTR_RD) ? " RD" : "",
 		(mask & OHCI_INTR_SF) ? " SF" : "",
 		(mask & OHCI_INTR_WDH) ? " WDH" : "",
 		(mask & OHCI_INTR_SO) ? " SO" : ""
 		);
 }
 static void maybe_print_eds (char *label, __u32 value)
 {
 	ed_t *edp = (ed_t *)value;
 	if (value) {
 		dbg ("%s %08x", label, value);
 		dbg ("%08x", edp->hwINFO);
 		dbg ("%08x", edp->hwTailP);
 		dbg ("%08x", edp->hwHeadP);
 		dbg ("%08x", edp->hwNextED);
 	}
 }
 static char * hcfs2string (int state)
 {
 	switch (state) {
 		case OHCI_USB_RESET:	return "reset";
 		case OHCI_USB_RESUME:	return "resume";
 		case OHCI_USB_OPER:	return "operational";
 		case OHCI_USB_SUSPEND:	return "suspend";
 	}
 	return "?";
 }
 /* dump control and status registers */
 static void ohci_dump_status (ohci_t *controller)
 {
 	struct ohci_regs	*regs = controller->regs;
 	__u32			temp;
 	temp = readl (&regs->revision) & 0xff;
 	if (temp != 0x10)
 		dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
 	temp = readl (&regs->control);
 	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
 		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
 		(temp & OHCI_CTRL_IR) ? " IR" : "",
 		hcfs2string (temp & OHCI_CTRL_HCFS),
 		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
 		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
 		(temp & OHCI_CTRL_IE) ? " IE" : "",
 		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
 		temp & OHCI_CTRL_CBSR
 		);
 	temp = readl (&regs->cmdstatus);
 	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 		(temp & OHCI_SOC) >> 16,
 		(temp & OHCI_OCR) ? " OCR" : "",
 		(temp & OHCI_BLF) ? " BLF" : "",
 		(temp & OHCI_CLF) ? " CLF" : "",
 		(temp & OHCI_HCR) ? " HCR" : ""
 		);
 	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
 	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
 	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
 	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
 	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
 	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
 	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
 	maybe_print_eds ("donehead", readl (&regs->donehead));
 }
 static void ohci_dump_roothub (ohci_t *controller, int verbose)
 {
 	__u32			temp, ndp, i;
 	temp = roothub_a (controller);
 	ndp = (temp & RH_A_NDP);
 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 	ndp = (ndp == 2) ? 1:0;
 #endif
 	if (verbose) {
 		dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
 			((temp & RH_A_POTPGT) >> 24) & 0xff,
 			(temp & RH_A_NOCP) ? " NOCP" : "",
 			(temp & RH_A_OCPM) ? " OCPM" : "",
 			(temp & RH_A_DT) ? " DT" : "",
 			(temp & RH_A_NPS) ? " NPS" : "",
 			(temp & RH_A_PSM) ? " PSM" : "",
 			ndp
 			);
 		temp = roothub_b (controller);
 		dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
 			temp,
 			(temp & RH_B_PPCM) >> 16,
 			(temp & RH_B_DR)
 			);
 		temp = roothub_status (controller);
 		dbg ("roothub.status: %08x%s%s%s%s%s%s",
 			temp,
 			(temp & RH_HS_CRWE) ? " CRWE" : "",
 			(temp & RH_HS_OCIC) ? " OCIC" : "",
 			(temp & RH_HS_LPSC) ? " LPSC" : "",
 			(temp & RH_HS_DRWE) ? " DRWE" : "",
 			(temp & RH_HS_OCI) ? " OCI" : "",
 			(temp & RH_HS_LPS) ? " LPS" : ""
 			);
 	}
 	for (i = 0; i < ndp; i++) {
 		temp = roothub_portstatus (controller, i);
 		dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
 			i,
 			temp,
 			(temp & RH_PS_PRSC) ? " PRSC" : "",
 			(temp & RH_PS_OCIC) ? " OCIC" : "",
 			(temp & RH_PS_PSSC) ? " PSSC" : "",
 			(temp & RH_PS_PESC) ? " PESC" : "",
 			(temp & RH_PS_CSC) ? " CSC" : "",
 			(temp & RH_PS_LSDA) ? " LSDA" : "",
 			(temp & RH_PS_PPS) ? " PPS" : "",
 			(temp & RH_PS_PRS) ? " PRS" : "",
 			(temp & RH_PS_POCI) ? " POCI" : "",
 			(temp & RH_PS_PSS) ? " PSS" : "",
 			(temp & RH_PS_PES) ? " PES" : "",
 			(temp & RH_PS_CCS) ? " CCS" : ""
 			);
 	}
 }
 static void ohci_dump (ohci_t *controller, int verbose)
 {
 	dbg ("OHCI controller usb-%s state", controller->slot_name);
 	/* dumps some of the state we know about */
 	ohci_dump_status (controller);
 	if (verbose)
 		ep_print_int_eds (controller, "hcca");
 	dbg ("hcca frame #%04x", controller->hcca->frame_no);
 	ohci_dump_roothub (controller, 1);
 #endif /* DEBUG */
 /*-------------------------------------------------------------------------*
  * Interface functions (URB)
  *-------------------------------------------------------------------------*/
 /* get a transfer request */
 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
 {
 	ohci_t *ohci;
 	ed_t * ed;
 	urb_priv_t *purb_priv = urb;
 	int i, size = 0;
 	struct usb_device *dev = urb->dev;
 	unsigned long pipe = urb->pipe;
 	void *buffer = urb->transfer_buffer;
 	int transfer_len = urb->transfer_buffer_length;
 	int interval = urb->interval;
 	ohci = &gohci;
 	/* when controller's hung, permit only roothub cleanup attempts
 	 * such as powering down ports */
 	if (ohci->disabled) {
 		err("sohci_submit_job: EPIPE");
 		return -1;
 	}
 	/* we're about to begin a new transaction here so mark the URB unfinished */
 	urb->finished = 0;
 	/* every endpoint has a ed, locate and fill it */
 	if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
 		err("sohci_submit_job: ENOMEM");
 		return -1;
 	}
 	/* for the private part of the URB we need the number of TDs (size) */
 	switch (usb_pipetype (pipe)) {
 		case PIPE_BULK: /* one TD for every 4096 Byte */
 			size = (transfer_len - 1) / 4096 + 1;
 			break;
 		case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
 			size = (transfer_len == 0)? 2:
 						(transfer_len - 1) / 4096 + 3;
 			break;
 		case PIPE_INTERRUPT: /* 1 TD */
 			size = 1;
 			break;
 	}
 	ed->purb = urb;
 	if (size >= (N_URB_TD - 1)) {
 		err("need %d TDs, only have %d", size, N_URB_TD);
 		return -1;
 	}
 	purb_priv->pipe = pipe;
 	/* fill the private part of the URB */
 	purb_priv->length = size;
 	purb_priv->ed = ed;
 	purb_priv->actual_length = 0;
 	/* allocate the TDs */
 	/* note that td[0] was allocated in ep_add_ed */
 	for (i = 0; i < size; i++) {
 		purb_priv->td[i] = td_alloc (dev);
 		if (!purb_priv->td[i]) {
 			purb_priv->length = i;
 			urb_free_priv (purb_priv);
 			err("sohci_submit_job: ENOMEM");
 			return -1;
 		}
 	}
 	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
 		urb_free_priv (purb_priv);
 		err("sohci_submit_job: EINVAL");
 		return -1;
 	}
 	/* link the ed into a chain if is not already */
 	if (ed->state != ED_OPER)
 		ep_link (ohci, ed);
 	/* fill the TDs and link it to the ed */
 	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
 	return 0;
 }
 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
 {
 	struct ohci_regs *regs = hc->regs;
 	switch (usb_pipetype (urb->pipe)) {
 	case PIPE_INTERRUPT:
 		/* implicitly requeued */
 		if (urb->dev->irq_handle &&
 				(urb->dev->irq_act_len = urb->actual_length)) {
 			writel (OHCI_INTR_WDH, &regs->intrenable);
 			readl (&regs->intrenable); /* PCI posting flush */
 			urb->dev->irq_handle(urb->dev);
 			writel (OHCI_INTR_WDH, &regs->intrdisable);
 			readl (&regs->intrdisable); /* PCI posting flush */
 		}
 		urb->actual_length = 0;
 		td_submit_job (
 				urb->dev,
 				urb->pipe,
 				urb->transfer_buffer,
 				urb->transfer_buffer_length,
 				NULL,
 				urb,
 				urb->interval);
 		break;
 	case PIPE_CONTROL:
 	case PIPE_BULK:
 		break;
 	default:
 		return 0;
 	}
 	return 1;
 }
 /*-------------------------------------------------------------------------*/
 #ifdef DEBUG
 /* tell us the current USB frame number */
 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
 {
 	ohci_t *ohci = &gohci;
 	return m16_swap (ohci->hcca->frame_no);
 }
 #endif
 /*-------------------------------------------------------------------------*
  * ED handling functions
  *-------------------------------------------------------------------------*/
 /* search for the right branch to insert an interrupt ed into the int tree
  * do some load ballancing;
  * returns the branch and
  * sets the interval to interval = 2^integer (ld (interval)) */
 static int ep_int_ballance (ohci_t * ohci, int interval, int load)
 {
 	int i, branch = 0;
 	/* search for the least loaded interrupt endpoint
 	 * branch of all 32 branches
 	 */
 	for (i = 0; i < 32; i++)
 		if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
 			branch = i;
 	branch = branch % interval;
 	for (i = branch; i < 32; i += interval)
 		ohci->ohci_int_load [i] += load;
 	return branch;
 }
 /*-------------------------------------------------------------------------*/
 /*  2^int( ld (inter)) */
 static int ep_2_n_interval (int inter)
 {
 	int i;
 	for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
 	return 1 << i;
 }
 /*-------------------------------------------------------------------------*/
 /* the int tree is a binary tree
  * in order to process it sequentially the indexes of the branches have to be mapped
  * the mapping reverses the bits of a word of num_bits length */
 static int ep_rev (int num_bits, int word)
 {
 	int i, wout = 0;
 	for (i = 0; i < num_bits; i++)
 		wout |= (((word >> i) & 1) << (num_bits - i - 1));
 	return wout;
 }
 /*-------------------------------------------------------------------------*
  * ED handling functions
  *-------------------------------------------------------------------------*/
 /* link an ed into one of the HC chains */
 static int ep_link (ohci_t *ohci, ed_t *edi)
 {
 	volatile ed_t *ed = edi;
 	int int_branch;
 	int i;
 	int inter;
 	int interval;
 	int load;
 	__u32 * ed_p;
 	ed->state = ED_OPER;
 	ed->int_interval = 0;
 	switch (ed->type) {
 	case PIPE_CONTROL:
 		ed->hwNextED = 0;
 		if (ohci->ed_controltail == NULL) {
 			writel (ed, &ohci->regs->ed_controlhead);
 		} else {
 			ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
 		}
 		ed->ed_prev = ohci->ed_controltail;
 		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 			!ohci->ed_rm_list[1] && !ohci->sleeping) {
 			ohci->hc_control |= OHCI_CTRL_CLE;
 			writel (ohci->hc_control, &ohci->regs->control);
 		}
 		ohci->ed_controltail = edi;
 		break;
 	case PIPE_BULK:
 		ed->hwNextED = 0;
 		if (ohci->ed_bulktail == NULL) {
 			writel (ed, &ohci->regs->ed_bulkhead);
 		} else {
 			ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
 		}
 		ed->ed_prev = ohci->ed_bulktail;
 		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 			!ohci->ed_rm_list[1] && !ohci->sleeping) {
 			ohci->hc_control |= OHCI_CTRL_BLE;
 			writel (ohci->hc_control, &ohci->regs->control);
 		}
 		ohci->ed_bulktail = edi;
 		break;
 	case PIPE_INTERRUPT:
 		load = ed->int_load;
 		interval = ep_2_n_interval (ed->int_period);
 		ed->int_interval = interval;
 		int_branch = ep_int_ballance (ohci, interval, load);
 		ed->int_branch = int_branch;
 		for (i = 0; i < ep_rev (6, interval); i += inter) {
 			inter = 1;
 			for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
 				(*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
 				ed_p = &(((ed_t *)ed_p)->hwNextED))
 					inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
 			ed->hwNextED = *ed_p;
 			*ed_p = m32_swap((unsigned long)ed);
 		}
 		break;
 	}
 	return 0;
 }
 /*-------------------------------------------------------------------------*/
 /* scan the periodic table to find and unlink this ED */
 static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
 		unsigned index, unsigned period)
 {
 	for (; index < NUM_INTS; index += period) {
 		__u32	*ed_p = &ohci->hcca->int_table [index];
 		/* ED might have been unlinked through another path */
 		while (*ed_p != 0) {
 			if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {
 				*ed_p = ed->hwNextED;
 				break;
 			}
 			ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);
 		}
 	}
 }
 /* unlink an ed from one of the HC chains.
  * just the link to the ed is unlinked.
  * the link from the ed still points to another operational ed or 0
  * so the HC can eventually finish the processing of the unlinked ed */
 static int ep_unlink (ohci_t *ohci, ed_t *edi)
 {
 	volatile ed_t *ed = edi;
 	int i;
 	ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
 	switch (ed->type) {
 	case PIPE_CONTROL:
 		if (ed->ed_prev == NULL) {
 			if (!ed->hwNextED) {
 				ohci->hc_control &= ~OHCI_CTRL_CLE;
 				writel (ohci->hc_control, &ohci->regs->control);
 			}
 			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
 		} else {
 			ed->ed_prev->hwNextED = ed->hwNextED;
 		}
 		if (ohci->ed_controltail == ed) {
 			ohci->ed_controltail = ed->ed_prev;
 		} else {
 			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 		}
 		break;
 	case PIPE_BULK:
 		if (ed->ed_prev == NULL) {
 			if (!ed->hwNextED) {
 				ohci->hc_control &= ~OHCI_CTRL_BLE;
 				writel (ohci->hc_control, &ohci->regs->control);
 			}
 			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
 		} else {
 			ed->ed_prev->hwNextED = ed->hwNextED;
 		}
 		if (ohci->ed_bulktail == ed) {
 			ohci->ed_bulktail = ed->ed_prev;
 		} else {
 			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 		}
 		break;
 	case PIPE_INTERRUPT:
 		periodic_unlink (ohci, ed, 0, 1);
 		for (i = ed->int_branch; i < 32; i += ed->int_interval)
 		    ohci->ohci_int_load[i] -= ed->int_load;
 		break;
 	}
 	ed->state = ED_UNLINK;
 	return 0;
 }
 /*-------------------------------------------------------------------------*/
 /* add/reinit an endpoint; this should be done once at the
  * usb_set_configuration command, but the USB stack is a little bit
  * stateless so we do it at every transaction if the state of the ed
  * is ED_NEW then a dummy td is added and the state is changed to
  * ED_UNLINK in all other cases the state is left unchanged the ed
  * info fields are setted anyway even though most of them should not
  * change
  */
 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
 		int interval, int load)
 {
 	td_t *td;
 	ed_t *ed_ret;
 	volatile ed_t *ed;
 	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
 			(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
 	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
 		err("ep_add_ed: pending delete");
 		/* pending delete request */
 		return NULL;
 	}
 	if (ed->state == ED_NEW) {
 		ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
 		/* dummy td; end of td list for ed */
 		td = td_alloc (usb_dev);
 		ed->hwTailP = m32_swap ((unsigned long)td);
 		ed->hwHeadP = ed->hwTailP;
 		ed->state = ED_UNLINK;
 		ed->type = usb_pipetype (pipe);
 		ohci_dev.ed_cnt++;
 	}
 	ed->hwINFO = m32_swap (usb_pipedevice (pipe)
 			| usb_pipeendpoint (pipe) << 7
 			| (usb_pipeisoc (pipe)? 0x8000: 0)
 			| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
 			| usb_pipeslow (pipe) << 13
 			| usb_maxpacket (usb_dev, pipe) << 16);
 	if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
 		ed->int_period = interval;
 		ed->int_load = load;
 	}
 	return ed_ret;
 }
 /*-------------------------------------------------------------------------*
  * TD handling functions
  *-------------------------------------------------------------------------*/
 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 static void td_fill (ohci_t *ohci, unsigned int info,
 	void *data, int len,
 	struct usb_device *dev, int index, urb_priv_t *urb_priv)
 {
 	volatile td_t  *td, *td_pt;
 #ifdef OHCI_FILL_TRACE
 	int i;
 #endif
 	if (index > urb_priv->length) {
 		err("index > length");
 		return;
 	}
 	/* use this td as the next dummy */
 	td_pt = urb_priv->td [index];
 	td_pt->hwNextTD = 0;
 	/* fill the old dummy TD */
 	td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
 	td->ed = urb_priv->ed;
 	td->next_dl_td = NULL;
 	td->index = index;
 	td->data = (__u32)data;
 #ifdef OHCI_FILL_TRACE
 	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
 		for (i = 0; i < len; i++)
 		printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
 		printf("\n");
 	}
 #endif
 	if (!len)
 		data = 0;
 	td->hwINFO = m32_swap (info);
 	td->hwCBP = m32_swap ((unsigned long)data);
 	if (data)
 		td->hwBE = m32_swap ((unsigned long)(data + len - 1));
 	else
 		td->hwBE = 0;
 	td->hwNextTD = m32_swap ((unsigned long)td_pt);
 	/* append to queue */
 	td->ed->hwTailP = td->hwNextTD;
 }
 /*-------------------------------------------------------------------------*/
 /* prepare all TDs of a transfer */
 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
 	int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
 {
 	ohci_t *ohci = &gohci;
 	int data_len = transfer_len;
 	void *data;
 	int cnt = 0;
 	__u32 info = 0;
 	unsigned int toggle = 0;
 	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
 	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
 		toggle = TD_T_TOGGLE;
 	} else {
 		toggle = TD_T_DATA0;
 		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
 	}
 	urb->td_cnt = 0;
 	if (data_len)
 		data = buffer;
 	else
 		data = 0;
 	switch (usb_pipetype (pipe)) {
 	case PIPE_BULK:
 		info = usb_pipeout (pipe)?
 			TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
 		while(data_len > 4096) {
 			td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
 			data += 4096; data_len -= 4096; cnt++;
 		}
 		info = usb_pipeout (pipe)?
 			TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
 		td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
 		cnt++;
 		if (!ohci->sleeping)
 			writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
 		break;
 	case PIPE_CONTROL:
 		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 		td_fill (ohci, info, setup, 8, dev, cnt++, urb);
 		if (data_len > 0) {
 			info = usb_pipeout (pipe)?
 				TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
 			/* NOTE:  mishandles transfers >8K, some >4K */
 			td_fill (ohci, info, data, data_len, dev, cnt++, urb);
 		}
 		info = usb_pipeout (pipe)?
 			TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
 		td_fill (ohci, info, data, 0, dev, cnt++, urb);
 		if (!ohci->sleeping)
 			writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
 		break;
 	case PIPE_INTERRUPT:
 		info = usb_pipeout (urb->pipe)?
 			TD_CC | TD_DP_OUT | toggle:
 			TD_CC | TD_R | TD_DP_IN | toggle;
 		td_fill (ohci, info, data, data_len, dev, cnt++, urb);
 		break;
 	}
 	if (urb->length != cnt)
 		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
 }
 /*-------------------------------------------------------------------------*
  * Done List handling functions
  *-------------------------------------------------------------------------*/
 /* calculate the transfer length and update the urb */
 static void dl_transfer_length(td_t * td)
 {
 	__u32 tdINFO, tdBE, tdCBP;
 	urb_priv_t *lurb_priv = td->ed->purb;
 	tdINFO = m32_swap (td->hwINFO);
 	tdBE   = m32_swap (td->hwBE);
 	tdCBP  = m32_swap (td->hwCBP);
 	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
 	    ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
 		if (tdBE != 0) {
 			if (td->hwCBP == 0)
 				lurb_priv->actual_length += tdBE - td->data + 1;
 			else
 				lurb_priv->actual_length += tdCBP - td->data;
 		}
 	}
 }
 /*-------------------------------------------------------------------------*/
 /* replies to the request have to be on a FIFO basis so
  * we reverse the reversed done-list */
 static td_t * dl_reverse_done_list (ohci_t *ohci)
 {
 	__u32 td_list_hc;
 	td_t *td_rev = NULL;
 	td_t *td_list = NULL;
 	urb_priv_t *lurb_priv = NULL;
 	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
 	ohci->hcca->done_head = 0;
 	while (td_list_hc) {
 		td_list = (td_t *)td_list_hc;
 		if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
 			lurb_priv = td_list->ed->purb;
 			dbg(" USB-error/status: %x : %p",
 					TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
 			if (td_list->ed->hwHeadP & m32_swap (0x1)) {
 				if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
 					td_list->ed->hwHeadP =
 						(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
 									(td_list->ed->hwHeadP & m32_swap (0x2));
 					lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
 				} else
 					td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
 			}
 #ifdef CONFIG_MPC5200
 			td_list->hwNextTD = 0;
 #endif
 		}
 		td_list->next_dl_td = td_rev;
 		td_rev = td_list;
 		td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
 	}
 	return td_list;
 }
 /*-------------------------------------------------------------------------*/
 /* td done list */
 static int dl_done_list (ohci_t *ohci, td_t *td_list)
 {
 	td_t *td_list_next = NULL;
 	ed_t *ed;
 	int cc = 0;
 	int stat = 0;
 	/* urb_t *urb; */
 	urb_priv_t *lurb_priv;
 	__u32 tdINFO, edHeadP, edTailP;
 	while (td_list) {
 		td_list_next = td_list->next_dl_td;
 		tdINFO = m32_swap (td_list->hwINFO);
 		ed = td_list->ed;
 		lurb_priv = ed->purb;
 		dl_transfer_length(td_list);
 		/* error code of transfer */
 		cc = TD_CC_GET (tdINFO);
 		if (cc != 0) {
 			dbg("ConditionCode %#x", cc);
 			stat = cc_to_error[cc];
 		}
 		/* see if this done list makes for all TD's of current URB,
 		 * and mark the URB finished if so */
 		if (++(lurb_priv->td_cnt) == lurb_priv->length) {
 #if 1
 			if ((ed->state & (ED_OPER | ED_UNLINK)) &&
 			    (lurb_priv->state != URB_DEL))
 #else
 			if ((ed->state & (ED_OPER | ED_UNLINK)))
 #endif
 				lurb_priv->finished = sohci_return_job(ohci,
 						lurb_priv);
 			else
 				dbg("dl_done_list: strange.., ED state %x, ed->state\n");
 		} else
 			dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
 				lurb_priv->length);
 		if (ed->state != ED_NEW &&
 			  (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
 			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
 			edTailP = m32_swap (ed->hwTailP);
 			/* unlink eds if they are not busy */
 			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
 				ep_unlink (ohci, ed);
 		}
 		td_list = td_list_next;
 	}
 	return stat;
 }
 /*-------------------------------------------------------------------------*
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 /* Device descriptor */
 static __u8 root_hub_dev_des[] =
 {
 	0x12,	    /*	__u8  bLength; */
 	0x01,	    /*	__u8  bDescriptorType; Device */
 	0x10,	    /*	__u16 bcdUSB; v1.1 */
 	0x01,
 	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
 	0x00,	    /*	__u8  bDeviceSubClass; */
 	0x00,	    /*	__u8  bDeviceProtocol; */
 	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
 	0x00,	    /*	__u16 idVendor; */
 	0x00,
 	0x00,	    /*	__u16 idProduct; */
 	0x00,
 	0x00,	    /*	__u16 bcdDevice; */
 	0x00,
 	0x00,	    /*	__u8  iManufacturer; */
 	0x01,	    /*	__u8  iProduct; */
 	0x00,	    /*	__u8  iSerialNumber; */
 	0x01	    /*	__u8  bNumConfigurations; */
 };
 /* Configuration descriptor */
 static __u8 root_hub_config_des[] =
 {
 	0x09,	    /*	__u8  bLength; */
 	0x02,	    /*	__u8  bDescriptorType; Configuration */
 	0x19,	    /*	__u16 wTotalLength; */
 	0x00,
 	0x01,	    /*	__u8  bNumInterfaces; */
 	0x01,	    /*	__u8  bConfigurationValue; */
 	0x00,	    /*	__u8  iConfiguration; */
 	0x40,	    /*	__u8  bmAttributes;
 		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
 	0x00,	    /*	__u8  MaxPower; */
 	/* interface */
 	0x09,	    /*	__u8  if_bLength; */
 	0x04,	    /*	__u8  if_bDescriptorType; Interface */
 	0x00,	    /*	__u8  if_bInterfaceNumber; */
 	0x00,	    /*	__u8  if_bAlternateSetting; */
 	0x01,	    /*	__u8  if_bNumEndpoints; */
 	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
 	0x00,	    /*	__u8  if_bInterfaceSubClass; */
 	0x00,	    /*	__u8  if_bInterfaceProtocol; */
 	0x00,	    /*	__u8  if_iInterface; */
 	/* endpoint */
 	0x07,	    /*	__u8  ep_bLength; */
 	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
 	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
 	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
 	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
 	0x00,
 	0xff	    /*	__u8  ep_bInterval; 255 ms */
 };
 static unsigned char root_hub_str_index0[] =
 {
 	0x04,			/*  __u8  bLength; */
 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
 	0x09,			/*  __u8  lang ID */
 	0x04,			/*  __u8  lang ID */
 };
 static unsigned char root_hub_str_index1[] =
 {
 	28,			/*  __u8  bLength; */
 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
 	'O',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'H',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'C',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'I',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	' ',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'R',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'o',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'o',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	't',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	' ',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'H',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'u',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 	'b',			/*  __u8  Unicode */
 	0,				/*  __u8  Unicode */
 };
 /* Hub class-specific descriptor is constructed dynamically */
 /*-------------------------------------------------------------------------*/
 #define OK(x)			len = (x); break
 #ifdef DEBUG
 #define WR_RH_STAT(x)		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
 #define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
 #else
 #define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
 #define WR_RH_PORTSTAT(x)	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
 #endif
 #define RD_RH_STAT		roothub_status(&gohci)
 #define RD_RH_PORTSTAT		roothub_portstatus(&gohci,wIndex-1)
 /* request to virtual root hub */
 int rh_check_port_status(ohci_t *controller)
 {
 	__u32 temp, ndp, i;
 	int res;
 	res = -1;
 	temp = roothub_a (controller);
 	ndp = (temp & RH_A_NDP);
 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 	ndp = (ndp == 2) ? 1:0;
 #endif
 	for (i = 0; i < ndp; i++) {
 		temp = roothub_portstatus (controller, i);
 		/* check for a device disconnect */
 		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
 			(RH_PS_PESC | RH_PS_CSC)) &&
 			((temp & RH_PS_CCS) == 0)) {
 			res = i;
 			break;
 		}
 	}
 	return res;
 }
 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 		void *buffer, int transfer_len, struct devrequest *cmd)
 {
 	void * data = buffer;
 	int leni = transfer_len;
 	int len = 0;
 	int stat = 0;
 	__u32 datab[4];
 	__u8 *data_buf = (__u8 *)datab;
 	__u16 bmRType_bReq;
 	__u16 wValue;
 	__u16 wIndex;
 	__u16 wLength;
 #ifdef DEBUG
 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 #else
 	wait_ms(1);
 #endif
 	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
 		info("Root-Hub submit IRQ: NOT implemented");
 		return 0;
 	}
 	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
 	wValue	      = cpu_to_le16 (cmd->value);
 	wIndex	      = cpu_to_le16 (cmd->index);
 	wLength	      = cpu_to_le16 (cmd->length);
 	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
 		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
 	switch (bmRType_bReq) {
 	/* Request Destination:
 	   without flags: Device,
 	   RH_INTERFACE: interface,
 	   RH_ENDPOINT: endpoint,
 	   RH_CLASS means HUB here,
 	   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
 	*/
 	case RH_GET_STATUS:
 			*(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
 	case RH_GET_STATUS | RH_INTERFACE:
 			*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
 	case RH_GET_STATUS | RH_ENDPOINT:
 			*(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
 	case RH_GET_STATUS | RH_CLASS:
 			*(__u32 *) data_buf = cpu_to_le32 (
 				RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
 			OK (4);
 	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
 			*(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
 	case RH_CLEAR_FEATURE | RH_ENDPOINT:
 		switch (wValue) {
 			case (RH_ENDPOINT_STALL): OK (0);
 		}
 		break;
 	case RH_CLEAR_FEATURE | RH_CLASS:
 		switch (wValue) {
 			case RH_C_HUB_LOCAL_POWER:
 				OK(0);
 			case (RH_C_HUB_OVER_CURRENT):
 					WR_RH_STAT(RH_HS_OCIC); OK (0);
 		}
 		break;
 	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
 		switch (wValue) {
 			case (RH_PORT_ENABLE):
 					WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
 			case (RH_PORT_SUSPEND):
 					WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
 			case (RH_PORT_POWER):
 					WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
 			case (RH_C_PORT_CONNECTION):
 					WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
 			case (RH_C_PORT_ENABLE):
 					WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
 			case (RH_C_PORT_SUSPEND):
 					WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
 			case (RH_C_PORT_OVER_CURRENT):
 					WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
 			case (RH_C_PORT_RESET):
 					WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
 		}
 		break;
 	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
 		switch (wValue) {
 			case (RH_PORT_SUSPEND):
 					WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
 			case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
 					if (RD_RH_PORTSTAT & RH_PS_CCS)
 					    WR_RH_PORTSTAT (RH_PS_PRS);
 					OK (0);
 			case (RH_PORT_POWER):
 					WR_RH_PORTSTAT (RH_PS_PPS );
 					wait_ms(100);
 					OK (0);
 			case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
 					if (RD_RH_PORTSTAT & RH_PS_CCS)
 					    WR_RH_PORTSTAT (RH_PS_PES );
 					OK (0);
 		}
 		break;
 	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
 	case RH_GET_DESCRIPTOR:
 		switch ((wValue & 0xff00) >> 8) {
 			case (0x01): /* device descriptor */
 				len = min_t(unsigned int,
 					  leni,
 					  min_t(unsigned int,
 					      sizeof (root_hub_dev_des),
 					      wLength));
 				data_buf = root_hub_dev_des; OK(len);
 			case (0x02): /* configuration descriptor */
 				len = min_t(unsigned int,
 					  leni,
 					  min_t(unsigned int,
 					      sizeof (root_hub_config_des),
 					      wLength));
 				data_buf = root_hub_config_des; OK(len);
 			case (0x03): /* string descriptors */
 				if(wValue==0x0300) {
 					len = min_t(unsigned int,
 						  leni,
 						  min_t(unsigned int,
 						      sizeof (root_hub_str_index0),
 						      wLength));
 					data_buf = root_hub_str_index0;
 					OK(len);
 				}
 				if(wValue==0x0301) {
 					len = min_t(unsigned int,
 						  leni,
 						  min_t(unsigned int,
 						      sizeof (root_hub_str_index1),
 						      wLength));
 					data_buf = root_hub_str_index1;
 					OK(len);
 			}
 			default:
 				stat = USB_ST_STALLED;
 		}
 		break;
 	case RH_GET_DESCRIPTOR | RH_CLASS:
 	{
 		__u32 temp = roothub_a (&gohci);
 		data_buf [0] = 9;		/* min length; */
 		data_buf [1] = 0x29;
 		data_buf [2] = temp & RH_A_NDP;
 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 		data_buf [2] = (data_buf [2] == 2) ? 1:0;
 #endif
 		data_buf [3] = 0;
 		if (temp & RH_A_PSM)	/* per-port power switching? */
 			data_buf [3] |= 0x1;
 		if (temp & RH_A_NOCP)	/* no overcurrent reporting? */
 			data_buf [3] |= 0x10;
 		else if (temp & RH_A_OCPM)	/* per-port overcurrent reporting? */
 			data_buf [3] |= 0x8;
 		/* corresponds to data_buf[4-7] */
 		datab [1] = 0;
 		data_buf [5] = (temp & RH_A_POTPGT) >> 24;
 		temp = roothub_b (&gohci);
 		data_buf [7] = temp & RH_B_DR;
 		if (data_buf [2] < 7) {
 			data_buf [8] = 0xff;
 		} else {
 			data_buf [0] += 2;
 			data_buf [8] = (temp & RH_B_DR) >> 8;
 			data_buf [10] = data_buf [9] = 0xff;
 		}
 		len = min_t(unsigned int, leni,
 			    min_t(unsigned int, data_buf [0], wLength));
 		OK (len);
 	}
 	case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK (1);
 	case RH_SET_CONFIGURATION:	WR_RH_STAT (0x10000); OK (0);
 	default:
 		dbg ("unsupported root hub command");
 		stat = USB_ST_STALLED;
 	}
 #ifdef	DEBUG
 	ohci_dump_roothub (&gohci, 1);
 #else
 	wait_ms(1);
 #endif
 	len = min_t(int, len, leni);
 	if (data != data_buf)
 	    memcpy (data, data_buf, len);
 	dev->act_len = len;
 	dev->status = stat;
 #ifdef DEBUG
 	pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
 #else
 	wait_ms(1);
 #endif
 	return stat;
 }
 /*-------------------------------------------------------------------------*/
 /* common code for handling submit messages - used for all but root hub */
 /* accesses. */
 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		int transfer_len, struct devrequest *setup, int interval)
 {
 	int stat = 0;
 	int maxsize = usb_maxpacket(dev, pipe);
 	int timeout;
 	urb_priv_t *urb;
 	urb = malloc(sizeof(urb_priv_t));
 	memset(urb, 0, sizeof(urb_priv_t));
 	urb->dev = dev;
 	urb->pipe = pipe;
 	urb->transfer_buffer = buffer;
 	urb->transfer_buffer_length = transfer_len;
 	urb->interval = interval;
 	/* device pulled? Shortcut the action. */
 	if (devgone == dev) {
 		dev->status = USB_ST_CRC_ERR;
 		return 0;
 	}
 #ifdef DEBUG
 	urb->actual_length = 0;
 	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
 #else
 	wait_ms(1);
 #endif
 	if (!maxsize) {
 		err("submit_common_message: pipesize for pipe %lx is zero",
 			pipe);
 		return -1;
 	}
 	if (sohci_submit_job(urb, setup) < 0) {
 		err("sohci_submit_job failed");
 		return -1;
 	}
 #if 0
 	wait_ms(10);
 	/* ohci_dump_status(&gohci); */
 #endif
 	/* allow more time for a BULK device to react - some are slow */
 #define BULK_TO	 5000	/* timeout in milliseconds */
 	if (usb_pipetype (pipe) == PIPE_BULK)
 		timeout = BULK_TO;
 	else
 		timeout = 100;
 	/* wait for it to complete */
 	for (;;) {
 		/* check whether the controller is done */
 		stat = hc_interrupt();
 		if (stat < 0) {
 			stat = USB_ST_CRC_ERR;
 			break;
 		}
 		/* NOTE: since we are not interrupt driven in U-Boot and always
 		 * handle only one URB at a time, we cannot assume the
 		 * transaction finished on the first successful return from
 		 * hc_interrupt().. unless the flag for current URB is set,
 		 * meaning that all TD's to/from device got actually
 		 * transferred and processed. If the current URB is not
 		 * finished we need to re-iterate this loop so as
 		 * hc_interrupt() gets called again as there needs to be some
 		 * more TD's to process still */
 		if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
 			/* 0xff is returned for an SF-interrupt */
 			break;
 		}
 		if (--timeout) {
 			wait_ms(1);
 			if (!urb->finished)
 				dbg("\%");
 		} else {
 			err("CTL:TIMEOUT ");
 			dbg("submit_common_msg: TO status %x\n", stat);
 			urb->finished = 1;
 			stat = USB_ST_CRC_ERR;
 			break;
 		}
 	}
 	dev->status = stat;
 	dev->act_len = transfer_len;
 #ifdef DEBUG
 	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
 #else
 	wait_ms(1);
 #endif
 	/* free TDs in urb_priv */
 	if (usb_pipetype (pipe) != PIPE_INTERRUPT)
 		urb_free_priv (urb);
 	return 0;
 }
 /* submit routines called from usb.c */
 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		int transfer_len)
 {
 	info("submit_bulk_msg");
 	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
 }
 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		int transfer_len, struct devrequest *setup)
 {
 	int maxsize = usb_maxpacket(dev, pipe);
 	info("submit_control_msg");
 #ifdef DEBUG
 	pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
 #else
 	wait_ms(1);
 #endif
 	if (!maxsize) {
 		err("submit_control_message: pipesize for pipe %lx is zero",
 			pipe);
 		return -1;
 	}
 	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
 		gohci.rh.dev = dev;
 		/* root hub - redirect */
 		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
 			setup);
 	}
 	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
 }
 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		int transfer_len, int interval)
 {
 	info("submit_int_msg");
 	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
 			interval);
 }
 /*-------------------------------------------------------------------------*
  * HC functions
  *-------------------------------------------------------------------------*/
 /* reset the HC and BUS */
 static int hc_reset (ohci_t *ohci)
 {
 	int timeout = 30;
 	int smm_timeout = 50; /* 0,5 sec */
 	dbg("%s\n", __FUNCTION__);
 	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
 		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
 		info("USB HC TakeOver from SMM");
 		while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
 			wait_ms (10);
 			if (--smm_timeout == 0) {
 				err("USB HC TakeOver failed!");
 				return -1;
 			}
 		}
 	}
 	/* Disable HC interrupts */
 	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
 	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
 		ohci->slot_name,
 		readl(&ohci->regs->control));
 	/* Reset USB (needed by some controllers) */
 	ohci->hc_control = 0;
 	writel (ohci->hc_control, &ohci->regs->control);
 	/* HC Reset requires max 10 us delay */
 	writel (OHCI_HCR,  &ohci->regs->cmdstatus);
 	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 		if (--timeout == 0) {
 			err("USB HC reset timed out!");
 			return -1;
 		}
 		udelay (1);
 	}
 	return 0;
 }
 /*-------------------------------------------------------------------------*/
 /* Start an OHCI controller, set the BUS operational
  * enable interrupts
  * connect the virtual root hub */
 static int hc_start (ohci_t * ohci)
 {
 	__u32 mask;
 	unsigned int fminterval;
 	ohci->disabled = 1;
 	/* Tell the controller where the control and bulk lists are
 	 * The lists are empty now. */
 	writel (0, &ohci->regs->ed_controlhead);
 	writel (0, &ohci->regs->ed_bulkhead);
 	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
 	fminterval = 0x2edf;
 	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
 	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
 	writel (fminterval, &ohci->regs->fminterval);
 	writel (0x628, &ohci->regs->lsthresh);
 	/* start controller operations */
 	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
 	ohci->disabled = 0;
 	writel (ohci->hc_control, &ohci->regs->control);
 	/* disable all interrupts */
 	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
 			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
 			OHCI_INTR_OC | OHCI_INTR_MIE);
 	writel (mask, &ohci->regs->intrdisable);
 	/* clear all interrupts */
 	mask &= ~OHCI_INTR_MIE;
 	writel (mask, &ohci->regs->intrstatus);
 	/* Choose the interrupts we care about now  - but w/o MIE */
 	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
 	writel (mask, &ohci->regs->intrenable);
 #ifdef	OHCI_USE_NPS
 	/* required for AMD-756 and some Mac platforms */
 	writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
 		&ohci->regs->roothub.a);
 	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
 #endif	/* OHCI_USE_NPS */
 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
 	/* POTPGT delay is bits 24-31, in 2 ms units. */
 	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
 	/* connect the virtual root hub */
 	ohci->rh.devnum = 0;
 	return 0;
 }
 /*-------------------------------------------------------------------------*/
 /* Poll USB interrupt. */
 void usb_event_poll(void)
 {
 	hc_interrupt();
 }
 /* an interrupt happens */
 static int hc_interrupt (void)
 {
 	ohci_t *ohci = &gohci;
 	struct ohci_regs *regs = ohci->regs;
 	int ints;
 	int stat = -1;
 	if ((ohci->hcca->done_head != 0) &&
 	    !(m32_swap (ohci->hcca->done_head) & 0x01)) {
 		ints =  OHCI_INTR_WDH;
 	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
 		ohci->disabled++;
 		err ("%s device removed!", ohci->slot_name);
 		return -1;
 	} else if ((ints &= readl (&regs->intrenable)) == 0) {
 		dbg("hc_interrupt: returning..\n");
 		return 0xff;
 	}
 	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
 	if (ints & OHCI_INTR_RHSC) {
 		got_rhsc = 1;
 		stat = 0xff;
 	}
 	if (ints & OHCI_INTR_UE) {
 		ohci->disabled++;
 		err ("OHCI Unrecoverable Error, controller usb-%s disabled",
 			ohci->slot_name);
 		/* e.g. due to PCI Master/Target Abort */
 #ifdef	DEBUG
 		ohci_dump (ohci, 1);
 #else
 	wait_ms(1);
 #endif
 		/* FIXME: be optimistic, hope that bug won't repeat often. */
 		/* Make some non-interrupt context restart the controller. */
 		/* Count and limit the retries though; either hardware or */
 		/* software errors can go forever... */
 		hc_reset (ohci);
 		return -1;
 	}
 	if (ints & OHCI_INTR_WDH) {
 		wait_ms(1);
 		writel (OHCI_INTR_WDH, &regs->intrdisable);
 		(void)readl (&regs->intrdisable); /* flush */
 		stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
 		writel (OHCI_INTR_WDH, &regs->intrenable);
 		(void)readl (&regs->intrdisable); /* flush */
 	}
 	if (ints & OHCI_INTR_SO) {
 		dbg("USB Schedule overrun\n");
 		writel (OHCI_INTR_SO, &regs->intrenable);
 		stat = -1;
 	}
 	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
 	if (ints & OHCI_INTR_SF) {
 		unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
 		wait_ms(1);
 		writel (OHCI_INTR_SF, &regs->intrdisable);
 		if (ohci->ed_rm_list[frame] != NULL)
 			writel (OHCI_INTR_SF, &regs->intrenable);
 		stat = 0xff;
 	}
 	writel (ints, &regs->intrstatus);
 	return stat;
 }
 /*-------------------------------------------------------------------------*/
 /*-------------------------------------------------------------------------*/
 /* De-allocate all resources.. */
 static void hc_release_ohci (ohci_t *ohci)
 {
 	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
 	if (!ohci->disabled)
 		hc_reset (ohci);
 }
 /*-------------------------------------------------------------------------*/
 /*
  * low level initalisation routine, called from usb.c
  */
 static char ohci_inited = 0;
 int usb_lowlevel_init(void)
 {
 #ifdef CONFIG_PCI_OHCI
 	pci_dev_t pdev;
 #endif
 #ifdef CFG_USB_OHCI_CPU_INIT
 	/* cpu dependant init */
 	if(usb_cpu_init())
 		return -1;
 #endif
 #ifdef CFG_USB_OHCI_BOARD_INIT
 	/*  board dependant init */
 	if(usb_board_init())
 		return -1;
 #endif
 	memset (&gohci, 0, sizeof (ohci_t));
 	/* align the storage */
 	if ((__u32)&ghcca[0] & 0xff) {
 		err("HCCA not aligned!!");
 		return -1;
 	}
 	phcca = &ghcca[0];
 	info("aligned ghcca %p", phcca);
 	memset(&ohci_dev, 0, sizeof(struct ohci_device));
 	if ((__u32)&ohci_dev.ed[0] & 0x7) {
 		err("EDs not aligned!!");
 		return -1;
 	}
 	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
 	if ((__u32)gtd & 0x7) {
 		err("TDs not aligned!!");
 		return -1;
 	}
 	ptd = gtd;
 	gohci.hcca = phcca;
 	memset (phcca, 0, sizeof (struct ohci_hcca));
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
 #ifdef CONFIG_PCI_OHCI
 	pdev = pci_find_devices(ohci_pci_ids, 0);
 	if (pdev != -1) {
 		u16 vid, did;
 		u32 base;
 		pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
 		pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
 		printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
 				vid, did, (pdev >> 16) & 0xff,
 				(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
 		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
 		printf("OHCI regs address 0x%08x\n", base);
 		gohci.regs = (struct ohci_regs *)base;
 	} else
 		return -1;
 #else
 	gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
 #endif
 	gohci.flags = 0;
 	gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
 	if (hc_reset (&gohci) < 0) {
 		hc_release_ohci (&gohci);
 		err ("can't reset usb-%s", gohci.slot_name);
 #ifdef CFG_USB_OHCI_BOARD_INIT
 		/* board dependant cleanup */
 		usb_board_init_fail();
 #endif
 #ifdef CFG_USB_OHCI_CPU_INIT
 		/* cpu dependant cleanup */
 		usb_cpu_init_fail();
 #endif
 		return -1;
 	}
 	/* FIXME this is a second HC reset; why?? */
 	/* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
 	   wait_ms(10); */
 	if (hc_start (&gohci) < 0) {
 		err ("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci (&gohci);
 		/* Initialization failed */
 #ifdef CFG_USB_OHCI_BOARD_INIT
 		/* board dependant cleanup */
 		usb_board_stop();
 #endif
 #ifdef CFG_USB_OHCI_CPU_INIT
 		/* cpu dependant cleanup */
 		usb_cpu_stop();
 #endif
 		return -1;
 	}
 #ifdef	DEBUG
 	ohci_dump (&gohci, 1);
 #else
 	wait_ms(1);
 #endif
 	ohci_inited = 1;
 	return 0;
 }
 int usb_lowlevel_stop(void)
 {
 	/* this gets called really early - before the controller has */
 	/* even been initialized! */
 	if (!ohci_inited)
 		return 0;
 	/* TODO release any interrupts, etc. */
 	/* call hc_release_ohci() here ? */
 	hc_reset (&gohci);
 #ifdef CFG_USB_OHCI_BOARD_INIT
 	/* board dependant cleanup */
 	if(usb_board_stop())
 		return -1;
 #endif
 #ifdef CFG_USB_OHCI_CPU_INIT
 	/* cpu dependant cleanup */
 	if(usb_cpu_stop())
 		return -1;
 #endif
 	return 0;
 }
 #endif /* CONFIG_USB_OHCI_NEW */

 /*
  * linux/include/asm-arm/arch-at91/hardware.h
  *
  *  Copyright (C) 2003 SAN People
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 #include <asm/sizes.h>
 #ifndef __ASSEMBLY__
 #include "AT91RM9200.h"
-#else
-#include "AT91RM9200_inc.h"
 #endif
 /* Virtual and Physical base address for system peripherals */
 #define AT91_SYS_BASE		0xFFFFF000 /*4K */
 /* Virtual and Physical base addresses of user peripherals */
 #define AT91_SPI_BASE		0xFFFE0000 /*16K */
 #define AT91_SSC2_BASE		0xFFFD8000 /*16K */
 #define AT91_SSC1_BASE		0xFFFD4000 /*16K */
 #define AT91_SSC0_BASE		0xFFFD0000 /*16K */
 #define AT91_USART3_BASE	0xFFFCC000 /*16K */
 #define AT91_USART2_BASE	0xFFFC8000 /*16K */
 #define AT91_USART1_BASE	0xFFFC4000 /*16K */
 #define AT91_USART0_BASE	0xFFFC0000 /*16K */
 #define AT91_EMAC_BASE		0xFFFBC000 /*16K */
 #define AT91_TWI_BASE		0xFFFB8000 /*16K */
 #define AT91_MCI_BASE		0xFFFB4000 /*16K */
 #define AT91_UDP_BASE		0xFFFB0000 /*16K */
 #define AT91_TCB1_BASE		0xFFFA4000 /*16K */
 #define AT91_TCB0_BASE		0xFFFA0000 /*16K */
 #define AT91_USB_HOST_BASE	0x00300000
 /*
  * Where in virtual memory the IO devices (timers, system controllers
  * and so on)
  */
 #define AT91_IO_BASE		0xF0000000	/* Virt/Phys Address of IO */
 /* FLASH */
 #define AT91_FLASH_BASE		0x10000000	/* NCS0 */
 /* SDRAM */
 #define AT91_SDRAM_BASE		0x20000000	/* NCS1 */
 /* SmartMedia */
 #define AT91_SMARTMEDIA_BASE	0x40000000	/* NCS3 */
 /* Definition of interrupt priority levels */
 #define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
 #define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
 #define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
 #define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
 #define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
 #define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
 #define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
 #define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
 #endif