Eric Lee / smarc-uboot

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Commit ed3c64f1acc958a7ee1a97f23acda13105f89443

Authored by Ramon Fried
Committed by Joe Hershberger
1 parent 5a1899f9fc
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

net: macb: add dma_burst_length config 

GEM support higher DMA burst writes/reads than the default (4).
add configuration structure with dma burst length so it could be
applied later to DMA configuration.

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 1 changed file with 21 additions and 1 deletions Inline Diff

1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2005-2006 Atmel Corporation 3 * Copyright (C) 2005-2006 Atmel Corporation
4 */ 4 */
5 #include <common.h> 5 #include <common.h>
6 #include <clk.h> 6 #include <clk.h>
7 #include <dm.h> 7 #include <dm.h>
8 8
9 /* 9 /*
10 * The u-boot networking stack is a little weird. It seems like the 10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any 11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those 12 * regard to the hardware that's supposed to actually receive those
13 * packets. 13 * packets.
14 * 14 *
15 * The MACB receives packets into 128-byte receive buffers, so the 15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll 16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet 17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it. 18 * wraps around the DMA ring so that we have to copy it.
19 * 19 *
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer 21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of 22 * and one TX buffer, each of which can hold a ethernet packet of
23 * maximum size. 23 * maximum size.
24 * 24 *
25 * For some reason, the networking core unconditionally specifies a 25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called 26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any 27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here... 28 * core modifications here...
29 */ 29 */
30 30
31 #include <net.h> 31 #include <net.h>
32 #ifndef CONFIG_DM_ETH 32 #ifndef CONFIG_DM_ETH
33 #include <netdev.h> 33 #include <netdev.h>
34 #endif 34 #endif
35 #include <malloc.h> 35 #include <malloc.h>
36 #include <miiphy.h> 36 #include <miiphy.h>
37 37
38 #include <linux/mii.h> 38 #include <linux/mii.h>
39 #include <asm/io.h> 39 #include <asm/io.h>
40 #include <asm/dma-mapping.h> 40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h> 41 #include <asm/arch/clk.h>
42 #include <linux/errno.h> 42 #include <linux/errno.h>
43 43
44 #include "macb.h" 44 #include "macb.h"
45 45
46 DECLARE_GLOBAL_DATA_PTR; 46 DECLARE_GLOBAL_DATA_PTR;
47 47
48 #define MACB_RX_BUFFER_SIZE 4096 48 #define MACB_RX_BUFFER_SIZE 4096
49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50 #define MACB_TX_RING_SIZE 16 50 #define MACB_TX_RING_SIZE 16
51 #define MACB_TX_TIMEOUT 1000 51 #define MACB_TX_TIMEOUT 1000
52 #define MACB_AUTONEG_TIMEOUT 5000000 52 #define MACB_AUTONEG_TIMEOUT 5000000
53 53
54 #ifdef CONFIG_MACB_ZYNQ 54 #ifdef CONFIG_MACB_ZYNQ
55 /* INCR4 AHB bursts */ 55 /* INCR4 AHB bursts */
56 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004 56 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
57 /* Use full configured addressable space (8 Kb) */ 57 /* Use full configured addressable space (8 Kb) */
58 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300 58 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
59 /* Use full configured addressable space (4 Kb) */ 59 /* Use full configured addressable space (4 Kb) */
60 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400 60 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
61 /* Set RXBUF with use of 128 byte */ 61 /* Set RXBUF with use of 128 byte */
62 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000 62 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
63 #define MACB_ZYNQ_GEM_DMACR_INIT \ 63 #define MACB_ZYNQ_GEM_DMACR_INIT \
64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \ 64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \ 65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \ 66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_RXBUF) 67 MACB_ZYNQ_GEM_DMACR_RXBUF)
68 #endif 68 #endif
69 69
70 struct macb_dma_desc { 70 struct macb_dma_desc {
71 u32 addr; 71 u32 addr;
72 u32 ctrl; 72 u32 ctrl;
73 }; 73 };
74 74
75 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 75 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
76 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 76 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
77 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 77 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
78 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 78 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
79 79
80 #define RXBUF_FRMLEN_MASK 0x00000fff 80 #define RXBUF_FRMLEN_MASK 0x00000fff
81 #define TXBUF_FRMLEN_MASK 0x000007ff 81 #define TXBUF_FRMLEN_MASK 0x000007ff
82 82
83 struct macb_device { 83 struct macb_device {
84 void *regs; 84 void *regs;
85 unsigned int dma_burst_length;
85 86
86 unsigned int rx_tail; 87 unsigned int rx_tail;
87 unsigned int tx_head; 88 unsigned int tx_head;
88 unsigned int tx_tail; 89 unsigned int tx_tail;
89 unsigned int next_rx_tail; 90 unsigned int next_rx_tail;
90 bool wrapped; 91 bool wrapped;
91 92
92 void *rx_buffer; 93 void *rx_buffer;
93 void *tx_buffer; 94 void *tx_buffer;
94 struct macb_dma_desc *rx_ring; 95 struct macb_dma_desc *rx_ring;
95 struct macb_dma_desc *tx_ring; 96 struct macb_dma_desc *tx_ring;
96 97
97 unsigned long rx_buffer_dma; 98 unsigned long rx_buffer_dma;
98 unsigned long rx_ring_dma; 99 unsigned long rx_ring_dma;
99 unsigned long tx_ring_dma; 100 unsigned long tx_ring_dma;
100 101
101 struct macb_dma_desc *dummy_desc; 102 struct macb_dma_desc *dummy_desc;
102 unsigned long dummy_desc_dma; 103 unsigned long dummy_desc_dma;
103 104
104 const struct device *dev; 105 const struct device *dev;
105 #ifndef CONFIG_DM_ETH 106 #ifndef CONFIG_DM_ETH
106 struct eth_device netdev; 107 struct eth_device netdev;
107 #endif 108 #endif
108 unsigned short phy_addr; 109 unsigned short phy_addr;
109 struct mii_dev *bus; 110 struct mii_dev *bus;
110 #ifdef CONFIG_PHYLIB 111 #ifdef CONFIG_PHYLIB
111 struct phy_device *phydev; 112 struct phy_device *phydev;
112 #endif 113 #endif
113 114
114 #ifdef CONFIG_DM_ETH 115 #ifdef CONFIG_DM_ETH
115 #ifdef CONFIG_CLK 116 #ifdef CONFIG_CLK
116 unsigned long pclk_rate; 117 unsigned long pclk_rate;
117 #endif 118 #endif
118 phy_interface_t phy_interface; 119 phy_interface_t phy_interface;
119 #endif 120 #endif
120 }; 121 };
122
123 struct macb_config {
124 unsigned int dma_burst_length;
125 };
126
121 #ifndef CONFIG_DM_ETH 127 #ifndef CONFIG_DM_ETH
122 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 128 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
123 #endif 129 #endif
124 130
125 static int macb_is_gem(struct macb_device *macb) 131 static int macb_is_gem(struct macb_device *macb)
126 { 132 {
127 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2; 133 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
128 } 134 }
129 135
130 #ifndef cpu_is_sama5d2 136 #ifndef cpu_is_sama5d2
131 #define cpu_is_sama5d2() 0 137 #define cpu_is_sama5d2() 0
132 #endif 138 #endif
133 139
134 #ifndef cpu_is_sama5d4 140 #ifndef cpu_is_sama5d4
135 #define cpu_is_sama5d4() 0 141 #define cpu_is_sama5d4() 0
136 #endif 142 #endif
137 143
138 static int gem_is_gigabit_capable(struct macb_device *macb) 144 static int gem_is_gigabit_capable(struct macb_device *macb)
139 { 145 {
140 /* 146 /*
141 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 147 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
142 * configured to support only 10/100. 148 * configured to support only 10/100.
143 */ 149 */
144 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 150 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
145 } 151 }
146 152
147 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 153 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
148 { 154 {
149 unsigned long netctl; 155 unsigned long netctl;
150 unsigned long netstat; 156 unsigned long netstat;
151 unsigned long frame; 157 unsigned long frame;
152 158
153 netctl = macb_readl(macb, NCR); 159 netctl = macb_readl(macb, NCR);
154 netctl |= MACB_BIT(MPE); 160 netctl |= MACB_BIT(MPE);
155 macb_writel(macb, NCR, netctl); 161 macb_writel(macb, NCR, netctl);
156 162
157 frame = (MACB_BF(SOF, 1) 163 frame = (MACB_BF(SOF, 1)
158 | MACB_BF(RW, 1) 164 | MACB_BF(RW, 1)
159 | MACB_BF(PHYA, macb->phy_addr) 165 | MACB_BF(PHYA, macb->phy_addr)
160 | MACB_BF(REGA, reg) 166 | MACB_BF(REGA, reg)
161 | MACB_BF(CODE, 2) 167 | MACB_BF(CODE, 2)
162 | MACB_BF(DATA, value)); 168 | MACB_BF(DATA, value));
163 macb_writel(macb, MAN, frame); 169 macb_writel(macb, MAN, frame);
164 170
165 do { 171 do {
166 netstat = macb_readl(macb, NSR); 172 netstat = macb_readl(macb, NSR);
167 } while (!(netstat & MACB_BIT(IDLE))); 173 } while (!(netstat & MACB_BIT(IDLE)));
168 174
169 netctl = macb_readl(macb, NCR); 175 netctl = macb_readl(macb, NCR);
170 netctl &= ~MACB_BIT(MPE); 176 netctl &= ~MACB_BIT(MPE);
171 macb_writel(macb, NCR, netctl); 177 macb_writel(macb, NCR, netctl);
172 } 178 }
173 179
174 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 180 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
175 { 181 {
176 unsigned long netctl; 182 unsigned long netctl;
177 unsigned long netstat; 183 unsigned long netstat;
178 unsigned long frame; 184 unsigned long frame;
179 185
180 netctl = macb_readl(macb, NCR); 186 netctl = macb_readl(macb, NCR);
181 netctl |= MACB_BIT(MPE); 187 netctl |= MACB_BIT(MPE);
182 macb_writel(macb, NCR, netctl); 188 macb_writel(macb, NCR, netctl);
183 189
184 frame = (MACB_BF(SOF, 1) 190 frame = (MACB_BF(SOF, 1)
185 | MACB_BF(RW, 2) 191 | MACB_BF(RW, 2)
186 | MACB_BF(PHYA, macb->phy_addr) 192 | MACB_BF(PHYA, macb->phy_addr)
187 | MACB_BF(REGA, reg) 193 | MACB_BF(REGA, reg)
188 | MACB_BF(CODE, 2)); 194 | MACB_BF(CODE, 2));
189 macb_writel(macb, MAN, frame); 195 macb_writel(macb, MAN, frame);
190 196
191 do { 197 do {
192 netstat = macb_readl(macb, NSR); 198 netstat = macb_readl(macb, NSR);
193 } while (!(netstat & MACB_BIT(IDLE))); 199 } while (!(netstat & MACB_BIT(IDLE)));
194 200
195 frame = macb_readl(macb, MAN); 201 frame = macb_readl(macb, MAN);
196 202
197 netctl = macb_readl(macb, NCR); 203 netctl = macb_readl(macb, NCR);
198 netctl &= ~MACB_BIT(MPE); 204 netctl &= ~MACB_BIT(MPE);
199 macb_writel(macb, NCR, netctl); 205 macb_writel(macb, NCR, netctl);
200 206
201 return MACB_BFEXT(DATA, frame); 207 return MACB_BFEXT(DATA, frame);
202 } 208 }
203 209
204 void __weak arch_get_mdio_control(const char *name) 210 void __weak arch_get_mdio_control(const char *name)
205 { 211 {
206 return; 212 return;
207 } 213 }
208 214
209 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 215 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
210 216
211 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) 217 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
212 { 218 {
213 u16 value = 0; 219 u16 value = 0;
214 #ifdef CONFIG_DM_ETH 220 #ifdef CONFIG_DM_ETH
215 struct udevice *dev = eth_get_dev_by_name(bus->name); 221 struct udevice *dev = eth_get_dev_by_name(bus->name);
216 struct macb_device *macb = dev_get_priv(dev); 222 struct macb_device *macb = dev_get_priv(dev);
217 #else 223 #else
218 struct eth_device *dev = eth_get_dev_by_name(bus->name); 224 struct eth_device *dev = eth_get_dev_by_name(bus->name);
219 struct macb_device *macb = to_macb(dev); 225 struct macb_device *macb = to_macb(dev);
220 #endif 226 #endif
221 227
222 if (macb->phy_addr != phy_adr) 228 if (macb->phy_addr != phy_adr)
223 return -1; 229 return -1;
224 230
225 arch_get_mdio_control(bus->name); 231 arch_get_mdio_control(bus->name);
226 value = macb_mdio_read(macb, reg); 232 value = macb_mdio_read(macb, reg);
227 233
228 return value; 234 return value;
229 } 235 }
230 236
231 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, 237 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
232 u16 value) 238 u16 value)
233 { 239 {
234 #ifdef CONFIG_DM_ETH 240 #ifdef CONFIG_DM_ETH
235 struct udevice *dev = eth_get_dev_by_name(bus->name); 241 struct udevice *dev = eth_get_dev_by_name(bus->name);
236 struct macb_device *macb = dev_get_priv(dev); 242 struct macb_device *macb = dev_get_priv(dev);
237 #else 243 #else
238 struct eth_device *dev = eth_get_dev_by_name(bus->name); 244 struct eth_device *dev = eth_get_dev_by_name(bus->name);
239 struct macb_device *macb = to_macb(dev); 245 struct macb_device *macb = to_macb(dev);
240 #endif 246 #endif
241 247
242 if (macb->phy_addr != phy_adr) 248 if (macb->phy_addr != phy_adr)
243 return -1; 249 return -1;
244 250
245 arch_get_mdio_control(bus->name); 251 arch_get_mdio_control(bus->name);
246 macb_mdio_write(macb, reg, value); 252 macb_mdio_write(macb, reg, value);
247 253
248 return 0; 254 return 0;
249 } 255 }
250 #endif 256 #endif
251 257
252 #define RX 1 258 #define RX 1
253 #define TX 0 259 #define TX 0
254 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 260 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
255 { 261 {
256 if (rx) 262 if (rx)
257 invalidate_dcache_range(macb->rx_ring_dma, 263 invalidate_dcache_range(macb->rx_ring_dma,
258 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE, 264 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
259 PKTALIGN)); 265 PKTALIGN));
260 else 266 else
261 invalidate_dcache_range(macb->tx_ring_dma, 267 invalidate_dcache_range(macb->tx_ring_dma,
262 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE, 268 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
263 PKTALIGN)); 269 PKTALIGN));
264 } 270 }
265 271
266 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 272 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
267 { 273 {
268 if (rx) 274 if (rx)
269 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 275 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
270 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN)); 276 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
271 else 277 else
272 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 278 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
273 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN)); 279 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
274 } 280 }
275 281
276 static inline void macb_flush_rx_buffer(struct macb_device *macb) 282 static inline void macb_flush_rx_buffer(struct macb_device *macb)
277 { 283 {
278 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 284 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
279 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 285 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
280 } 286 }
281 287
282 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 288 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
283 { 289 {
284 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 290 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
285 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 291 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
286 } 292 }
287 293
288 #if defined(CONFIG_CMD_NET) 294 #if defined(CONFIG_CMD_NET)
289 295
290 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 296 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
291 int length) 297 int length)
292 { 298 {
293 unsigned long paddr, ctrl; 299 unsigned long paddr, ctrl;
294 unsigned int tx_head = macb->tx_head; 300 unsigned int tx_head = macb->tx_head;
295 int i; 301 int i;
296 302
297 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 303 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
298 304
299 ctrl = length & TXBUF_FRMLEN_MASK; 305 ctrl = length & TXBUF_FRMLEN_MASK;
300 ctrl |= MACB_BIT(TX_LAST); 306 ctrl |= MACB_BIT(TX_LAST);
301 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 307 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
302 ctrl |= MACB_BIT(TX_WRAP); 308 ctrl |= MACB_BIT(TX_WRAP);
303 macb->tx_head = 0; 309 macb->tx_head = 0;
304 } else { 310 } else {
305 macb->tx_head++; 311 macb->tx_head++;
306 } 312 }
307 313
308 macb->tx_ring[tx_head].ctrl = ctrl; 314 macb->tx_ring[tx_head].ctrl = ctrl;
309 macb->tx_ring[tx_head].addr = paddr; 315 macb->tx_ring[tx_head].addr = paddr;
310 barrier(); 316 barrier();
311 macb_flush_ring_desc(macb, TX); 317 macb_flush_ring_desc(macb, TX);
312 /* Do we need check paddr and length is dcache line aligned? */ 318 /* Do we need check paddr and length is dcache line aligned? */
313 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 319 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
314 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 320 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
315 321
316 /* 322 /*
317 * I guess this is necessary because the networking core may 323 * I guess this is necessary because the networking core may
318 * re-use the transmit buffer as soon as we return... 324 * re-use the transmit buffer as soon as we return...
319 */ 325 */
320 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 326 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
321 barrier(); 327 barrier();
322 macb_invalidate_ring_desc(macb, TX); 328 macb_invalidate_ring_desc(macb, TX);
323 ctrl = macb->tx_ring[tx_head].ctrl; 329 ctrl = macb->tx_ring[tx_head].ctrl;
324 if (ctrl & MACB_BIT(TX_USED)) 330 if (ctrl & MACB_BIT(TX_USED))
325 break; 331 break;
326 udelay(1); 332 udelay(1);
327 } 333 }
328 334
329 dma_unmap_single(packet, length, paddr); 335 dma_unmap_single(packet, length, paddr);
330 336
331 if (i <= MACB_TX_TIMEOUT) { 337 if (i <= MACB_TX_TIMEOUT) {
332 if (ctrl & MACB_BIT(TX_UNDERRUN)) 338 if (ctrl & MACB_BIT(TX_UNDERRUN))
333 printf("%s: TX underrun\n", name); 339 printf("%s: TX underrun\n", name);
334 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) 340 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
335 printf("%s: TX buffers exhausted in mid frame\n", name); 341 printf("%s: TX buffers exhausted in mid frame\n", name);
336 } else { 342 } else {
337 printf("%s: TX timeout\n", name); 343 printf("%s: TX timeout\n", name);
338 } 344 }
339 345
340 /* No one cares anyway */ 346 /* No one cares anyway */
341 return 0; 347 return 0;
342 } 348 }
343 349
344 static void reclaim_rx_buffers(struct macb_device *macb, 350 static void reclaim_rx_buffers(struct macb_device *macb,
345 unsigned int new_tail) 351 unsigned int new_tail)
346 { 352 {
347 unsigned int i; 353 unsigned int i;
348 354
349 i = macb->rx_tail; 355 i = macb->rx_tail;
350 356
351 macb_invalidate_ring_desc(macb, RX); 357 macb_invalidate_ring_desc(macb, RX);
352 while (i > new_tail) { 358 while (i > new_tail) {
353 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED); 359 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
354 i++; 360 i++;
355 if (i > MACB_RX_RING_SIZE) 361 if (i > MACB_RX_RING_SIZE)
356 i = 0; 362 i = 0;
357 } 363 }
358 364
359 while (i < new_tail) { 365 while (i < new_tail) {
360 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED); 366 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
361 i++; 367 i++;
362 } 368 }
363 369
364 barrier(); 370 barrier();
365 macb_flush_ring_desc(macb, RX); 371 macb_flush_ring_desc(macb, RX);
366 macb->rx_tail = new_tail; 372 macb->rx_tail = new_tail;
367 } 373 }
368 374
369 static int _macb_recv(struct macb_device *macb, uchar **packetp) 375 static int _macb_recv(struct macb_device *macb, uchar **packetp)
370 { 376 {
371 unsigned int next_rx_tail = macb->next_rx_tail; 377 unsigned int next_rx_tail = macb->next_rx_tail;
372 void *buffer; 378 void *buffer;
373 int length; 379 int length;
374 u32 status; 380 u32 status;
375 381
376 macb->wrapped = false; 382 macb->wrapped = false;
377 for (;;) { 383 for (;;) {
378 macb_invalidate_ring_desc(macb, RX); 384 macb_invalidate_ring_desc(macb, RX);
379 385
380 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED))) 386 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
381 return -EAGAIN; 387 return -EAGAIN;
382 388
383 status = macb->rx_ring[next_rx_tail].ctrl; 389 status = macb->rx_ring[next_rx_tail].ctrl;
384 if (status & MACB_BIT(RX_SOF)) { 390 if (status & MACB_BIT(RX_SOF)) {
385 if (next_rx_tail != macb->rx_tail) 391 if (next_rx_tail != macb->rx_tail)
386 reclaim_rx_buffers(macb, next_rx_tail); 392 reclaim_rx_buffers(macb, next_rx_tail);
387 macb->wrapped = false; 393 macb->wrapped = false;
388 } 394 }
389 395
390 if (status & MACB_BIT(RX_EOF)) { 396 if (status & MACB_BIT(RX_EOF)) {
391 buffer = macb->rx_buffer + 128 * macb->rx_tail; 397 buffer = macb->rx_buffer + 128 * macb->rx_tail;
392 length = status & RXBUF_FRMLEN_MASK; 398 length = status & RXBUF_FRMLEN_MASK;
393 399
394 macb_invalidate_rx_buffer(macb); 400 macb_invalidate_rx_buffer(macb);
395 if (macb->wrapped) { 401 if (macb->wrapped) {
396 unsigned int headlen, taillen; 402 unsigned int headlen, taillen;
397 403
398 headlen = 128 * (MACB_RX_RING_SIZE 404 headlen = 128 * (MACB_RX_RING_SIZE
399 - macb->rx_tail); 405 - macb->rx_tail);
400 taillen = length - headlen; 406 taillen = length - headlen;
401 memcpy((void *)net_rx_packets[0], 407 memcpy((void *)net_rx_packets[0],
402 buffer, headlen); 408 buffer, headlen);
403 memcpy((void *)net_rx_packets[0] + headlen, 409 memcpy((void *)net_rx_packets[0] + headlen,
404 macb->rx_buffer, taillen); 410 macb->rx_buffer, taillen);
405 *packetp = (void *)net_rx_packets[0]; 411 *packetp = (void *)net_rx_packets[0];
406 } else { 412 } else {
407 *packetp = buffer; 413 *packetp = buffer;
408 } 414 }
409 415
410 if (++next_rx_tail >= MACB_RX_RING_SIZE) 416 if (++next_rx_tail >= MACB_RX_RING_SIZE)
411 next_rx_tail = 0; 417 next_rx_tail = 0;
412 macb->next_rx_tail = next_rx_tail; 418 macb->next_rx_tail = next_rx_tail;
413 return length; 419 return length;
414 } else { 420 } else {
415 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 421 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
416 macb->wrapped = true; 422 macb->wrapped = true;
417 next_rx_tail = 0; 423 next_rx_tail = 0;
418 } 424 }
419 } 425 }
420 barrier(); 426 barrier();
421 } 427 }
422 } 428 }
423 429
424 static void macb_phy_reset(struct macb_device *macb, const char *name) 430 static void macb_phy_reset(struct macb_device *macb, const char *name)
425 { 431 {
426 int i; 432 int i;
427 u16 status, adv; 433 u16 status, adv;
428 434
429 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 435 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
430 macb_mdio_write(macb, MII_ADVERTISE, adv); 436 macb_mdio_write(macb, MII_ADVERTISE, adv);
431 printf("%s: Starting autonegotiation...\n", name); 437 printf("%s: Starting autonegotiation...\n", name);
432 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 438 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
433 | BMCR_ANRESTART)); 439 | BMCR_ANRESTART));
434 440
435 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 441 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
436 status = macb_mdio_read(macb, MII_BMSR); 442 status = macb_mdio_read(macb, MII_BMSR);
437 if (status & BMSR_ANEGCOMPLETE) 443 if (status & BMSR_ANEGCOMPLETE)
438 break; 444 break;
439 udelay(100); 445 udelay(100);
440 } 446 }
441 447
442 if (status & BMSR_ANEGCOMPLETE) 448 if (status & BMSR_ANEGCOMPLETE)
443 printf("%s: Autonegotiation complete\n", name); 449 printf("%s: Autonegotiation complete\n", name);
444 else 450 else
445 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 451 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
446 name, status); 452 name, status);
447 } 453 }
448 454
449 static int macb_phy_find(struct macb_device *macb, const char *name) 455 static int macb_phy_find(struct macb_device *macb, const char *name)
450 { 456 {
451 int i; 457 int i;
452 u16 phy_id; 458 u16 phy_id;
453 459
454 /* Search for PHY... */ 460 /* Search for PHY... */
455 for (i = 0; i < 32; i++) { 461 for (i = 0; i < 32; i++) {
456 macb->phy_addr = i; 462 macb->phy_addr = i;
457 phy_id = macb_mdio_read(macb, MII_PHYSID1); 463 phy_id = macb_mdio_read(macb, MII_PHYSID1);
458 if (phy_id != 0xffff) { 464 if (phy_id != 0xffff) {
459 printf("%s: PHY present at %d\n", name, i); 465 printf("%s: PHY present at %d\n", name, i);
460 return 0; 466 return 0;
461 } 467 }
462 } 468 }
463 469
464 /* PHY isn't up to snuff */ 470 /* PHY isn't up to snuff */
465 printf("%s: PHY not found\n", name); 471 printf("%s: PHY not found\n", name);
466 472
467 return -ENODEV; 473 return -ENODEV;
468 } 474 }
469 475
470 /** 476 /**
471 * macb_linkspd_cb - Linkspeed change callback function 477 * macb_linkspd_cb - Linkspeed change callback function
472 * @dev/@regs: MACB udevice (DM version) or 478 * @dev/@regs: MACB udevice (DM version) or
473 * Base Register of MACB devices (non-DM version) 479 * Base Register of MACB devices (non-DM version)
474 * @speed: Linkspeed 480 * @speed: Linkspeed
475 * Returns 0 when operation success and negative errno number 481 * Returns 0 when operation success and negative errno number
476 * when operation failed. 482 * when operation failed.
477 */ 483 */
478 #ifdef CONFIG_DM_ETH 484 #ifdef CONFIG_DM_ETH
479 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) 485 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
480 { 486 {
481 #ifdef CONFIG_CLK 487 #ifdef CONFIG_CLK
482 struct clk tx_clk; 488 struct clk tx_clk;
483 ulong rate; 489 ulong rate;
484 int ret; 490 int ret;
485 491
486 /* 492 /*
487 * "tx_clk" is an optional clock source for MACB. 493 * "tx_clk" is an optional clock source for MACB.
488 * Ignore if it does not exist in DT. 494 * Ignore if it does not exist in DT.
489 */ 495 */
490 ret = clk_get_by_name(dev, "tx_clk", &tx_clk); 496 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
491 if (ret) 497 if (ret)
492 return 0; 498 return 0;
493 499
494 switch (speed) { 500 switch (speed) {
495 case _10BASET: 501 case _10BASET:
496 rate = 2500000; /* 2.5 MHz */ 502 rate = 2500000; /* 2.5 MHz */
497 break; 503 break;
498 case _100BASET: 504 case _100BASET:
499 rate = 25000000; /* 25 MHz */ 505 rate = 25000000; /* 25 MHz */
500 break; 506 break;
501 case _1000BASET: 507 case _1000BASET:
502 rate = 125000000; /* 125 MHz */ 508 rate = 125000000; /* 125 MHz */
503 break; 509 break;
504 default: 510 default:
505 /* does not change anything */ 511 /* does not change anything */
506 return 0; 512 return 0;
507 } 513 }
508 514
509 if (tx_clk.dev) { 515 if (tx_clk.dev) {
510 ret = clk_set_rate(&tx_clk, rate); 516 ret = clk_set_rate(&tx_clk, rate);
511 if (ret) 517 if (ret)
512 return ret; 518 return ret;
513 } 519 }
514 #endif 520 #endif
515 521
516 return 0; 522 return 0;
517 } 523 }
518 #else 524 #else
519 int __weak macb_linkspd_cb(void *regs, unsigned int speed) 525 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
520 { 526 {
521 return 0; 527 return 0;
522 } 528 }
523 #endif 529 #endif
524 530
525 #ifdef CONFIG_DM_ETH 531 #ifdef CONFIG_DM_ETH
526 static int macb_phy_init(struct udevice *dev, const char *name) 532 static int macb_phy_init(struct udevice *dev, const char *name)
527 #else 533 #else
528 static int macb_phy_init(struct macb_device *macb, const char *name) 534 static int macb_phy_init(struct macb_device *macb, const char *name)
529 #endif 535 #endif
530 { 536 {
531 #ifdef CONFIG_DM_ETH 537 #ifdef CONFIG_DM_ETH
532 struct macb_device *macb = dev_get_priv(dev); 538 struct macb_device *macb = dev_get_priv(dev);
533 #endif 539 #endif
534 u32 ncfgr; 540 u32 ncfgr;
535 u16 phy_id, status, adv, lpa; 541 u16 phy_id, status, adv, lpa;
536 int media, speed, duplex; 542 int media, speed, duplex;
537 int ret; 543 int ret;
538 int i; 544 int i;
539 545
540 arch_get_mdio_control(name); 546 arch_get_mdio_control(name);
541 /* Auto-detect phy_addr */ 547 /* Auto-detect phy_addr */
542 ret = macb_phy_find(macb, name); 548 ret = macb_phy_find(macb, name);
543 if (ret) 549 if (ret)
544 return ret; 550 return ret;
545 551
546 /* Check if the PHY is up to snuff... */ 552 /* Check if the PHY is up to snuff... */
547 phy_id = macb_mdio_read(macb, MII_PHYSID1); 553 phy_id = macb_mdio_read(macb, MII_PHYSID1);
548 if (phy_id == 0xffff) { 554 if (phy_id == 0xffff) {
549 printf("%s: No PHY present\n", name); 555 printf("%s: No PHY present\n", name);
550 return -ENODEV; 556 return -ENODEV;
551 } 557 }
552 558
553 #ifdef CONFIG_PHYLIB 559 #ifdef CONFIG_PHYLIB
554 #ifdef CONFIG_DM_ETH 560 #ifdef CONFIG_DM_ETH
555 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, 561 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
556 macb->phy_interface); 562 macb->phy_interface);
557 #else 563 #else
558 /* need to consider other phy interface mode */ 564 /* need to consider other phy interface mode */
559 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 565 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
560 PHY_INTERFACE_MODE_RGMII); 566 PHY_INTERFACE_MODE_RGMII);
561 #endif 567 #endif
562 if (!macb->phydev) { 568 if (!macb->phydev) {
563 printf("phy_connect failed\n"); 569 printf("phy_connect failed\n");
564 return -ENODEV; 570 return -ENODEV;
565 } 571 }
566 572
567 phy_config(macb->phydev); 573 phy_config(macb->phydev);
568 #endif 574 #endif
569 575
570 status = macb_mdio_read(macb, MII_BMSR); 576 status = macb_mdio_read(macb, MII_BMSR);
571 if (!(status & BMSR_LSTATUS)) { 577 if (!(status & BMSR_LSTATUS)) {
572 /* Try to re-negotiate if we don't have link already. */ 578 /* Try to re-negotiate if we don't have link already. */
573 macb_phy_reset(macb, name); 579 macb_phy_reset(macb, name);
574 580
575 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 581 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
576 status = macb_mdio_read(macb, MII_BMSR); 582 status = macb_mdio_read(macb, MII_BMSR);
577 if (status & BMSR_LSTATUS) { 583 if (status & BMSR_LSTATUS) {
578 /* 584 /*
579 * Delay a bit after the link is established, 585 * Delay a bit after the link is established,
580 * so that the next xfer does not fail 586 * so that the next xfer does not fail
581 */ 587 */
582 mdelay(10); 588 mdelay(10);
583 break; 589 break;
584 } 590 }
585 udelay(100); 591 udelay(100);
586 } 592 }
587 } 593 }
588 594
589 if (!(status & BMSR_LSTATUS)) { 595 if (!(status & BMSR_LSTATUS)) {
590 printf("%s: link down (status: 0x%04x)\n", 596 printf("%s: link down (status: 0x%04x)\n",
591 name, status); 597 name, status);
592 return -ENETDOWN; 598 return -ENETDOWN;
593 } 599 }
594 600
595 /* First check for GMAC and that it is GiB capable */ 601 /* First check for GMAC and that it is GiB capable */
596 if (gem_is_gigabit_capable(macb)) { 602 if (gem_is_gigabit_capable(macb)) {
597 lpa = macb_mdio_read(macb, MII_LPA); 603 lpa = macb_mdio_read(macb, MII_LPA);
598 604
599 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL | 605 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
600 LPA_1000XHALF)) { 606 LPA_1000XHALF)) {
601 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ? 607 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
602 1 : 0); 608 1 : 0);
603 609
604 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 610 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
605 name, 611 name,
606 duplex ? "full" : "half", 612 duplex ? "full" : "half",
607 lpa); 613 lpa);
608 614
609 ncfgr = macb_readl(macb, NCFGR); 615 ncfgr = macb_readl(macb, NCFGR);
610 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 616 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
611 ncfgr |= GEM_BIT(GBE); 617 ncfgr |= GEM_BIT(GBE);
612 618
613 if (duplex) 619 if (duplex)
614 ncfgr |= MACB_BIT(FD); 620 ncfgr |= MACB_BIT(FD);
615 621
616 macb_writel(macb, NCFGR, ncfgr); 622 macb_writel(macb, NCFGR, ncfgr);
617 623
618 #ifdef CONFIG_DM_ETH 624 #ifdef CONFIG_DM_ETH
619 ret = macb_linkspd_cb(dev, _1000BASET); 625 ret = macb_linkspd_cb(dev, _1000BASET);
620 #else 626 #else
621 ret = macb_linkspd_cb(macb->regs, _1000BASET); 627 ret = macb_linkspd_cb(macb->regs, _1000BASET);
622 #endif 628 #endif
623 if (ret) 629 if (ret)
624 return ret; 630 return ret;
625 631
626 return 0; 632 return 0;
627 } 633 }
628 } 634 }
629 635
630 /* fall back for EMAC checking */ 636 /* fall back for EMAC checking */
631 adv = macb_mdio_read(macb, MII_ADVERTISE); 637 adv = macb_mdio_read(macb, MII_ADVERTISE);
632 lpa = macb_mdio_read(macb, MII_LPA); 638 lpa = macb_mdio_read(macb, MII_LPA);
633 media = mii_nway_result(lpa & adv); 639 media = mii_nway_result(lpa & adv);
634 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 640 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
635 ? 1 : 0); 641 ? 1 : 0);
636 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 642 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
637 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 643 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
638 name, 644 name,
639 speed ? "100" : "10", 645 speed ? "100" : "10",
640 duplex ? "full" : "half", 646 duplex ? "full" : "half",
641 lpa); 647 lpa);
642 648
643 ncfgr = macb_readl(macb, NCFGR); 649 ncfgr = macb_readl(macb, NCFGR);
644 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 650 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
645 if (speed) { 651 if (speed) {
646 ncfgr |= MACB_BIT(SPD); 652 ncfgr |= MACB_BIT(SPD);
647 #ifdef CONFIG_DM_ETH 653 #ifdef CONFIG_DM_ETH
648 ret = macb_linkspd_cb(dev, _100BASET); 654 ret = macb_linkspd_cb(dev, _100BASET);
649 #else 655 #else
650 ret = macb_linkspd_cb(macb->regs, _100BASET); 656 ret = macb_linkspd_cb(macb->regs, _100BASET);
651 #endif 657 #endif
652 } else { 658 } else {
653 #ifdef CONFIG_DM_ETH 659 #ifdef CONFIG_DM_ETH
654 ret = macb_linkspd_cb(dev, _10BASET); 660 ret = macb_linkspd_cb(dev, _10BASET);
655 #else 661 #else
656 ret = macb_linkspd_cb(macb->regs, _10BASET); 662 ret = macb_linkspd_cb(macb->regs, _10BASET);
657 #endif 663 #endif
658 } 664 }
659 665
660 if (ret) 666 if (ret)
661 return ret; 667 return ret;
662 668
663 if (duplex) 669 if (duplex)
664 ncfgr |= MACB_BIT(FD); 670 ncfgr |= MACB_BIT(FD);
665 macb_writel(macb, NCFGR, ncfgr); 671 macb_writel(macb, NCFGR, ncfgr);
666 672
667 return 0; 673 return 0;
668 } 674 }
669 675
670 static int gmac_init_multi_queues(struct macb_device *macb) 676 static int gmac_init_multi_queues(struct macb_device *macb)
671 { 677 {
672 int i, num_queues = 1; 678 int i, num_queues = 1;
673 u32 queue_mask; 679 u32 queue_mask;
674 680
675 /* bit 0 is never set but queue 0 always exists */ 681 /* bit 0 is never set but queue 0 always exists */
676 queue_mask = gem_readl(macb, DCFG6) & 0xff; 682 queue_mask = gem_readl(macb, DCFG6) & 0xff;
677 queue_mask |= 0x1; 683 queue_mask |= 0x1;
678 684
679 for (i = 1; i < MACB_MAX_QUEUES; i++) 685 for (i = 1; i < MACB_MAX_QUEUES; i++)
680 if (queue_mask & (1 << i)) 686 if (queue_mask & (1 << i))
681 num_queues++; 687 num_queues++;
682 688
683 macb->dummy_desc->ctrl = MACB_BIT(TX_USED); 689 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
684 macb->dummy_desc->addr = 0; 690 macb->dummy_desc->addr = 0;
685 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 691 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
686 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); 692 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
687 693
688 for (i = 1; i < num_queues; i++) 694 for (i = 1; i < num_queues; i++)
689 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 695 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
690 696
691 return 0; 697 return 0;
692 } 698 }
693 699
694 #ifdef CONFIG_DM_ETH 700 #ifdef CONFIG_DM_ETH
695 static int _macb_init(struct udevice *dev, const char *name) 701 static int _macb_init(struct udevice *dev, const char *name)
696 #else 702 #else
697 static int _macb_init(struct macb_device *macb, const char *name) 703 static int _macb_init(struct macb_device *macb, const char *name)
698 #endif 704 #endif
699 { 705 {
700 #ifdef CONFIG_DM_ETH 706 #ifdef CONFIG_DM_ETH
701 struct macb_device *macb = dev_get_priv(dev); 707 struct macb_device *macb = dev_get_priv(dev);
702 #endif 708 #endif
703 unsigned long paddr; 709 unsigned long paddr;
704 int ret; 710 int ret;
705 int i; 711 int i;
706 712
707 /* 713 /*
708 * macb_halt should have been called at some point before now, 714 * macb_halt should have been called at some point before now,
709 * so we'll assume the controller is idle. 715 * so we'll assume the controller is idle.
710 */ 716 */
711 717
712 /* initialize DMA descriptors */ 718 /* initialize DMA descriptors */
713 paddr = macb->rx_buffer_dma; 719 paddr = macb->rx_buffer_dma;
714 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 720 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
715 if (i == (MACB_RX_RING_SIZE - 1)) 721 if (i == (MACB_RX_RING_SIZE - 1))
716 paddr |= MACB_BIT(RX_WRAP); 722 paddr |= MACB_BIT(RX_WRAP);
717 macb->rx_ring[i].addr = paddr; 723 macb->rx_ring[i].addr = paddr;
718 macb->rx_ring[i].ctrl = 0; 724 macb->rx_ring[i].ctrl = 0;
719 paddr += 128; 725 paddr += 128;
720 } 726 }
721 macb_flush_ring_desc(macb, RX); 727 macb_flush_ring_desc(macb, RX);
722 macb_flush_rx_buffer(macb); 728 macb_flush_rx_buffer(macb);
723 729
724 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 730 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
725 macb->tx_ring[i].addr = 0; 731 macb->tx_ring[i].addr = 0;
726 if (i == (MACB_TX_RING_SIZE - 1)) 732 if (i == (MACB_TX_RING_SIZE - 1))
727 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) | 733 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
728 MACB_BIT(TX_WRAP); 734 MACB_BIT(TX_WRAP);
729 else 735 else
730 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); 736 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
731 } 737 }
732 macb_flush_ring_desc(macb, TX); 738 macb_flush_ring_desc(macb, TX);
733 739
734 macb->rx_tail = 0; 740 macb->rx_tail = 0;
735 macb->tx_head = 0; 741 macb->tx_head = 0;
736 macb->tx_tail = 0; 742 macb->tx_tail = 0;
737 macb->next_rx_tail = 0; 743 macb->next_rx_tail = 0;
738 744
739 #ifdef CONFIG_MACB_ZYNQ 745 #ifdef CONFIG_MACB_ZYNQ
740 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); 746 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
741 #endif 747 #endif
742 748
743 macb_writel(macb, RBQP, macb->rx_ring_dma); 749 macb_writel(macb, RBQP, macb->rx_ring_dma);
744 macb_writel(macb, TBQP, macb->tx_ring_dma); 750 macb_writel(macb, TBQP, macb->tx_ring_dma);
745 751
746 if (macb_is_gem(macb)) { 752 if (macb_is_gem(macb)) {
747 /* Check the multi queue and initialize the queue for tx */ 753 /* Check the multi queue and initialize the queue for tx */
748 gmac_init_multi_queues(macb); 754 gmac_init_multi_queues(macb);
749 755
750 /* 756 /*
751 * When the GMAC IP with GE feature, this bit is used to 757 * When the GMAC IP with GE feature, this bit is used to
752 * select interface between RGMII and GMII. 758 * select interface between RGMII and GMII.
753 * When the GMAC IP without GE feature, this bit is used 759 * When the GMAC IP without GE feature, this bit is used
754 * to select interface between RMII and MII. 760 * to select interface between RMII and MII.
755 */ 761 */
756 #ifdef CONFIG_DM_ETH 762 #ifdef CONFIG_DM_ETH
757 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) || 763 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
758 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII)) 764 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
759 gem_writel(macb, USRIO, GEM_BIT(RGMII)); 765 gem_writel(macb, USRIO, GEM_BIT(RGMII));
760 else 766 else
761 gem_writel(macb, USRIO, 0); 767 gem_writel(macb, USRIO, 0);
762 768
763 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) { 769 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
764 unsigned int ncfgr = macb_readl(macb, NCFGR); 770 unsigned int ncfgr = macb_readl(macb, NCFGR);
765 771
766 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 772 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
767 macb_writel(macb, NCFGR, ncfgr); 773 macb_writel(macb, NCFGR, ncfgr);
768 } 774 }
769 #else 775 #else
770 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 776 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
771 gem_writel(macb, USRIO, GEM_BIT(RGMII)); 777 gem_writel(macb, USRIO, GEM_BIT(RGMII));
772 #else 778 #else
773 gem_writel(macb, USRIO, 0); 779 gem_writel(macb, USRIO, 0);
774 #endif 780 #endif
775 #endif 781 #endif
776 } else { 782 } else {
777 /* choose RMII or MII mode. This depends on the board */ 783 /* choose RMII or MII mode. This depends on the board */
778 #ifdef CONFIG_DM_ETH 784 #ifdef CONFIG_DM_ETH
779 #ifdef CONFIG_AT91FAMILY 785 #ifdef CONFIG_AT91FAMILY
780 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 786 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
781 macb_writel(macb, USRIO, 787 macb_writel(macb, USRIO,
782 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 788 MACB_BIT(RMII) | MACB_BIT(CLKEN));
783 } else { 789 } else {
784 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 790 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
785 } 791 }
786 #else 792 #else
787 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 793 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
788 macb_writel(macb, USRIO, 0); 794 macb_writel(macb, USRIO, 0);
789 else 795 else
790 macb_writel(macb, USRIO, MACB_BIT(MII)); 796 macb_writel(macb, USRIO, MACB_BIT(MII));
791 #endif 797 #endif
792 #else 798 #else
793 #ifdef CONFIG_RMII 799 #ifdef CONFIG_RMII
794 #ifdef CONFIG_AT91FAMILY 800 #ifdef CONFIG_AT91FAMILY
795 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 801 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
796 #else 802 #else
797 macb_writel(macb, USRIO, 0); 803 macb_writel(macb, USRIO, 0);
798 #endif 804 #endif
799 #else 805 #else
800 #ifdef CONFIG_AT91FAMILY 806 #ifdef CONFIG_AT91FAMILY
801 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 807 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
802 #else 808 #else
803 macb_writel(macb, USRIO, MACB_BIT(MII)); 809 macb_writel(macb, USRIO, MACB_BIT(MII));
804 #endif 810 #endif
805 #endif /* CONFIG_RMII */ 811 #endif /* CONFIG_RMII */
806 #endif 812 #endif
807 } 813 }
808 814
809 #ifdef CONFIG_DM_ETH 815 #ifdef CONFIG_DM_ETH
810 ret = macb_phy_init(dev, name); 816 ret = macb_phy_init(dev, name);
811 #else 817 #else
812 ret = macb_phy_init(macb, name); 818 ret = macb_phy_init(macb, name);
813 #endif 819 #endif
814 if (ret) 820 if (ret)
815 return ret; 821 return ret;
816 822
817 /* Enable TX and RX */ 823 /* Enable TX and RX */
818 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 824 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
819 825
820 return 0; 826 return 0;
821 } 827 }
822 828
823 static void _macb_halt(struct macb_device *macb) 829 static void _macb_halt(struct macb_device *macb)
824 { 830 {
825 u32 ncr, tsr; 831 u32 ncr, tsr;
826 832
827 /* Halt the controller and wait for any ongoing transmission to end. */ 833 /* Halt the controller and wait for any ongoing transmission to end. */
828 ncr = macb_readl(macb, NCR); 834 ncr = macb_readl(macb, NCR);
829 ncr |= MACB_BIT(THALT); 835 ncr |= MACB_BIT(THALT);
830 macb_writel(macb, NCR, ncr); 836 macb_writel(macb, NCR, ncr);
831 837
832 do { 838 do {
833 tsr = macb_readl(macb, TSR); 839 tsr = macb_readl(macb, TSR);
834 } while (tsr & MACB_BIT(TGO)); 840 } while (tsr & MACB_BIT(TGO));
835 841
836 /* Disable TX and RX, and clear statistics */ 842 /* Disable TX and RX, and clear statistics */
837 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 843 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
838 } 844 }
839 845
840 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 846 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
841 { 847 {
842 u32 hwaddr_bottom; 848 u32 hwaddr_bottom;
843 u16 hwaddr_top; 849 u16 hwaddr_top;
844 850
845 /* set hardware address */ 851 /* set hardware address */
846 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 852 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
847 enetaddr[2] << 16 | enetaddr[3] << 24; 853 enetaddr[2] << 16 | enetaddr[3] << 24;
848 macb_writel(macb, SA1B, hwaddr_bottom); 854 macb_writel(macb, SA1B, hwaddr_bottom);
849 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 855 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
850 macb_writel(macb, SA1T, hwaddr_top); 856 macb_writel(macb, SA1T, hwaddr_top);
851 return 0; 857 return 0;
852 } 858 }
853 859
854 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 860 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
855 { 861 {
856 u32 config; 862 u32 config;
857 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 863 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
858 unsigned long macb_hz = macb->pclk_rate; 864 unsigned long macb_hz = macb->pclk_rate;
859 #else 865 #else
860 unsigned long macb_hz = get_macb_pclk_rate(id); 866 unsigned long macb_hz = get_macb_pclk_rate(id);
861 #endif 867 #endif
862 868
863 if (macb_hz < 20000000) 869 if (macb_hz < 20000000)
864 config = MACB_BF(CLK, MACB_CLK_DIV8); 870 config = MACB_BF(CLK, MACB_CLK_DIV8);
865 else if (macb_hz < 40000000) 871 else if (macb_hz < 40000000)
866 config = MACB_BF(CLK, MACB_CLK_DIV16); 872 config = MACB_BF(CLK, MACB_CLK_DIV16);
867 else if (macb_hz < 80000000) 873 else if (macb_hz < 80000000)
868 config = MACB_BF(CLK, MACB_CLK_DIV32); 874 config = MACB_BF(CLK, MACB_CLK_DIV32);
869 else 875 else
870 config = MACB_BF(CLK, MACB_CLK_DIV64); 876 config = MACB_BF(CLK, MACB_CLK_DIV64);
871 877
872 return config; 878 return config;
873 } 879 }
874 880
875 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 881 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
876 { 882 {
877 u32 config; 883 u32 config;
878 884
879 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 885 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
880 unsigned long macb_hz = macb->pclk_rate; 886 unsigned long macb_hz = macb->pclk_rate;
881 #else 887 #else
882 unsigned long macb_hz = get_macb_pclk_rate(id); 888 unsigned long macb_hz = get_macb_pclk_rate(id);
883 #endif 889 #endif
884 890
885 if (macb_hz < 20000000) 891 if (macb_hz < 20000000)
886 config = GEM_BF(CLK, GEM_CLK_DIV8); 892 config = GEM_BF(CLK, GEM_CLK_DIV8);
887 else if (macb_hz < 40000000) 893 else if (macb_hz < 40000000)
888 config = GEM_BF(CLK, GEM_CLK_DIV16); 894 config = GEM_BF(CLK, GEM_CLK_DIV16);
889 else if (macb_hz < 80000000) 895 else if (macb_hz < 80000000)
890 config = GEM_BF(CLK, GEM_CLK_DIV32); 896 config = GEM_BF(CLK, GEM_CLK_DIV32);
891 else if (macb_hz < 120000000) 897 else if (macb_hz < 120000000)
892 config = GEM_BF(CLK, GEM_CLK_DIV48); 898 config = GEM_BF(CLK, GEM_CLK_DIV48);
893 else if (macb_hz < 160000000) 899 else if (macb_hz < 160000000)
894 config = GEM_BF(CLK, GEM_CLK_DIV64); 900 config = GEM_BF(CLK, GEM_CLK_DIV64);
895 else if (macb_hz < 240000000) 901 else if (macb_hz < 240000000)
896 config = GEM_BF(CLK, GEM_CLK_DIV96); 902 config = GEM_BF(CLK, GEM_CLK_DIV96);
897 else if (macb_hz < 320000000) 903 else if (macb_hz < 320000000)
898 config = GEM_BF(CLK, GEM_CLK_DIV128); 904 config = GEM_BF(CLK, GEM_CLK_DIV128);
899 else 905 else
900 config = GEM_BF(CLK, GEM_CLK_DIV224); 906 config = GEM_BF(CLK, GEM_CLK_DIV224);
901 907
902 return config; 908 return config;
903 } 909 }
904 910
905 /* 911 /*
906 * Get the DMA bus width field of the network configuration register that we 912 * Get the DMA bus width field of the network configuration register that we
907 * should program. We find the width from decoding the design configuration 913 * should program. We find the width from decoding the design configuration
908 * register to find the maximum supported data bus width. 914 * register to find the maximum supported data bus width.
909 */ 915 */
910 static u32 macb_dbw(struct macb_device *macb) 916 static u32 macb_dbw(struct macb_device *macb)
911 { 917 {
912 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 918 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
913 case 4: 919 case 4:
914 return GEM_BF(DBW, GEM_DBW128); 920 return GEM_BF(DBW, GEM_DBW128);
915 case 2: 921 case 2:
916 return GEM_BF(DBW, GEM_DBW64); 922 return GEM_BF(DBW, GEM_DBW64);
917 case 1: 923 case 1:
918 default: 924 default:
919 return GEM_BF(DBW, GEM_DBW32); 925 return GEM_BF(DBW, GEM_DBW32);
920 } 926 }
921 } 927 }
922 928
923 static void _macb_eth_initialize(struct macb_device *macb) 929 static void _macb_eth_initialize(struct macb_device *macb)
924 { 930 {
925 int id = 0; /* This is not used by functions we call */ 931 int id = 0; /* This is not used by functions we call */
926 u32 ncfgr; 932 u32 ncfgr;
927 933
928 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 934 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
929 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 935 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
930 &macb->rx_buffer_dma); 936 &macb->rx_buffer_dma);
931 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 937 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
932 &macb->rx_ring_dma); 938 &macb->rx_ring_dma);
933 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 939 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
934 &macb->tx_ring_dma); 940 &macb->tx_ring_dma);
935 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 941 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
936 &macb->dummy_desc_dma); 942 &macb->dummy_desc_dma);
937 943
938 /* 944 /*
939 * Do some basic initialization so that we at least can talk 945 * Do some basic initialization so that we at least can talk
940 * to the PHY 946 * to the PHY
941 */ 947 */
942 if (macb_is_gem(macb)) { 948 if (macb_is_gem(macb)) {
943 ncfgr = gem_mdc_clk_div(id, macb); 949 ncfgr = gem_mdc_clk_div(id, macb);
944 ncfgr |= macb_dbw(macb); 950 ncfgr |= macb_dbw(macb);
945 } else { 951 } else {
946 ncfgr = macb_mdc_clk_div(id, macb); 952 ncfgr = macb_mdc_clk_div(id, macb);
947 } 953 }
948 954
949 macb_writel(macb, NCFGR, ncfgr); 955 macb_writel(macb, NCFGR, ncfgr);
950 } 956 }
951 957
952 #ifndef CONFIG_DM_ETH 958 #ifndef CONFIG_DM_ETH
953 static int macb_send(struct eth_device *netdev, void *packet, int length) 959 static int macb_send(struct eth_device *netdev, void *packet, int length)
954 { 960 {
955 struct macb_device *macb = to_macb(netdev); 961 struct macb_device *macb = to_macb(netdev);
956 962
957 return _macb_send(macb, netdev->name, packet, length); 963 return _macb_send(macb, netdev->name, packet, length);
958 } 964 }
959 965
960 static int macb_recv(struct eth_device *netdev) 966 static int macb_recv(struct eth_device *netdev)
961 { 967 {
962 struct macb_device *macb = to_macb(netdev); 968 struct macb_device *macb = to_macb(netdev);
963 uchar *packet; 969 uchar *packet;
964 int length; 970 int length;
965 971
966 macb->wrapped = false; 972 macb->wrapped = false;
967 for (;;) { 973 for (;;) {
968 macb->next_rx_tail = macb->rx_tail; 974 macb->next_rx_tail = macb->rx_tail;
969 length = _macb_recv(macb, &packet); 975 length = _macb_recv(macb, &packet);
970 if (length >= 0) { 976 if (length >= 0) {
971 net_process_received_packet(packet, length); 977 net_process_received_packet(packet, length);
972 reclaim_rx_buffers(macb, macb->next_rx_tail); 978 reclaim_rx_buffers(macb, macb->next_rx_tail);
973 } else { 979 } else {
974 return length; 980 return length;
975 } 981 }
976 } 982 }
977 } 983 }
978 984
979 static int macb_init(struct eth_device *netdev, bd_t *bd) 985 static int macb_init(struct eth_device *netdev, bd_t *bd)
980 { 986 {
981 struct macb_device *macb = to_macb(netdev); 987 struct macb_device *macb = to_macb(netdev);
982 988
983 return _macb_init(macb, netdev->name); 989 return _macb_init(macb, netdev->name);
984 } 990 }
985 991
986 static void macb_halt(struct eth_device *netdev) 992 static void macb_halt(struct eth_device *netdev)
987 { 993 {
988 struct macb_device *macb = to_macb(netdev); 994 struct macb_device *macb = to_macb(netdev);
989 995
990 return _macb_halt(macb); 996 return _macb_halt(macb);
991 } 997 }
992 998
993 static int macb_write_hwaddr(struct eth_device *netdev) 999 static int macb_write_hwaddr(struct eth_device *netdev)
994 { 1000 {
995 struct macb_device *macb = to_macb(netdev); 1001 struct macb_device *macb = to_macb(netdev);
996 1002
997 return _macb_write_hwaddr(macb, netdev->enetaddr); 1003 return _macb_write_hwaddr(macb, netdev->enetaddr);
998 } 1004 }
999 1005
1000 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 1006 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1001 { 1007 {
1002 struct macb_device *macb; 1008 struct macb_device *macb;
1003 struct eth_device *netdev; 1009 struct eth_device *netdev;
1004 1010
1005 macb = malloc(sizeof(struct macb_device)); 1011 macb = malloc(sizeof(struct macb_device));
1006 if (!macb) { 1012 if (!macb) {
1007 printf("Error: Failed to allocate memory for MACB%d\n", id); 1013 printf("Error: Failed to allocate memory for MACB%d\n", id);
1008 return -1; 1014 return -1;
1009 } 1015 }
1010 memset(macb, 0, sizeof(struct macb_device)); 1016 memset(macb, 0, sizeof(struct macb_device));
1011 1017
1012 netdev = &macb->netdev; 1018 netdev = &macb->netdev;
1013 1019
1014 macb->regs = regs; 1020 macb->regs = regs;
1015 macb->phy_addr = phy_addr; 1021 macb->phy_addr = phy_addr;
1016 1022
1017 if (macb_is_gem(macb)) 1023 if (macb_is_gem(macb))
1018 sprintf(netdev->name, "gmac%d", id); 1024 sprintf(netdev->name, "gmac%d", id);
1019 else 1025 else
1020 sprintf(netdev->name, "macb%d", id); 1026 sprintf(netdev->name, "macb%d", id);
1021 1027
1022 netdev->init = macb_init; 1028 netdev->init = macb_init;
1023 netdev->halt = macb_halt; 1029 netdev->halt = macb_halt;
1024 netdev->send = macb_send; 1030 netdev->send = macb_send;
1025 netdev->recv = macb_recv; 1031 netdev->recv = macb_recv;
1026 netdev->write_hwaddr = macb_write_hwaddr; 1032 netdev->write_hwaddr = macb_write_hwaddr;
1027 1033
1028 _macb_eth_initialize(macb); 1034 _macb_eth_initialize(macb);
1029 1035
1030 eth_register(netdev); 1036 eth_register(netdev);
1031 1037
1032 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1038 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1033 int retval; 1039 int retval;
1034 struct mii_dev *mdiodev = mdio_alloc(); 1040 struct mii_dev *mdiodev = mdio_alloc();
1035 if (!mdiodev) 1041 if (!mdiodev)
1036 return -ENOMEM; 1042 return -ENOMEM;
1037 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); 1043 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1038 mdiodev->read = macb_miiphy_read; 1044 mdiodev->read = macb_miiphy_read;
1039 mdiodev->write = macb_miiphy_write; 1045 mdiodev->write = macb_miiphy_write;
1040 1046
1041 retval = mdio_register(mdiodev); 1047 retval = mdio_register(mdiodev);
1042 if (retval < 0) 1048 if (retval < 0)
1043 return retval; 1049 return retval;
1044 macb->bus = miiphy_get_dev_by_name(netdev->name); 1050 macb->bus = miiphy_get_dev_by_name(netdev->name);
1045 #endif 1051 #endif
1046 return 0; 1052 return 0;
1047 } 1053 }
1048 #endif /* !CONFIG_DM_ETH */ 1054 #endif /* !CONFIG_DM_ETH */
1049 1055
1050 #ifdef CONFIG_DM_ETH 1056 #ifdef CONFIG_DM_ETH
1051 1057
1052 static int macb_start(struct udevice *dev) 1058 static int macb_start(struct udevice *dev)
1053 { 1059 {
1054 return _macb_init(dev, dev->name); 1060 return _macb_init(dev, dev->name);
1055 } 1061 }
1056 1062
1057 static int macb_send(struct udevice *dev, void *packet, int length) 1063 static int macb_send(struct udevice *dev, void *packet, int length)
1058 { 1064 {
1059 struct macb_device *macb = dev_get_priv(dev); 1065 struct macb_device *macb = dev_get_priv(dev);
1060 1066
1061 return _macb_send(macb, dev->name, packet, length); 1067 return _macb_send(macb, dev->name, packet, length);
1062 } 1068 }
1063 1069
1064 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 1070 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1065 { 1071 {
1066 struct macb_device *macb = dev_get_priv(dev); 1072 struct macb_device *macb = dev_get_priv(dev);
1067 1073
1068 macb->next_rx_tail = macb->rx_tail; 1074 macb->next_rx_tail = macb->rx_tail;
1069 macb->wrapped = false; 1075 macb->wrapped = false;
1070 1076
1071 return _macb_recv(macb, packetp); 1077 return _macb_recv(macb, packetp);
1072 } 1078 }
1073 1079
1074 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 1080 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1075 { 1081 {
1076 struct macb_device *macb = dev_get_priv(dev); 1082 struct macb_device *macb = dev_get_priv(dev);
1077 1083
1078 reclaim_rx_buffers(macb, macb->next_rx_tail); 1084 reclaim_rx_buffers(macb, macb->next_rx_tail);
1079 1085
1080 return 0; 1086 return 0;
1081 } 1087 }
1082 1088
1083 static void macb_stop(struct udevice *dev) 1089 static void macb_stop(struct udevice *dev)
1084 { 1090 {
1085 struct macb_device *macb = dev_get_priv(dev); 1091 struct macb_device *macb = dev_get_priv(dev);
1086 1092
1087 _macb_halt(macb); 1093 _macb_halt(macb);
1088 } 1094 }
1089 1095
1090 static int macb_write_hwaddr(struct udevice *dev) 1096 static int macb_write_hwaddr(struct udevice *dev)
1091 { 1097 {
1092 struct eth_pdata *plat = dev_get_platdata(dev); 1098 struct eth_pdata *plat = dev_get_platdata(dev);
1093 struct macb_device *macb = dev_get_priv(dev); 1099 struct macb_device *macb = dev_get_priv(dev);
1094 1100
1095 return _macb_write_hwaddr(macb, plat->enetaddr); 1101 return _macb_write_hwaddr(macb, plat->enetaddr);
1096 } 1102 }
1097 1103
1098 static const struct eth_ops macb_eth_ops = { 1104 static const struct eth_ops macb_eth_ops = {
1099 .start = macb_start, 1105 .start = macb_start,
1100 .send = macb_send, 1106 .send = macb_send,
1101 .recv = macb_recv, 1107 .recv = macb_recv,
1102 .stop = macb_stop, 1108 .stop = macb_stop,
1103 .free_pkt = macb_free_pkt, 1109 .free_pkt = macb_free_pkt,
1104 .write_hwaddr = macb_write_hwaddr, 1110 .write_hwaddr = macb_write_hwaddr,
1105 }; 1111 };
1106 1112
1107 #ifdef CONFIG_CLK 1113 #ifdef CONFIG_CLK
1108 static int macb_enable_clk(struct udevice *dev) 1114 static int macb_enable_clk(struct udevice *dev)
1109 { 1115 {
1110 struct macb_device *macb = dev_get_priv(dev); 1116 struct macb_device *macb = dev_get_priv(dev);
1111 struct clk clk; 1117 struct clk clk;
1112 ulong clk_rate; 1118 ulong clk_rate;
1113 int ret; 1119 int ret;
1114 1120
1115 ret = clk_get_by_index(dev, 0, &clk); 1121 ret = clk_get_by_index(dev, 0, &clk);
1116 if (ret) 1122 if (ret)
1117 return -EINVAL; 1123 return -EINVAL;
1118 1124
1119 /* 1125 /*
1120 * If clock driver didn't support enable or disable then 1126 * If clock driver didn't support enable or disable then
1121 * we get -ENOSYS from clk_enable(). To handle this, we 1127 * we get -ENOSYS from clk_enable(). To handle this, we
1122 * don't fail for ret == -ENOSYS. 1128 * don't fail for ret == -ENOSYS.
1123 */ 1129 */
1124 ret = clk_enable(&clk); 1130 ret = clk_enable(&clk);
1125 if (ret && ret != -ENOSYS) 1131 if (ret && ret != -ENOSYS)
1126 return ret; 1132 return ret;
1127 1133
1128 clk_rate = clk_get_rate(&clk); 1134 clk_rate = clk_get_rate(&clk);
1129 if (!clk_rate) 1135 if (!clk_rate)
1130 return -EINVAL; 1136 return -EINVAL;
1131 1137
1132 macb->pclk_rate = clk_rate; 1138 macb->pclk_rate = clk_rate;
1133 1139
1134 return 0; 1140 return 0;
1135 } 1141 }
1136 #endif 1142 #endif
1137 1143
1144 static const struct macb_config default_gem_config = {
1145 .dma_burst_length = 16,
1146 };
1147
1138 static int macb_eth_probe(struct udevice *dev) 1148 static int macb_eth_probe(struct udevice *dev)
1139 { 1149 {
1150 const struct macb_config *macb_config;
1140 struct eth_pdata *pdata = dev_get_platdata(dev); 1151 struct eth_pdata *pdata = dev_get_platdata(dev);
1141 struct macb_device *macb = dev_get_priv(dev); 1152 struct macb_device *macb = dev_get_priv(dev);
1142 const char *phy_mode; 1153 const char *phy_mode;
1143 __maybe_unused int ret; 1154 __maybe_unused int ret;
1144 1155
1145 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1156 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1146 NULL); 1157 NULL);
1147 if (phy_mode) 1158 if (phy_mode)
1148 macb->phy_interface = phy_get_interface_by_name(phy_mode); 1159 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1149 if (macb->phy_interface == -1) { 1160 if (macb->phy_interface == -1) {
1150 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1161 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1151 return -EINVAL; 1162 return -EINVAL;
1152 } 1163 }
1153 1164
1154 macb->regs = (void *)pdata->iobase; 1165 macb->regs = (void *)pdata->iobase;
1155 1166
1167 macb_config = (struct macb_config *)dev_get_driver_data(dev);
1168 if (!macb_config)
1169 macb_config = &default_gem_config;
1170
1171 macb->dma_burst_length = macb_config->dma_burst_length;
1156 #ifdef CONFIG_CLK 1172 #ifdef CONFIG_CLK
1157 ret = macb_enable_clk(dev); 1173 ret = macb_enable_clk(dev);
1158 if (ret) 1174 if (ret)
1159 return ret; 1175 return ret;
1160 #endif 1176 #endif
1161 1177
1162 _macb_eth_initialize(macb); 1178 _macb_eth_initialize(macb);
1163 1179
1164 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1180 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1165 macb->bus = mdio_alloc(); 1181 macb->bus = mdio_alloc();
1166 if (!macb->bus) 1182 if (!macb->bus)
1167 return -ENOMEM; 1183 return -ENOMEM;
1168 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); 1184 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1169 macb->bus->read = macb_miiphy_read; 1185 macb->bus->read = macb_miiphy_read;
1170 macb->bus->write = macb_miiphy_write; 1186 macb->bus->write = macb_miiphy_write;
1171 1187
1172 ret = mdio_register(macb->bus); 1188 ret = mdio_register(macb->bus);
1173 if (ret < 0) 1189 if (ret < 0)
1174 return ret; 1190 return ret;
1175 macb->bus = miiphy_get_dev_by_name(dev->name); 1191 macb->bus = miiphy_get_dev_by_name(dev->name);
1176 #endif 1192 #endif
1177 1193
1178 return 0; 1194 return 0;
1179 } 1195 }
1180 1196
1181 static int macb_eth_remove(struct udevice *dev) 1197 static int macb_eth_remove(struct udevice *dev)
1182 { 1198 {
1183 struct macb_device *macb = dev_get_priv(dev); 1199 struct macb_device *macb = dev_get_priv(dev);
1184 1200
1185 #ifdef CONFIG_PHYLIB 1201 #ifdef CONFIG_PHYLIB
1186 free(macb->phydev); 1202 free(macb->phydev);
1187 #endif 1203 #endif
1188 mdio_unregister(macb->bus); 1204 mdio_unregister(macb->bus);
1189 mdio_free(macb->bus); 1205 mdio_free(macb->bus);
1190 1206
1191 return 0; 1207 return 0;
1192 } 1208 }
1193 1209
1194 /** 1210 /**
1195 * macb_late_eth_ofdata_to_platdata 1211 * macb_late_eth_ofdata_to_platdata
1196 * @dev: udevice struct 1212 * @dev: udevice struct
1197 * Returns 0 when operation success and negative errno number 1213 * Returns 0 when operation success and negative errno number
1198 * when operation failed. 1214 * when operation failed.
1199 */ 1215 */
1200 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev) 1216 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1201 { 1217 {
1202 return 0; 1218 return 0;
1203 } 1219 }
1204 1220
1205 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1221 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1206 { 1222 {
1207 struct eth_pdata *pdata = dev_get_platdata(dev); 1223 struct eth_pdata *pdata = dev_get_platdata(dev);
1208 1224
1209 pdata->iobase = (phys_addr_t)dev_remap_addr(dev); 1225 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1210 if (!pdata->iobase) 1226 if (!pdata->iobase)
1211 return -EINVAL; 1227 return -EINVAL;
1212 1228
1213 return macb_late_eth_ofdata_to_platdata(dev); 1229 return macb_late_eth_ofdata_to_platdata(dev);
1214 } 1230 }
1215 1231
1232 static const struct macb_config sama5d4_config = {
1233 .dma_burst_length = 4,
1234 };
1235
1216 static const struct udevice_id macb_eth_ids[] = { 1236 static const struct udevice_id macb_eth_ids[] = {
1217 { .compatible = "cdns,macb" }, 1237 { .compatible = "cdns,macb" },
1218 { .compatible = "cdns,at91sam9260-macb" }, 1238 { .compatible = "cdns,at91sam9260-macb" },
1219 { .compatible = "atmel,sama5d2-gem" }, 1239 { .compatible = "atmel,sama5d2-gem" },
1220 { .compatible = "atmel,sama5d3-gem" }, 1240 { .compatible = "atmel,sama5d3-gem" },
1221 { .compatible = "atmel,sama5d4-gem" }, 1241 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1222 { .compatible = "cdns,zynq-gem" }, 1242 { .compatible = "cdns,zynq-gem" },
1223 { } 1243 { }
1224 }; 1244 };
1225 1245
1226 U_BOOT_DRIVER(eth_macb) = { 1246 U_BOOT_DRIVER(eth_macb) = {
1227 .name = "eth_macb", 1247 .name = "eth_macb",
1228 .id = UCLASS_ETH, 1248 .id = UCLASS_ETH,
1229 .of_match = macb_eth_ids, 1249 .of_match = macb_eth_ids,
1230 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1250 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1231 .probe = macb_eth_probe, 1251 .probe = macb_eth_probe,
1232 .remove = macb_eth_remove, 1252 .remove = macb_eth_remove,
1233 .ops = &macb_eth_ops, 1253 .ops = &macb_eth_ops,
1234 .priv_auto_alloc_size = sizeof(struct macb_device), 1254 .priv_auto_alloc_size = sizeof(struct macb_device),
1235 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1255 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1236 }; 1256 };
1237 #endif 1257 #endif
1238 1258
1239 #endif 1259 #endif
1240 1260