Eric Lee / smarc-uboot

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Commit f3cac5384074f3c20b5bcbbdbccbe1e2e25ffc76

Authored by Stefan Roese
1 parent c1ab75c7d4
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Invalidate d-cache when used as init-ram 

We need to invalidate the data cache after it has been used as init-ram.

This problem was detected on the lwmon5 update.

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 1 changed file with 5 additions and 0 deletions Inline Diff

arch/powerpc/cpu/ppc4xx/start.S
Diff comments   View file @ f3cac53
1 /* 1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> 4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering 5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC 6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com> 7 * Grant Erickson <gerickson@nuovations.com>
8 * 8 *
9 * See file CREDITS for list of people who contributed to this 9 * See file CREDITS for list of people who contributed to this
10 * project. 10 * project.
11 * 11 *
12 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version. 15 * the License, or (at your option) any later version.
16 * 16 *
17 * This program is distributed in the hope that it will be useful, 17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 * 21 *
22 * You should have received a copy of the GNU General Public License 22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software 23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA 25 * MA 02111-1307 USA
26 */ 26 */
27 /*------------------------------------------------------------------------------+ 27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the 28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below. 29 * GNU General Public License version 2, or under the license below.
30 * 30 *
31 * This source code has been made available to you by IBM on an AS-IS 31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM 32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including 33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either 34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or 35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license. 36 * patent applications is to be implied by the copyright license.
37 * 37 *
38 * Any user of this software should understand that IBM cannot provide 38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for 39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software. 40 * any consequences resulting from the use of this software.
41 * 41 *
42 * Any person who transfers this source code or any derivative work 42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the 43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software. 44 * preceding two paragraphs in the transferred software.
45 * 45 *
46 * COPYRIGHT I B M CORPORATION 1995 46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *------------------------------------------------------------------------------- 48 *-------------------------------------------------------------------------------
49 */ 49 */
50 50
51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards 51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * 52 *
53 * 53 *
54 * The processor starts at 0xfffffffc and the code is executed 54 * The processor starts at 0xfffffffc and the code is executed
55 * from flash/rom. 55 * from flash/rom.
56 * in memory, but as long we don't jump around before relocating. 56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has 57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok. 58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole 59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of 60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap. 61 * the flash somewhere up there in the memorymap.
62 * 62 *
63 * board_init will change CS0 to be positioned at the correct 63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0 64 * address and (s)dram will be positioned at address 0
65 */ 65 */
66 #include <config.h> 66 #include <config.h>
67 #include <ppc4xx.h> 67 #include <ppc4xx.h>
68 #include <timestamp.h> 68 #include <timestamp.h>
69 #include <version.h> 69 #include <version.h>
70 70
71 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 71 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
72 72
73 #include <ppc_asm.tmpl> 73 #include <ppc_asm.tmpl>
74 #include <ppc_defs.h> 74 #include <ppc_defs.h>
75 75
76 #include <asm/cache.h> 76 #include <asm/cache.h>
77 #include <asm/mmu.h> 77 #include <asm/mmu.h>
78 #include <asm/ppc4xx-isram.h> 78 #include <asm/ppc4xx-isram.h>
79 79
80 #ifndef CONFIG_IDENT_STRING 80 #ifndef CONFIG_IDENT_STRING
81 #define CONFIG_IDENT_STRING "" 81 #define CONFIG_IDENT_STRING ""
82 #endif 82 #endif
83 83
84 #ifdef CONFIG_SYS_INIT_DCACHE_CS 84 #ifdef CONFIG_SYS_INIT_DCACHE_CS
85 # if (CONFIG_SYS_INIT_DCACHE_CS == 0) 85 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
86 # define PBxAP PB1AP 86 # define PBxAP PB1AP
87 # define PBxCR PB0CR 87 # define PBxCR PB0CR
88 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) 88 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP 89 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR 90 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
91 # endif 91 # endif
92 # endif 92 # endif
93 # if (CONFIG_SYS_INIT_DCACHE_CS == 1) 93 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
94 # define PBxAP PB1AP 94 # define PBxAP PB1AP
95 # define PBxCR PB1CR 95 # define PBxCR PB1CR
96 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) 96 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP 97 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR 98 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
99 # endif 99 # endif
100 # endif 100 # endif
101 # if (CONFIG_SYS_INIT_DCACHE_CS == 2) 101 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
102 # define PBxAP PB2AP 102 # define PBxAP PB2AP
103 # define PBxCR PB2CR 103 # define PBxCR PB2CR
104 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) 104 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP 105 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR 106 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
107 # endif 107 # endif
108 # endif 108 # endif
109 # if (CONFIG_SYS_INIT_DCACHE_CS == 3) 109 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
110 # define PBxAP PB3AP 110 # define PBxAP PB3AP
111 # define PBxCR PB3CR 111 # define PBxCR PB3CR
112 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) 112 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP 113 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR 114 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
115 # endif 115 # endif
116 # endif 116 # endif
117 # if (CONFIG_SYS_INIT_DCACHE_CS == 4) 117 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
118 # define PBxAP PB4AP 118 # define PBxAP PB4AP
119 # define PBxCR PB4CR 119 # define PBxCR PB4CR
120 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) 120 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP 121 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR 122 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
123 # endif 123 # endif
124 # endif 124 # endif
125 # if (CONFIG_SYS_INIT_DCACHE_CS == 5) 125 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
126 # define PBxAP PB5AP 126 # define PBxAP PB5AP
127 # define PBxCR PB5CR 127 # define PBxCR PB5CR
128 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) 128 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP 129 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR 130 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
131 # endif 131 # endif
132 # endif 132 # endif
133 # if (CONFIG_SYS_INIT_DCACHE_CS == 6) 133 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
134 # define PBxAP PB6AP 134 # define PBxAP PB6AP
135 # define PBxCR PB6CR 135 # define PBxCR PB6CR
136 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) 136 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP 137 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR 138 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
139 # endif 139 # endif
140 # endif 140 # endif
141 # if (CONFIG_SYS_INIT_DCACHE_CS == 7) 141 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
142 # define PBxAP PB7AP 142 # define PBxAP PB7AP
143 # define PBxCR PB7CR 143 # define PBxCR PB7CR
144 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) 144 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP 145 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR 146 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
147 # endif 147 # endif
148 # endif 148 # endif
149 # ifndef PBxAP_VAL 149 # ifndef PBxAP_VAL
150 # define PBxAP_VAL 0 150 # define PBxAP_VAL 0
151 # endif 151 # endif
152 # ifndef PBxCR_VAL 152 # ifndef PBxCR_VAL
153 # define PBxCR_VAL 0 153 # define PBxCR_VAL 0
154 # endif 154 # endif
155 /* 155 /*
156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB 156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
157 * used as temporary stack pointer for the primordial stack 157 * used as temporary stack pointer for the primordial stack
158 */ 158 */
159 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR 159 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ 160 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
161 EBC_BXAP_TWT_ENCODE(7) | \ 161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \ 162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \ 163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \ 164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \ 165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \ 166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \ 167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \ 168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \ 169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \ 170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \ 171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED) 172 EBC_BXAP_PEN_DISABLED)
173 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ 173 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR 174 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ 175 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
176 EBC_BXCR_BS_64MB | \ 176 EBC_BXCR_BS_64MB | \
177 EBC_BXCR_BU_RW | \ 177 EBC_BXCR_BU_RW | \
178 EBC_BXCR_BW_16BIT) 178 EBC_BXCR_BW_16BIT)
179 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ 179 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180 # ifndef CONFIG_SYS_INIT_RAM_PATTERN 180 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
181 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD 181 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
182 # endif 182 # endif
183 #endif /* CONFIG_SYS_INIT_DCACHE_CS */ 183 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
184 184
185 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) 185 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! 186 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
187 #endif 187 #endif
188 188
189 /* 189 /*
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions 190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering 191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. 192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
193 */ 193 */
194 #if !defined(CONFIG_SYS_FLASH_BASE) 194 #if !defined(CONFIG_SYS_FLASH_BASE)
195 /* If not already defined, set it to the "last" 128MByte region */ 195 /* If not already defined, set it to the "last" 128MByte region */
196 # define CONFIG_SYS_FLASH_BASE 0xf8000000 196 # define CONFIG_SYS_FLASH_BASE 0xf8000000
197 #endif 197 #endif
198 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) 198 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199 # define CONFIG_SYS_ICACHE_SACR_VALUE \ 199 # define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ 200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ 201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) 202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ 203 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
204 204
205 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) 205 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206 # define CONFIG_SYS_DCACHE_SACR_VALUE \ 206 # define CONFIG_SYS_DCACHE_SACR_VALUE \
207 (0x00000000) 207 (0x00000000)
208 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ 208 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
209 209
210 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH) 210 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
211 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */ 211 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
212 #endif 212 #endif
213 213
214 #define function_prolog(func_name) .text; \ 214 #define function_prolog(func_name) .text; \
215 .align 2; \ 215 .align 2; \
216 .globl func_name; \ 216 .globl func_name; \
217 func_name: 217 func_name:
218 #define function_epilog(func_name) .type func_name,@function; \ 218 #define function_epilog(func_name) .type func_name,@function; \
219 .size func_name,.-func_name 219 .size func_name,.-func_name
220 220
221 /* We don't want the MMU yet. 221 /* We don't want the MMU yet.
222 */ 222 */
223 #undef MSR_KERNEL 223 #undef MSR_KERNEL
224 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 224 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
225 225
226 226
227 .extern ext_bus_cntlr_init 227 .extern ext_bus_cntlr_init
228 #ifdef CONFIG_NAND_U_BOOT 228 #ifdef CONFIG_NAND_U_BOOT
229 .extern reconfig_tlb0 229 .extern reconfig_tlb0
230 #endif 230 #endif
231 231
232 /* 232 /*
233 * Set up GOT: Global Offset Table 233 * Set up GOT: Global Offset Table
234 * 234 *
235 * Use r12 to access the GOT 235 * Use r12 to access the GOT
236 */ 236 */
237 #if !defined(CONFIG_NAND_SPL) 237 #if !defined(CONFIG_NAND_SPL)
238 START_GOT 238 START_GOT
239 GOT_ENTRY(_GOT2_TABLE_) 239 GOT_ENTRY(_GOT2_TABLE_)
240 GOT_ENTRY(_FIXUP_TABLE_) 240 GOT_ENTRY(_FIXUP_TABLE_)
241 241
242 GOT_ENTRY(_start) 242 GOT_ENTRY(_start)
243 GOT_ENTRY(_start_of_vectors) 243 GOT_ENTRY(_start_of_vectors)
244 GOT_ENTRY(_end_of_vectors) 244 GOT_ENTRY(_end_of_vectors)
245 GOT_ENTRY(transfer_to_handler) 245 GOT_ENTRY(transfer_to_handler)
246 246
247 GOT_ENTRY(__init_end) 247 GOT_ENTRY(__init_end)
248 GOT_ENTRY(_end) 248 GOT_ENTRY(_end)
249 GOT_ENTRY(__bss_start) 249 GOT_ENTRY(__bss_start)
250 END_GOT 250 END_GOT
251 #endif /* CONFIG_NAND_SPL */ 251 #endif /* CONFIG_NAND_SPL */
252 252
253 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 253 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
254 /* 254 /*
255 * NAND U-Boot image is started from offset 0 255 * NAND U-Boot image is started from offset 0
256 */ 256 */
257 .text 257 .text
258 #if defined(CONFIG_440) 258 #if defined(CONFIG_440)
259 bl reconfig_tlb0 259 bl reconfig_tlb0
260 #endif 260 #endif
261 GET_GOT 261 GET_GOT
262 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 262 bl cpu_init_f /* run low-level CPU init code (from Flash) */
263 bl board_init_f 263 bl board_init_f
264 #endif 264 #endif
265 265
266 #if defined(CONFIG_SYS_RAMBOOT) 266 #if defined(CONFIG_SYS_RAMBOOT)
267 /* 267 /*
268 * 4xx RAM-booting U-Boot image is started from offset 0 268 * 4xx RAM-booting U-Boot image is started from offset 0
269 */ 269 */
270 .text 270 .text
271 bl _start_440 271 bl _start_440
272 #endif 272 #endif
273 273
274 /* 274 /*
275 * 440 Startup -- on reset only the top 4k of the effective 275 * 440 Startup -- on reset only the top 4k of the effective
276 * address space is mapped in by an entry in the instruction 276 * address space is mapped in by an entry in the instruction
277 * and data shadow TLB. The .bootpg section is located in the 277 * and data shadow TLB. The .bootpg section is located in the
278 * top 4k & does only what's necessary to map in the the rest 278 * top 4k & does only what's necessary to map in the the rest
279 * of the boot rom. Once the boot rom is mapped in we can 279 * of the boot rom. Once the boot rom is mapped in we can
280 * proceed with normal startup. 280 * proceed with normal startup.
281 * 281 *
282 * NOTE: CS0 only covers the top 2MB of the effective address 282 * NOTE: CS0 only covers the top 2MB of the effective address
283 * space after reset. 283 * space after reset.
284 */ 284 */
285 285
286 #if defined(CONFIG_440) 286 #if defined(CONFIG_440)
287 #if !defined(CONFIG_NAND_SPL) 287 #if !defined(CONFIG_NAND_SPL)
288 .section .bootpg,"ax" 288 .section .bootpg,"ax"
289 #endif 289 #endif
290 .globl _start_440 290 .globl _start_440
291 291
292 /**************************************************************************/ 292 /**************************************************************************/
293 _start_440: 293 _start_440:
294 /*--------------------------------------------------------------------+ 294 /*--------------------------------------------------------------------+
295 | 440EPX BUP Change - Hardware team request 295 | 440EPX BUP Change - Hardware team request
296 +--------------------------------------------------------------------*/ 296 +--------------------------------------------------------------------*/
297 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 297 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
298 sync 298 sync
299 nop 299 nop
300 nop 300 nop
301 #endif 301 #endif
302 /*----------------------------------------------------------------+ 302 /*----------------------------------------------------------------+
303 | Core bug fix. Clear the esr 303 | Core bug fix. Clear the esr
304 +-----------------------------------------------------------------*/ 304 +-----------------------------------------------------------------*/
305 li r0,0 305 li r0,0
306 mtspr SPRN_ESR,r0 306 mtspr SPRN_ESR,r0
307 /*----------------------------------------------------------------*/ 307 /*----------------------------------------------------------------*/
308 /* Clear and set up some registers. */ 308 /* Clear and set up some registers. */
309 /*----------------------------------------------------------------*/ 309 /*----------------------------------------------------------------*/
310 iccci r0,r0 /* NOTE: operands not used for 440 */ 310 iccci r0,r0 /* NOTE: operands not used for 440 */
311 dccci r0,r0 /* NOTE: operands not used for 440 */ 311 dccci r0,r0 /* NOTE: operands not used for 440 */
312 sync 312 sync
313 li r0,0 313 li r0,0
314 mtspr SPRN_SRR0,r0 314 mtspr SPRN_SRR0,r0
315 mtspr SPRN_SRR1,r0 315 mtspr SPRN_SRR1,r0
316 mtspr SPRN_CSRR0,r0 316 mtspr SPRN_CSRR0,r0
317 mtspr SPRN_CSRR1,r0 317 mtspr SPRN_CSRR1,r0
318 /* NOTE: 440GX adds machine check status regs */ 318 /* NOTE: 440GX adds machine check status regs */
319 #if defined(CONFIG_440) && !defined(CONFIG_440GP) 319 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
320 mtspr SPRN_MCSRR0,r0 320 mtspr SPRN_MCSRR0,r0
321 mtspr SPRN_MCSRR1,r0 321 mtspr SPRN_MCSRR1,r0
322 mfspr r1,SPRN_MCSR 322 mfspr r1,SPRN_MCSR
323 mtspr SPRN_MCSR,r1 323 mtspr SPRN_MCSR,r1
324 #endif 324 #endif
325 325
326 /*----------------------------------------------------------------*/ 326 /*----------------------------------------------------------------*/
327 /* CCR0 init */ 327 /* CCR0 init */
328 /*----------------------------------------------------------------*/ 328 /*----------------------------------------------------------------*/
329 /* Disable store gathering & broadcast, guarantee inst/data 329 /* Disable store gathering & broadcast, guarantee inst/data
330 * cache block touch, force load/store alignment 330 * cache block touch, force load/store alignment
331 * (see errata 1.12: 440_33) 331 * (see errata 1.12: 440_33)
332 */ 332 */
333 lis r1,0x0030 /* store gathering & broadcast disable */ 333 lis r1,0x0030 /* store gathering & broadcast disable */
334 ori r1,r1,0x6000 /* cache touch */ 334 ori r1,r1,0x6000 /* cache touch */
335 mtspr SPRN_CCR0,r1 335 mtspr SPRN_CCR0,r1
336 336
337 /*----------------------------------------------------------------*/ 337 /*----------------------------------------------------------------*/
338 /* Initialize debug */ 338 /* Initialize debug */
339 /*----------------------------------------------------------------*/ 339 /*----------------------------------------------------------------*/
340 mfspr r1,SPRN_DBCR0 340 mfspr r1,SPRN_DBCR0
341 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ 341 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
342 bne skip_debug_init /* if set, don't clear debug register */ 342 bne skip_debug_init /* if set, don't clear debug register */
343 mtspr SPRN_DBCR0,r0 343 mtspr SPRN_DBCR0,r0
344 mtspr SPRN_DBCR1,r0 344 mtspr SPRN_DBCR1,r0
345 mtspr SPRN_DBCR2,r0 345 mtspr SPRN_DBCR2,r0
346 mtspr SPRN_IAC1,r0 346 mtspr SPRN_IAC1,r0
347 mtspr SPRN_IAC2,r0 347 mtspr SPRN_IAC2,r0
348 mtspr SPRN_IAC3,r0 348 mtspr SPRN_IAC3,r0
349 mtspr SPRN_DAC1,r0 349 mtspr SPRN_DAC1,r0
350 mtspr SPRN_DAC2,r0 350 mtspr SPRN_DAC2,r0
351 mtspr SPRN_DVC1,r0 351 mtspr SPRN_DVC1,r0
352 mtspr SPRN_DVC2,r0 352 mtspr SPRN_DVC2,r0
353 353
354 mfspr r1,SPRN_DBSR 354 mfspr r1,SPRN_DBSR
355 mtspr SPRN_DBSR,r1 /* Clear all valid bits */ 355 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
356 skip_debug_init: 356 skip_debug_init:
357 357
358 #if defined (CONFIG_440SPE) 358 #if defined (CONFIG_440SPE)
359 /*----------------------------------------------------------------+ 359 /*----------------------------------------------------------------+
360 | Initialize Core Configuration Reg1. 360 | Initialize Core Configuration Reg1.
361 | a. ICDPEI: Record even parity. Normal operation. 361 | a. ICDPEI: Record even parity. Normal operation.
362 | b. ICTPEI: Record even parity. Normal operation. 362 | b. ICTPEI: Record even parity. Normal operation.
363 | c. DCTPEI: Record even parity. Normal operation. 363 | c. DCTPEI: Record even parity. Normal operation.
364 | d. DCDPEI: Record even parity. Normal operation. 364 | d. DCDPEI: Record even parity. Normal operation.
365 | e. DCUPEI: Record even parity. Normal operation. 365 | e. DCUPEI: Record even parity. Normal operation.
366 | f. DCMPEI: Record even parity. Normal operation. 366 | f. DCMPEI: Record even parity. Normal operation.
367 | g. FCOM: Normal operation 367 | g. FCOM: Normal operation
368 | h. MMUPEI: Record even parity. Normal operation. 368 | h. MMUPEI: Record even parity. Normal operation.
369 | i. FFF: Flush only as much data as necessary. 369 | i. FFF: Flush only as much data as necessary.
370 | j. TCS: Timebase increments from CPU clock. 370 | j. TCS: Timebase increments from CPU clock.
371 +-----------------------------------------------------------------*/ 371 +-----------------------------------------------------------------*/
372 li r0,0 372 li r0,0
373 mtspr SPRN_CCR1, r0 373 mtspr SPRN_CCR1, r0
374 374
375 /*----------------------------------------------------------------+ 375 /*----------------------------------------------------------------+
376 | Reset the timebase. 376 | Reset the timebase.
377 | The previous write to CCR1 sets the timebase source. 377 | The previous write to CCR1 sets the timebase source.
378 +-----------------------------------------------------------------*/ 378 +-----------------------------------------------------------------*/
379 mtspr SPRN_TBWL, r0 379 mtspr SPRN_TBWL, r0
380 mtspr SPRN_TBWU, r0 380 mtspr SPRN_TBWU, r0
381 #endif 381 #endif
382 382
383 /*----------------------------------------------------------------*/ 383 /*----------------------------------------------------------------*/
384 /* Setup interrupt vectors */ 384 /* Setup interrupt vectors */
385 /*----------------------------------------------------------------*/ 385 /*----------------------------------------------------------------*/
386 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ 386 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
387 li r1,0x0100 387 li r1,0x0100
388 mtspr SPRN_IVOR0,r1 /* Critical input */ 388 mtspr SPRN_IVOR0,r1 /* Critical input */
389 li r1,0x0200 389 li r1,0x0200
390 mtspr SPRN_IVOR1,r1 /* Machine check */ 390 mtspr SPRN_IVOR1,r1 /* Machine check */
391 li r1,0x0300 391 li r1,0x0300
392 mtspr SPRN_IVOR2,r1 /* Data storage */ 392 mtspr SPRN_IVOR2,r1 /* Data storage */
393 li r1,0x0400 393 li r1,0x0400
394 mtspr SPRN_IVOR3,r1 /* Instruction storage */ 394 mtspr SPRN_IVOR3,r1 /* Instruction storage */
395 li r1,0x0500 395 li r1,0x0500
396 mtspr SPRN_IVOR4,r1 /* External interrupt */ 396 mtspr SPRN_IVOR4,r1 /* External interrupt */
397 li r1,0x0600 397 li r1,0x0600
398 mtspr SPRN_IVOR5,r1 /* Alignment */ 398 mtspr SPRN_IVOR5,r1 /* Alignment */
399 li r1,0x0700 399 li r1,0x0700
400 mtspr SPRN_IVOR6,r1 /* Program check */ 400 mtspr SPRN_IVOR6,r1 /* Program check */
401 li r1,0x0800 401 li r1,0x0800
402 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ 402 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
403 li r1,0x0c00 403 li r1,0x0c00
404 mtspr SPRN_IVOR8,r1 /* System call */ 404 mtspr SPRN_IVOR8,r1 /* System call */
405 li r1,0x0a00 405 li r1,0x0a00
406 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ 406 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
407 li r1,0x0900 407 li r1,0x0900
408 mtspr SPRN_IVOR10,r1 /* Decrementer */ 408 mtspr SPRN_IVOR10,r1 /* Decrementer */
409 li r1,0x1300 409 li r1,0x1300
410 mtspr SPRN_IVOR13,r1 /* Data TLB error */ 410 mtspr SPRN_IVOR13,r1 /* Data TLB error */
411 li r1,0x1400 411 li r1,0x1400
412 mtspr SPRN_IVOR14,r1 /* Instr TLB error */ 412 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
413 li r1,0x2000 413 li r1,0x2000
414 mtspr SPRN_IVOR15,r1 /* Debug */ 414 mtspr SPRN_IVOR15,r1 /* Debug */
415 415
416 /*----------------------------------------------------------------*/ 416 /*----------------------------------------------------------------*/
417 /* Configure cache regions */ 417 /* Configure cache regions */
418 /*----------------------------------------------------------------*/ 418 /*----------------------------------------------------------------*/
419 mtspr SPRN_INV0,r0 419 mtspr SPRN_INV0,r0
420 mtspr SPRN_INV1,r0 420 mtspr SPRN_INV1,r0
421 mtspr SPRN_INV2,r0 421 mtspr SPRN_INV2,r0
422 mtspr SPRN_INV3,r0 422 mtspr SPRN_INV3,r0
423 mtspr SPRN_DNV0,r0 423 mtspr SPRN_DNV0,r0
424 mtspr SPRN_DNV1,r0 424 mtspr SPRN_DNV1,r0
425 mtspr SPRN_DNV2,r0 425 mtspr SPRN_DNV2,r0
426 mtspr SPRN_DNV3,r0 426 mtspr SPRN_DNV3,r0
427 mtspr SPRN_ITV0,r0 427 mtspr SPRN_ITV0,r0
428 mtspr SPRN_ITV1,r0 428 mtspr SPRN_ITV1,r0
429 mtspr SPRN_ITV2,r0 429 mtspr SPRN_ITV2,r0
430 mtspr SPRN_ITV3,r0 430 mtspr SPRN_ITV3,r0
431 mtspr SPRN_DTV0,r0 431 mtspr SPRN_DTV0,r0
432 mtspr SPRN_DTV1,r0 432 mtspr SPRN_DTV1,r0
433 mtspr SPRN_DTV2,r0 433 mtspr SPRN_DTV2,r0
434 mtspr SPRN_DTV3,r0 434 mtspr SPRN_DTV3,r0
435 435
436 /*----------------------------------------------------------------*/ 436 /*----------------------------------------------------------------*/
437 /* Cache victim limits */ 437 /* Cache victim limits */
438 /*----------------------------------------------------------------*/ 438 /*----------------------------------------------------------------*/
439 /* floors 0, ceiling max to use the entire cache -- nothing locked 439 /* floors 0, ceiling max to use the entire cache -- nothing locked
440 */ 440 */
441 lis r1,0x0001 441 lis r1,0x0001
442 ori r1,r1,0xf800 442 ori r1,r1,0xf800
443 mtspr SPRN_IVLIM,r1 443 mtspr SPRN_IVLIM,r1
444 mtspr SPRN_DVLIM,r1 444 mtspr SPRN_DVLIM,r1
445 445
446 /*----------------------------------------------------------------+ 446 /*----------------------------------------------------------------+
447 |Initialize MMUCR[STID] = 0. 447 |Initialize MMUCR[STID] = 0.
448 +-----------------------------------------------------------------*/ 448 +-----------------------------------------------------------------*/
449 mfspr r0,SPRN_MMUCR 449 mfspr r0,SPRN_MMUCR
450 addis r1,0,0xFFFF 450 addis r1,0,0xFFFF
451 ori r1,r1,0xFF00 451 ori r1,r1,0xFF00
452 and r0,r0,r1 452 and r0,r0,r1
453 mtspr SPRN_MMUCR,r0 453 mtspr SPRN_MMUCR,r0
454 454
455 /*----------------------------------------------------------------*/ 455 /*----------------------------------------------------------------*/
456 /* Clear all TLB entries -- TID = 0, TS = 0 */ 456 /* Clear all TLB entries -- TID = 0, TS = 0 */
457 /*----------------------------------------------------------------*/ 457 /*----------------------------------------------------------------*/
458 addis r0,0,0x0000 458 addis r0,0,0x0000
459 #ifdef CONFIG_SYS_RAMBOOT 459 #ifdef CONFIG_SYS_RAMBOOT
460 li r4,0 /* Start with TLB #0 */ 460 li r4,0 /* Start with TLB #0 */
461 #else 461 #else
462 li r4,1 /* Start with TLB #1 */ 462 li r4,1 /* Start with TLB #1 */
463 #endif 463 #endif
464 li r1,64 /* 64 TLB entries */ 464 li r1,64 /* 64 TLB entries */
465 sub r1,r1,r4 /* calculate last TLB # */ 465 sub r1,r1,r4 /* calculate last TLB # */
466 mtctr r1 466 mtctr r1
467 rsttlb: 467 rsttlb:
468 #ifdef CONFIG_SYS_RAMBOOT 468 #ifdef CONFIG_SYS_RAMBOOT
469 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ 469 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
470 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ 470 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
471 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ 471 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
472 #endif 472 #endif
473 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ 473 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
474 tlbwe r0,r4,1 474 tlbwe r0,r4,1
475 tlbwe r0,r4,2 475 tlbwe r0,r4,2
476 tlbnxt: addi r4,r4,1 /* Next TLB */ 476 tlbnxt: addi r4,r4,1 /* Next TLB */
477 bdnz rsttlb 477 bdnz rsttlb
478 478
479 /*----------------------------------------------------------------*/ 479 /*----------------------------------------------------------------*/
480 /* TLB entry setup -- step thru tlbtab */ 480 /* TLB entry setup -- step thru tlbtab */
481 /*----------------------------------------------------------------*/ 481 /*----------------------------------------------------------------*/
482 #if defined(CONFIG_440SPE_REVA) 482 #if defined(CONFIG_440SPE_REVA)
483 /*----------------------------------------------------------------*/ 483 /*----------------------------------------------------------------*/
484 /* We have different TLB tables for revA and rev B of 440SPe */ 484 /* We have different TLB tables for revA and rev B of 440SPe */
485 /*----------------------------------------------------------------*/ 485 /*----------------------------------------------------------------*/
486 mfspr r1, PVR 486 mfspr r1, PVR
487 lis r0,0x5342 487 lis r0,0x5342
488 ori r0,r0,0x1891 488 ori r0,r0,0x1891
489 cmpw r7,r1,r0 489 cmpw r7,r1,r0
490 bne r7,..revA 490 bne r7,..revA
491 bl tlbtabB 491 bl tlbtabB
492 b ..goon 492 b ..goon
493 ..revA: 493 ..revA:
494 bl tlbtabA 494 bl tlbtabA
495 ..goon: 495 ..goon:
496 #else 496 #else
497 bl tlbtab /* Get tlbtab pointer */ 497 bl tlbtab /* Get tlbtab pointer */
498 #endif 498 #endif
499 mr r5,r0 499 mr r5,r0
500 li r1,0x003f /* 64 TLB entries max */ 500 li r1,0x003f /* 64 TLB entries max */
501 mtctr r1 501 mtctr r1
502 li r4,0 /* TLB # */ 502 li r4,0 /* TLB # */
503 503
504 addi r5,r5,-4 504 addi r5,r5,-4
505 1: 505 1:
506 #ifdef CONFIG_SYS_RAMBOOT 506 #ifdef CONFIG_SYS_RAMBOOT
507 tlbre r3,r4,0 /* Read contents from TLB word #0 */ 507 tlbre r3,r4,0 /* Read contents from TLB word #0 */
508 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ 508 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
509 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ 509 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
510 #endif 510 #endif
511 lwzu r0,4(r5) 511 lwzu r0,4(r5)
512 cmpwi r0,0 512 cmpwi r0,0
513 beq 2f /* 0 marks end */ 513 beq 2f /* 0 marks end */
514 lwzu r1,4(r5) 514 lwzu r1,4(r5)
515 lwzu r2,4(r5) 515 lwzu r2,4(r5)
516 tlbwe r0,r4,0 /* TLB Word 0 */ 516 tlbwe r0,r4,0 /* TLB Word 0 */
517 tlbwe r1,r4,1 /* TLB Word 1 */ 517 tlbwe r1,r4,1 /* TLB Word 1 */
518 tlbwe r2,r4,2 /* TLB Word 2 */ 518 tlbwe r2,r4,2 /* TLB Word 2 */
519 tlbnx2: addi r4,r4,1 /* Next TLB */ 519 tlbnx2: addi r4,r4,1 /* Next TLB */
520 bdnz 1b 520 bdnz 1b
521 521
522 /*----------------------------------------------------------------*/ 522 /*----------------------------------------------------------------*/
523 /* Continue from 'normal' start */ 523 /* Continue from 'normal' start */
524 /*----------------------------------------------------------------*/ 524 /*----------------------------------------------------------------*/
525 2: 525 2:
526 bl 3f 526 bl 3f
527 b _start 527 b _start
528 528
529 3: li r0,0 529 3: li r0,0
530 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ 530 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
531 mflr r1 531 mflr r1
532 mtspr SPRN_SRR0,r1 532 mtspr SPRN_SRR0,r1
533 rfi 533 rfi
534 #endif /* CONFIG_440 */ 534 #endif /* CONFIG_440 */
535 535
536 /* 536 /*
537 * r3 - 1st arg to board_init(): IMMP pointer 537 * r3 - 1st arg to board_init(): IMMP pointer
538 * r4 - 2nd arg to board_init(): boot flag 538 * r4 - 2nd arg to board_init(): boot flag
539 */ 539 */
540 #ifndef CONFIG_NAND_SPL 540 #ifndef CONFIG_NAND_SPL
541 .text 541 .text
542 .long 0x27051956 /* U-Boot Magic Number */ 542 .long 0x27051956 /* U-Boot Magic Number */
543 .globl version_string 543 .globl version_string
544 version_string: 544 version_string:
545 .ascii U_BOOT_VERSION 545 .ascii U_BOOT_VERSION
546 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 546 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
547 .ascii CONFIG_IDENT_STRING, "\0" 547 .ascii CONFIG_IDENT_STRING, "\0"
548 548
549 . = EXC_OFF_SYS_RESET 549 . = EXC_OFF_SYS_RESET
550 .globl _start_of_vectors 550 .globl _start_of_vectors
551 _start_of_vectors: 551 _start_of_vectors:
552 552
553 /* Critical input. */ 553 /* Critical input. */
554 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) 554 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
555 555
556 #ifdef CONFIG_440 556 #ifdef CONFIG_440
557 /* Machine check */ 557 /* Machine check */
558 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 558 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
559 #else 559 #else
560 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) 560 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
561 #endif /* CONFIG_440 */ 561 #endif /* CONFIG_440 */
562 562
563 /* Data Storage exception. */ 563 /* Data Storage exception. */
564 STD_EXCEPTION(0x300, DataStorage, UnknownException) 564 STD_EXCEPTION(0x300, DataStorage, UnknownException)
565 565
566 /* Instruction Storage exception. */ 566 /* Instruction Storage exception. */
567 STD_EXCEPTION(0x400, InstStorage, UnknownException) 567 STD_EXCEPTION(0x400, InstStorage, UnknownException)
568 568
569 /* External Interrupt exception. */ 569 /* External Interrupt exception. */
570 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 570 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
571 571
572 /* Alignment exception. */ 572 /* Alignment exception. */
573 . = 0x600 573 . = 0x600
574 Alignment: 574 Alignment:
575 EXCEPTION_PROLOG(SRR0, SRR1) 575 EXCEPTION_PROLOG(SRR0, SRR1)
576 mfspr r4,DAR 576 mfspr r4,DAR
577 stw r4,_DAR(r21) 577 stw r4,_DAR(r21)
578 mfspr r5,DSISR 578 mfspr r5,DSISR
579 stw r5,_DSISR(r21) 579 stw r5,_DSISR(r21)
580 addi r3,r1,STACK_FRAME_OVERHEAD 580 addi r3,r1,STACK_FRAME_OVERHEAD
581 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 581 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
582 582
583 /* Program check exception */ 583 /* Program check exception */
584 . = 0x700 584 . = 0x700
585 ProgramCheck: 585 ProgramCheck:
586 EXCEPTION_PROLOG(SRR0, SRR1) 586 EXCEPTION_PROLOG(SRR0, SRR1)
587 addi r3,r1,STACK_FRAME_OVERHEAD 587 addi r3,r1,STACK_FRAME_OVERHEAD
588 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 588 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
589 MSR_KERNEL, COPY_EE) 589 MSR_KERNEL, COPY_EE)
590 590
591 #ifdef CONFIG_440 591 #ifdef CONFIG_440
592 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 592 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
593 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) 593 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
594 STD_EXCEPTION(0xa00, APU, UnknownException) 594 STD_EXCEPTION(0xa00, APU, UnknownException)
595 #endif 595 #endif
596 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 596 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
597 597
598 #ifdef CONFIG_440 598 #ifdef CONFIG_440
599 STD_EXCEPTION(0x1300, DataTLBError, UnknownException) 599 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
600 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) 600 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
601 #else 601 #else
602 STD_EXCEPTION(0x1000, PIT, DecrementerPITException) 602 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
603 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 603 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
604 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 604 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
605 #endif 605 #endif
606 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) 606 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
607 607
608 .globl _end_of_vectors 608 .globl _end_of_vectors
609 _end_of_vectors: 609 _end_of_vectors:
610 . = _START_OFFSET 610 . = _START_OFFSET
611 #endif 611 #endif
612 .globl _start 612 .globl _start
613 _start: 613 _start:
614 614
615 /*****************************************************************************/ 615 /*****************************************************************************/
616 #if defined(CONFIG_440) 616 #if defined(CONFIG_440)
617 617
618 /*----------------------------------------------------------------*/ 618 /*----------------------------------------------------------------*/
619 /* Clear and set up some registers. */ 619 /* Clear and set up some registers. */
620 /*----------------------------------------------------------------*/ 620 /*----------------------------------------------------------------*/
621 li r0,0x0000 621 li r0,0x0000
622 lis r1,0xffff 622 lis r1,0xffff
623 mtspr SPRN_DEC,r0 /* prevent dec exceptions */ 623 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
624 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ 624 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
625 mtspr SPRN_TBWU,r0 625 mtspr SPRN_TBWU,r0
626 mtspr SPRN_TSR,r1 /* clear all timer exception status */ 626 mtspr SPRN_TSR,r1 /* clear all timer exception status */
627 mtspr SPRN_TCR,r0 /* disable all */ 627 mtspr SPRN_TCR,r0 /* disable all */
628 mtspr SPRN_ESR,r0 /* clear exception syndrome register */ 628 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
629 mtxer r0 /* clear integer exception register */ 629 mtxer r0 /* clear integer exception register */
630 630
631 /*----------------------------------------------------------------*/ 631 /*----------------------------------------------------------------*/
632 /* Debug setup -- some (not very good) ice's need an event*/ 632 /* Debug setup -- some (not very good) ice's need an event*/
633 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ 633 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
634 /* value you need in this case 0x8cff 0000 should do the trick */ 634 /* value you need in this case 0x8cff 0000 should do the trick */
635 /*----------------------------------------------------------------*/ 635 /*----------------------------------------------------------------*/
636 #if defined(CONFIG_SYS_INIT_DBCR) 636 #if defined(CONFIG_SYS_INIT_DBCR)
637 lis r1,0xffff 637 lis r1,0xffff
638 ori r1,r1,0xffff 638 ori r1,r1,0xffff
639 mtspr SPRN_DBSR,r1 /* Clear all status bits */ 639 mtspr SPRN_DBSR,r1 /* Clear all status bits */
640 lis r0,CONFIG_SYS_INIT_DBCR@h 640 lis r0,CONFIG_SYS_INIT_DBCR@h
641 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 641 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
642 mtspr SPRN_DBCR0,r0 642 mtspr SPRN_DBCR0,r0
643 isync 643 isync
644 #endif 644 #endif
645 645
646 /*----------------------------------------------------------------*/ 646 /*----------------------------------------------------------------*/
647 /* Setup the internal SRAM */ 647 /* Setup the internal SRAM */
648 /*----------------------------------------------------------------*/ 648 /*----------------------------------------------------------------*/
649 li r0,0 649 li r0,0
650 650
651 #ifdef CONFIG_SYS_INIT_RAM_DCACHE 651 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
652 /* Clear Dcache to use as RAM */ 652 /* Clear Dcache to use as RAM */
653 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h 653 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
654 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 654 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
655 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h 655 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
656 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l 656 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
657 rlwinm. r5,r4,0,27,31 657 rlwinm. r5,r4,0,27,31
658 rlwinm r5,r4,27,5,31 658 rlwinm r5,r4,27,5,31
659 beq ..d_ran 659 beq ..d_ran
660 addi r5,r5,0x0001 660 addi r5,r5,0x0001
661 ..d_ran: 661 ..d_ran:
662 mtctr r5 662 mtctr r5
663 ..d_ag: 663 ..d_ag:
664 dcbz r0,r3 664 dcbz r0,r3
665 addi r3,r3,32 665 addi r3,r3,32
666 bdnz ..d_ag 666 bdnz ..d_ag
667 667
668 /* 668 /*
669 * Lock the init-ram/stack in d-cache, so that other regions 669 * Lock the init-ram/stack in d-cache, so that other regions
670 * may use d-cache as well 670 * may use d-cache as well
671 * Note, that this current implementation locks exactly 4k 671 * Note, that this current implementation locks exactly 4k
672 * of d-cache, so please make sure that you don't define a 672 * of d-cache, so please make sure that you don't define a
673 * bigger init-ram area. Take a look at the lwmon5 440EPx 673 * bigger init-ram area. Take a look at the lwmon5 440EPx
674 * implementation as a reference. 674 * implementation as a reference.
675 */ 675 */
676 msync 676 msync
677 isync 677 isync
678 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ 678 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
679 lis r1,0x0201 679 lis r1,0x0201
680 ori r1,r1,0xf808 680 ori r1,r1,0xf808
681 mtspr SPRN_DVLIM,r1 681 mtspr SPRN_DVLIM,r1
682 lis r1,0x0808 682 lis r1,0x0808
683 ori r1,r1,0x0808 683 ori r1,r1,0x0808
684 mtspr SPRN_DNV0,r1 684 mtspr SPRN_DNV0,r1
685 mtspr SPRN_DNV1,r1 685 mtspr SPRN_DNV1,r1
686 mtspr SPRN_DNV2,r1 686 mtspr SPRN_DNV2,r1
687 mtspr SPRN_DNV3,r1 687 mtspr SPRN_DNV3,r1
688 mtspr SPRN_DTV0,r1 688 mtspr SPRN_DTV0,r1
689 mtspr SPRN_DTV1,r1 689 mtspr SPRN_DTV1,r1
690 mtspr SPRN_DTV2,r1 690 mtspr SPRN_DTV2,r1
691 mtspr SPRN_DTV3,r1 691 mtspr SPRN_DTV3,r1
692 msync 692 msync
693 isync 693 isync
694 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ 694 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
695 695
696 /* 440EP & 440GR are only 440er PPC's without internal SRAM */ 696 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
697 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) 697 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
698 /* not all PPC's have internal SRAM usable as L2-cache */ 698 /* not all PPC's have internal SRAM usable as L2-cache */
699 #if defined(CONFIG_440GX) || \ 699 #if defined(CONFIG_440GX) || \
700 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 700 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
701 defined(CONFIG_460SX) 701 defined(CONFIG_460SX)
702 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ 702 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
703 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) 703 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
704 lis r1, 0x0000 704 lis r1, 0x0000
705 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ 705 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
706 mtdcr L2_CACHE_CFG,r1 706 mtdcr L2_CACHE_CFG,r1
707 #endif 707 #endif
708 708
709 lis r2,0x7fff 709 lis r2,0x7fff
710 ori r2,r2,0xffff 710 ori r2,r2,0xffff
711 mfdcr r1,ISRAM0_DPC 711 mfdcr r1,ISRAM0_DPC
712 and r1,r1,r2 /* Disable parity check */ 712 and r1,r1,r2 /* Disable parity check */
713 mtdcr ISRAM0_DPC,r1 713 mtdcr ISRAM0_DPC,r1
714 mfdcr r1,ISRAM0_PMEG 714 mfdcr r1,ISRAM0_PMEG
715 and r1,r1,r2 /* Disable pwr mgmt */ 715 and r1,r1,r2 /* Disable pwr mgmt */
716 mtdcr ISRAM0_PMEG,r1 716 mtdcr ISRAM0_PMEG,r1
717 717
718 lis r1,0x8000 /* BAS = 8000_0000 */ 718 lis r1,0x8000 /* BAS = 8000_0000 */
719 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) 719 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
720 ori r1,r1,0x0980 /* first 64k */ 720 ori r1,r1,0x0980 /* first 64k */
721 mtdcr ISRAM0_SB0CR,r1 721 mtdcr ISRAM0_SB0CR,r1
722 lis r1,0x8001 722 lis r1,0x8001
723 ori r1,r1,0x0980 /* second 64k */ 723 ori r1,r1,0x0980 /* second 64k */
724 mtdcr ISRAM0_SB1CR,r1 724 mtdcr ISRAM0_SB1CR,r1
725 lis r1, 0x8002 725 lis r1, 0x8002
726 ori r1,r1, 0x0980 /* third 64k */ 726 ori r1,r1, 0x0980 /* third 64k */
727 mtdcr ISRAM0_SB2CR,r1 727 mtdcr ISRAM0_SB2CR,r1
728 lis r1, 0x8003 728 lis r1, 0x8003
729 ori r1,r1, 0x0980 /* fourth 64k */ 729 ori r1,r1, 0x0980 /* fourth 64k */
730 mtdcr ISRAM0_SB3CR,r1 730 mtdcr ISRAM0_SB3CR,r1
731 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) 731 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
732 lis r1,0x0000 /* BAS = X_0000_0000 */ 732 lis r1,0x0000 /* BAS = X_0000_0000 */
733 ori r1,r1,0x0984 /* first 64k */ 733 ori r1,r1,0x0984 /* first 64k */
734 mtdcr ISRAM0_SB0CR,r1 734 mtdcr ISRAM0_SB0CR,r1
735 lis r1,0x0001 735 lis r1,0x0001
736 ori r1,r1,0x0984 /* second 64k */ 736 ori r1,r1,0x0984 /* second 64k */
737 mtdcr ISRAM0_SB1CR,r1 737 mtdcr ISRAM0_SB1CR,r1
738 lis r1, 0x0002 738 lis r1, 0x0002
739 ori r1,r1, 0x0984 /* third 64k */ 739 ori r1,r1, 0x0984 /* third 64k */
740 mtdcr ISRAM0_SB2CR,r1 740 mtdcr ISRAM0_SB2CR,r1
741 lis r1, 0x0003 741 lis r1, 0x0003
742 ori r1,r1, 0x0984 /* fourth 64k */ 742 ori r1,r1, 0x0984 /* fourth 64k */
743 mtdcr ISRAM0_SB3CR,r1 743 mtdcr ISRAM0_SB3CR,r1
744 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 744 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
745 lis r2,0x7fff 745 lis r2,0x7fff
746 ori r2,r2,0xffff 746 ori r2,r2,0xffff
747 mfdcr r1,ISRAM1_DPC 747 mfdcr r1,ISRAM1_DPC
748 and r1,r1,r2 /* Disable parity check */ 748 and r1,r1,r2 /* Disable parity check */
749 mtdcr ISRAM1_DPC,r1 749 mtdcr ISRAM1_DPC,r1
750 mfdcr r1,ISRAM1_PMEG 750 mfdcr r1,ISRAM1_PMEG
751 and r1,r1,r2 /* Disable pwr mgmt */ 751 and r1,r1,r2 /* Disable pwr mgmt */
752 mtdcr ISRAM1_PMEG,r1 752 mtdcr ISRAM1_PMEG,r1
753 753
754 lis r1,0x0004 /* BAS = 4_0004_0000 */ 754 lis r1,0x0004 /* BAS = 4_0004_0000 */
755 ori r1,r1,0x0984 /* 64k */ 755 ori r1,r1,0x0984 /* 64k */
756 mtdcr ISRAM1_SB0CR,r1 756 mtdcr ISRAM1_SB0CR,r1
757 #endif 757 #endif
758 #elif defined(CONFIG_460SX) 758 #elif defined(CONFIG_460SX)
759 lis r1,0x0000 /* BAS = 0000_0000 */ 759 lis r1,0x0000 /* BAS = 0000_0000 */
760 ori r1,r1,0x0B84 /* first 128k */ 760 ori r1,r1,0x0B84 /* first 128k */
761 mtdcr ISRAM0_SB0CR,r1 761 mtdcr ISRAM0_SB0CR,r1
762 lis r1,0x0001 762 lis r1,0x0001
763 ori r1,r1,0x0B84 /* second 128k */ 763 ori r1,r1,0x0B84 /* second 128k */
764 mtdcr ISRAM0_SB1CR,r1 764 mtdcr ISRAM0_SB1CR,r1
765 lis r1, 0x0002 765 lis r1, 0x0002
766 ori r1,r1, 0x0B84 /* third 128k */ 766 ori r1,r1, 0x0B84 /* third 128k */
767 mtdcr ISRAM0_SB2CR,r1 767 mtdcr ISRAM0_SB2CR,r1
768 lis r1, 0x0003 768 lis r1, 0x0003
769 ori r1,r1, 0x0B84 /* fourth 128k */ 769 ori r1,r1, 0x0B84 /* fourth 128k */
770 mtdcr ISRAM0_SB3CR,r1 770 mtdcr ISRAM0_SB3CR,r1
771 #elif defined(CONFIG_440GP) 771 #elif defined(CONFIG_440GP)
772 ori r1,r1,0x0380 /* 8k rw */ 772 ori r1,r1,0x0380 /* 8k rw */
773 mtdcr ISRAM0_SB0CR,r1 773 mtdcr ISRAM0_SB0CR,r1
774 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ 774 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
775 #endif 775 #endif
776 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ 776 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
777 777
778 /*----------------------------------------------------------------*/ 778 /*----------------------------------------------------------------*/
779 /* Setup the stack in internal SRAM */ 779 /* Setup the stack in internal SRAM */
780 /*----------------------------------------------------------------*/ 780 /*----------------------------------------------------------------*/
781 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 781 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
782 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 782 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
783 li r0,0 783 li r0,0
784 stwu r0,-4(r1) 784 stwu r0,-4(r1)
785 stwu r0,-4(r1) /* Terminate call chain */ 785 stwu r0,-4(r1) /* Terminate call chain */
786 786
787 stwu r1,-8(r1) /* Save back chain and move SP */ 787 stwu r1,-8(r1) /* Save back chain and move SP */
788 lis r0,RESET_VECTOR@h /* Address of reset vector */ 788 lis r0,RESET_VECTOR@h /* Address of reset vector */
789 ori r0,r0, RESET_VECTOR@l 789 ori r0,r0, RESET_VECTOR@l
790 stwu r1,-8(r1) /* Save back chain and move SP */ 790 stwu r1,-8(r1) /* Save back chain and move SP */
791 stw r0,+12(r1) /* Save return addr (underflow vect) */ 791 stw r0,+12(r1) /* Save return addr (underflow vect) */
792 792
793 #ifdef CONFIG_NAND_SPL 793 #ifdef CONFIG_NAND_SPL
794 bl nand_boot_common /* will not return */ 794 bl nand_boot_common /* will not return */
795 #else 795 #else
796 GET_GOT 796 GET_GOT
797 797
798 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 798 bl cpu_init_f /* run low-level CPU init code (from Flash) */
799 bl board_init_f 799 bl board_init_f
800 #endif 800 #endif
801 801
802 #endif /* CONFIG_440 */ 802 #endif /* CONFIG_440 */
803 803
804 /*****************************************************************************/ 804 /*****************************************************************************/
805 #ifdef CONFIG_IOP480 805 #ifdef CONFIG_IOP480
806 /*----------------------------------------------------------------------- */ 806 /*----------------------------------------------------------------------- */
807 /* Set up some machine state registers. */ 807 /* Set up some machine state registers. */
808 /*----------------------------------------------------------------------- */ 808 /*----------------------------------------------------------------------- */
809 addi r0,r0,0x0000 /* initialize r0 to zero */ 809 addi r0,r0,0x0000 /* initialize r0 to zero */
810 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ 810 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
811 mttcr r0 /* timer control register */ 811 mttcr r0 /* timer control register */
812 mtexier r0 /* disable all interrupts */ 812 mtexier r0 /* disable all interrupts */
813 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ 813 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
814 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ 814 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
815 mtdbsr r4 /* clear/reset the dbsr */ 815 mtdbsr r4 /* clear/reset the dbsr */
816 mtexisr r4 /* clear all pending interrupts */ 816 mtexisr r4 /* clear all pending interrupts */
817 addis r4,r0,0x8000 817 addis r4,r0,0x8000
818 mtexier r4 /* enable critical exceptions */ 818 mtexier r4 /* enable critical exceptions */
819 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ 819 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
820 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ 820 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
821 mtiocr r4 /* since bit not used) & DRC to latch */ 821 mtiocr r4 /* since bit not used) & DRC to latch */
822 /* data bus on rising edge of CAS */ 822 /* data bus on rising edge of CAS */
823 /*----------------------------------------------------------------------- */ 823 /*----------------------------------------------------------------------- */
824 /* Clear XER. */ 824 /* Clear XER. */
825 /*----------------------------------------------------------------------- */ 825 /*----------------------------------------------------------------------- */
826 mtxer r0 826 mtxer r0
827 /*----------------------------------------------------------------------- */ 827 /*----------------------------------------------------------------------- */
828 /* Invalidate i-cache and d-cache TAG arrays. */ 828 /* Invalidate i-cache and d-cache TAG arrays. */
829 /*----------------------------------------------------------------------- */ 829 /*----------------------------------------------------------------------- */
830 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ 830 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
831 addi r4,0,1024 /* 1/4 of I-cache */ 831 addi r4,0,1024 /* 1/4 of I-cache */
832 ..cloop: 832 ..cloop:
833 iccci 0,r3 833 iccci 0,r3
834 iccci r4,r3 834 iccci r4,r3
835 dccci 0,r3 835 dccci 0,r3
836 addic. r3,r3,-16 /* move back one cache line */ 836 addic. r3,r3,-16 /* move back one cache line */
837 bne ..cloop /* loop back to do rest until r3 = 0 */ 837 bne ..cloop /* loop back to do rest until r3 = 0 */
838 838
839 /* */ 839 /* */
840 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ 840 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
841 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ 841 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
842 /* */ 842 /* */
843 843
844 /* first copy IOP480 register base address into r3 */ 844 /* first copy IOP480 register base address into r3 */
845 addis r3,0,0x5000 /* IOP480 register base address hi */ 845 addis r3,0,0x5000 /* IOP480 register base address hi */
846 /* ori r3,r3,0x0000 / IOP480 register base address lo */ 846 /* ori r3,r3,0x0000 / IOP480 register base address lo */
847 847
848 #ifdef CONFIG_ADCIOP 848 #ifdef CONFIG_ADCIOP
849 /* use r4 as the working variable */ 849 /* use r4 as the working variable */
850 /* turn on CS3 (LOCCTL.7) */ 850 /* turn on CS3 (LOCCTL.7) */
851 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ 851 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
852 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ 852 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
853 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ 853 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
854 #endif 854 #endif
855 855
856 #ifdef CONFIG_DASA_SIM 856 #ifdef CONFIG_DASA_SIM
857 /* use r4 as the working variable */ 857 /* use r4 as the working variable */
858 /* turn on MA17 (LOCCTL.7) */ 858 /* turn on MA17 (LOCCTL.7) */
859 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ 859 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
860 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ 860 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
861 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ 861 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
862 #endif 862 #endif
863 863
864 /* turn on MA16..13 (LCS0BRD.12 = 0) */ 864 /* turn on MA16..13 (LCS0BRD.12 = 0) */
865 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ 865 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
866 andi. r4,r4,0xefff /* make bit 12 = 0 */ 866 andi. r4,r4,0xefff /* make bit 12 = 0 */
867 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ 867 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
868 868
869 /* make sure above stores all comlete before going on */ 869 /* make sure above stores all comlete before going on */
870 sync 870 sync
871 871
872 /* last thing, set local init status done bit (DEVINIT.31) */ 872 /* last thing, set local init status done bit (DEVINIT.31) */
873 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ 873 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
874 oris r4,r4,0x8000 /* make bit 31 = 1 */ 874 oris r4,r4,0x8000 /* make bit 31 = 1 */
875 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ 875 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
876 876
877 /* clear all pending interrupts and disable all interrupts */ 877 /* clear all pending interrupts and disable all interrupts */
878 li r4,-1 /* set p1 to 0xffffffff */ 878 li r4,-1 /* set p1 to 0xffffffff */
879 stw r4,0x1b0(r3) /* clear all pending interrupts */ 879 stw r4,0x1b0(r3) /* clear all pending interrupts */
880 stw r4,0x1b8(r3) /* clear all pending interrupts */ 880 stw r4,0x1b8(r3) /* clear all pending interrupts */
881 li r4,0 /* set r4 to 0 */ 881 li r4,0 /* set r4 to 0 */
882 stw r4,0x1b4(r3) /* disable all interrupts */ 882 stw r4,0x1b4(r3) /* disable all interrupts */
883 stw r4,0x1bc(r3) /* disable all interrupts */ 883 stw r4,0x1bc(r3) /* disable all interrupts */
884 884
885 /* make sure above stores all comlete before going on */ 885 /* make sure above stores all comlete before going on */
886 sync 886 sync
887 887
888 /* Set-up icache cacheability. */ 888 /* Set-up icache cacheability. */
889 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h 889 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
890 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l 890 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
891 mticcr r1 891 mticcr r1
892 isync 892 isync
893 893
894 /* Set-up dcache cacheability. */ 894 /* Set-up dcache cacheability. */
895 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h 895 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
896 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l 896 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
897 mtdccr r1 897 mtdccr r1
898 898
899 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h 899 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
900 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ 900 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
901 li r0, 0 /* Make room for stack frame header and */ 901 li r0, 0 /* Make room for stack frame header and */
902 stwu r0, -4(r1) /* clear final stack frame so that */ 902 stwu r0, -4(r1) /* clear final stack frame so that */
903 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 903 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
904 904
905 GET_GOT /* initialize GOT access */ 905 GET_GOT /* initialize GOT access */
906 906
907 bl board_init_f /* run first part of init code (from Flash) */ 907 bl board_init_f /* run first part of init code (from Flash) */
908 908
909 #endif /* CONFIG_IOP480 */ 909 #endif /* CONFIG_IOP480 */
910 910
911 /*****************************************************************************/ 911 /*****************************************************************************/
912 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ 912 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
913 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ 913 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
914 defined(CONFIG_405EX) || defined(CONFIG_405) 914 defined(CONFIG_405EX) || defined(CONFIG_405)
915 /*----------------------------------------------------------------------- */ 915 /*----------------------------------------------------------------------- */
916 /* Clear and set up some registers. */ 916 /* Clear and set up some registers. */
917 /*----------------------------------------------------------------------- */ 917 /*----------------------------------------------------------------------- */
918 addi r4,r0,0x0000 918 addi r4,r0,0x0000
919 #if !defined(CONFIG_405EX) 919 #if !defined(CONFIG_405EX)
920 mtspr SPRN_SGR,r4 920 mtspr SPRN_SGR,r4
921 #else 921 #else
922 /* 922 /*
923 * On 405EX, completely clearing the SGR leads to PPC hangup 923 * On 405EX, completely clearing the SGR leads to PPC hangup
924 * upon PCIe configuration access. The PCIe memory regions 924 * upon PCIe configuration access. The PCIe memory regions
925 * need to be guarded! 925 * need to be guarded!
926 */ 926 */
927 lis r3,0x0000 927 lis r3,0x0000
928 ori r3,r3,0x7FFC 928 ori r3,r3,0x7FFC
929 mtspr SPRN_SGR,r3 929 mtspr SPRN_SGR,r3
930 #endif 930 #endif
931 mtspr SPRN_DCWR,r4 931 mtspr SPRN_DCWR,r4
932 mtesr r4 /* clear Exception Syndrome Reg */ 932 mtesr r4 /* clear Exception Syndrome Reg */
933 mttcr r4 /* clear Timer Control Reg */ 933 mttcr r4 /* clear Timer Control Reg */
934 mtxer r4 /* clear Fixed-Point Exception Reg */ 934 mtxer r4 /* clear Fixed-Point Exception Reg */
935 mtevpr r4 /* clear Exception Vector Prefix Reg */ 935 mtevpr r4 /* clear Exception Vector Prefix Reg */
936 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ 936 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
937 /* dbsr is cleared by setting bits to 1) */ 937 /* dbsr is cleared by setting bits to 1) */
938 mtdbsr r4 /* clear/reset the dbsr */ 938 mtdbsr r4 /* clear/reset the dbsr */
939 939
940 /* Invalidate the i- and d-caches. */ 940 /* Invalidate the i- and d-caches. */
941 bl invalidate_icache 941 bl invalidate_icache
942 bl invalidate_dcache 942 bl invalidate_dcache
943 943
944 /* Set-up icache cacheability. */ 944 /* Set-up icache cacheability. */
945 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h 945 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
946 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l 946 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
947 mticcr r4 947 mticcr r4
948 isync 948 isync
949 949
950 /* Set-up dcache cacheability. */ 950 /* Set-up dcache cacheability. */
951 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h 951 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
952 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l 952 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
953 mtdccr r4 953 mtdccr r4
954 954
955 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ 955 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
956 && !defined (CONFIG_XILINX_405) 956 && !defined (CONFIG_XILINX_405)
957 /*----------------------------------------------------------------------- */ 957 /*----------------------------------------------------------------------- */
958 /* Tune the speed and size for flash CS0 */ 958 /* Tune the speed and size for flash CS0 */
959 /*----------------------------------------------------------------------- */ 959 /*----------------------------------------------------------------------- */
960 bl ext_bus_cntlr_init 960 bl ext_bus_cntlr_init
961 #endif 961 #endif
962 962
963 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) 963 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
964 /* 964 /*
965 * For boards that don't have OCM and can't use the data cache 965 * For boards that don't have OCM and can't use the data cache
966 * for their primordial stack, setup stack here directly after the 966 * for their primordial stack, setup stack here directly after the
967 * SDRAM is initialized in ext_bus_cntlr_init. 967 * SDRAM is initialized in ext_bus_cntlr_init.
968 */ 968 */
969 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h 969 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
970 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ 970 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
971 971
972 li r0, 0 /* Make room for stack frame header and */ 972 li r0, 0 /* Make room for stack frame header and */
973 stwu r0, -4(r1) /* clear final stack frame so that */ 973 stwu r0, -4(r1) /* clear final stack frame so that */
974 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 974 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
975 /* 975 /*
976 * Set up a dummy frame to store reset vector as return address. 976 * Set up a dummy frame to store reset vector as return address.
977 * this causes stack underflow to reset board. 977 * this causes stack underflow to reset board.
978 */ 978 */
979 stwu r1, -8(r1) /* Save back chain and move SP */ 979 stwu r1, -8(r1) /* Save back chain and move SP */
980 lis r0, RESET_VECTOR@h /* Address of reset vector */ 980 lis r0, RESET_VECTOR@h /* Address of reset vector */
981 ori r0, r0, RESET_VECTOR@l 981 ori r0, r0, RESET_VECTOR@l
982 stwu r1, -8(r1) /* Save back chain and move SP */ 982 stwu r1, -8(r1) /* Save back chain and move SP */
983 stw r0, +12(r1) /* Save return addr (underflow vect) */ 983 stw r0, +12(r1) /* Save return addr (underflow vect) */
984 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ 984 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
985 985
986 #if defined(CONFIG_405EP) 986 #if defined(CONFIG_405EP)
987 /*----------------------------------------------------------------------- */ 987 /*----------------------------------------------------------------------- */
988 /* DMA Status, clear to come up clean */ 988 /* DMA Status, clear to come up clean */
989 /*----------------------------------------------------------------------- */ 989 /*----------------------------------------------------------------------- */
990 addis r3,r0, 0xFFFF /* Clear all existing DMA status */ 990 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
991 ori r3,r3, 0xFFFF 991 ori r3,r3, 0xFFFF
992 mtdcr DMASR, r3 992 mtdcr DMASR, r3
993 993
994 bl ppc405ep_init /* do ppc405ep specific init */ 994 bl ppc405ep_init /* do ppc405ep specific init */
995 #endif /* CONFIG_405EP */ 995 #endif /* CONFIG_405EP */
996 996
997 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) 997 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
998 #if defined(CONFIG_405EZ) 998 #if defined(CONFIG_405EZ)
999 /******************************************************************** 999 /********************************************************************
1000 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 1000 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1001 *******************************************************************/ 1001 *******************************************************************/
1002 /* 1002 /*
1003 * We can map the OCM on the PLB3, so map it at 1003 * We can map the OCM on the PLB3, so map it at
1004 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 1004 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1005 */ 1005 */
1006 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 1006 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1007 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 1007 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1008 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ 1008 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1009 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ 1009 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1010 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ 1010 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1011 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ 1011 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1012 isync 1012 isync
1013 1013
1014 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 1014 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1015 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 1015 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1016 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ 1016 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1017 mtdcr OCM0_DSRC1, r3 /* Set Data Side */ 1017 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1018 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ 1018 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1019 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ 1019 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1020 mtdcr OCM0_DSRC2, r3 /* Set Data Side */ 1020 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1021 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ 1021 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1022 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ 1022 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1023 mtdcr OCM0_DISDPC,r3 1023 mtdcr OCM0_DISDPC,r3
1024 1024
1025 isync 1025 isync
1026 #else /* CONFIG_405EZ */ 1026 #else /* CONFIG_405EZ */
1027 /******************************************************************** 1027 /********************************************************************
1028 * Setup OCM - On Chip Memory 1028 * Setup OCM - On Chip Memory
1029 *******************************************************************/ 1029 *******************************************************************/
1030 /* Setup OCM */ 1030 /* Setup OCM */
1031 lis r0, 0x7FFF 1031 lis r0, 0x7FFF
1032 ori r0, r0, 0xFFFF 1032 ori r0, r0, 0xFFFF
1033 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ 1033 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1034 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ 1034 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1035 and r3, r3, r0 /* disable data-side IRAM */ 1035 and r3, r3, r0 /* disable data-side IRAM */
1036 and r4, r4, r0 /* disable data-side IRAM */ 1036 and r4, r4, r0 /* disable data-side IRAM */
1037 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ 1037 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1038 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ 1038 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1039 isync 1039 isync
1040 1040
1041 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 1041 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1042 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 1042 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1043 mtdcr OCM0_DSARC, r3 1043 mtdcr OCM0_DSARC, r3
1044 addis r4, 0, 0xC000 /* OCM data area enabled */ 1044 addis r4, 0, 0xC000 /* OCM data area enabled */
1045 mtdcr OCM0_DSCNTL, r4 1045 mtdcr OCM0_DSCNTL, r4
1046 isync 1046 isync
1047 #endif /* CONFIG_405EZ */ 1047 #endif /* CONFIG_405EZ */
1048 #endif 1048 #endif
1049 1049
1050 /*----------------------------------------------------------------------- */ 1050 /*----------------------------------------------------------------------- */
1051 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ 1051 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1052 /*----------------------------------------------------------------------- */ 1052 /*----------------------------------------------------------------------- */
1053 #ifdef CONFIG_SYS_INIT_DCACHE_CS 1053 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1054 li r4, PBxAP 1054 li r4, PBxAP
1055 mtdcr EBC0_CFGADDR, r4 1055 mtdcr EBC0_CFGADDR, r4
1056 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h 1056 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1057 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l 1057 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1058 mtdcr EBC0_CFGDATA, r4 1058 mtdcr EBC0_CFGDATA, r4
1059 1059
1060 addi r4, 0, PBxCR 1060 addi r4, 0, PBxCR
1061 mtdcr EBC0_CFGADDR, r4 1061 mtdcr EBC0_CFGADDR, r4
1062 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h 1062 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1063 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l 1063 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1064 mtdcr EBC0_CFGDATA, r4 1064 mtdcr EBC0_CFGDATA, r4
1065 1065
1066 /* 1066 /*
1067 * Enable the data cache for the 128MB storage access control region 1067 * Enable the data cache for the 128MB storage access control region
1068 * at CONFIG_SYS_INIT_RAM_ADDR. 1068 * at CONFIG_SYS_INIT_RAM_ADDR.
1069 */ 1069 */
1070 mfdccr r4 1070 mfdccr r4
1071 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h 1071 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1072 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l 1072 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1073 mtdccr r4 1073 mtdccr r4
1074 1074
1075 /* 1075 /*
1076 * Preallocate data cache lines to be used to avoid a subsequent 1076 * Preallocate data cache lines to be used to avoid a subsequent
1077 * cache miss and an ensuing machine check exception when exceptions 1077 * cache miss and an ensuing machine check exception when exceptions
1078 * are enabled. 1078 * are enabled.
1079 */ 1079 */
1080 li r0, 0 1080 li r0, 0
1081 1081
1082 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h 1082 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1083 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l 1083 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1084 1084
1085 lis r4, CONFIG_SYS_INIT_RAM_END@h 1085 lis r4, CONFIG_SYS_INIT_RAM_END@h
1086 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l 1086 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1087 1087
1088 /* 1088 /*
1089 * Convert the size, in bytes, to the number of cache lines/blocks 1089 * Convert the size, in bytes, to the number of cache lines/blocks
1090 * to preallocate. 1090 * to preallocate.
1091 */ 1091 */
1092 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) 1092 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1093 srwi r5, r4, L1_CACHE_SHIFT 1093 srwi r5, r4, L1_CACHE_SHIFT
1094 beq ..load_counter 1094 beq ..load_counter
1095 addi r5, r5, 0x0001 1095 addi r5, r5, 0x0001
1096 ..load_counter: 1096 ..load_counter:
1097 mtctr r5 1097 mtctr r5
1098 1098
1099 /* Preallocate the computed number of cache blocks. */ 1099 /* Preallocate the computed number of cache blocks. */
1100 ..alloc_dcache_block: 1100 ..alloc_dcache_block:
1101 dcba r0, r3 1101 dcba r0, r3
1102 addi r3, r3, L1_CACHE_BYTES 1102 addi r3, r3, L1_CACHE_BYTES
1103 bdnz ..alloc_dcache_block 1103 bdnz ..alloc_dcache_block
1104 sync 1104 sync
1105 1105
1106 /* 1106 /*
1107 * Load the initial stack pointer and data area and convert the size, 1107 * Load the initial stack pointer and data area and convert the size,
1108 * in bytes, to the number of words to initialize to a known value. 1108 * in bytes, to the number of words to initialize to a known value.
1109 */ 1109 */
1110 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h 1110 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1111 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l 1111 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1112 1112
1113 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h 1113 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1114 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l 1114 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1115 mtctr r4 1115 mtctr r4
1116 1116
1117 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h 1117 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1118 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l 1118 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1119 1119
1120 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h 1120 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1121 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l 1121 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1122 1122
1123 ..stackloop: 1123 ..stackloop:
1124 stwu r4, -4(r2) 1124 stwu r4, -4(r2)
1125 bdnz ..stackloop 1125 bdnz ..stackloop
1126 1126
1127 /* 1127 /*
1128 * Make room for stack frame header and clear final stack frame so 1128 * Make room for stack frame header and clear final stack frame so
1129 * that stack backtraces terminate cleanly. 1129 * that stack backtraces terminate cleanly.
1130 */ 1130 */
1131 stwu r0, -4(r1) 1131 stwu r0, -4(r1)
1132 stwu r0, -4(r1) 1132 stwu r0, -4(r1)
1133 1133
1134 /* 1134 /*
1135 * Set up a dummy frame to store reset vector as return address. 1135 * Set up a dummy frame to store reset vector as return address.
1136 * this causes stack underflow to reset board. 1136 * this causes stack underflow to reset board.
1137 */ 1137 */
1138 stwu r1, -8(r1) /* Save back chain and move SP */ 1138 stwu r1, -8(r1) /* Save back chain and move SP */
1139 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ 1139 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1140 ori r0, r0, RESET_VECTOR@l 1140 ori r0, r0, RESET_VECTOR@l
1141 stwu r1, -8(r1) /* Save back chain and move SP */ 1141 stwu r1, -8(r1) /* Save back chain and move SP */
1142 stw r0, +12(r1) /* Save return addr (underflow vect) */ 1142 stw r0, +12(r1) /* Save return addr (underflow vect) */
1143 1143
1144 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ 1144 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1145 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) 1145 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1146 /* 1146 /*
1147 * Stack in OCM. 1147 * Stack in OCM.
1148 */ 1148 */
1149 1149
1150 /* Set up Stack at top of OCM */ 1150 /* Set up Stack at top of OCM */
1151 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h 1151 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1152 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l 1152 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1153 1153
1154 /* Set up a zeroized stack frame so that backtrace works right */ 1154 /* Set up a zeroized stack frame so that backtrace works right */
1155 li r0, 0 1155 li r0, 0
1156 stwu r0, -4(r1) 1156 stwu r0, -4(r1)
1157 stwu r0, -4(r1) 1157 stwu r0, -4(r1)
1158 1158
1159 /* 1159 /*
1160 * Set up a dummy frame to store reset vector as return address. 1160 * Set up a dummy frame to store reset vector as return address.
1161 * this causes stack underflow to reset board. 1161 * this causes stack underflow to reset board.
1162 */ 1162 */
1163 stwu r1, -8(r1) /* Save back chain and move SP */ 1163 stwu r1, -8(r1) /* Save back chain and move SP */
1164 lis r0, RESET_VECTOR@h /* Address of reset vector */ 1164 lis r0, RESET_VECTOR@h /* Address of reset vector */
1165 ori r0, r0, RESET_VECTOR@l 1165 ori r0, r0, RESET_VECTOR@l
1166 stwu r1, -8(r1) /* Save back chain and move SP */ 1166 stwu r1, -8(r1) /* Save back chain and move SP */
1167 stw r0, +12(r1) /* Save return addr (underflow vect) */ 1167 stw r0, +12(r1) /* Save return addr (underflow vect) */
1168 #endif /* CONFIG_SYS_INIT_DCACHE_CS */ 1168 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1169 1169
1170 #ifdef CONFIG_NAND_SPL 1170 #ifdef CONFIG_NAND_SPL
1171 bl nand_boot_common /* will not return */ 1171 bl nand_boot_common /* will not return */
1172 #else 1172 #else
1173 GET_GOT /* initialize GOT access */ 1173 GET_GOT /* initialize GOT access */
1174 1174
1175 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 1175 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1176 1176
1177 /* NEVER RETURNS! */ 1177 /* NEVER RETURNS! */
1178 bl board_init_f /* run first part of init code (from Flash) */ 1178 bl board_init_f /* run first part of init code (from Flash) */
1179 #endif /* CONFIG_NAND_SPL */ 1179 #endif /* CONFIG_NAND_SPL */
1180 1180
1181 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ 1181 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1182 /*----------------------------------------------------------------------- */ 1182 /*----------------------------------------------------------------------- */
1183 1183
1184 1184
1185 #ifndef CONFIG_NAND_SPL 1185 #ifndef CONFIG_NAND_SPL
1186 /* 1186 /*
1187 * This code finishes saving the registers to the exception frame 1187 * This code finishes saving the registers to the exception frame
1188 * and jumps to the appropriate handler for the exception. 1188 * and jumps to the appropriate handler for the exception.
1189 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1189 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1190 */ 1190 */
1191 .globl transfer_to_handler 1191 .globl transfer_to_handler
1192 transfer_to_handler: 1192 transfer_to_handler:
1193 stw r22,_NIP(r21) 1193 stw r22,_NIP(r21)
1194 lis r22,MSR_POW@h 1194 lis r22,MSR_POW@h
1195 andc r23,r23,r22 1195 andc r23,r23,r22
1196 stw r23,_MSR(r21) 1196 stw r23,_MSR(r21)
1197 SAVE_GPR(7, r21) 1197 SAVE_GPR(7, r21)
1198 SAVE_4GPRS(8, r21) 1198 SAVE_4GPRS(8, r21)
1199 SAVE_8GPRS(12, r21) 1199 SAVE_8GPRS(12, r21)
1200 SAVE_8GPRS(24, r21) 1200 SAVE_8GPRS(24, r21)
1201 mflr r23 1201 mflr r23
1202 andi. r24,r23,0x3f00 /* get vector offset */ 1202 andi. r24,r23,0x3f00 /* get vector offset */
1203 stw r24,TRAP(r21) 1203 stw r24,TRAP(r21)
1204 li r22,0 1204 li r22,0
1205 stw r22,RESULT(r21) 1205 stw r22,RESULT(r21)
1206 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1206 mtspr SPRG2,r22 /* r1 is now kernel sp */
1207 lwz r24,0(r23) /* virtual address of handler */ 1207 lwz r24,0(r23) /* virtual address of handler */
1208 lwz r23,4(r23) /* where to go when done */ 1208 lwz r23,4(r23) /* where to go when done */
1209 mtspr SRR0,r24 1209 mtspr SRR0,r24
1210 mtspr SRR1,r20 1210 mtspr SRR1,r20
1211 mtlr r23 1211 mtlr r23
1212 SYNC 1212 SYNC
1213 rfi /* jump to handler, enable MMU */ 1213 rfi /* jump to handler, enable MMU */
1214 1214
1215 int_return: 1215 int_return:
1216 mfmsr r28 /* Disable interrupts */ 1216 mfmsr r28 /* Disable interrupts */
1217 li r4,0 1217 li r4,0
1218 ori r4,r4,MSR_EE 1218 ori r4,r4,MSR_EE
1219 andc r28,r28,r4 1219 andc r28,r28,r4
1220 SYNC /* Some chip revs need this... */ 1220 SYNC /* Some chip revs need this... */
1221 mtmsr r28 1221 mtmsr r28
1222 SYNC 1222 SYNC
1223 lwz r2,_CTR(r1) 1223 lwz r2,_CTR(r1)
1224 lwz r0,_LINK(r1) 1224 lwz r0,_LINK(r1)
1225 mtctr r2 1225 mtctr r2
1226 mtlr r0 1226 mtlr r0
1227 lwz r2,_XER(r1) 1227 lwz r2,_XER(r1)
1228 lwz r0,_CCR(r1) 1228 lwz r0,_CCR(r1)
1229 mtspr XER,r2 1229 mtspr XER,r2
1230 mtcrf 0xFF,r0 1230 mtcrf 0xFF,r0
1231 REST_10GPRS(3, r1) 1231 REST_10GPRS(3, r1)
1232 REST_10GPRS(13, r1) 1232 REST_10GPRS(13, r1)
1233 REST_8GPRS(23, r1) 1233 REST_8GPRS(23, r1)
1234 REST_GPR(31, r1) 1234 REST_GPR(31, r1)
1235 lwz r2,_NIP(r1) /* Restore environment */ 1235 lwz r2,_NIP(r1) /* Restore environment */
1236 lwz r0,_MSR(r1) 1236 lwz r0,_MSR(r1)
1237 mtspr SRR0,r2 1237 mtspr SRR0,r2
1238 mtspr SRR1,r0 1238 mtspr SRR1,r0
1239 lwz r0,GPR0(r1) 1239 lwz r0,GPR0(r1)
1240 lwz r2,GPR2(r1) 1240 lwz r2,GPR2(r1)
1241 lwz r1,GPR1(r1) 1241 lwz r1,GPR1(r1)
1242 SYNC 1242 SYNC
1243 rfi 1243 rfi
1244 1244
1245 crit_return: 1245 crit_return:
1246 mfmsr r28 /* Disable interrupts */ 1246 mfmsr r28 /* Disable interrupts */
1247 li r4,0 1247 li r4,0
1248 ori r4,r4,MSR_EE 1248 ori r4,r4,MSR_EE
1249 andc r28,r28,r4 1249 andc r28,r28,r4
1250 SYNC /* Some chip revs need this... */ 1250 SYNC /* Some chip revs need this... */
1251 mtmsr r28 1251 mtmsr r28
1252 SYNC 1252 SYNC
1253 lwz r2,_CTR(r1) 1253 lwz r2,_CTR(r1)
1254 lwz r0,_LINK(r1) 1254 lwz r0,_LINK(r1)
1255 mtctr r2 1255 mtctr r2
1256 mtlr r0 1256 mtlr r0
1257 lwz r2,_XER(r1) 1257 lwz r2,_XER(r1)
1258 lwz r0,_CCR(r1) 1258 lwz r0,_CCR(r1)
1259 mtspr XER,r2 1259 mtspr XER,r2
1260 mtcrf 0xFF,r0 1260 mtcrf 0xFF,r0
1261 REST_10GPRS(3, r1) 1261 REST_10GPRS(3, r1)
1262 REST_10GPRS(13, r1) 1262 REST_10GPRS(13, r1)
1263 REST_8GPRS(23, r1) 1263 REST_8GPRS(23, r1)
1264 REST_GPR(31, r1) 1264 REST_GPR(31, r1)
1265 lwz r2,_NIP(r1) /* Restore environment */ 1265 lwz r2,_NIP(r1) /* Restore environment */
1266 lwz r0,_MSR(r1) 1266 lwz r0,_MSR(r1)
1267 mtspr SPRN_CSRR0,r2 1267 mtspr SPRN_CSRR0,r2
1268 mtspr SPRN_CSRR1,r0 1268 mtspr SPRN_CSRR1,r0
1269 lwz r0,GPR0(r1) 1269 lwz r0,GPR0(r1)
1270 lwz r2,GPR2(r1) 1270 lwz r2,GPR2(r1)
1271 lwz r1,GPR1(r1) 1271 lwz r1,GPR1(r1)
1272 SYNC 1272 SYNC
1273 rfci 1273 rfci
1274 1274
1275 #ifdef CONFIG_440 1275 #ifdef CONFIG_440
1276 mck_return: 1276 mck_return:
1277 mfmsr r28 /* Disable interrupts */ 1277 mfmsr r28 /* Disable interrupts */
1278 li r4,0 1278 li r4,0
1279 ori r4,r4,MSR_EE 1279 ori r4,r4,MSR_EE
1280 andc r28,r28,r4 1280 andc r28,r28,r4
1281 SYNC /* Some chip revs need this... */ 1281 SYNC /* Some chip revs need this... */
1282 mtmsr r28 1282 mtmsr r28
1283 SYNC 1283 SYNC
1284 lwz r2,_CTR(r1) 1284 lwz r2,_CTR(r1)
1285 lwz r0,_LINK(r1) 1285 lwz r0,_LINK(r1)
1286 mtctr r2 1286 mtctr r2
1287 mtlr r0 1287 mtlr r0
1288 lwz r2,_XER(r1) 1288 lwz r2,_XER(r1)
1289 lwz r0,_CCR(r1) 1289 lwz r0,_CCR(r1)
1290 mtspr XER,r2 1290 mtspr XER,r2
1291 mtcrf 0xFF,r0 1291 mtcrf 0xFF,r0
1292 REST_10GPRS(3, r1) 1292 REST_10GPRS(3, r1)
1293 REST_10GPRS(13, r1) 1293 REST_10GPRS(13, r1)
1294 REST_8GPRS(23, r1) 1294 REST_8GPRS(23, r1)
1295 REST_GPR(31, r1) 1295 REST_GPR(31, r1)
1296 lwz r2,_NIP(r1) /* Restore environment */ 1296 lwz r2,_NIP(r1) /* Restore environment */
1297 lwz r0,_MSR(r1) 1297 lwz r0,_MSR(r1)
1298 mtspr SPRN_MCSRR0,r2 1298 mtspr SPRN_MCSRR0,r2
1299 mtspr SPRN_MCSRR1,r0 1299 mtspr SPRN_MCSRR1,r0
1300 lwz r0,GPR0(r1) 1300 lwz r0,GPR0(r1)
1301 lwz r2,GPR2(r1) 1301 lwz r2,GPR2(r1)
1302 lwz r1,GPR1(r1) 1302 lwz r1,GPR1(r1)
1303 SYNC 1303 SYNC
1304 rfmci 1304 rfmci
1305 #endif /* CONFIG_440 */ 1305 #endif /* CONFIG_440 */
1306 1306
1307 1307
1308 .globl get_pvr 1308 .globl get_pvr
1309 get_pvr: 1309 get_pvr:
1310 mfspr r3, PVR 1310 mfspr r3, PVR
1311 blr 1311 blr
1312 1312
1313 /*------------------------------------------------------------------------------- */ 1313 /*------------------------------------------------------------------------------- */
1314 /* Function: out16 */ 1314 /* Function: out16 */
1315 /* Description: Output 16 bits */ 1315 /* Description: Output 16 bits */
1316 /*------------------------------------------------------------------------------- */ 1316 /*------------------------------------------------------------------------------- */
1317 .globl out16 1317 .globl out16
1318 out16: 1318 out16:
1319 sth r4,0x0000(r3) 1319 sth r4,0x0000(r3)
1320 blr 1320 blr
1321 1321
1322 /*------------------------------------------------------------------------------- */ 1322 /*------------------------------------------------------------------------------- */
1323 /* Function: out16r */ 1323 /* Function: out16r */
1324 /* Description: Byte reverse and output 16 bits */ 1324 /* Description: Byte reverse and output 16 bits */
1325 /*------------------------------------------------------------------------------- */ 1325 /*------------------------------------------------------------------------------- */
1326 .globl out16r 1326 .globl out16r
1327 out16r: 1327 out16r:
1328 sthbrx r4,r0,r3 1328 sthbrx r4,r0,r3
1329 blr 1329 blr
1330 1330
1331 /*------------------------------------------------------------------------------- */ 1331 /*------------------------------------------------------------------------------- */
1332 /* Function: out32r */ 1332 /* Function: out32r */
1333 /* Description: Byte reverse and output 32 bits */ 1333 /* Description: Byte reverse and output 32 bits */
1334 /*------------------------------------------------------------------------------- */ 1334 /*------------------------------------------------------------------------------- */
1335 .globl out32r 1335 .globl out32r
1336 out32r: 1336 out32r:
1337 stwbrx r4,r0,r3 1337 stwbrx r4,r0,r3
1338 blr 1338 blr
1339 1339
1340 /*------------------------------------------------------------------------------- */ 1340 /*------------------------------------------------------------------------------- */
1341 /* Function: in16 */ 1341 /* Function: in16 */
1342 /* Description: Input 16 bits */ 1342 /* Description: Input 16 bits */
1343 /*------------------------------------------------------------------------------- */ 1343 /*------------------------------------------------------------------------------- */
1344 .globl in16 1344 .globl in16
1345 in16: 1345 in16:
1346 lhz r3,0x0000(r3) 1346 lhz r3,0x0000(r3)
1347 blr 1347 blr
1348 1348
1349 /*------------------------------------------------------------------------------- */ 1349 /*------------------------------------------------------------------------------- */
1350 /* Function: in16r */ 1350 /* Function: in16r */
1351 /* Description: Input 16 bits and byte reverse */ 1351 /* Description: Input 16 bits and byte reverse */
1352 /*------------------------------------------------------------------------------- */ 1352 /*------------------------------------------------------------------------------- */
1353 .globl in16r 1353 .globl in16r
1354 in16r: 1354 in16r:
1355 lhbrx r3,r0,r3 1355 lhbrx r3,r0,r3
1356 blr 1356 blr
1357 1357
1358 /*------------------------------------------------------------------------------- */ 1358 /*------------------------------------------------------------------------------- */
1359 /* Function: in32r */ 1359 /* Function: in32r */
1360 /* Description: Input 32 bits and byte reverse */ 1360 /* Description: Input 32 bits and byte reverse */
1361 /*------------------------------------------------------------------------------- */ 1361 /*------------------------------------------------------------------------------- */
1362 .globl in32r 1362 .globl in32r
1363 in32r: 1363 in32r:
1364 lwbrx r3,r0,r3 1364 lwbrx r3,r0,r3
1365 blr 1365 blr
1366 1366
1367 /* 1367 /*
1368 * void relocate_code (addr_sp, gd, addr_moni) 1368 * void relocate_code (addr_sp, gd, addr_moni)
1369 * 1369 *
1370 * This "function" does not return, instead it continues in RAM 1370 * This "function" does not return, instead it continues in RAM
1371 * after relocating the monitor code. 1371 * after relocating the monitor code.
1372 * 1372 *
1373 * r3 = Relocated stack pointer 1373 * r3 = Relocated stack pointer
1374 * r4 = Relocated global data pointer 1374 * r4 = Relocated global data pointer
1375 * r5 = Relocated text pointer 1375 * r5 = Relocated text pointer
1376 */ 1376 */
1377 .globl relocate_code 1377 .globl relocate_code
1378 relocate_code: 1378 relocate_code:
1379 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) 1379 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1380 /* 1380 /*
1381 * We need to flush the initial global data (gd_t) before the dcache 1381 * We need to flush the initial global data (gd_t) before the dcache
1382 * will be invalidated. 1382 * will be invalidated.
1383 */ 1383 */
1384 1384
1385 /* Save registers */ 1385 /* Save registers */
1386 mr r9, r3 1386 mr r9, r3
1387 mr r10, r4 1387 mr r10, r4
1388 mr r11, r5 1388 mr r11, r5
1389 1389
1390 /* Flush initial global data range */ 1390 /* Flush initial global data range */
1391 mr r3, r4 1391 mr r3, r4
1392 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l 1392 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1393 bl flush_dcache_range 1393 bl flush_dcache_range
1394 1394
1395 #if defined(CONFIG_SYS_INIT_DCACHE_CS) 1395 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1396 /* 1396 /*
1397 * Undo the earlier data cache set-up for the primordial stack and 1397 * Undo the earlier data cache set-up for the primordial stack and
1398 * data area. First, invalidate the data cache and then disable data 1398 * data area. First, invalidate the data cache and then disable data
1399 * cacheability for that area. Finally, restore the EBC values, if 1399 * cacheability for that area. Finally, restore the EBC values, if
1400 * any. 1400 * any.
1401 */ 1401 */
1402 1402
1403 /* Invalidate the primordial stack and data area in cache */ 1403 /* Invalidate the primordial stack and data area in cache */
1404 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h 1404 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1405 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l 1405 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1406 1406
1407 lis r4, CONFIG_SYS_INIT_RAM_END@h 1407 lis r4, CONFIG_SYS_INIT_RAM_END@h
1408 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l 1408 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1409 add r4, r4, r3 1409 add r4, r4, r3
1410 1410
1411 bl invalidate_dcache_range 1411 bl invalidate_dcache_range
1412 1412
1413 /* Disable cacheability for the region */ 1413 /* Disable cacheability for the region */
1414 mfdccr r3 1414 mfdccr r3
1415 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h 1415 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1416 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l 1416 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1417 and r3, r3, r4 1417 and r3, r3, r4
1418 mtdccr r3 1418 mtdccr r3
1419 1419
1420 /* Restore the EBC parameters */ 1420 /* Restore the EBC parameters */
1421 li r3, PBxAP 1421 li r3, PBxAP
1422 mtdcr EBC0_CFGADDR, r3 1422 mtdcr EBC0_CFGADDR, r3
1423 lis r3, PBxAP_VAL@h 1423 lis r3, PBxAP_VAL@h
1424 ori r3, r3, PBxAP_VAL@l 1424 ori r3, r3, PBxAP_VAL@l
1425 mtdcr EBC0_CFGDATA, r3 1425 mtdcr EBC0_CFGDATA, r3
1426 1426
1427 li r3, PBxCR 1427 li r3, PBxCR
1428 mtdcr EBC0_CFGADDR, r3 1428 mtdcr EBC0_CFGADDR, r3
1429 lis r3, PBxCR_VAL@h 1429 lis r3, PBxCR_VAL@h
1430 ori r3, r3, PBxCR_VAL@l 1430 ori r3, r3, PBxCR_VAL@l
1431 mtdcr EBC0_CFGDATA, r3 1431 mtdcr EBC0_CFGDATA, r3
1432 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ 1432 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1433 1433
1434 /* Restore registers */ 1434 /* Restore registers */
1435 mr r3, r9 1435 mr r3, r9
1436 mr r4, r10 1436 mr r4, r10
1437 mr r5, r11 1437 mr r5, r11
1438 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ 1438 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1439 1439
1440 #ifdef CONFIG_SYS_INIT_RAM_DCACHE 1440 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1441 /* 1441 /*
1442 * Unlock the previously locked d-cache 1442 * Unlock the previously locked d-cache
1443 */ 1443 */
1444 msync 1444 msync
1445 isync 1445 isync
1446 /* set TFLOOR/NFLOOR to 0 again */ 1446 /* set TFLOOR/NFLOOR to 0 again */
1447 lis r6,0x0001 1447 lis r6,0x0001
1448 ori r6,r6,0xf800 1448 ori r6,r6,0xf800
1449 mtspr SPRN_DVLIM,r6 1449 mtspr SPRN_DVLIM,r6
1450 lis r6,0x0000 1450 lis r6,0x0000
1451 ori r6,r6,0x0000 1451 ori r6,r6,0x0000
1452 mtspr SPRN_DNV0,r6 1452 mtspr SPRN_DNV0,r6
1453 mtspr SPRN_DNV1,r6 1453 mtspr SPRN_DNV1,r6
1454 mtspr SPRN_DNV2,r6 1454 mtspr SPRN_DNV2,r6
1455 mtspr SPRN_DNV3,r6 1455 mtspr SPRN_DNV3,r6
1456 mtspr SPRN_DTV0,r6 1456 mtspr SPRN_DTV0,r6
1457 mtspr SPRN_DTV1,r6 1457 mtspr SPRN_DTV1,r6
1458 mtspr SPRN_DTV2,r6 1458 mtspr SPRN_DTV2,r6
1459 mtspr SPRN_DTV3,r6 1459 mtspr SPRN_DTV3,r6
1460 msync 1460 msync
1461 isync 1461 isync
1462
1463 /* Invalidate data cache, now no longer our stack */
1464 dccci 0,0
1465 sync
1466 isync
1462 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ 1467 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1463 1468
1464 /* 1469 /*
1465 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) 1470 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1466 * to speed up the boot process. Now this cache needs to be disabled. 1471 * to speed up the boot process. Now this cache needs to be disabled.
1467 */ 1472 */
1468 #if defined(CONFIG_440) 1473 #if defined(CONFIG_440)
1469 /* Clear all potential pending exceptions */ 1474 /* Clear all potential pending exceptions */
1470 mfspr r1,SPRN_MCSR 1475 mfspr r1,SPRN_MCSR
1471 mtspr SPRN_MCSR,r1 1476 mtspr SPRN_MCSR,r1
1472 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ 1477 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1473 tlbre r0,r1,0x0002 /* Read contents */ 1478 tlbre r0,r1,0x0002 /* Read contents */
1474 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ 1479 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1475 tlbwe r0,r1,0x0002 /* Save it out */ 1480 tlbwe r0,r1,0x0002 /* Save it out */
1476 sync 1481 sync
1477 isync 1482 isync
1478 #endif /* defined(CONFIG_440) */ 1483 #endif /* defined(CONFIG_440) */
1479 mr r1, r3 /* Set new stack pointer */ 1484 mr r1, r3 /* Set new stack pointer */
1480 mr r9, r4 /* Save copy of Init Data pointer */ 1485 mr r9, r4 /* Save copy of Init Data pointer */
1481 mr r10, r5 /* Save copy of Destination Address */ 1486 mr r10, r5 /* Save copy of Destination Address */
1482 1487
1483 GET_GOT 1488 GET_GOT
1484 mr r3, r5 /* Destination Address */ 1489 mr r3, r5 /* Destination Address */
1485 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1490 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1486 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 1491 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1487 lwz r5, GOT(__init_end) 1492 lwz r5, GOT(__init_end)
1488 sub r5, r5, r4 1493 sub r5, r5, r4
1489 li r6, L1_CACHE_BYTES /* Cache Line Size */ 1494 li r6, L1_CACHE_BYTES /* Cache Line Size */
1490 1495
1491 /* 1496 /*
1492 * Fix GOT pointer: 1497 * Fix GOT pointer:
1493 * 1498 *
1494 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1499 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1495 * 1500 *
1496 * Offset: 1501 * Offset:
1497 */ 1502 */
1498 sub r15, r10, r4 1503 sub r15, r10, r4
1499 1504
1500 /* First our own GOT */ 1505 /* First our own GOT */
1501 add r12, r12, r15 1506 add r12, r12, r15
1502 /* then the one used by the C code */ 1507 /* then the one used by the C code */
1503 add r30, r30, r15 1508 add r30, r30, r15
1504 1509
1505 /* 1510 /*
1506 * Now relocate code 1511 * Now relocate code
1507 */ 1512 */
1508 1513
1509 cmplw cr1,r3,r4 1514 cmplw cr1,r3,r4
1510 addi r0,r5,3 1515 addi r0,r5,3
1511 srwi. r0,r0,2 1516 srwi. r0,r0,2
1512 beq cr1,4f /* In place copy is not necessary */ 1517 beq cr1,4f /* In place copy is not necessary */
1513 beq 7f /* Protect against 0 count */ 1518 beq 7f /* Protect against 0 count */
1514 mtctr r0 1519 mtctr r0
1515 bge cr1,2f 1520 bge cr1,2f
1516 1521
1517 la r8,-4(r4) 1522 la r8,-4(r4)
1518 la r7,-4(r3) 1523 la r7,-4(r3)
1519 1: lwzu r0,4(r8) 1524 1: lwzu r0,4(r8)
1520 stwu r0,4(r7) 1525 stwu r0,4(r7)
1521 bdnz 1b 1526 bdnz 1b
1522 b 4f 1527 b 4f
1523 1528
1524 2: slwi r0,r0,2 1529 2: slwi r0,r0,2
1525 add r8,r4,r0 1530 add r8,r4,r0
1526 add r7,r3,r0 1531 add r7,r3,r0
1527 3: lwzu r0,-4(r8) 1532 3: lwzu r0,-4(r8)
1528 stwu r0,-4(r7) 1533 stwu r0,-4(r7)
1529 bdnz 3b 1534 bdnz 3b
1530 1535
1531 /* 1536 /*
1532 * Now flush the cache: note that we must start from a cache aligned 1537 * Now flush the cache: note that we must start from a cache aligned
1533 * address. Otherwise we might miss one cache line. 1538 * address. Otherwise we might miss one cache line.
1534 */ 1539 */
1535 4: cmpwi r6,0 1540 4: cmpwi r6,0
1536 add r5,r3,r5 1541 add r5,r3,r5
1537 beq 7f /* Always flush prefetch queue in any case */ 1542 beq 7f /* Always flush prefetch queue in any case */
1538 subi r0,r6,1 1543 subi r0,r6,1
1539 andc r3,r3,r0 1544 andc r3,r3,r0
1540 mr r4,r3 1545 mr r4,r3
1541 5: dcbst 0,r4 1546 5: dcbst 0,r4
1542 add r4,r4,r6 1547 add r4,r4,r6
1543 cmplw r4,r5 1548 cmplw r4,r5
1544 blt 5b 1549 blt 5b
1545 sync /* Wait for all dcbst to complete on bus */ 1550 sync /* Wait for all dcbst to complete on bus */
1546 mr r4,r3 1551 mr r4,r3
1547 6: icbi 0,r4 1552 6: icbi 0,r4
1548 add r4,r4,r6 1553 add r4,r4,r6
1549 cmplw r4,r5 1554 cmplw r4,r5
1550 blt 6b 1555 blt 6b
1551 7: sync /* Wait for all icbi to complete on bus */ 1556 7: sync /* Wait for all icbi to complete on bus */
1552 isync 1557 isync
1553 1558
1554 /* 1559 /*
1555 * We are done. Do not return, instead branch to second part of board 1560 * We are done. Do not return, instead branch to second part of board
1556 * initialization, now running from RAM. 1561 * initialization, now running from RAM.
1557 */ 1562 */
1558 1563
1559 addi r0, r10, in_ram - _start + _START_OFFSET 1564 addi r0, r10, in_ram - _start + _START_OFFSET
1560 mtlr r0 1565 mtlr r0
1561 blr /* NEVER RETURNS! */ 1566 blr /* NEVER RETURNS! */
1562 1567
1563 in_ram: 1568 in_ram:
1564 1569
1565 /* 1570 /*
1566 * Relocation Function, r12 point to got2+0x8000 1571 * Relocation Function, r12 point to got2+0x8000
1567 * 1572 *
1568 * Adjust got2 pointers, no need to check for 0, this code 1573 * Adjust got2 pointers, no need to check for 0, this code
1569 * already puts a few entries in the table. 1574 * already puts a few entries in the table.
1570 */ 1575 */
1571 li r0,__got2_entries@sectoff@l 1576 li r0,__got2_entries@sectoff@l
1572 la r3,GOT(_GOT2_TABLE_) 1577 la r3,GOT(_GOT2_TABLE_)
1573 lwz r11,GOT(_GOT2_TABLE_) 1578 lwz r11,GOT(_GOT2_TABLE_)
1574 mtctr r0 1579 mtctr r0
1575 sub r11,r3,r11 1580 sub r11,r3,r11
1576 addi r3,r3,-4 1581 addi r3,r3,-4
1577 1: lwzu r0,4(r3) 1582 1: lwzu r0,4(r3)
1578 cmpwi r0,0 1583 cmpwi r0,0
1579 beq- 2f 1584 beq- 2f
1580 add r0,r0,r11 1585 add r0,r0,r11
1581 stw r0,0(r3) 1586 stw r0,0(r3)
1582 2: bdnz 1b 1587 2: bdnz 1b
1583 1588
1584 /* 1589 /*
1585 * Now adjust the fixups and the pointers to the fixups 1590 * Now adjust the fixups and the pointers to the fixups
1586 * in case we need to move ourselves again. 1591 * in case we need to move ourselves again.
1587 */ 1592 */
1588 li r0,__fixup_entries@sectoff@l 1593 li r0,__fixup_entries@sectoff@l
1589 lwz r3,GOT(_FIXUP_TABLE_) 1594 lwz r3,GOT(_FIXUP_TABLE_)
1590 cmpwi r0,0 1595 cmpwi r0,0
1591 mtctr r0 1596 mtctr r0
1592 addi r3,r3,-4 1597 addi r3,r3,-4
1593 beq 4f 1598 beq 4f
1594 3: lwzu r4,4(r3) 1599 3: lwzu r4,4(r3)
1595 lwzux r0,r4,r11 1600 lwzux r0,r4,r11
1596 add r0,r0,r11 1601 add r0,r0,r11
1597 stw r10,0(r3) 1602 stw r10,0(r3)
1598 stw r0,0(r4) 1603 stw r0,0(r4)
1599 bdnz 3b 1604 bdnz 3b
1600 4: 1605 4:
1601 clear_bss: 1606 clear_bss:
1602 /* 1607 /*
1603 * Now clear BSS segment 1608 * Now clear BSS segment
1604 */ 1609 */
1605 lwz r3,GOT(__bss_start) 1610 lwz r3,GOT(__bss_start)
1606 lwz r4,GOT(_end) 1611 lwz r4,GOT(_end)
1607 1612
1608 cmplw 0, r3, r4 1613 cmplw 0, r3, r4
1609 beq 7f 1614 beq 7f
1610 1615
1611 li r0, 0 1616 li r0, 0
1612 1617
1613 andi. r5, r4, 3 1618 andi. r5, r4, 3
1614 beq 6f 1619 beq 6f
1615 sub r4, r4, r5 1620 sub r4, r4, r5
1616 mtctr r5 1621 mtctr r5
1617 mr r5, r4 1622 mr r5, r4
1618 5: stb r0, 0(r5) 1623 5: stb r0, 0(r5)
1619 addi r5, r5, 1 1624 addi r5, r5, 1
1620 bdnz 5b 1625 bdnz 5b
1621 6: 1626 6:
1622 stw r0, 0(r3) 1627 stw r0, 0(r3)
1623 addi r3, r3, 4 1628 addi r3, r3, 4
1624 cmplw 0, r3, r4 1629 cmplw 0, r3, r4
1625 bne 6b 1630 bne 6b
1626 1631
1627 7: 1632 7:
1628 mr r3, r9 /* Init Data pointer */ 1633 mr r3, r9 /* Init Data pointer */
1629 mr r4, r10 /* Destination Address */ 1634 mr r4, r10 /* Destination Address */
1630 bl board_init_r 1635 bl board_init_r
1631 1636
1632 /* 1637 /*
1633 * Copy exception vector code to low memory 1638 * Copy exception vector code to low memory
1634 * 1639 *
1635 * r3: dest_addr 1640 * r3: dest_addr
1636 * r7: source address, r8: end address, r9: target address 1641 * r7: source address, r8: end address, r9: target address
1637 */ 1642 */
1638 .globl trap_init 1643 .globl trap_init
1639 trap_init: 1644 trap_init:
1640 mflr r4 /* save link register */ 1645 mflr r4 /* save link register */
1641 GET_GOT 1646 GET_GOT
1642 lwz r7, GOT(_start_of_vectors) 1647 lwz r7, GOT(_start_of_vectors)
1643 lwz r8, GOT(_end_of_vectors) 1648 lwz r8, GOT(_end_of_vectors)
1644 1649
1645 li r9, 0x100 /* reset vector always at 0x100 */ 1650 li r9, 0x100 /* reset vector always at 0x100 */
1646 1651
1647 cmplw 0, r7, r8 1652 cmplw 0, r7, r8
1648 bgelr /* return if r7>=r8 - just in case */ 1653 bgelr /* return if r7>=r8 - just in case */
1649 1: 1654 1:
1650 lwz r0, 0(r7) 1655 lwz r0, 0(r7)
1651 stw r0, 0(r9) 1656 stw r0, 0(r9)
1652 addi r7, r7, 4 1657 addi r7, r7, 4
1653 addi r9, r9, 4 1658 addi r9, r9, 4
1654 cmplw 0, r7, r8 1659 cmplw 0, r7, r8
1655 bne 1b 1660 bne 1b
1656 1661
1657 /* 1662 /*
1658 * relocate `hdlr' and `int_return' entries 1663 * relocate `hdlr' and `int_return' entries
1659 */ 1664 */
1660 li r7, .L_MachineCheck - _start + _START_OFFSET 1665 li r7, .L_MachineCheck - _start + _START_OFFSET
1661 li r8, Alignment - _start + _START_OFFSET 1666 li r8, Alignment - _start + _START_OFFSET
1662 2: 1667 2:
1663 bl trap_reloc 1668 bl trap_reloc
1664 addi r7, r7, 0x100 /* next exception vector */ 1669 addi r7, r7, 0x100 /* next exception vector */
1665 cmplw 0, r7, r8 1670 cmplw 0, r7, r8
1666 blt 2b 1671 blt 2b
1667 1672
1668 li r7, .L_Alignment - _start + _START_OFFSET 1673 li r7, .L_Alignment - _start + _START_OFFSET
1669 bl trap_reloc 1674 bl trap_reloc
1670 1675
1671 li r7, .L_ProgramCheck - _start + _START_OFFSET 1676 li r7, .L_ProgramCheck - _start + _START_OFFSET
1672 bl trap_reloc 1677 bl trap_reloc
1673 1678
1674 #ifdef CONFIG_440 1679 #ifdef CONFIG_440
1675 li r7, .L_FPUnavailable - _start + _START_OFFSET 1680 li r7, .L_FPUnavailable - _start + _START_OFFSET
1676 bl trap_reloc 1681 bl trap_reloc
1677 1682
1678 li r7, .L_Decrementer - _start + _START_OFFSET 1683 li r7, .L_Decrementer - _start + _START_OFFSET
1679 bl trap_reloc 1684 bl trap_reloc
1680 1685
1681 li r7, .L_APU - _start + _START_OFFSET 1686 li r7, .L_APU - _start + _START_OFFSET
1682 bl trap_reloc 1687 bl trap_reloc
1683 1688
1684 li r7, .L_InstructionTLBError - _start + _START_OFFSET 1689 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1685 bl trap_reloc 1690 bl trap_reloc
1686 1691
1687 li r7, .L_DataTLBError - _start + _START_OFFSET 1692 li r7, .L_DataTLBError - _start + _START_OFFSET
1688 bl trap_reloc 1693 bl trap_reloc
1689 #else /* CONFIG_440 */ 1694 #else /* CONFIG_440 */
1690 li r7, .L_PIT - _start + _START_OFFSET 1695 li r7, .L_PIT - _start + _START_OFFSET
1691 bl trap_reloc 1696 bl trap_reloc
1692 1697
1693 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET 1698 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1694 bl trap_reloc 1699 bl trap_reloc
1695 1700
1696 li r7, .L_DataTLBMiss - _start + _START_OFFSET 1701 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1697 bl trap_reloc 1702 bl trap_reloc
1698 #endif /* CONFIG_440 */ 1703 #endif /* CONFIG_440 */
1699 1704
1700 li r7, .L_DebugBreakpoint - _start + _START_OFFSET 1705 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1701 bl trap_reloc 1706 bl trap_reloc
1702 1707
1703 #if !defined(CONFIG_440) 1708 #if !defined(CONFIG_440)
1704 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ 1709 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1705 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ 1710 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1706 mtmsr r7 /* change MSR */ 1711 mtmsr r7 /* change MSR */
1707 #else 1712 #else
1708 bl __440_msr_set 1713 bl __440_msr_set
1709 b __440_msr_continue 1714 b __440_msr_continue
1710 1715
1711 __440_msr_set: 1716 __440_msr_set:
1712 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ 1717 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1713 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ 1718 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1714 mtspr SPRN_SRR1,r7 1719 mtspr SPRN_SRR1,r7
1715 mflr r7 1720 mflr r7
1716 mtspr SPRN_SRR0,r7 1721 mtspr SPRN_SRR0,r7
1717 rfi 1722 rfi
1718 __440_msr_continue: 1723 __440_msr_continue:
1719 #endif 1724 #endif
1720 1725
1721 mtlr r4 /* restore link register */ 1726 mtlr r4 /* restore link register */
1722 blr 1727 blr
1723 1728
1724 #if defined(CONFIG_440) 1729 #if defined(CONFIG_440)
1725 /*----------------------------------------------------------------------------+ 1730 /*----------------------------------------------------------------------------+
1726 | dcbz_area. 1731 | dcbz_area.
1727 +----------------------------------------------------------------------------*/ 1732 +----------------------------------------------------------------------------*/
1728 function_prolog(dcbz_area) 1733 function_prolog(dcbz_area)
1729 rlwinm. r5,r4,0,27,31 1734 rlwinm. r5,r4,0,27,31
1730 rlwinm r5,r4,27,5,31 1735 rlwinm r5,r4,27,5,31
1731 beq ..d_ra2 1736 beq ..d_ra2
1732 addi r5,r5,0x0001 1737 addi r5,r5,0x0001
1733 ..d_ra2:mtctr r5 1738 ..d_ra2:mtctr r5
1734 ..d_ag2:dcbz r0,r3 1739 ..d_ag2:dcbz r0,r3
1735 addi r3,r3,32 1740 addi r3,r3,32
1736 bdnz ..d_ag2 1741 bdnz ..d_ag2
1737 sync 1742 sync
1738 blr 1743 blr
1739 function_epilog(dcbz_area) 1744 function_epilog(dcbz_area)
1740 #endif /* CONFIG_440 */ 1745 #endif /* CONFIG_440 */
1741 #endif /* CONFIG_NAND_SPL */ 1746 #endif /* CONFIG_NAND_SPL */
1742 1747
1743 /*------------------------------------------------------------------------------- */ 1748 /*------------------------------------------------------------------------------- */
1744 /* Function: in8 */ 1749 /* Function: in8 */
1745 /* Description: Input 8 bits */ 1750 /* Description: Input 8 bits */
1746 /*------------------------------------------------------------------------------- */ 1751 /*------------------------------------------------------------------------------- */
1747 .globl in8 1752 .globl in8
1748 in8: 1753 in8:
1749 lbz r3,0x0000(r3) 1754 lbz r3,0x0000(r3)
1750 blr 1755 blr
1751 1756
1752 /*------------------------------------------------------------------------------- */ 1757 /*------------------------------------------------------------------------------- */
1753 /* Function: out8 */ 1758 /* Function: out8 */
1754 /* Description: Output 8 bits */ 1759 /* Description: Output 8 bits */
1755 /*------------------------------------------------------------------------------- */ 1760 /*------------------------------------------------------------------------------- */
1756 .globl out8 1761 .globl out8
1757 out8: 1762 out8:
1758 stb r4,0x0000(r3) 1763 stb r4,0x0000(r3)
1759 blr 1764 blr
1760 1765
1761 /*------------------------------------------------------------------------------- */ 1766 /*------------------------------------------------------------------------------- */
1762 /* Function: out32 */ 1767 /* Function: out32 */
1763 /* Description: Output 32 bits */ 1768 /* Description: Output 32 bits */
1764 /*------------------------------------------------------------------------------- */ 1769 /*------------------------------------------------------------------------------- */
1765 .globl out32 1770 .globl out32
1766 out32: 1771 out32:
1767 stw r4,0x0000(r3) 1772 stw r4,0x0000(r3)
1768 blr 1773 blr
1769 1774
1770 /*------------------------------------------------------------------------------- */ 1775 /*------------------------------------------------------------------------------- */
1771 /* Function: in32 */ 1776 /* Function: in32 */
1772 /* Description: Input 32 bits */ 1777 /* Description: Input 32 bits */
1773 /*------------------------------------------------------------------------------- */ 1778 /*------------------------------------------------------------------------------- */
1774 .globl in32 1779 .globl in32
1775 in32: 1780 in32:
1776 lwz 3,0x0000(3) 1781 lwz 3,0x0000(3)
1777 blr 1782 blr
1778 1783
1779 /**************************************************************************/ 1784 /**************************************************************************/
1780 /* PPC405EP specific stuff */ 1785 /* PPC405EP specific stuff */
1781 /**************************************************************************/ 1786 /**************************************************************************/
1782 #ifdef CONFIG_405EP 1787 #ifdef CONFIG_405EP
1783 ppc405ep_init: 1788 ppc405ep_init:
1784 1789
1785 #ifdef CONFIG_BUBINGA 1790 #ifdef CONFIG_BUBINGA
1786 /* 1791 /*
1787 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate 1792 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1788 * function) to support FPGA and NVRAM accesses below. 1793 * function) to support FPGA and NVRAM accesses below.
1789 */ 1794 */
1790 1795
1791 lis r3,GPIO0_OSRH@h /* config GPIO output select */ 1796 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1792 ori r3,r3,GPIO0_OSRH@l 1797 ori r3,r3,GPIO0_OSRH@l
1793 lis r4,CONFIG_SYS_GPIO0_OSRH@h 1798 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1794 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l 1799 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1795 stw r4,0(r3) 1800 stw r4,0(r3)
1796 lis r3,GPIO0_OSRL@h 1801 lis r3,GPIO0_OSRL@h
1797 ori r3,r3,GPIO0_OSRL@l 1802 ori r3,r3,GPIO0_OSRL@l
1798 lis r4,CONFIG_SYS_GPIO0_OSRL@h 1803 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1799 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l 1804 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1800 stw r4,0(r3) 1805 stw r4,0(r3)
1801 1806
1802 lis r3,GPIO0_ISR1H@h /* config GPIO input select */ 1807 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1803 ori r3,r3,GPIO0_ISR1H@l 1808 ori r3,r3,GPIO0_ISR1H@l
1804 lis r4,CONFIG_SYS_GPIO0_ISR1H@h 1809 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1805 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l 1810 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1806 stw r4,0(r3) 1811 stw r4,0(r3)
1807 lis r3,GPIO0_ISR1L@h 1812 lis r3,GPIO0_ISR1L@h
1808 ori r3,r3,GPIO0_ISR1L@l 1813 ori r3,r3,GPIO0_ISR1L@l
1809 lis r4,CONFIG_SYS_GPIO0_ISR1L@h 1814 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1810 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l 1815 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1811 stw r4,0(r3) 1816 stw r4,0(r3)
1812 1817
1813 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ 1818 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1814 ori r3,r3,GPIO0_TSRH@l 1819 ori r3,r3,GPIO0_TSRH@l
1815 lis r4,CONFIG_SYS_GPIO0_TSRH@h 1820 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1816 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l 1821 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1817 stw r4,0(r3) 1822 stw r4,0(r3)
1818 lis r3,GPIO0_TSRL@h 1823 lis r3,GPIO0_TSRL@h
1819 ori r3,r3,GPIO0_TSRL@l 1824 ori r3,r3,GPIO0_TSRL@l
1820 lis r4,CONFIG_SYS_GPIO0_TSRL@h 1825 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1821 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l 1826 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1822 stw r4,0(r3) 1827 stw r4,0(r3)
1823 1828
1824 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ 1829 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1825 ori r3,r3,GPIO0_TCR@l 1830 ori r3,r3,GPIO0_TCR@l
1826 lis r4,CONFIG_SYS_GPIO0_TCR@h 1831 lis r4,CONFIG_SYS_GPIO0_TCR@h
1827 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l 1832 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1828 stw r4,0(r3) 1833 stw r4,0(r3)
1829 1834
1830 li r3,PB1AP /* program EBC bank 1 for RTC access */ 1835 li r3,PB1AP /* program EBC bank 1 for RTC access */
1831 mtdcr EBC0_CFGADDR,r3 1836 mtdcr EBC0_CFGADDR,r3
1832 lis r3,CONFIG_SYS_EBC_PB1AP@h 1837 lis r3,CONFIG_SYS_EBC_PB1AP@h
1833 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l 1838 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1834 mtdcr EBC0_CFGDATA,r3 1839 mtdcr EBC0_CFGDATA,r3
1835 li r3,PB1CR 1840 li r3,PB1CR
1836 mtdcr EBC0_CFGADDR,r3 1841 mtdcr EBC0_CFGADDR,r3
1837 lis r3,CONFIG_SYS_EBC_PB1CR@h 1842 lis r3,CONFIG_SYS_EBC_PB1CR@h
1838 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l 1843 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1839 mtdcr EBC0_CFGDATA,r3 1844 mtdcr EBC0_CFGDATA,r3
1840 1845
1841 li r3,PB1AP /* program EBC bank 1 for RTC access */ 1846 li r3,PB1AP /* program EBC bank 1 for RTC access */
1842 mtdcr EBC0_CFGADDR,r3 1847 mtdcr EBC0_CFGADDR,r3
1843 lis r3,CONFIG_SYS_EBC_PB1AP@h 1848 lis r3,CONFIG_SYS_EBC_PB1AP@h
1844 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l 1849 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1845 mtdcr EBC0_CFGDATA,r3 1850 mtdcr EBC0_CFGDATA,r3
1846 li r3,PB1CR 1851 li r3,PB1CR
1847 mtdcr EBC0_CFGADDR,r3 1852 mtdcr EBC0_CFGADDR,r3
1848 lis r3,CONFIG_SYS_EBC_PB1CR@h 1853 lis r3,CONFIG_SYS_EBC_PB1CR@h
1849 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l 1854 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1850 mtdcr EBC0_CFGDATA,r3 1855 mtdcr EBC0_CFGDATA,r3
1851 1856
1852 li r3,PB4AP /* program EBC bank 4 for FPGA access */ 1857 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1853 mtdcr EBC0_CFGADDR,r3 1858 mtdcr EBC0_CFGADDR,r3
1854 lis r3,CONFIG_SYS_EBC_PB4AP@h 1859 lis r3,CONFIG_SYS_EBC_PB4AP@h
1855 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l 1860 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1856 mtdcr EBC0_CFGDATA,r3 1861 mtdcr EBC0_CFGDATA,r3
1857 li r3,PB4CR 1862 li r3,PB4CR
1858 mtdcr EBC0_CFGADDR,r3 1863 mtdcr EBC0_CFGADDR,r3
1859 lis r3,CONFIG_SYS_EBC_PB4CR@h 1864 lis r3,CONFIG_SYS_EBC_PB4CR@h
1860 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l 1865 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1861 mtdcr EBC0_CFGDATA,r3 1866 mtdcr EBC0_CFGDATA,r3
1862 #endif 1867 #endif
1863 1868
1864 /* 1869 /*
1865 !----------------------------------------------------------------------- 1870 !-----------------------------------------------------------------------
1866 ! Check to see if chip is in bypass mode. 1871 ! Check to see if chip is in bypass mode.
1867 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a 1872 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1868 ! CPU reset Otherwise, skip this step and keep going. 1873 ! CPU reset Otherwise, skip this step and keep going.
1869 ! Note: Running BIOS in bypass mode is not supported since PLB speed 1874 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1870 ! will not be fast enough for the SDRAM (min 66MHz) 1875 ! will not be fast enough for the SDRAM (min 66MHz)
1871 !----------------------------------------------------------------------- 1876 !-----------------------------------------------------------------------
1872 */ 1877 */
1873 mfdcr r5, CPC0_PLLMR1 1878 mfdcr r5, CPC0_PLLMR1
1874 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ 1879 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1875 cmpi cr0,0,r4,0x1 1880 cmpi cr0,0,r4,0x1
1876 1881
1877 beq pll_done /* if SSCS =b'1' then PLL has */ 1882 beq pll_done /* if SSCS =b'1' then PLL has */
1878 /* already been set */ 1883 /* already been set */
1879 /* and CPU has been reset */ 1884 /* and CPU has been reset */
1880 /* so skip to next section */ 1885 /* so skip to next section */
1881 1886
1882 #ifdef CONFIG_BUBINGA 1887 #ifdef CONFIG_BUBINGA
1883 /* 1888 /*
1884 !----------------------------------------------------------------------- 1889 !-----------------------------------------------------------------------
1885 ! Read NVRAM to get value to write in PLLMR. 1890 ! Read NVRAM to get value to write in PLLMR.
1886 ! If value has not been correctly saved, write default value 1891 ! If value has not been correctly saved, write default value
1887 ! Default config values (assuming on-board 33MHz SYS_CLK) are above. 1892 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1888 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. 1893 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1889 ! 1894 !
1890 ! WARNING: This code assumes the first three words in the nvram_t 1895 ! WARNING: This code assumes the first three words in the nvram_t
1891 ! structure in openbios.h. Changing the beginning of 1896 ! structure in openbios.h. Changing the beginning of
1892 ! the structure will break this code. 1897 ! the structure will break this code.
1893 ! 1898 !
1894 !----------------------------------------------------------------------- 1899 !-----------------------------------------------------------------------
1895 */ 1900 */
1896 addis r3,0,NVRAM_BASE@h 1901 addis r3,0,NVRAM_BASE@h
1897 addi r3,r3,NVRAM_BASE@l 1902 addi r3,r3,NVRAM_BASE@l
1898 1903
1899 lwz r4, 0(r3) 1904 lwz r4, 0(r3)
1900 addis r5,0,NVRVFY1@h 1905 addis r5,0,NVRVFY1@h
1901 addi r5,r5,NVRVFY1@l 1906 addi r5,r5,NVRVFY1@l
1902 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ 1907 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1903 bne ..no_pllset 1908 bne ..no_pllset
1904 addi r3,r3,4 1909 addi r3,r3,4
1905 lwz r4, 0(r3) 1910 lwz r4, 0(r3)
1906 addis r5,0,NVRVFY2@h 1911 addis r5,0,NVRVFY2@h
1907 addi r5,r5,NVRVFY2@l 1912 addi r5,r5,NVRVFY2@l
1908 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ 1913 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1909 bne ..no_pllset 1914 bne ..no_pllset
1910 addi r3,r3,8 /* Skip over conf_size */ 1915 addi r3,r3,8 /* Skip over conf_size */
1911 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ 1916 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1912 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ 1917 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1913 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ 1918 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1914 cmpi cr0,0,r5,1 /* See if PLL is locked */ 1919 cmpi cr0,0,r5,1 /* See if PLL is locked */
1915 beq pll_write 1920 beq pll_write
1916 ..no_pllset: 1921 ..no_pllset:
1917 #endif /* CONFIG_BUBINGA */ 1922 #endif /* CONFIG_BUBINGA */
1918 1923
1919 #ifdef CONFIG_TAIHU 1924 #ifdef CONFIG_TAIHU
1920 mfdcr r4, CPC0_BOOT 1925 mfdcr r4, CPC0_BOOT
1921 andi. r5, r4, CPC0_BOOT_SEP@l 1926 andi. r5, r4, CPC0_BOOT_SEP@l
1922 bne strap_1 /* serial eeprom present */ 1927 bne strap_1 /* serial eeprom present */
1923 addis r5,0,CPLD_REG0_ADDR@h 1928 addis r5,0,CPLD_REG0_ADDR@h
1924 ori r5,r5,CPLD_REG0_ADDR@l 1929 ori r5,r5,CPLD_REG0_ADDR@l
1925 andi. r5, r5, 0x10 1930 andi. r5, r5, 0x10
1926 bne _pci_66mhz 1931 bne _pci_66mhz
1927 #endif /* CONFIG_TAIHU */ 1932 #endif /* CONFIG_TAIHU */
1928 1933
1929 #if defined(CONFIG_ZEUS) 1934 #if defined(CONFIG_ZEUS)
1930 mfdcr r4, CPC0_BOOT 1935 mfdcr r4, CPC0_BOOT
1931 andi. r5, r4, CPC0_BOOT_SEP@l 1936 andi. r5, r4, CPC0_BOOT_SEP@l
1932 bne strap_1 /* serial eeprom present */ 1937 bne strap_1 /* serial eeprom present */
1933 lis r3,0x0000 1938 lis r3,0x0000
1934 addi r3,r3,0x3030 1939 addi r3,r3,0x3030
1935 lis r4,0x8042 1940 lis r4,0x8042
1936 addi r4,r4,0x223e 1941 addi r4,r4,0x223e
1937 b 1f 1942 b 1f
1938 strap_1: 1943 strap_1:
1939 mfdcr r3, CPC0_PLLMR0 1944 mfdcr r3, CPC0_PLLMR0
1940 mfdcr r4, CPC0_PLLMR1 1945 mfdcr r4, CPC0_PLLMR1
1941 b 1f 1946 b 1f
1942 #endif 1947 #endif
1943 1948
1944 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ 1949 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1945 ori r3,r3,PLLMR0_DEFAULT@l /* */ 1950 ori r3,r3,PLLMR0_DEFAULT@l /* */
1946 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ 1951 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1947 ori r4,r4,PLLMR1_DEFAULT@l /* */ 1952 ori r4,r4,PLLMR1_DEFAULT@l /* */
1948 1953
1949 #ifdef CONFIG_TAIHU 1954 #ifdef CONFIG_TAIHU
1950 b 1f 1955 b 1f
1951 _pci_66mhz: 1956 _pci_66mhz:
1952 addis r3,0,PLLMR0_DEFAULT_PCI66@h 1957 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1953 ori r3,r3,PLLMR0_DEFAULT_PCI66@l 1958 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1954 addis r4,0,PLLMR1_DEFAULT_PCI66@h 1959 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1955 ori r4,r4,PLLMR1_DEFAULT_PCI66@l 1960 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1956 b 1f 1961 b 1f
1957 strap_1: 1962 strap_1:
1958 mfdcr r3, CPC0_PLLMR0 1963 mfdcr r3, CPC0_PLLMR0
1959 mfdcr r4, CPC0_PLLMR1 1964 mfdcr r4, CPC0_PLLMR1
1960 #endif /* CONFIG_TAIHU */ 1965 #endif /* CONFIG_TAIHU */
1961 1966
1962 1: 1967 1:
1963 b pll_write /* Write the CPC0_PLLMR with new value */ 1968 b pll_write /* Write the CPC0_PLLMR with new value */
1964 1969
1965 pll_done: 1970 pll_done:
1966 /* 1971 /*
1967 !----------------------------------------------------------------------- 1972 !-----------------------------------------------------------------------
1968 ! Clear Soft Reset Register 1973 ! Clear Soft Reset Register
1969 ! This is needed to enable PCI if not booting from serial EPROM 1974 ! This is needed to enable PCI if not booting from serial EPROM
1970 !----------------------------------------------------------------------- 1975 !-----------------------------------------------------------------------
1971 */ 1976 */
1972 addi r3, 0, 0x0 1977 addi r3, 0, 0x0
1973 mtdcr CPC0_SRR, r3 1978 mtdcr CPC0_SRR, r3
1974 1979
1975 addis r3,0,0x0010 1980 addis r3,0,0x0010
1976 mtctr r3 1981 mtctr r3
1977 pci_wait: 1982 pci_wait:
1978 bdnz pci_wait 1983 bdnz pci_wait
1979 1984
1980 blr /* return to main code */ 1985 blr /* return to main code */
1981 1986
1982 /* 1987 /*
1983 !----------------------------------------------------------------------------- 1988 !-----------------------------------------------------------------------------
1984 ! Function: pll_write 1989 ! Function: pll_write
1985 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation 1990 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1986 ! That is: 1991 ! That is:
1987 ! 1. Pll is first disabled (de-activated by putting in bypass mode) 1992 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1988 ! 2. PLL is reset 1993 ! 2. PLL is reset
1989 ! 3. Clock dividers are set while PLL is held in reset and bypassed 1994 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1990 ! 4. PLL Reset is cleared 1995 ! 4. PLL Reset is cleared
1991 ! 5. Wait 100us for PLL to lock 1996 ! 5. Wait 100us for PLL to lock
1992 ! 6. A core reset is performed 1997 ! 6. A core reset is performed
1993 ! Input: r3 = Value to write to CPC0_PLLMR0 1998 ! Input: r3 = Value to write to CPC0_PLLMR0
1994 ! Input: r4 = Value to write to CPC0_PLLMR1 1999 ! Input: r4 = Value to write to CPC0_PLLMR1
1995 ! Output r3 = none 2000 ! Output r3 = none
1996 !----------------------------------------------------------------------------- 2001 !-----------------------------------------------------------------------------
1997 */ 2002 */
1998 .globl pll_write 2003 .globl pll_write
1999 pll_write: 2004 pll_write:
2000 mfdcr r5, CPC0_UCR 2005 mfdcr r5, CPC0_UCR
2001 andis. r5,r5,0xFFFF 2006 andis. r5,r5,0xFFFF
2002 ori r5,r5,0x0101 /* Stop the UART clocks */ 2007 ori r5,r5,0x0101 /* Stop the UART clocks */
2003 mtdcr CPC0_UCR,r5 /* Before changing PLL */ 2008 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2004 2009
2005 mfdcr r5, CPC0_PLLMR1 2010 mfdcr r5, CPC0_PLLMR1
2006 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ 2011 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2007 mtdcr CPC0_PLLMR1,r5 2012 mtdcr CPC0_PLLMR1,r5
2008 oris r5,r5,0x4000 /* Set PLL Reset */ 2013 oris r5,r5,0x4000 /* Set PLL Reset */
2009 mtdcr CPC0_PLLMR1,r5 2014 mtdcr CPC0_PLLMR1,r5
2010 2015
2011 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ 2016 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2012 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ 2017 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2013 oris r5,r5,0x4000 /* Set PLL Reset */ 2018 oris r5,r5,0x4000 /* Set PLL Reset */
2014 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ 2019 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2015 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ 2020 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2016 mtdcr CPC0_PLLMR1,r5 2021 mtdcr CPC0_PLLMR1,r5
2017 2022
2018 /* 2023 /*
2019 ! Wait min of 100us for PLL to lock. 2024 ! Wait min of 100us for PLL to lock.
2020 ! See CMOS 27E databook for more info. 2025 ! See CMOS 27E databook for more info.
2021 ! At 200MHz, that means waiting 20,000 instructions 2026 ! At 200MHz, that means waiting 20,000 instructions
2022 */ 2027 */
2023 addi r3,0,20000 /* 2000 = 0x4e20 */ 2028 addi r3,0,20000 /* 2000 = 0x4e20 */
2024 mtctr r3 2029 mtctr r3
2025 pll_wait: 2030 pll_wait:
2026 bdnz pll_wait 2031 bdnz pll_wait
2027 2032
2028 oris r5,r5,0x8000 /* Enable PLL */ 2033 oris r5,r5,0x8000 /* Enable PLL */
2029 mtdcr CPC0_PLLMR1,r5 /* Engage */ 2034 mtdcr CPC0_PLLMR1,r5 /* Engage */
2030 2035
2031 /* 2036 /*
2032 * Reset CPU to guarantee timings are OK 2037 * Reset CPU to guarantee timings are OK
2033 * Not sure if this is needed... 2038 * Not sure if this is needed...
2034 */ 2039 */
2035 addis r3,0,0x1000 2040 addis r3,0,0x1000
2036 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ 2041 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2037 /* execution will continue from the poweron */ 2042 /* execution will continue from the poweron */
2038 /* vector of 0xfffffffc */ 2043 /* vector of 0xfffffffc */
2039 #endif /* CONFIG_405EP */ 2044 #endif /* CONFIG_405EP */
2040 2045
2041 #if defined(CONFIG_440) 2046 #if defined(CONFIG_440)
2042 /*----------------------------------------------------------------------------+ 2047 /*----------------------------------------------------------------------------+
2043 | mttlb3. 2048 | mttlb3.
2044 +----------------------------------------------------------------------------*/ 2049 +----------------------------------------------------------------------------*/
2045 function_prolog(mttlb3) 2050 function_prolog(mttlb3)
2046 TLBWE(4,3,2) 2051 TLBWE(4,3,2)
2047 blr 2052 blr
2048 function_epilog(mttlb3) 2053 function_epilog(mttlb3)
2049 2054
2050 /*----------------------------------------------------------------------------+ 2055 /*----------------------------------------------------------------------------+
2051 | mftlb3. 2056 | mftlb3.
2052 +----------------------------------------------------------------------------*/ 2057 +----------------------------------------------------------------------------*/
2053 function_prolog(mftlb3) 2058 function_prolog(mftlb3)
2054 TLBRE(3,3,2) 2059 TLBRE(3,3,2)
2055 blr 2060 blr
2056 function_epilog(mftlb3) 2061 function_epilog(mftlb3)
2057 2062
2058 /*----------------------------------------------------------------------------+ 2063 /*----------------------------------------------------------------------------+
2059 | mttlb2. 2064 | mttlb2.
2060 +----------------------------------------------------------------------------*/ 2065 +----------------------------------------------------------------------------*/
2061 function_prolog(mttlb2) 2066 function_prolog(mttlb2)
2062 TLBWE(4,3,1) 2067 TLBWE(4,3,1)
2063 blr 2068 blr
2064 function_epilog(mttlb2) 2069 function_epilog(mttlb2)
2065 2070
2066 /*----------------------------------------------------------------------------+ 2071 /*----------------------------------------------------------------------------+
2067 | mftlb2. 2072 | mftlb2.
2068 +----------------------------------------------------------------------------*/ 2073 +----------------------------------------------------------------------------*/
2069 function_prolog(mftlb2) 2074 function_prolog(mftlb2)
2070 TLBRE(3,3,1) 2075 TLBRE(3,3,1)
2071 blr 2076 blr
2072 function_epilog(mftlb2) 2077 function_epilog(mftlb2)
2073 2078
2074 /*----------------------------------------------------------------------------+ 2079 /*----------------------------------------------------------------------------+
2075 | mttlb1. 2080 | mttlb1.
2076 +----------------------------------------------------------------------------*/ 2081 +----------------------------------------------------------------------------*/
2077 function_prolog(mttlb1) 2082 function_prolog(mttlb1)
2078 TLBWE(4,3,0) 2083 TLBWE(4,3,0)
2079 blr 2084 blr
2080 function_epilog(mttlb1) 2085 function_epilog(mttlb1)
2081 2086
2082 /*----------------------------------------------------------------------------+ 2087 /*----------------------------------------------------------------------------+
2083 | mftlb1. 2088 | mftlb1.
2084 +----------------------------------------------------------------------------*/ 2089 +----------------------------------------------------------------------------*/
2085 function_prolog(mftlb1) 2090 function_prolog(mftlb1)
2086 TLBRE(3,3,0) 2091 TLBRE(3,3,0)
2087 blr 2092 blr
2088 function_epilog(mftlb1) 2093 function_epilog(mftlb1)
2089 #endif /* CONFIG_440 */ 2094 #endif /* CONFIG_440 */
2090 2095
2091 #if defined(CONFIG_NAND_SPL) 2096 #if defined(CONFIG_NAND_SPL)
2092 /* 2097 /*
2093 * void nand_boot_relocate(dst, src, bytes) 2098 * void nand_boot_relocate(dst, src, bytes)
2094 * 2099 *
2095 * r3 = Destination address to copy code to (in SDRAM) 2100 * r3 = Destination address to copy code to (in SDRAM)
2096 * r4 = Source address to copy code from 2101 * r4 = Source address to copy code from
2097 * r5 = size to copy in bytes 2102 * r5 = size to copy in bytes
2098 */ 2103 */
2099 nand_boot_relocate: 2104 nand_boot_relocate:
2100 mr r6,r3 2105 mr r6,r3
2101 mr r7,r4 2106 mr r7,r4
2102 mflr r8 2107 mflr r8
2103 2108
2104 /* 2109 /*
2105 * Copy SPL from icache into SDRAM 2110 * Copy SPL from icache into SDRAM
2106 */ 2111 */
2107 subi r3,r3,4 2112 subi r3,r3,4
2108 subi r4,r4,4 2113 subi r4,r4,4
2109 srwi r5,r5,2 2114 srwi r5,r5,2
2110 mtctr r5 2115 mtctr r5
2111 ..spl_loop: 2116 ..spl_loop:
2112 lwzu r0,4(r4) 2117 lwzu r0,4(r4)
2113 stwu r0,4(r3) 2118 stwu r0,4(r3)
2114 bdnz ..spl_loop 2119 bdnz ..spl_loop
2115 2120
2116 /* 2121 /*
2117 * Calculate "corrected" link register, so that we "continue" 2122 * Calculate "corrected" link register, so that we "continue"
2118 * in execution in destination range 2123 * in execution in destination range
2119 */ 2124 */
2120 sub r3,r7,r6 /* r3 = src - dst */ 2125 sub r3,r7,r6 /* r3 = src - dst */
2121 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ 2126 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2122 mtlr r8 2127 mtlr r8
2123 blr 2128 blr
2124 2129
2125 nand_boot_common: 2130 nand_boot_common:
2126 /* 2131 /*
2127 * First initialize SDRAM. It has to be available *before* calling 2132 * First initialize SDRAM. It has to be available *before* calling
2128 * nand_boot(). 2133 * nand_boot().
2129 */ 2134 */
2130 lis r3,CONFIG_SYS_SDRAM_BASE@h 2135 lis r3,CONFIG_SYS_SDRAM_BASE@h
2131 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l 2136 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2132 bl initdram 2137 bl initdram
2133 2138
2134 /* 2139 /*
2135 * Now copy the 4k SPL code into SDRAM and continue execution 2140 * Now copy the 4k SPL code into SDRAM and continue execution
2136 * from there. 2141 * from there.
2137 */ 2142 */
2138 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h 2143 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2139 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l 2144 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2140 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h 2145 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2141 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l 2146 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2142 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h 2147 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2143 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l 2148 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2144 bl nand_boot_relocate 2149 bl nand_boot_relocate
2145 2150
2146 /* 2151 /*
2147 * We're running from SDRAM now!!! 2152 * We're running from SDRAM now!!!
2148 * 2153 *
2149 * It is necessary for 4xx systems to relocate from running at 2154 * It is necessary for 4xx systems to relocate from running at
2150 * the original location (0xfffffxxx) to somewhere else (SDRAM 2155 * the original location (0xfffffxxx) to somewhere else (SDRAM
2151 * preferably). This is because CS0 needs to be reconfigured for 2156 * preferably). This is because CS0 needs to be reconfigured for
2152 * NAND access. And we can't reconfigure this CS when currently 2157 * NAND access. And we can't reconfigure this CS when currently
2153 * "running" from it. 2158 * "running" from it.
2154 */ 2159 */
2155 2160
2156 /* 2161 /*
2157 * Finally call nand_boot() to load main NAND U-Boot image from 2162 * Finally call nand_boot() to load main NAND U-Boot image from
2158 * NAND and jump to it. 2163 * NAND and jump to it.
2159 */ 2164 */
2160 bl nand_boot /* will not return */ 2165 bl nand_boot /* will not return */
2161 #endif /* CONFIG_NAND_SPL */ 2166 #endif /* CONFIG_NAND_SPL */
2162 2167