Commit f466d2deb304f63bd28a04b116ab309d4417e730
1 parent
85f84661b0
Exists in
smarc-8mm-p9.0.0_2.0.0_ga
and in
1 other branch
rewrite LPDDR4 timing parameters
Showing 19 changed files with 3468 additions and 68 deletions Inline Diff
- board/embedian/smarcimx8mq/lpddr4_timing.c
- configs/smarcimx8mq_2g_ser0_ind_android_defconfig
- configs/smarcimx8mq_2g_ser0_ind_android_uuu_defconfig
- configs/smarcimx8mq_2g_ser0_ind_androidthings_defconfig
- configs/smarcimx8mq_2g_ser0_ind_defconfig
- configs/smarcimx8mq_2g_ser1_ind_android_defconfig
- configs/smarcimx8mq_2g_ser1_ind_android_uuu_defconfig
- configs/smarcimx8mq_2g_ser1_ind_androidthings_defconfig
- configs/smarcimx8mq_2g_ser1_ind_defconfig
- configs/smarcimx8mq_2g_ser2_ind_android_defconfig
- configs/smarcimx8mq_2g_ser2_ind_android_uuu_defconfig
- configs/smarcimx8mq_2g_ser2_ind_androidthings_defconfig
- configs/smarcimx8mq_2g_ser2_ind_defconfig
- configs/smarcimx8mq_2g_ser3_ind_android_defconfig
- configs/smarcimx8mq_2g_ser3_ind_android_uuu_defconfig
- configs/smarcimx8mq_2g_ser3_ind_androidthings_defconfig
- configs/smarcimx8mq_2g_ser3_ind_defconfig
- drivers/ram/Kconfig
- include/configs/smarcimx8mq.h
board/embedian/smarcimx8mq/lpddr4_timing.c
1 | /* | 1 | /* |
2 | * Copyright 2018 NXP | 2 | * Copyright 2018 NXP |
3 | * | 3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | * | 5 | * |
6 | * Generated code from MX8M_DDR_tool | 6 | * Generated code from MX8M_DDR_tool |
7 | * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga | 7 | * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga |
8 | */ | 8 | */ |
9 | 9 | ||
10 | #include <common.h> | ||
11 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
12 | #include <asm/arch/imx8m_ddr.h> | 11 | #include <asm/arch/imx8m_ddr.h> |
13 | 12 | #include <common.h> | |
13 | #if defined(CONFIG_2GB_LPDDR4) | ||
14 | struct dram_cfg_param ddr_ddrc_cfg[] = { | 14 | struct dram_cfg_param ddr_ddrc_cfg[] = { |
15 | /** Initialize DDRC registers **/ | 15 | /** Initialize DDRC registers **/ |
16 | {0x3d400304,0x1}, | 16 | {0x3d400304,0x1}, |
17 | {0x3d400030,0x1}, | 17 | {0x3d400030,0x1}, |
18 | #if CONFIG_IND | ||
19 | {0x3d400000,0xa1080020}, | ||
20 | #else | ||
21 | {0x3d400000,0xa3080020}, | 18 | {0x3d400000,0xa3080020}, |
22 | #endif | ||
23 | {0x3d400028,0x0}, | 19 | {0x3d400028,0x0}, |
24 | {0x3d400020,0x203}, | 20 | {0x3d400020,0x203}, |
25 | {0x3d400024,0x3e800}, | 21 | {0x3d400024,0x3e800}, |
26 | {0x3d400064,0x6100e0}, | 22 | {0x3d400064,0x6100e0}, |
27 | {0x3d4000d0,0xc003061c}, | 23 | {0x3d4000d0,0xc003061c}, |
28 | {0x3d4000d4,0x9e0000}, | 24 | {0x3d4000d4,0x9e0000}, |
29 | {0x3d4000dc,0xd4002d}, | 25 | {0x3d4000dc,0xd4002d}, |
30 | {0x3d4000e0,0x310008}, | 26 | {0x3d4000e0,0x310008}, |
31 | {0x3d4000e8,0x66004a}, | 27 | {0x3d4000e8,0x66004a}, |
32 | {0x3d4000ec,0x16004a}, | 28 | {0x3d4000ec,0x16004a}, |
33 | {0x3d400100,0x1a201b22}, | 29 | {0x3d400100,0x1a201b22}, |
34 | {0x3d400104,0x60633}, | 30 | {0x3d400104,0x60633}, |
35 | {0x3d40010c,0xc0c000}, | 31 | {0x3d40010c,0xc0c000}, |
36 | {0x3d400110,0xf04080f}, | 32 | {0x3d400110,0xf04080f}, |
37 | {0x3d400114,0x2040c0c}, | 33 | {0x3d400114,0x2040c0c}, |
38 | {0x3d400118,0x1010007}, | 34 | {0x3d400118,0x1010007}, |
39 | {0x3d40011c,0x401}, | 35 | {0x3d40011c,0x401}, |
40 | {0x3d400130,0x20600}, | 36 | {0x3d400130,0x20600}, |
41 | {0x3d400134,0xc100002}, | 37 | {0x3d400134,0xc100002}, |
42 | {0x3d400138,0xe6}, | 38 | {0x3d400138,0xe6}, |
43 | {0x3d400144,0xa00050}, | 39 | {0x3d400144,0xa00050}, |
44 | {0x3d400180,0xc3200018}, | 40 | {0x3d400180,0xc3200018}, |
45 | {0x3d400184,0x28061a8}, | 41 | {0x3d400184,0x28061a8}, |
46 | {0x3d400188,0x0}, | 42 | {0x3d400188,0x0}, |
47 | {0x3d400190,0x497820a}, | 43 | {0x3d400190,0x497820a}, |
48 | {0x3d400194,0x80303}, | 44 | {0x3d400194,0x80303}, |
49 | {0x3d4001a0,0xe0400018}, | 45 | {0x3d4001a0,0xe0400018}, |
50 | {0x3d4001a4,0xdf00e4}, | 46 | {0x3d4001a4,0xdf00e4}, |
51 | {0x3d4001a8,0x80000000}, | 47 | {0x3d4001a8,0x80000000}, |
52 | {0x3d4001b0,0x11}, | 48 | {0x3d4001b0,0x11}, |
53 | {0x3d4001b4,0x170a}, | 49 | {0x3d4001b4,0x170a}, |
54 | {0x3d4001c0,0x1}, | 50 | {0x3d4001c0,0x1}, |
55 | {0x3d4001c4,0x1}, | 51 | {0x3d4001c4,0x1}, |
56 | {0x3d4000f4,0x639}, | 52 | {0x3d4000f4,0x639}, |
57 | {0x3d400108,0x70e1617}, | 53 | {0x3d400108,0x70e1617}, |
58 | #if CONFIG_2GB_LPDDR4 | 54 | {0x3d400200,0x16}, |
59 | #if CONFIG_IND | ||
60 | {0x3d400200,0x1f}, | ||
61 | #else | ||
62 | {0x3d400200,0x16}, | ||
63 | #endif | ||
64 | #elif CONFIG_4GB_LPDDR4 | ||
65 | {0x3d400200,0x17}, | ||
66 | #else | ||
67 | #error unsupported memory size | ||
68 | #endif | ||
69 | {0x3d40020c,0x0}, | 55 | {0x3d40020c,0x0}, |
70 | {0x3d400210,0x1f1f}, | 56 | {0x3d400210,0x1f1f}, |
71 | {0x3d400204,0x80808}, | 57 | {0x3d400204,0x80808}, |
72 | {0x3d400214,0x7070707}, | 58 | {0x3d400214,0x7070707}, |
73 | #if CONFIG_2GB_LPDDR4 | ||
74 | #if CONFIG_IND | ||
75 | {0x3d400218,0x7070707}, | ||
76 | #else | ||
77 | {0x3d400218,0xf070707}, | 59 | {0x3d400218,0xf070707}, |
78 | #endif | ||
79 | #elif CONFIG_4GB_LPDDR4 | ||
80 | {0x3d400218,0x7070707}, | ||
81 | #else | ||
82 | #error unsupported memory size | ||
83 | #endif | ||
84 | {0x3d402020,0x1}, | 60 | {0x3d402020,0x1}, |
85 | {0x3d402024,0xd0c0}, | 61 | {0x3d402024,0xd0c0}, |
86 | {0x3d402050,0x20d040}, | 62 | {0x3d402050,0x20d040}, |
87 | {0x3d402064,0x14002f}, | 63 | {0x3d402064,0x14002f}, |
88 | {0x3d4020dc,0x940009}, | 64 | {0x3d4020dc,0x940009}, |
89 | {0x3d4020e0,0x310000}, | 65 | {0x3d4020e0,0x310000}, |
90 | {0x3d4020e8,0x66004a}, | 66 | {0x3d4020e8,0x66004a}, |
91 | {0x3d4020ec,0x16004a}, | 67 | {0x3d4020ec,0x16004a}, |
92 | {0x3d402100,0xb070508}, | 68 | {0x3d402100,0xb070508}, |
93 | {0x3d402104,0x3040b}, | 69 | {0x3d402104,0x3040b}, |
94 | {0x3d402108,0x305090c}, | 70 | {0x3d402108,0x305090c}, |
95 | {0x3d40210c,0x505000}, | 71 | {0x3d40210c,0x505000}, |
96 | {0x3d402110,0x4040204}, | 72 | {0x3d402110,0x4040204}, |
97 | {0x3d402114,0x2030303}, | 73 | {0x3d402114,0x2030303}, |
98 | {0x3d402118,0x1010004}, | 74 | {0x3d402118,0x1010004}, |
99 | {0x3d40211c,0x301}, | 75 | {0x3d40211c,0x301}, |
100 | {0x3d402130,0x20300}, | 76 | {0x3d402130,0x20300}, |
101 | {0x3d402134,0xa100002}, | 77 | {0x3d402134,0xa100002}, |
102 | {0x3d402138,0x31}, | 78 | {0x3d402138,0x31}, |
103 | {0x3d402144,0x220011}, | 79 | {0x3d402144,0x220011}, |
104 | {0x3d402180,0xc0a70006}, | 80 | {0x3d402180,0xc0a70006}, |
105 | {0x3d402190,0x3858202}, | 81 | {0x3d402190,0x3858202}, |
106 | {0x3d402194,0x80303}, | 82 | {0x3d402194,0x80303}, |
107 | {0x3d4021b4,0x502}, | 83 | {0x3d4021b4,0x502}, |
108 | {0x3d400244,0x0}, | 84 | {0x3d400244,0x0}, |
109 | {0x3d400250,0x29001505}, | 85 | {0x3d400250,0x29001505}, |
110 | {0x3d400254,0x2c}, | 86 | {0x3d400254,0x2c}, |
111 | {0x3d40025c,0x5900575b}, | 87 | {0x3d40025c,0x5900575b}, |
112 | {0x3d400264,0x90000096}, | 88 | {0x3d400264,0x90000096}, |
113 | {0x3d40026c,0x1000012c}, | 89 | {0x3d40026c,0x1000012c}, |
114 | {0x3d400300,0x16}, | 90 | {0x3d400300,0x16}, |
115 | {0x3d400304,0x0}, | 91 | {0x3d400304,0x0}, |
116 | {0x3d40030c,0x0}, | 92 | {0x3d40030c,0x0}, |
117 | {0x3d400320,0x1}, | 93 | {0x3d400320,0x1}, |
118 | {0x3d40036c,0x11}, | 94 | {0x3d40036c,0x11}, |
119 | {0x3d400400,0x111}, | 95 | {0x3d400400,0x111}, |
120 | {0x3d400404,0x10f3}, | 96 | {0x3d400404,0x10f3}, |
121 | {0x3d400408,0x72ff}, | 97 | {0x3d400408,0x72ff}, |
122 | {0x3d400490,0x1}, | 98 | {0x3d400490,0x1}, |
123 | {0x3d400494,0xe00}, | 99 | {0x3d400494,0xe00}, |
124 | {0x3d400498,0x62ffff}, | 100 | {0x3d400498,0x62ffff}, |
125 | {0x3d40049c,0xe00}, | 101 | {0x3d40049c,0xe00}, |
126 | {0x3d4004a0,0xffff}, | 102 | {0x3d4004a0,0xffff}, |
127 | }; | 103 | }; |
128 | 104 | ||
129 | /* PHY Initialize Configuration */ | 105 | /* PHY Initialize Configuration */ |
130 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | 106 | struct dram_cfg_param ddr_ddrphy_cfg[] = { |
131 | {0x100a0,0x0}, | 107 | {0x100a0,0x0}, |
132 | {0x100a1,0x1}, | 108 | {0x100a1,0x1}, |
133 | {0x100a2,0x2}, | 109 | {0x100a2,0x2}, |
134 | {0x100a3,0x3}, | 110 | {0x100a3,0x3}, |
135 | {0x100a4,0x4}, | 111 | {0x100a4,0x4}, |
136 | {0x100a5,0x5}, | 112 | {0x100a5,0x5}, |
137 | {0x100a6,0x6}, | 113 | {0x100a6,0x6}, |
138 | {0x100a7,0x7}, | 114 | {0x100a7,0x7}, |
139 | {0x110a0,0x0}, | 115 | {0x110a0,0x0}, |
140 | {0x110a1,0x1}, | 116 | {0x110a1,0x1}, |
141 | {0x110a2,0x2}, | 117 | {0x110a2,0x2}, |
142 | {0x110a3,0x3}, | 118 | {0x110a3,0x3}, |
143 | {0x110a4,0x4}, | 119 | {0x110a4,0x4}, |
144 | {0x110a5,0x7}, | 120 | {0x110a5,0x7}, |
145 | {0x110a6,0x6}, | 121 | {0x110a6,0x6}, |
146 | {0x110a7,0x5}, | 122 | {0x110a7,0x5}, |
147 | {0x120a0,0x0}, | 123 | {0x120a0,0x0}, |
148 | {0x120a1,0x1}, | 124 | {0x120a1,0x1}, |
149 | {0x120a2,0x2}, | 125 | {0x120a2,0x2}, |
150 | {0x120a3,0x3}, | 126 | {0x120a3,0x3}, |
151 | {0x120a4,0x4}, | 127 | {0x120a4,0x4}, |
152 | {0x120a5,0x5}, | 128 | {0x120a5,0x5}, |
153 | {0x120a6,0x6}, | 129 | {0x120a6,0x6}, |
154 | {0x120a7,0x7}, | 130 | {0x120a7,0x7}, |
155 | {0x130a0,0x0}, | 131 | {0x130a0,0x0}, |
156 | {0x130a1,0x1}, | 132 | {0x130a1,0x1}, |
157 | {0x130a2,0x2}, | 133 | {0x130a2,0x2}, |
158 | {0x130a3,0x3}, | 134 | {0x130a3,0x3}, |
159 | {0x130a4,0x4}, | 135 | {0x130a4,0x4}, |
160 | {0x130a5,0x5}, | 136 | {0x130a5,0x5}, |
161 | {0x130a6,0x6}, | 137 | {0x130a6,0x6}, |
162 | {0x130a7,0x7}, | 138 | {0x130a7,0x7}, |
163 | {0x20110,0x2}, | 139 | {0x20110,0x2}, |
164 | {0x20111,0x3}, | 140 | {0x20111,0x3}, |
165 | {0x20112,0x4}, | 141 | {0x20112,0x4}, |
166 | {0x20113,0x5}, | 142 | {0x20113,0x5}, |
167 | {0x20114,0x0}, | 143 | {0x20114,0x0}, |
168 | {0x20115,0x1}, | 144 | {0x20115,0x1}, |
169 | {0x1005f,0x1ff}, | 145 | {0x1005f,0x1ff}, |
170 | {0x1015f,0x1ff}, | 146 | {0x1015f,0x1ff}, |
171 | {0x1105f,0x1ff}, | 147 | {0x1105f,0x1ff}, |
172 | {0x1115f,0x1ff}, | 148 | {0x1115f,0x1ff}, |
173 | {0x1205f,0x1ff}, | 149 | {0x1205f,0x1ff}, |
174 | {0x1215f,0x1ff}, | 150 | {0x1215f,0x1ff}, |
175 | {0x1305f,0x1ff}, | 151 | {0x1305f,0x1ff}, |
176 | {0x1315f,0x1ff}, | 152 | {0x1315f,0x1ff}, |
177 | {0x11005f,0x1ff}, | 153 | {0x11005f,0x1ff}, |
178 | {0x11015f,0x1ff}, | 154 | {0x11015f,0x1ff}, |
179 | {0x11105f,0x1ff}, | 155 | {0x11105f,0x1ff}, |
180 | {0x11115f,0x1ff}, | 156 | {0x11115f,0x1ff}, |
181 | {0x11205f,0x1ff}, | 157 | {0x11205f,0x1ff}, |
182 | {0x11215f,0x1ff}, | 158 | {0x11215f,0x1ff}, |
183 | {0x11305f,0x1ff}, | 159 | {0x11305f,0x1ff}, |
184 | {0x11315f,0x1ff}, | 160 | {0x11315f,0x1ff}, |
185 | {0x55,0x1ff}, | 161 | {0x55,0x1ff}, |
186 | {0x1055,0x1ff}, | 162 | {0x1055,0x1ff}, |
187 | {0x2055,0x1ff}, | 163 | {0x2055,0x1ff}, |
188 | {0x3055,0x1ff}, | 164 | {0x3055,0x1ff}, |
189 | {0x4055,0x1ff}, | 165 | {0x4055,0x1ff}, |
190 | {0x5055,0x1ff}, | 166 | {0x5055,0x1ff}, |
191 | {0x6055,0x1ff}, | 167 | {0x6055,0x1ff}, |
192 | {0x7055,0x1ff}, | 168 | {0x7055,0x1ff}, |
193 | {0x8055,0x1ff}, | 169 | {0x8055,0x1ff}, |
194 | {0x9055,0x1ff}, | 170 | {0x9055,0x1ff}, |
195 | {0x200c5,0x19}, | 171 | {0x200c5,0x19}, |
196 | {0x1200c5,0x7}, | 172 | {0x1200c5,0x7}, |
197 | {0x2002e,0x2}, | 173 | {0x2002e,0x2}, |
198 | {0x12002e,0x1}, | 174 | {0x12002e,0x1}, |
199 | {0x90204,0x0}, | 175 | {0x90204,0x0}, |
200 | {0x190204,0x0}, | 176 | {0x190204,0x0}, |
201 | {0x20024,0x1ab}, | 177 | {0x20024,0x1ab}, |
202 | {0x2003a,0x0}, | 178 | {0x2003a,0x0}, |
203 | {0x120024,0x1ab}, | 179 | {0x120024,0x1ab}, |
204 | {0x2003a,0x0}, | 180 | {0x2003a,0x0}, |
205 | {0x20056,0x3}, | 181 | {0x20056,0x3}, |
206 | {0x120056,0xa}, | 182 | {0x120056,0xa}, |
207 | {0x1004d,0xe00}, | 183 | {0x1004d,0xe00}, |
208 | {0x1014d,0xe00}, | 184 | {0x1014d,0xe00}, |
209 | {0x1104d,0xe00}, | 185 | {0x1104d,0xe00}, |
210 | {0x1114d,0xe00}, | 186 | {0x1114d,0xe00}, |
211 | {0x1204d,0xe00}, | 187 | {0x1204d,0xe00}, |
212 | {0x1214d,0xe00}, | 188 | {0x1214d,0xe00}, |
213 | {0x1304d,0xe00}, | 189 | {0x1304d,0xe00}, |
214 | {0x1314d,0xe00}, | 190 | {0x1314d,0xe00}, |
215 | {0x11004d,0xe00}, | 191 | {0x11004d,0xe00}, |
216 | {0x11014d,0xe00}, | 192 | {0x11014d,0xe00}, |
217 | {0x11104d,0xe00}, | 193 | {0x11104d,0xe00}, |
218 | {0x11114d,0xe00}, | 194 | {0x11114d,0xe00}, |
219 | {0x11204d,0xe00}, | 195 | {0x11204d,0xe00}, |
220 | {0x11214d,0xe00}, | 196 | {0x11214d,0xe00}, |
221 | {0x11304d,0xe00}, | 197 | {0x11304d,0xe00}, |
222 | {0x11314d,0xe00}, | 198 | {0x11314d,0xe00}, |
223 | {0x10049,0xeba}, | 199 | {0x10049,0xeba}, |
224 | {0x10149,0xeba}, | 200 | {0x10149,0xeba}, |
225 | {0x11049,0xeba}, | 201 | {0x11049,0xeba}, |
226 | {0x11149,0xeba}, | 202 | {0x11149,0xeba}, |
227 | {0x12049,0xeba}, | 203 | {0x12049,0xeba}, |
228 | {0x12149,0xeba}, | 204 | {0x12149,0xeba}, |
229 | {0x13049,0xeba}, | 205 | {0x13049,0xeba}, |
230 | {0x13149,0xeba}, | 206 | {0x13149,0xeba}, |
231 | {0x110049,0xeba}, | 207 | {0x110049,0xeba}, |
232 | {0x110149,0xeba}, | 208 | {0x110149,0xeba}, |
233 | {0x111049,0xeba}, | 209 | {0x111049,0xeba}, |
234 | {0x111149,0xeba}, | 210 | {0x111149,0xeba}, |
235 | {0x112049,0xeba}, | 211 | {0x112049,0xeba}, |
236 | {0x112149,0xeba}, | 212 | {0x112149,0xeba}, |
237 | {0x113049,0xeba}, | 213 | {0x113049,0xeba}, |
238 | {0x113149,0xeba}, | 214 | {0x113149,0xeba}, |
239 | {0x43,0x63}, | 215 | {0x43,0x63}, |
240 | {0x1043,0x63}, | 216 | {0x1043,0x63}, |
241 | {0x2043,0x63}, | 217 | {0x2043,0x63}, |
242 | {0x3043,0x63}, | 218 | {0x3043,0x63}, |
243 | {0x4043,0x63}, | 219 | {0x4043,0x63}, |
244 | {0x5043,0x63}, | 220 | {0x5043,0x63}, |
245 | {0x6043,0x63}, | 221 | {0x6043,0x63}, |
246 | {0x7043,0x63}, | 222 | {0x7043,0x63}, |
247 | {0x8043,0x63}, | 223 | {0x8043,0x63}, |
248 | {0x9043,0x63}, | 224 | {0x9043,0x63}, |
249 | {0x20018,0x3}, | 225 | {0x20018,0x3}, |
250 | {0x20075,0x4}, | 226 | {0x20075,0x4}, |
251 | {0x20050,0x0}, | 227 | {0x20050,0x0}, |
252 | {0x20008,0x320}, | 228 | {0x20008,0x320}, |
253 | {0x120008,0xa7}, | 229 | {0x120008,0xa7}, |
254 | {0x20088,0x9}, | 230 | {0x20088,0x9}, |
255 | {0x200b2,0xdc}, | 231 | {0x200b2,0xdc}, |
256 | {0x10043,0x5a1}, | 232 | {0x10043,0x5a1}, |
257 | {0x10143,0x5a1}, | 233 | {0x10143,0x5a1}, |
258 | {0x11043,0x5a1}, | 234 | {0x11043,0x5a1}, |
259 | {0x11143,0x5a1}, | 235 | {0x11143,0x5a1}, |
260 | {0x12043,0x5a1}, | 236 | {0x12043,0x5a1}, |
261 | {0x12143,0x5a1}, | 237 | {0x12143,0x5a1}, |
262 | {0x13043,0x5a1}, | 238 | {0x13043,0x5a1}, |
263 | {0x13143,0x5a1}, | 239 | {0x13143,0x5a1}, |
264 | {0x1200b2,0xdc}, | 240 | {0x1200b2,0xdc}, |
265 | {0x110043,0x5a1}, | 241 | {0x110043,0x5a1}, |
266 | {0x110143,0x5a1}, | 242 | {0x110143,0x5a1}, |
267 | {0x111043,0x5a1}, | 243 | {0x111043,0x5a1}, |
268 | {0x111143,0x5a1}, | 244 | {0x111143,0x5a1}, |
269 | {0x112043,0x5a1}, | 245 | {0x112043,0x5a1}, |
270 | {0x112143,0x5a1}, | 246 | {0x112143,0x5a1}, |
271 | {0x113043,0x5a1}, | 247 | {0x113043,0x5a1}, |
272 | {0x113143,0x5a1}, | 248 | {0x113143,0x5a1}, |
273 | {0x200fa,0x1}, | 249 | {0x200fa,0x1}, |
274 | {0x1200fa,0x1}, | 250 | {0x1200fa,0x1}, |
275 | {0x20019,0x1}, | 251 | {0x20019,0x1}, |
276 | {0x120019,0x1}, | 252 | {0x120019,0x1}, |
277 | {0x200f0,0x0}, | 253 | {0x200f0,0x0}, |
278 | {0x200f1,0x0}, | 254 | {0x200f1,0x0}, |
279 | {0x200f2,0x4444}, | 255 | {0x200f2,0x4444}, |
280 | {0x200f3,0x8888}, | 256 | {0x200f3,0x8888}, |
281 | {0x200f4,0x5555}, | 257 | {0x200f4,0x5555}, |
282 | {0x200f5,0x0}, | 258 | {0x200f5,0x0}, |
283 | {0x200f6,0x0}, | 259 | {0x200f6,0x0}, |
284 | {0x200f7,0xf000}, | 260 | {0x200f7,0xf000}, |
285 | {0x20025,0x0}, | 261 | {0x20025,0x0}, |
286 | {0x2002d,0x0}, | 262 | {0x2002d,0x0}, |
287 | {0x12002d,0x0}, | 263 | {0x12002d,0x0}, |
288 | {0x200c7,0x80}, | 264 | {0x200c7,0x80}, |
289 | {0x1200c7,0x80}, | 265 | {0x1200c7,0x80}, |
290 | {0x200ca,0x106}, | 266 | {0x200ca,0x106}, |
291 | {0x1200ca,0x106}, | 267 | {0x1200ca,0x106}, |
292 | }; | 268 | }; |
293 | 269 | ||
294 | /* ddr phy trained csr */ | 270 | /* ddr phy trained csr */ |
295 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | 271 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { |
296 | { 0x200b2, 0x0 }, | 272 | { 0x200b2, 0x0 }, |
297 | { 0x1200b2, 0x0 }, | 273 | { 0x1200b2, 0x0 }, |
298 | { 0x2200b2, 0x0 }, | 274 | { 0x2200b2, 0x0 }, |
299 | { 0x200cb, 0x0 }, | 275 | { 0x200cb, 0x0 }, |
300 | { 0x10043, 0x0 }, | 276 | { 0x10043, 0x0 }, |
301 | { 0x110043, 0x0 }, | 277 | { 0x110043, 0x0 }, |
302 | { 0x210043, 0x0 }, | 278 | { 0x210043, 0x0 }, |
303 | { 0x10143, 0x0 }, | 279 | { 0x10143, 0x0 }, |
304 | { 0x110143, 0x0 }, | 280 | { 0x110143, 0x0 }, |
305 | { 0x210143, 0x0 }, | 281 | { 0x210143, 0x0 }, |
306 | { 0x11043, 0x0 }, | 282 | { 0x11043, 0x0 }, |
307 | { 0x111043, 0x0 }, | 283 | { 0x111043, 0x0 }, |
308 | { 0x211043, 0x0 }, | 284 | { 0x211043, 0x0 }, |
309 | { 0x11143, 0x0 }, | 285 | { 0x11143, 0x0 }, |
310 | { 0x111143, 0x0 }, | 286 | { 0x111143, 0x0 }, |
311 | { 0x211143, 0x0 }, | 287 | { 0x211143, 0x0 }, |
312 | { 0x12043, 0x0 }, | 288 | { 0x12043, 0x0 }, |
313 | { 0x112043, 0x0 }, | 289 | { 0x112043, 0x0 }, |
314 | { 0x212043, 0x0 }, | 290 | { 0x212043, 0x0 }, |
315 | { 0x12143, 0x0 }, | 291 | { 0x12143, 0x0 }, |
316 | { 0x112143, 0x0 }, | 292 | { 0x112143, 0x0 }, |
317 | { 0x212143, 0x0 }, | 293 | { 0x212143, 0x0 }, |
318 | { 0x13043, 0x0 }, | 294 | { 0x13043, 0x0 }, |
319 | { 0x113043, 0x0 }, | 295 | { 0x113043, 0x0 }, |
320 | { 0x213043, 0x0 }, | 296 | { 0x213043, 0x0 }, |
321 | { 0x13143, 0x0 }, | 297 | { 0x13143, 0x0 }, |
322 | { 0x113143, 0x0 }, | 298 | { 0x113143, 0x0 }, |
323 | { 0x213143, 0x0 }, | 299 | { 0x213143, 0x0 }, |
324 | { 0x80, 0x0 }, | 300 | { 0x80, 0x0 }, |
325 | { 0x100080, 0x0 }, | 301 | { 0x100080, 0x0 }, |
326 | { 0x200080, 0x0 }, | 302 | { 0x200080, 0x0 }, |
327 | { 0x1080, 0x0 }, | 303 | { 0x1080, 0x0 }, |
328 | { 0x101080, 0x0 }, | 304 | { 0x101080, 0x0 }, |
329 | { 0x201080, 0x0 }, | 305 | { 0x201080, 0x0 }, |
330 | { 0x2080, 0x0 }, | 306 | { 0x2080, 0x0 }, |
331 | { 0x102080, 0x0 }, | 307 | { 0x102080, 0x0 }, |
332 | { 0x202080, 0x0 }, | 308 | { 0x202080, 0x0 }, |
333 | { 0x3080, 0x0 }, | 309 | { 0x3080, 0x0 }, |
334 | { 0x103080, 0x0 }, | 310 | { 0x103080, 0x0 }, |
335 | { 0x203080, 0x0 }, | 311 | { 0x203080, 0x0 }, |
336 | { 0x4080, 0x0 }, | 312 | { 0x4080, 0x0 }, |
337 | { 0x104080, 0x0 }, | 313 | { 0x104080, 0x0 }, |
338 | { 0x204080, 0x0 }, | 314 | { 0x204080, 0x0 }, |
339 | { 0x5080, 0x0 }, | 315 | { 0x5080, 0x0 }, |
340 | { 0x105080, 0x0 }, | 316 | { 0x105080, 0x0 }, |
341 | { 0x205080, 0x0 }, | 317 | { 0x205080, 0x0 }, |
342 | { 0x6080, 0x0 }, | 318 | { 0x6080, 0x0 }, |
343 | { 0x106080, 0x0 }, | 319 | { 0x106080, 0x0 }, |
344 | { 0x206080, 0x0 }, | 320 | { 0x206080, 0x0 }, |
345 | { 0x7080, 0x0 }, | 321 | { 0x7080, 0x0 }, |
346 | { 0x107080, 0x0 }, | 322 | { 0x107080, 0x0 }, |
347 | { 0x207080, 0x0 }, | 323 | { 0x207080, 0x0 }, |
348 | { 0x8080, 0x0 }, | 324 | { 0x8080, 0x0 }, |
349 | { 0x108080, 0x0 }, | 325 | { 0x108080, 0x0 }, |
350 | { 0x208080, 0x0 }, | 326 | { 0x208080, 0x0 }, |
351 | { 0x9080, 0x0 }, | 327 | { 0x9080, 0x0 }, |
352 | { 0x109080, 0x0 }, | 328 | { 0x109080, 0x0 }, |
353 | { 0x209080, 0x0 }, | 329 | { 0x209080, 0x0 }, |
354 | { 0x10080, 0x0 }, | 330 | { 0x10080, 0x0 }, |
355 | { 0x110080, 0x0 }, | 331 | { 0x110080, 0x0 }, |
356 | { 0x210080, 0x0 }, | 332 | { 0x210080, 0x0 }, |
357 | { 0x10180, 0x0 }, | 333 | { 0x10180, 0x0 }, |
358 | { 0x110180, 0x0 }, | 334 | { 0x110180, 0x0 }, |
359 | { 0x210180, 0x0 }, | 335 | { 0x210180, 0x0 }, |
360 | { 0x11080, 0x0 }, | 336 | { 0x11080, 0x0 }, |
361 | { 0x111080, 0x0 }, | 337 | { 0x111080, 0x0 }, |
362 | { 0x211080, 0x0 }, | 338 | { 0x211080, 0x0 }, |
363 | { 0x11180, 0x0 }, | 339 | { 0x11180, 0x0 }, |
364 | { 0x111180, 0x0 }, | 340 | { 0x111180, 0x0 }, |
365 | { 0x211180, 0x0 }, | 341 | { 0x211180, 0x0 }, |
366 | { 0x12080, 0x0 }, | 342 | { 0x12080, 0x0 }, |
367 | { 0x112080, 0x0 }, | 343 | { 0x112080, 0x0 }, |
368 | { 0x212080, 0x0 }, | 344 | { 0x212080, 0x0 }, |
369 | { 0x12180, 0x0 }, | 345 | { 0x12180, 0x0 }, |
370 | { 0x112180, 0x0 }, | 346 | { 0x112180, 0x0 }, |
371 | { 0x212180, 0x0 }, | 347 | { 0x212180, 0x0 }, |
372 | { 0x13080, 0x0 }, | 348 | { 0x13080, 0x0 }, |
373 | { 0x113080, 0x0 }, | 349 | { 0x113080, 0x0 }, |
374 | { 0x213080, 0x0 }, | 350 | { 0x213080, 0x0 }, |
375 | { 0x13180, 0x0 }, | 351 | { 0x13180, 0x0 }, |
376 | { 0x113180, 0x0 }, | 352 | { 0x113180, 0x0 }, |
377 | { 0x213180, 0x0 }, | 353 | { 0x213180, 0x0 }, |
378 | { 0x10081, 0x0 }, | 354 | { 0x10081, 0x0 }, |
379 | { 0x110081, 0x0 }, | 355 | { 0x110081, 0x0 }, |
380 | { 0x210081, 0x0 }, | 356 | { 0x210081, 0x0 }, |
381 | { 0x10181, 0x0 }, | 357 | { 0x10181, 0x0 }, |
382 | { 0x110181, 0x0 }, | 358 | { 0x110181, 0x0 }, |
383 | { 0x210181, 0x0 }, | 359 | { 0x210181, 0x0 }, |
384 | { 0x11081, 0x0 }, | 360 | { 0x11081, 0x0 }, |
385 | { 0x111081, 0x0 }, | 361 | { 0x111081, 0x0 }, |
386 | { 0x211081, 0x0 }, | 362 | { 0x211081, 0x0 }, |
387 | { 0x11181, 0x0 }, | 363 | { 0x11181, 0x0 }, |
388 | { 0x111181, 0x0 }, | 364 | { 0x111181, 0x0 }, |
389 | { 0x211181, 0x0 }, | 365 | { 0x211181, 0x0 }, |
390 | { 0x12081, 0x0 }, | 366 | { 0x12081, 0x0 }, |
391 | { 0x112081, 0x0 }, | 367 | { 0x112081, 0x0 }, |
392 | { 0x212081, 0x0 }, | 368 | { 0x212081, 0x0 }, |
393 | { 0x12181, 0x0 }, | 369 | { 0x12181, 0x0 }, |
394 | { 0x112181, 0x0 }, | 370 | { 0x112181, 0x0 }, |
395 | { 0x212181, 0x0 }, | 371 | { 0x212181, 0x0 }, |
396 | { 0x13081, 0x0 }, | 372 | { 0x13081, 0x0 }, |
397 | { 0x113081, 0x0 }, | 373 | { 0x113081, 0x0 }, |
398 | { 0x213081, 0x0 }, | 374 | { 0x213081, 0x0 }, |
399 | { 0x13181, 0x0 }, | 375 | { 0x13181, 0x0 }, |
400 | { 0x113181, 0x0 }, | 376 | { 0x113181, 0x0 }, |
401 | { 0x213181, 0x0 }, | 377 | { 0x213181, 0x0 }, |
402 | { 0x100d0, 0x0 }, | 378 | { 0x100d0, 0x0 }, |
403 | { 0x1100d0, 0x0 }, | 379 | { 0x1100d0, 0x0 }, |
404 | { 0x2100d0, 0x0 }, | 380 | { 0x2100d0, 0x0 }, |
405 | { 0x101d0, 0x0 }, | 381 | { 0x101d0, 0x0 }, |
406 | { 0x1101d0, 0x0 }, | 382 | { 0x1101d0, 0x0 }, |
407 | { 0x2101d0, 0x0 }, | 383 | { 0x2101d0, 0x0 }, |
408 | { 0x110d0, 0x0 }, | 384 | { 0x110d0, 0x0 }, |
409 | { 0x1110d0, 0x0 }, | 385 | { 0x1110d0, 0x0 }, |
410 | { 0x2110d0, 0x0 }, | 386 | { 0x2110d0, 0x0 }, |
411 | { 0x111d0, 0x0 }, | 387 | { 0x111d0, 0x0 }, |
412 | { 0x1111d0, 0x0 }, | 388 | { 0x1111d0, 0x0 }, |
413 | { 0x2111d0, 0x0 }, | 389 | { 0x2111d0, 0x0 }, |
414 | { 0x120d0, 0x0 }, | 390 | { 0x120d0, 0x0 }, |
415 | { 0x1120d0, 0x0 }, | 391 | { 0x1120d0, 0x0 }, |
416 | { 0x2120d0, 0x0 }, | 392 | { 0x2120d0, 0x0 }, |
417 | { 0x121d0, 0x0 }, | 393 | { 0x121d0, 0x0 }, |
418 | { 0x1121d0, 0x0 }, | 394 | { 0x1121d0, 0x0 }, |
419 | { 0x2121d0, 0x0 }, | 395 | { 0x2121d0, 0x0 }, |
420 | { 0x130d0, 0x0 }, | 396 | { 0x130d0, 0x0 }, |
421 | { 0x1130d0, 0x0 }, | 397 | { 0x1130d0, 0x0 }, |
422 | { 0x2130d0, 0x0 }, | 398 | { 0x2130d0, 0x0 }, |
423 | { 0x131d0, 0x0 }, | 399 | { 0x131d0, 0x0 }, |
424 | { 0x1131d0, 0x0 }, | 400 | { 0x1131d0, 0x0 }, |
425 | { 0x2131d0, 0x0 }, | 401 | { 0x2131d0, 0x0 }, |
426 | { 0x100d1, 0x0 }, | 402 | { 0x100d1, 0x0 }, |
427 | { 0x1100d1, 0x0 }, | 403 | { 0x1100d1, 0x0 }, |
428 | { 0x2100d1, 0x0 }, | 404 | { 0x2100d1, 0x0 }, |
429 | { 0x101d1, 0x0 }, | 405 | { 0x101d1, 0x0 }, |
430 | { 0x1101d1, 0x0 }, | 406 | { 0x1101d1, 0x0 }, |
431 | { 0x2101d1, 0x0 }, | 407 | { 0x2101d1, 0x0 }, |
432 | { 0x110d1, 0x0 }, | 408 | { 0x110d1, 0x0 }, |
433 | { 0x1110d1, 0x0 }, | 409 | { 0x1110d1, 0x0 }, |
434 | { 0x2110d1, 0x0 }, | 410 | { 0x2110d1, 0x0 }, |
435 | { 0x111d1, 0x0 }, | 411 | { 0x111d1, 0x0 }, |
436 | { 0x1111d1, 0x0 }, | 412 | { 0x1111d1, 0x0 }, |
437 | { 0x2111d1, 0x0 }, | 413 | { 0x2111d1, 0x0 }, |
438 | { 0x120d1, 0x0 }, | 414 | { 0x120d1, 0x0 }, |
439 | { 0x1120d1, 0x0 }, | 415 | { 0x1120d1, 0x0 }, |
440 | { 0x2120d1, 0x0 }, | 416 | { 0x2120d1, 0x0 }, |
441 | { 0x121d1, 0x0 }, | 417 | { 0x121d1, 0x0 }, |
442 | { 0x1121d1, 0x0 }, | 418 | { 0x1121d1, 0x0 }, |
443 | { 0x2121d1, 0x0 }, | 419 | { 0x2121d1, 0x0 }, |
444 | { 0x130d1, 0x0 }, | 420 | { 0x130d1, 0x0 }, |
445 | { 0x1130d1, 0x0 }, | 421 | { 0x1130d1, 0x0 }, |
446 | { 0x2130d1, 0x0 }, | 422 | { 0x2130d1, 0x0 }, |
447 | { 0x131d1, 0x0 }, | 423 | { 0x131d1, 0x0 }, |
448 | { 0x1131d1, 0x0 }, | 424 | { 0x1131d1, 0x0 }, |
449 | { 0x2131d1, 0x0 }, | 425 | { 0x2131d1, 0x0 }, |
450 | { 0x10068, 0x0 }, | 426 | { 0x10068, 0x0 }, |
451 | { 0x10168, 0x0 }, | 427 | { 0x10168, 0x0 }, |
452 | { 0x10268, 0x0 }, | 428 | { 0x10268, 0x0 }, |
453 | { 0x10368, 0x0 }, | 429 | { 0x10368, 0x0 }, |
454 | { 0x10468, 0x0 }, | 430 | { 0x10468, 0x0 }, |
455 | { 0x10568, 0x0 }, | 431 | { 0x10568, 0x0 }, |
456 | { 0x10668, 0x0 }, | 432 | { 0x10668, 0x0 }, |
457 | { 0x10768, 0x0 }, | 433 | { 0x10768, 0x0 }, |
458 | { 0x10868, 0x0 }, | 434 | { 0x10868, 0x0 }, |
459 | { 0x11068, 0x0 }, | 435 | { 0x11068, 0x0 }, |
460 | { 0x11168, 0x0 }, | 436 | { 0x11168, 0x0 }, |
461 | { 0x11268, 0x0 }, | 437 | { 0x11268, 0x0 }, |
462 | { 0x11368, 0x0 }, | 438 | { 0x11368, 0x0 }, |
463 | { 0x11468, 0x0 }, | 439 | { 0x11468, 0x0 }, |
464 | { 0x11568, 0x0 }, | 440 | { 0x11568, 0x0 }, |
465 | { 0x11668, 0x0 }, | 441 | { 0x11668, 0x0 }, |
466 | { 0x11768, 0x0 }, | 442 | { 0x11768, 0x0 }, |
467 | { 0x11868, 0x0 }, | 443 | { 0x11868, 0x0 }, |
468 | { 0x12068, 0x0 }, | 444 | { 0x12068, 0x0 }, |
469 | { 0x12168, 0x0 }, | 445 | { 0x12168, 0x0 }, |
470 | { 0x12268, 0x0 }, | 446 | { 0x12268, 0x0 }, |
471 | { 0x12368, 0x0 }, | 447 | { 0x12368, 0x0 }, |
472 | { 0x12468, 0x0 }, | 448 | { 0x12468, 0x0 }, |
473 | { 0x12568, 0x0 }, | 449 | { 0x12568, 0x0 }, |
474 | { 0x12668, 0x0 }, | 450 | { 0x12668, 0x0 }, |
475 | { 0x12768, 0x0 }, | 451 | { 0x12768, 0x0 }, |
476 | { 0x12868, 0x0 }, | 452 | { 0x12868, 0x0 }, |
477 | { 0x13068, 0x0 }, | 453 | { 0x13068, 0x0 }, |
478 | { 0x13168, 0x0 }, | 454 | { 0x13168, 0x0 }, |
479 | { 0x13268, 0x0 }, | 455 | { 0x13268, 0x0 }, |
480 | { 0x13368, 0x0 }, | 456 | { 0x13368, 0x0 }, |
481 | { 0x13468, 0x0 }, | 457 | { 0x13468, 0x0 }, |
482 | { 0x13568, 0x0 }, | 458 | { 0x13568, 0x0 }, |
483 | { 0x13668, 0x0 }, | 459 | { 0x13668, 0x0 }, |
484 | { 0x13768, 0x0 }, | 460 | { 0x13768, 0x0 }, |
485 | { 0x13868, 0x0 }, | 461 | { 0x13868, 0x0 }, |
486 | { 0x10069, 0x0 }, | 462 | { 0x10069, 0x0 }, |
487 | { 0x10169, 0x0 }, | 463 | { 0x10169, 0x0 }, |
488 | { 0x10269, 0x0 }, | 464 | { 0x10269, 0x0 }, |
489 | { 0x10369, 0x0 }, | 465 | { 0x10369, 0x0 }, |
490 | { 0x10469, 0x0 }, | 466 | { 0x10469, 0x0 }, |
491 | { 0x10569, 0x0 }, | 467 | { 0x10569, 0x0 }, |
492 | { 0x10669, 0x0 }, | 468 | { 0x10669, 0x0 }, |
493 | { 0x10769, 0x0 }, | 469 | { 0x10769, 0x0 }, |
494 | { 0x10869, 0x0 }, | 470 | { 0x10869, 0x0 }, |
495 | { 0x11069, 0x0 }, | 471 | { 0x11069, 0x0 }, |
496 | { 0x11169, 0x0 }, | 472 | { 0x11169, 0x0 }, |
497 | { 0x11269, 0x0 }, | 473 | { 0x11269, 0x0 }, |
498 | { 0x11369, 0x0 }, | 474 | { 0x11369, 0x0 }, |
499 | { 0x11469, 0x0 }, | 475 | { 0x11469, 0x0 }, |
500 | { 0x11569, 0x0 }, | 476 | { 0x11569, 0x0 }, |
501 | { 0x11669, 0x0 }, | 477 | { 0x11669, 0x0 }, |
502 | { 0x11769, 0x0 }, | 478 | { 0x11769, 0x0 }, |
503 | { 0x11869, 0x0 }, | 479 | { 0x11869, 0x0 }, |
504 | { 0x12069, 0x0 }, | 480 | { 0x12069, 0x0 }, |
505 | { 0x12169, 0x0 }, | 481 | { 0x12169, 0x0 }, |
506 | { 0x12269, 0x0 }, | 482 | { 0x12269, 0x0 }, |
507 | { 0x12369, 0x0 }, | 483 | { 0x12369, 0x0 }, |
508 | { 0x12469, 0x0 }, | 484 | { 0x12469, 0x0 }, |
509 | { 0x12569, 0x0 }, | 485 | { 0x12569, 0x0 }, |
510 | { 0x12669, 0x0 }, | 486 | { 0x12669, 0x0 }, |
511 | { 0x12769, 0x0 }, | 487 | { 0x12769, 0x0 }, |
512 | { 0x12869, 0x0 }, | 488 | { 0x12869, 0x0 }, |
513 | { 0x13069, 0x0 }, | 489 | { 0x13069, 0x0 }, |
514 | { 0x13169, 0x0 }, | 490 | { 0x13169, 0x0 }, |
515 | { 0x13269, 0x0 }, | 491 | { 0x13269, 0x0 }, |
516 | { 0x13369, 0x0 }, | 492 | { 0x13369, 0x0 }, |
517 | { 0x13469, 0x0 }, | 493 | { 0x13469, 0x0 }, |
518 | { 0x13569, 0x0 }, | 494 | { 0x13569, 0x0 }, |
519 | { 0x13669, 0x0 }, | 495 | { 0x13669, 0x0 }, |
520 | { 0x13769, 0x0 }, | 496 | { 0x13769, 0x0 }, |
521 | { 0x13869, 0x0 }, | 497 | { 0x13869, 0x0 }, |
522 | { 0x1008c, 0x0 }, | 498 | { 0x1008c, 0x0 }, |
523 | { 0x11008c, 0x0 }, | 499 | { 0x11008c, 0x0 }, |
524 | { 0x21008c, 0x0 }, | 500 | { 0x21008c, 0x0 }, |
525 | { 0x1018c, 0x0 }, | 501 | { 0x1018c, 0x0 }, |
526 | { 0x11018c, 0x0 }, | 502 | { 0x11018c, 0x0 }, |
527 | { 0x21018c, 0x0 }, | 503 | { 0x21018c, 0x0 }, |
528 | { 0x1108c, 0x0 }, | 504 | { 0x1108c, 0x0 }, |
529 | { 0x11108c, 0x0 }, | 505 | { 0x11108c, 0x0 }, |
530 | { 0x21108c, 0x0 }, | 506 | { 0x21108c, 0x0 }, |
531 | { 0x1118c, 0x0 }, | 507 | { 0x1118c, 0x0 }, |
532 | { 0x11118c, 0x0 }, | 508 | { 0x11118c, 0x0 }, |
533 | { 0x21118c, 0x0 }, | 509 | { 0x21118c, 0x0 }, |
534 | { 0x1208c, 0x0 }, | 510 | { 0x1208c, 0x0 }, |
535 | { 0x11208c, 0x0 }, | 511 | { 0x11208c, 0x0 }, |
536 | { 0x21208c, 0x0 }, | 512 | { 0x21208c, 0x0 }, |
537 | { 0x1218c, 0x0 }, | 513 | { 0x1218c, 0x0 }, |
538 | { 0x11218c, 0x0 }, | 514 | { 0x11218c, 0x0 }, |
539 | { 0x21218c, 0x0 }, | 515 | { 0x21218c, 0x0 }, |
540 | { 0x1308c, 0x0 }, | 516 | { 0x1308c, 0x0 }, |
541 | { 0x11308c, 0x0 }, | 517 | { 0x11308c, 0x0 }, |
542 | { 0x21308c, 0x0 }, | 518 | { 0x21308c, 0x0 }, |
543 | { 0x1318c, 0x0 }, | 519 | { 0x1318c, 0x0 }, |
544 | { 0x11318c, 0x0 }, | 520 | { 0x11318c, 0x0 }, |
545 | { 0x21318c, 0x0 }, | 521 | { 0x21318c, 0x0 }, |
546 | { 0x1008d, 0x0 }, | 522 | { 0x1008d, 0x0 }, |
547 | { 0x11008d, 0x0 }, | 523 | { 0x11008d, 0x0 }, |
548 | { 0x21008d, 0x0 }, | 524 | { 0x21008d, 0x0 }, |
549 | { 0x1018d, 0x0 }, | 525 | { 0x1018d, 0x0 }, |
550 | { 0x11018d, 0x0 }, | 526 | { 0x11018d, 0x0 }, |
551 | { 0x21018d, 0x0 }, | 527 | { 0x21018d, 0x0 }, |
552 | { 0x1108d, 0x0 }, | 528 | { 0x1108d, 0x0 }, |
553 | { 0x11108d, 0x0 }, | 529 | { 0x11108d, 0x0 }, |
554 | { 0x21108d, 0x0 }, | 530 | { 0x21108d, 0x0 }, |
555 | { 0x1118d, 0x0 }, | 531 | { 0x1118d, 0x0 }, |
556 | { 0x11118d, 0x0 }, | 532 | { 0x11118d, 0x0 }, |
557 | { 0x21118d, 0x0 }, | 533 | { 0x21118d, 0x0 }, |
558 | { 0x1208d, 0x0 }, | 534 | { 0x1208d, 0x0 }, |
559 | { 0x11208d, 0x0 }, | 535 | { 0x11208d, 0x0 }, |
560 | { 0x21208d, 0x0 }, | 536 | { 0x21208d, 0x0 }, |
561 | { 0x1218d, 0x0 }, | 537 | { 0x1218d, 0x0 }, |
562 | { 0x11218d, 0x0 }, | 538 | { 0x11218d, 0x0 }, |
563 | { 0x21218d, 0x0 }, | 539 | { 0x21218d, 0x0 }, |
564 | { 0x1308d, 0x0 }, | 540 | { 0x1308d, 0x0 }, |
565 | { 0x11308d, 0x0 }, | 541 | { 0x11308d, 0x0 }, |
566 | { 0x21308d, 0x0 }, | 542 | { 0x21308d, 0x0 }, |
567 | { 0x1318d, 0x0 }, | 543 | { 0x1318d, 0x0 }, |
568 | { 0x11318d, 0x0 }, | 544 | { 0x11318d, 0x0 }, |
569 | { 0x21318d, 0x0 }, | 545 | { 0x21318d, 0x0 }, |
570 | { 0x100c0, 0x0 }, | 546 | { 0x100c0, 0x0 }, |
571 | { 0x1100c0, 0x0 }, | 547 | { 0x1100c0, 0x0 }, |
572 | { 0x2100c0, 0x0 }, | 548 | { 0x2100c0, 0x0 }, |
573 | { 0x101c0, 0x0 }, | 549 | { 0x101c0, 0x0 }, |
574 | { 0x1101c0, 0x0 }, | 550 | { 0x1101c0, 0x0 }, |
575 | { 0x2101c0, 0x0 }, | 551 | { 0x2101c0, 0x0 }, |
576 | { 0x102c0, 0x0 }, | 552 | { 0x102c0, 0x0 }, |
577 | { 0x1102c0, 0x0 }, | 553 | { 0x1102c0, 0x0 }, |
578 | { 0x2102c0, 0x0 }, | 554 | { 0x2102c0, 0x0 }, |
579 | { 0x103c0, 0x0 }, | 555 | { 0x103c0, 0x0 }, |
580 | { 0x1103c0, 0x0 }, | 556 | { 0x1103c0, 0x0 }, |
581 | { 0x2103c0, 0x0 }, | 557 | { 0x2103c0, 0x0 }, |
582 | { 0x104c0, 0x0 }, | 558 | { 0x104c0, 0x0 }, |
583 | { 0x1104c0, 0x0 }, | 559 | { 0x1104c0, 0x0 }, |
584 | { 0x2104c0, 0x0 }, | 560 | { 0x2104c0, 0x0 }, |
585 | { 0x105c0, 0x0 }, | 561 | { 0x105c0, 0x0 }, |
586 | { 0x1105c0, 0x0 }, | 562 | { 0x1105c0, 0x0 }, |
587 | { 0x2105c0, 0x0 }, | 563 | { 0x2105c0, 0x0 }, |
588 | { 0x106c0, 0x0 }, | 564 | { 0x106c0, 0x0 }, |
589 | { 0x1106c0, 0x0 }, | 565 | { 0x1106c0, 0x0 }, |
590 | { 0x2106c0, 0x0 }, | 566 | { 0x2106c0, 0x0 }, |
591 | { 0x107c0, 0x0 }, | 567 | { 0x107c0, 0x0 }, |
592 | { 0x1107c0, 0x0 }, | 568 | { 0x1107c0, 0x0 }, |
593 | { 0x2107c0, 0x0 }, | 569 | { 0x2107c0, 0x0 }, |
594 | { 0x108c0, 0x0 }, | 570 | { 0x108c0, 0x0 }, |
595 | { 0x1108c0, 0x0 }, | 571 | { 0x1108c0, 0x0 }, |
596 | { 0x2108c0, 0x0 }, | 572 | { 0x2108c0, 0x0 }, |
597 | { 0x110c0, 0x0 }, | 573 | { 0x110c0, 0x0 }, |
598 | { 0x1110c0, 0x0 }, | 574 | { 0x1110c0, 0x0 }, |
599 | { 0x2110c0, 0x0 }, | 575 | { 0x2110c0, 0x0 }, |
600 | { 0x111c0, 0x0 }, | 576 | { 0x111c0, 0x0 }, |
601 | { 0x1111c0, 0x0 }, | 577 | { 0x1111c0, 0x0 }, |
602 | { 0x2111c0, 0x0 }, | 578 | { 0x2111c0, 0x0 }, |
603 | { 0x112c0, 0x0 }, | 579 | { 0x112c0, 0x0 }, |
604 | { 0x1112c0, 0x0 }, | 580 | { 0x1112c0, 0x0 }, |
605 | { 0x2112c0, 0x0 }, | 581 | { 0x2112c0, 0x0 }, |
606 | { 0x113c0, 0x0 }, | 582 | { 0x113c0, 0x0 }, |
607 | { 0x1113c0, 0x0 }, | 583 | { 0x1113c0, 0x0 }, |
608 | { 0x2113c0, 0x0 }, | 584 | { 0x2113c0, 0x0 }, |
609 | { 0x114c0, 0x0 }, | 585 | { 0x114c0, 0x0 }, |
610 | { 0x1114c0, 0x0 }, | 586 | { 0x1114c0, 0x0 }, |
611 | { 0x2114c0, 0x0 }, | 587 | { 0x2114c0, 0x0 }, |
612 | { 0x115c0, 0x0 }, | 588 | { 0x115c0, 0x0 }, |
613 | { 0x1115c0, 0x0 }, | 589 | { 0x1115c0, 0x0 }, |
614 | { 0x2115c0, 0x0 }, | 590 | { 0x2115c0, 0x0 }, |
615 | { 0x116c0, 0x0 }, | 591 | { 0x116c0, 0x0 }, |
616 | { 0x1116c0, 0x0 }, | 592 | { 0x1116c0, 0x0 }, |
617 | { 0x2116c0, 0x0 }, | 593 | { 0x2116c0, 0x0 }, |
618 | { 0x117c0, 0x0 }, | 594 | { 0x117c0, 0x0 }, |
619 | { 0x1117c0, 0x0 }, | 595 | { 0x1117c0, 0x0 }, |
620 | { 0x2117c0, 0x0 }, | 596 | { 0x2117c0, 0x0 }, |
621 | { 0x118c0, 0x0 }, | 597 | { 0x118c0, 0x0 }, |
622 | { 0x1118c0, 0x0 }, | 598 | { 0x1118c0, 0x0 }, |
623 | { 0x2118c0, 0x0 }, | 599 | { 0x2118c0, 0x0 }, |
624 | { 0x120c0, 0x0 }, | 600 | { 0x120c0, 0x0 }, |
625 | { 0x1120c0, 0x0 }, | 601 | { 0x1120c0, 0x0 }, |
626 | { 0x2120c0, 0x0 }, | 602 | { 0x2120c0, 0x0 }, |
627 | { 0x121c0, 0x0 }, | 603 | { 0x121c0, 0x0 }, |
628 | { 0x1121c0, 0x0 }, | 604 | { 0x1121c0, 0x0 }, |
629 | { 0x2121c0, 0x0 }, | 605 | { 0x2121c0, 0x0 }, |
630 | { 0x122c0, 0x0 }, | 606 | { 0x122c0, 0x0 }, |
631 | { 0x1122c0, 0x0 }, | 607 | { 0x1122c0, 0x0 }, |
632 | { 0x2122c0, 0x0 }, | 608 | { 0x2122c0, 0x0 }, |
633 | { 0x123c0, 0x0 }, | 609 | { 0x123c0, 0x0 }, |
634 | { 0x1123c0, 0x0 }, | 610 | { 0x1123c0, 0x0 }, |
635 | { 0x2123c0, 0x0 }, | 611 | { 0x2123c0, 0x0 }, |
636 | { 0x124c0, 0x0 }, | 612 | { 0x124c0, 0x0 }, |
637 | { 0x1124c0, 0x0 }, | 613 | { 0x1124c0, 0x0 }, |
638 | { 0x2124c0, 0x0 }, | 614 | { 0x2124c0, 0x0 }, |
639 | { 0x125c0, 0x0 }, | 615 | { 0x125c0, 0x0 }, |
640 | { 0x1125c0, 0x0 }, | 616 | { 0x1125c0, 0x0 }, |
641 | { 0x2125c0, 0x0 }, | 617 | { 0x2125c0, 0x0 }, |
642 | { 0x126c0, 0x0 }, | 618 | { 0x126c0, 0x0 }, |
643 | { 0x1126c0, 0x0 }, | 619 | { 0x1126c0, 0x0 }, |
644 | { 0x2126c0, 0x0 }, | 620 | { 0x2126c0, 0x0 }, |
645 | { 0x127c0, 0x0 }, | 621 | { 0x127c0, 0x0 }, |
646 | { 0x1127c0, 0x0 }, | 622 | { 0x1127c0, 0x0 }, |
647 | { 0x2127c0, 0x0 }, | 623 | { 0x2127c0, 0x0 }, |
648 | { 0x128c0, 0x0 }, | 624 | { 0x128c0, 0x0 }, |
649 | { 0x1128c0, 0x0 }, | 625 | { 0x1128c0, 0x0 }, |
650 | { 0x2128c0, 0x0 }, | 626 | { 0x2128c0, 0x0 }, |
651 | { 0x130c0, 0x0 }, | 627 | { 0x130c0, 0x0 }, |
652 | { 0x1130c0, 0x0 }, | 628 | { 0x1130c0, 0x0 }, |
653 | { 0x2130c0, 0x0 }, | 629 | { 0x2130c0, 0x0 }, |
654 | { 0x131c0, 0x0 }, | 630 | { 0x131c0, 0x0 }, |
655 | { 0x1131c0, 0x0 }, | 631 | { 0x1131c0, 0x0 }, |
656 | { 0x2131c0, 0x0 }, | 632 | { 0x2131c0, 0x0 }, |
657 | { 0x132c0, 0x0 }, | 633 | { 0x132c0, 0x0 }, |
658 | { 0x1132c0, 0x0 }, | 634 | { 0x1132c0, 0x0 }, |
659 | { 0x2132c0, 0x0 }, | 635 | { 0x2132c0, 0x0 }, |
660 | { 0x133c0, 0x0 }, | 636 | { 0x133c0, 0x0 }, |
661 | { 0x1133c0, 0x0 }, | 637 | { 0x1133c0, 0x0 }, |
662 | { 0x2133c0, 0x0 }, | 638 | { 0x2133c0, 0x0 }, |
663 | { 0x134c0, 0x0 }, | 639 | { 0x134c0, 0x0 }, |
664 | { 0x1134c0, 0x0 }, | 640 | { 0x1134c0, 0x0 }, |
665 | { 0x2134c0, 0x0 }, | 641 | { 0x2134c0, 0x0 }, |
666 | { 0x135c0, 0x0 }, | 642 | { 0x135c0, 0x0 }, |
667 | { 0x1135c0, 0x0 }, | 643 | { 0x1135c0, 0x0 }, |
668 | { 0x2135c0, 0x0 }, | 644 | { 0x2135c0, 0x0 }, |
669 | { 0x136c0, 0x0 }, | 645 | { 0x136c0, 0x0 }, |
670 | { 0x1136c0, 0x0 }, | 646 | { 0x1136c0, 0x0 }, |
671 | { 0x2136c0, 0x0 }, | 647 | { 0x2136c0, 0x0 }, |
672 | { 0x137c0, 0x0 }, | 648 | { 0x137c0, 0x0 }, |
673 | { 0x1137c0, 0x0 }, | 649 | { 0x1137c0, 0x0 }, |
674 | { 0x2137c0, 0x0 }, | 650 | { 0x2137c0, 0x0 }, |
675 | { 0x138c0, 0x0 }, | 651 | { 0x138c0, 0x0 }, |
676 | { 0x1138c0, 0x0 }, | 652 | { 0x1138c0, 0x0 }, |
677 | { 0x2138c0, 0x0 }, | 653 | { 0x2138c0, 0x0 }, |
678 | { 0x100c1, 0x0 }, | 654 | { 0x100c1, 0x0 }, |
679 | { 0x1100c1, 0x0 }, | 655 | { 0x1100c1, 0x0 }, |
680 | { 0x2100c1, 0x0 }, | 656 | { 0x2100c1, 0x0 }, |
681 | { 0x101c1, 0x0 }, | 657 | { 0x101c1, 0x0 }, |
682 | { 0x1101c1, 0x0 }, | 658 | { 0x1101c1, 0x0 }, |
683 | { 0x2101c1, 0x0 }, | 659 | { 0x2101c1, 0x0 }, |
684 | { 0x102c1, 0x0 }, | 660 | { 0x102c1, 0x0 }, |
685 | { 0x1102c1, 0x0 }, | 661 | { 0x1102c1, 0x0 }, |
686 | { 0x2102c1, 0x0 }, | 662 | { 0x2102c1, 0x0 }, |
687 | { 0x103c1, 0x0 }, | 663 | { 0x103c1, 0x0 }, |
688 | { 0x1103c1, 0x0 }, | 664 | { 0x1103c1, 0x0 }, |
689 | { 0x2103c1, 0x0 }, | 665 | { 0x2103c1, 0x0 }, |
690 | { 0x104c1, 0x0 }, | 666 | { 0x104c1, 0x0 }, |
691 | { 0x1104c1, 0x0 }, | 667 | { 0x1104c1, 0x0 }, |
692 | { 0x2104c1, 0x0 }, | 668 | { 0x2104c1, 0x0 }, |
693 | { 0x105c1, 0x0 }, | 669 | { 0x105c1, 0x0 }, |
694 | { 0x1105c1, 0x0 }, | 670 | { 0x1105c1, 0x0 }, |
695 | { 0x2105c1, 0x0 }, | 671 | { 0x2105c1, 0x0 }, |
696 | { 0x106c1, 0x0 }, | 672 | { 0x106c1, 0x0 }, |
697 | { 0x1106c1, 0x0 }, | 673 | { 0x1106c1, 0x0 }, |
698 | { 0x2106c1, 0x0 }, | 674 | { 0x2106c1, 0x0 }, |
699 | { 0x107c1, 0x0 }, | 675 | { 0x107c1, 0x0 }, |
700 | { 0x1107c1, 0x0 }, | 676 | { 0x1107c1, 0x0 }, |
701 | { 0x2107c1, 0x0 }, | 677 | { 0x2107c1, 0x0 }, |
702 | { 0x108c1, 0x0 }, | 678 | { 0x108c1, 0x0 }, |
703 | { 0x1108c1, 0x0 }, | 679 | { 0x1108c1, 0x0 }, |
704 | { 0x2108c1, 0x0 }, | 680 | { 0x2108c1, 0x0 }, |
705 | { 0x110c1, 0x0 }, | 681 | { 0x110c1, 0x0 }, |
706 | { 0x1110c1, 0x0 }, | 682 | { 0x1110c1, 0x0 }, |
707 | { 0x2110c1, 0x0 }, | 683 | { 0x2110c1, 0x0 }, |
708 | { 0x111c1, 0x0 }, | 684 | { 0x111c1, 0x0 }, |
709 | { 0x1111c1, 0x0 }, | 685 | { 0x1111c1, 0x0 }, |
710 | { 0x2111c1, 0x0 }, | 686 | { 0x2111c1, 0x0 }, |
711 | { 0x112c1, 0x0 }, | 687 | { 0x112c1, 0x0 }, |
712 | { 0x1112c1, 0x0 }, | 688 | { 0x1112c1, 0x0 }, |
713 | { 0x2112c1, 0x0 }, | 689 | { 0x2112c1, 0x0 }, |
714 | { 0x113c1, 0x0 }, | 690 | { 0x113c1, 0x0 }, |
715 | { 0x1113c1, 0x0 }, | 691 | { 0x1113c1, 0x0 }, |
716 | { 0x2113c1, 0x0 }, | 692 | { 0x2113c1, 0x0 }, |
717 | { 0x114c1, 0x0 }, | 693 | { 0x114c1, 0x0 }, |
718 | { 0x1114c1, 0x0 }, | 694 | { 0x1114c1, 0x0 }, |
719 | { 0x2114c1, 0x0 }, | 695 | { 0x2114c1, 0x0 }, |
720 | { 0x115c1, 0x0 }, | 696 | { 0x115c1, 0x0 }, |
721 | { 0x1115c1, 0x0 }, | 697 | { 0x1115c1, 0x0 }, |
722 | { 0x2115c1, 0x0 }, | 698 | { 0x2115c1, 0x0 }, |
723 | { 0x116c1, 0x0 }, | 699 | { 0x116c1, 0x0 }, |
724 | { 0x1116c1, 0x0 }, | 700 | { 0x1116c1, 0x0 }, |
725 | { 0x2116c1, 0x0 }, | 701 | { 0x2116c1, 0x0 }, |
726 | { 0x117c1, 0x0 }, | 702 | { 0x117c1, 0x0 }, |
727 | { 0x1117c1, 0x0 }, | 703 | { 0x1117c1, 0x0 }, |
728 | { 0x2117c1, 0x0 }, | 704 | { 0x2117c1, 0x0 }, |
729 | { 0x118c1, 0x0 }, | 705 | { 0x118c1, 0x0 }, |
730 | { 0x1118c1, 0x0 }, | 706 | { 0x1118c1, 0x0 }, |
731 | { 0x2118c1, 0x0 }, | 707 | { 0x2118c1, 0x0 }, |
732 | { 0x120c1, 0x0 }, | 708 | { 0x120c1, 0x0 }, |
733 | { 0x1120c1, 0x0 }, | 709 | { 0x1120c1, 0x0 }, |
734 | { 0x2120c1, 0x0 }, | 710 | { 0x2120c1, 0x0 }, |
735 | { 0x121c1, 0x0 }, | 711 | { 0x121c1, 0x0 }, |
736 | { 0x1121c1, 0x0 }, | 712 | { 0x1121c1, 0x0 }, |
737 | { 0x2121c1, 0x0 }, | 713 | { 0x2121c1, 0x0 }, |
738 | { 0x122c1, 0x0 }, | 714 | { 0x122c1, 0x0 }, |
739 | { 0x1122c1, 0x0 }, | 715 | { 0x1122c1, 0x0 }, |
740 | { 0x2122c1, 0x0 }, | 716 | { 0x2122c1, 0x0 }, |
741 | { 0x123c1, 0x0 }, | 717 | { 0x123c1, 0x0 }, |
742 | { 0x1123c1, 0x0 }, | 718 | { 0x1123c1, 0x0 }, |
743 | { 0x2123c1, 0x0 }, | 719 | { 0x2123c1, 0x0 }, |
744 | { 0x124c1, 0x0 }, | 720 | { 0x124c1, 0x0 }, |
745 | { 0x1124c1, 0x0 }, | 721 | { 0x1124c1, 0x0 }, |
746 | { 0x2124c1, 0x0 }, | 722 | { 0x2124c1, 0x0 }, |
747 | { 0x125c1, 0x0 }, | 723 | { 0x125c1, 0x0 }, |
748 | { 0x1125c1, 0x0 }, | 724 | { 0x1125c1, 0x0 }, |
749 | { 0x2125c1, 0x0 }, | 725 | { 0x2125c1, 0x0 }, |
750 | { 0x126c1, 0x0 }, | 726 | { 0x126c1, 0x0 }, |
751 | { 0x1126c1, 0x0 }, | 727 | { 0x1126c1, 0x0 }, |
752 | { 0x2126c1, 0x0 }, | 728 | { 0x2126c1, 0x0 }, |
753 | { 0x127c1, 0x0 }, | 729 | { 0x127c1, 0x0 }, |
754 | { 0x1127c1, 0x0 }, | 730 | { 0x1127c1, 0x0 }, |
755 | { 0x2127c1, 0x0 }, | 731 | { 0x2127c1, 0x0 }, |
756 | { 0x128c1, 0x0 }, | 732 | { 0x128c1, 0x0 }, |
757 | { 0x1128c1, 0x0 }, | 733 | { 0x1128c1, 0x0 }, |
758 | { 0x2128c1, 0x0 }, | 734 | { 0x2128c1, 0x0 }, |
759 | { 0x130c1, 0x0 }, | 735 | { 0x130c1, 0x0 }, |
760 | { 0x1130c1, 0x0 }, | 736 | { 0x1130c1, 0x0 }, |
761 | { 0x2130c1, 0x0 }, | 737 | { 0x2130c1, 0x0 }, |
762 | { 0x131c1, 0x0 }, | 738 | { 0x131c1, 0x0 }, |
763 | { 0x1131c1, 0x0 }, | 739 | { 0x1131c1, 0x0 }, |
764 | { 0x2131c1, 0x0 }, | 740 | { 0x2131c1, 0x0 }, |
765 | { 0x132c1, 0x0 }, | 741 | { 0x132c1, 0x0 }, |
766 | { 0x1132c1, 0x0 }, | 742 | { 0x1132c1, 0x0 }, |
767 | { 0x2132c1, 0x0 }, | 743 | { 0x2132c1, 0x0 }, |
768 | { 0x133c1, 0x0 }, | 744 | { 0x133c1, 0x0 }, |
769 | { 0x1133c1, 0x0 }, | 745 | { 0x1133c1, 0x0 }, |
770 | { 0x2133c1, 0x0 }, | 746 | { 0x2133c1, 0x0 }, |
771 | { 0x134c1, 0x0 }, | 747 | { 0x134c1, 0x0 }, |
772 | { 0x1134c1, 0x0 }, | 748 | { 0x1134c1, 0x0 }, |
773 | { 0x2134c1, 0x0 }, | 749 | { 0x2134c1, 0x0 }, |
774 | { 0x135c1, 0x0 }, | 750 | { 0x135c1, 0x0 }, |
775 | { 0x1135c1, 0x0 }, | 751 | { 0x1135c1, 0x0 }, |
776 | { 0x2135c1, 0x0 }, | 752 | { 0x2135c1, 0x0 }, |
777 | { 0x136c1, 0x0 }, | 753 | { 0x136c1, 0x0 }, |
778 | { 0x1136c1, 0x0 }, | 754 | { 0x1136c1, 0x0 }, |
779 | { 0x2136c1, 0x0 }, | 755 | { 0x2136c1, 0x0 }, |
780 | { 0x137c1, 0x0 }, | 756 | { 0x137c1, 0x0 }, |
781 | { 0x1137c1, 0x0 }, | 757 | { 0x1137c1, 0x0 }, |
782 | { 0x2137c1, 0x0 }, | 758 | { 0x2137c1, 0x0 }, |
783 | { 0x138c1, 0x0 }, | 759 | { 0x138c1, 0x0 }, |
784 | { 0x1138c1, 0x0 }, | 760 | { 0x1138c1, 0x0 }, |
785 | { 0x2138c1, 0x0 }, | 761 | { 0x2138c1, 0x0 }, |
786 | { 0x10020, 0x0 }, | 762 | { 0x10020, 0x0 }, |
787 | { 0x110020, 0x0 }, | 763 | { 0x110020, 0x0 }, |
788 | { 0x210020, 0x0 }, | 764 | { 0x210020, 0x0 }, |
789 | { 0x11020, 0x0 }, | 765 | { 0x11020, 0x0 }, |
790 | { 0x111020, 0x0 }, | 766 | { 0x111020, 0x0 }, |
791 | { 0x211020, 0x0 }, | 767 | { 0x211020, 0x0 }, |
792 | { 0x12020, 0x0 }, | 768 | { 0x12020, 0x0 }, |
793 | { 0x112020, 0x0 }, | 769 | { 0x112020, 0x0 }, |
794 | { 0x212020, 0x0 }, | 770 | { 0x212020, 0x0 }, |
795 | { 0x13020, 0x0 }, | 771 | { 0x13020, 0x0 }, |
796 | { 0x113020, 0x0 }, | 772 | { 0x113020, 0x0 }, |
797 | { 0x213020, 0x0 }, | 773 | { 0x213020, 0x0 }, |
798 | { 0x20072, 0x0 }, | 774 | { 0x20072, 0x0 }, |
799 | { 0x20073, 0x0 }, | 775 | { 0x20073, 0x0 }, |
800 | { 0x20074, 0x0 }, | 776 | { 0x20074, 0x0 }, |
801 | { 0x100aa, 0x0 }, | 777 | { 0x100aa, 0x0 }, |
802 | { 0x110aa, 0x0 }, | 778 | { 0x110aa, 0x0 }, |
803 | { 0x120aa, 0x0 }, | 779 | { 0x120aa, 0x0 }, |
804 | { 0x130aa, 0x0 }, | 780 | { 0x130aa, 0x0 }, |
805 | { 0x20010, 0x0 }, | 781 | { 0x20010, 0x0 }, |
806 | { 0x120010, 0x0 }, | 782 | { 0x120010, 0x0 }, |
807 | { 0x220010, 0x0 }, | 783 | { 0x220010, 0x0 }, |
808 | { 0x20011, 0x0 }, | 784 | { 0x20011, 0x0 }, |
809 | { 0x120011, 0x0 }, | 785 | { 0x120011, 0x0 }, |
810 | { 0x220011, 0x0 }, | 786 | { 0x220011, 0x0 }, |
811 | { 0x100ae, 0x0 }, | 787 | { 0x100ae, 0x0 }, |
812 | { 0x1100ae, 0x0 }, | 788 | { 0x1100ae, 0x0 }, |
813 | { 0x2100ae, 0x0 }, | 789 | { 0x2100ae, 0x0 }, |
814 | { 0x100af, 0x0 }, | 790 | { 0x100af, 0x0 }, |
815 | { 0x1100af, 0x0 }, | 791 | { 0x1100af, 0x0 }, |
816 | { 0x2100af, 0x0 }, | 792 | { 0x2100af, 0x0 }, |
817 | { 0x110ae, 0x0 }, | 793 | { 0x110ae, 0x0 }, |
818 | { 0x1110ae, 0x0 }, | 794 | { 0x1110ae, 0x0 }, |
819 | { 0x2110ae, 0x0 }, | 795 | { 0x2110ae, 0x0 }, |
820 | { 0x110af, 0x0 }, | 796 | { 0x110af, 0x0 }, |
821 | { 0x1110af, 0x0 }, | 797 | { 0x1110af, 0x0 }, |
822 | { 0x2110af, 0x0 }, | 798 | { 0x2110af, 0x0 }, |
823 | { 0x120ae, 0x0 }, | 799 | { 0x120ae, 0x0 }, |
824 | { 0x1120ae, 0x0 }, | 800 | { 0x1120ae, 0x0 }, |
825 | { 0x2120ae, 0x0 }, | 801 | { 0x2120ae, 0x0 }, |
826 | { 0x120af, 0x0 }, | 802 | { 0x120af, 0x0 }, |
827 | { 0x1120af, 0x0 }, | 803 | { 0x1120af, 0x0 }, |
828 | { 0x2120af, 0x0 }, | 804 | { 0x2120af, 0x0 }, |
829 | { 0x130ae, 0x0 }, | 805 | { 0x130ae, 0x0 }, |
830 | { 0x1130ae, 0x0 }, | 806 | { 0x1130ae, 0x0 }, |
831 | { 0x2130ae, 0x0 }, | 807 | { 0x2130ae, 0x0 }, |
832 | { 0x130af, 0x0 }, | 808 | { 0x130af, 0x0 }, |
833 | { 0x1130af, 0x0 }, | 809 | { 0x1130af, 0x0 }, |
834 | { 0x2130af, 0x0 }, | 810 | { 0x2130af, 0x0 }, |
835 | { 0x20020, 0x0 }, | 811 | { 0x20020, 0x0 }, |
836 | { 0x120020, 0x0 }, | 812 | { 0x120020, 0x0 }, |
837 | { 0x220020, 0x0 }, | 813 | { 0x220020, 0x0 }, |
838 | { 0x100a0, 0x0 }, | 814 | { 0x100a0, 0x0 }, |
839 | { 0x100a1, 0x0 }, | 815 | { 0x100a1, 0x0 }, |
840 | { 0x100a2, 0x0 }, | 816 | { 0x100a2, 0x0 }, |
841 | { 0x100a3, 0x0 }, | 817 | { 0x100a3, 0x0 }, |
842 | { 0x100a4, 0x0 }, | 818 | { 0x100a4, 0x0 }, |
843 | { 0x100a5, 0x0 }, | 819 | { 0x100a5, 0x0 }, |
844 | { 0x100a6, 0x0 }, | 820 | { 0x100a6, 0x0 }, |
845 | { 0x100a7, 0x0 }, | 821 | { 0x100a7, 0x0 }, |
846 | { 0x110a0, 0x0 }, | 822 | { 0x110a0, 0x0 }, |
847 | { 0x110a1, 0x0 }, | 823 | { 0x110a1, 0x0 }, |
848 | { 0x110a2, 0x0 }, | 824 | { 0x110a2, 0x0 }, |
849 | { 0x110a3, 0x0 }, | 825 | { 0x110a3, 0x0 }, |
850 | { 0x110a4, 0x0 }, | 826 | { 0x110a4, 0x0 }, |
851 | { 0x110a5, 0x0 }, | 827 | { 0x110a5, 0x0 }, |
852 | { 0x110a6, 0x0 }, | 828 | { 0x110a6, 0x0 }, |
853 | { 0x110a7, 0x0 }, | 829 | { 0x110a7, 0x0 }, |
854 | { 0x120a0, 0x0 }, | 830 | { 0x120a0, 0x0 }, |
855 | { 0x120a1, 0x0 }, | 831 | { 0x120a1, 0x0 }, |
856 | { 0x120a2, 0x0 }, | 832 | { 0x120a2, 0x0 }, |
857 | { 0x120a3, 0x0 }, | 833 | { 0x120a3, 0x0 }, |
858 | { 0x120a4, 0x0 }, | 834 | { 0x120a4, 0x0 }, |
859 | { 0x120a5, 0x0 }, | 835 | { 0x120a5, 0x0 }, |
860 | { 0x120a6, 0x0 }, | 836 | { 0x120a6, 0x0 }, |
861 | { 0x120a7, 0x0 }, | 837 | { 0x120a7, 0x0 }, |
862 | { 0x130a0, 0x0 }, | 838 | { 0x130a0, 0x0 }, |
863 | { 0x130a1, 0x0 }, | 839 | { 0x130a1, 0x0 }, |
864 | { 0x130a2, 0x0 }, | 840 | { 0x130a2, 0x0 }, |
865 | { 0x130a3, 0x0 }, | 841 | { 0x130a3, 0x0 }, |
866 | { 0x130a4, 0x0 }, | 842 | { 0x130a4, 0x0 }, |
867 | { 0x130a5, 0x0 }, | 843 | { 0x130a5, 0x0 }, |
868 | { 0x130a6, 0x0 }, | 844 | { 0x130a6, 0x0 }, |
869 | { 0x130a7, 0x0 }, | 845 | { 0x130a7, 0x0 }, |
870 | { 0x2007c, 0x0 }, | 846 | { 0x2007c, 0x0 }, |
871 | { 0x12007c, 0x0 }, | 847 | { 0x12007c, 0x0 }, |
872 | { 0x22007c, 0x0 }, | 848 | { 0x22007c, 0x0 }, |
873 | { 0x2007d, 0x0 }, | 849 | { 0x2007d, 0x0 }, |
874 | { 0x12007d, 0x0 }, | 850 | { 0x12007d, 0x0 }, |
875 | { 0x22007d, 0x0 }, | 851 | { 0x22007d, 0x0 }, |
876 | { 0x400fd, 0x0 }, | 852 | { 0x400fd, 0x0 }, |
877 | { 0x400c0, 0x0 }, | 853 | { 0x400c0, 0x0 }, |
878 | { 0x90201, 0x0 }, | 854 | { 0x90201, 0x0 }, |
879 | { 0x190201, 0x0 }, | 855 | { 0x190201, 0x0 }, |
880 | { 0x290201, 0x0 }, | 856 | { 0x290201, 0x0 }, |
881 | { 0x90202, 0x0 }, | 857 | { 0x90202, 0x0 }, |
882 | { 0x190202, 0x0 }, | 858 | { 0x190202, 0x0 }, |
883 | { 0x290202, 0x0 }, | 859 | { 0x290202, 0x0 }, |
884 | { 0x90203, 0x0 }, | 860 | { 0x90203, 0x0 }, |
885 | { 0x190203, 0x0 }, | 861 | { 0x190203, 0x0 }, |
886 | { 0x290203, 0x0 }, | 862 | { 0x290203, 0x0 }, |
887 | { 0x90204, 0x0 }, | 863 | { 0x90204, 0x0 }, |
888 | { 0x190204, 0x0 }, | 864 | { 0x190204, 0x0 }, |
889 | { 0x290204, 0x0 }, | 865 | { 0x290204, 0x0 }, |
890 | { 0x90205, 0x0 }, | 866 | { 0x90205, 0x0 }, |
891 | { 0x190205, 0x0 }, | 867 | { 0x190205, 0x0 }, |
892 | { 0x290205, 0x0 }, | 868 | { 0x290205, 0x0 }, |
893 | { 0x90206, 0x0 }, | 869 | { 0x90206, 0x0 }, |
894 | { 0x190206, 0x0 }, | 870 | { 0x190206, 0x0 }, |
895 | { 0x290206, 0x0 }, | 871 | { 0x290206, 0x0 }, |
896 | { 0x90207, 0x0 }, | 872 | { 0x90207, 0x0 }, |
897 | { 0x190207, 0x0 }, | 873 | { 0x190207, 0x0 }, |
898 | { 0x290207, 0x0 }, | 874 | { 0x290207, 0x0 }, |
899 | { 0x90208, 0x0 }, | 875 | { 0x90208, 0x0 }, |
900 | { 0x190208, 0x0 }, | 876 | { 0x190208, 0x0 }, |
901 | { 0x290208, 0x0 }, | 877 | { 0x290208, 0x0 }, |
902 | { 0x10062, 0x0 }, | 878 | { 0x10062, 0x0 }, |
903 | { 0x10162, 0x0 }, | 879 | { 0x10162, 0x0 }, |
904 | { 0x10262, 0x0 }, | 880 | { 0x10262, 0x0 }, |
905 | { 0x10362, 0x0 }, | 881 | { 0x10362, 0x0 }, |
906 | { 0x10462, 0x0 }, | 882 | { 0x10462, 0x0 }, |
907 | { 0x10562, 0x0 }, | 883 | { 0x10562, 0x0 }, |
908 | { 0x10662, 0x0 }, | 884 | { 0x10662, 0x0 }, |
909 | { 0x10762, 0x0 }, | 885 | { 0x10762, 0x0 }, |
910 | { 0x10862, 0x0 }, | 886 | { 0x10862, 0x0 }, |
911 | { 0x11062, 0x0 }, | 887 | { 0x11062, 0x0 }, |
912 | { 0x11162, 0x0 }, | 888 | { 0x11162, 0x0 }, |
913 | { 0x11262, 0x0 }, | 889 | { 0x11262, 0x0 }, |
914 | { 0x11362, 0x0 }, | 890 | { 0x11362, 0x0 }, |
915 | { 0x11462, 0x0 }, | 891 | { 0x11462, 0x0 }, |
916 | { 0x11562, 0x0 }, | 892 | { 0x11562, 0x0 }, |
917 | { 0x11662, 0x0 }, | 893 | { 0x11662, 0x0 }, |
918 | { 0x11762, 0x0 }, | 894 | { 0x11762, 0x0 }, |
919 | { 0x11862, 0x0 }, | 895 | { 0x11862, 0x0 }, |
920 | { 0x12062, 0x0 }, | 896 | { 0x12062, 0x0 }, |
921 | { 0x12162, 0x0 }, | 897 | { 0x12162, 0x0 }, |
922 | { 0x12262, 0x0 }, | 898 | { 0x12262, 0x0 }, |
923 | { 0x12362, 0x0 }, | 899 | { 0x12362, 0x0 }, |
924 | { 0x12462, 0x0 }, | 900 | { 0x12462, 0x0 }, |
925 | { 0x12562, 0x0 }, | 901 | { 0x12562, 0x0 }, |
926 | { 0x12662, 0x0 }, | 902 | { 0x12662, 0x0 }, |
927 | { 0x12762, 0x0 }, | 903 | { 0x12762, 0x0 }, |
928 | { 0x12862, 0x0 }, | 904 | { 0x12862, 0x0 }, |
929 | { 0x13062, 0x0 }, | 905 | { 0x13062, 0x0 }, |
930 | { 0x13162, 0x0 }, | 906 | { 0x13162, 0x0 }, |
931 | { 0x13262, 0x0 }, | 907 | { 0x13262, 0x0 }, |
932 | { 0x13362, 0x0 }, | 908 | { 0x13362, 0x0 }, |
933 | { 0x13462, 0x0 }, | 909 | { 0x13462, 0x0 }, |
934 | { 0x13562, 0x0 }, | 910 | { 0x13562, 0x0 }, |
935 | { 0x13662, 0x0 }, | 911 | { 0x13662, 0x0 }, |
936 | { 0x13762, 0x0 }, | 912 | { 0x13762, 0x0 }, |
937 | { 0x13862, 0x0 }, | 913 | { 0x13862, 0x0 }, |
938 | { 0x20077, 0x0 }, | 914 | { 0x20077, 0x0 }, |
939 | { 0x10001, 0x0 }, | 915 | { 0x10001, 0x0 }, |
940 | { 0x11001, 0x0 }, | 916 | { 0x11001, 0x0 }, |
941 | { 0x12001, 0x0 }, | 917 | { 0x12001, 0x0 }, |
942 | { 0x13001, 0x0 }, | 918 | { 0x13001, 0x0 }, |
943 | { 0x10040, 0x0 }, | 919 | { 0x10040, 0x0 }, |
944 | { 0x10140, 0x0 }, | 920 | { 0x10140, 0x0 }, |
945 | { 0x10240, 0x0 }, | 921 | { 0x10240, 0x0 }, |
946 | { 0x10340, 0x0 }, | 922 | { 0x10340, 0x0 }, |
947 | { 0x10440, 0x0 }, | 923 | { 0x10440, 0x0 }, |
948 | { 0x10540, 0x0 }, | 924 | { 0x10540, 0x0 }, |
949 | { 0x10640, 0x0 }, | 925 | { 0x10640, 0x0 }, |
950 | { 0x10740, 0x0 }, | 926 | { 0x10740, 0x0 }, |
951 | { 0x10840, 0x0 }, | 927 | { 0x10840, 0x0 }, |
952 | { 0x10030, 0x0 }, | 928 | { 0x10030, 0x0 }, |
953 | { 0x10130, 0x0 }, | 929 | { 0x10130, 0x0 }, |
954 | { 0x10230, 0x0 }, | 930 | { 0x10230, 0x0 }, |
955 | { 0x10330, 0x0 }, | 931 | { 0x10330, 0x0 }, |
956 | { 0x10430, 0x0 }, | 932 | { 0x10430, 0x0 }, |
957 | { 0x10530, 0x0 }, | 933 | { 0x10530, 0x0 }, |
958 | { 0x10630, 0x0 }, | 934 | { 0x10630, 0x0 }, |
959 | { 0x10730, 0x0 }, | 935 | { 0x10730, 0x0 }, |
960 | { 0x10830, 0x0 }, | 936 | { 0x10830, 0x0 }, |
961 | { 0x11040, 0x0 }, | 937 | { 0x11040, 0x0 }, |
962 | { 0x11140, 0x0 }, | 938 | { 0x11140, 0x0 }, |
963 | { 0x11240, 0x0 }, | 939 | { 0x11240, 0x0 }, |
964 | { 0x11340, 0x0 }, | 940 | { 0x11340, 0x0 }, |
965 | { 0x11440, 0x0 }, | 941 | { 0x11440, 0x0 }, |
966 | { 0x11540, 0x0 }, | 942 | { 0x11540, 0x0 }, |
967 | { 0x11640, 0x0 }, | 943 | { 0x11640, 0x0 }, |
968 | { 0x11740, 0x0 }, | 944 | { 0x11740, 0x0 }, |
969 | { 0x11840, 0x0 }, | 945 | { 0x11840, 0x0 }, |
970 | { 0x11030, 0x0 }, | 946 | { 0x11030, 0x0 }, |
971 | { 0x11130, 0x0 }, | 947 | { 0x11130, 0x0 }, |
972 | { 0x11230, 0x0 }, | 948 | { 0x11230, 0x0 }, |
973 | { 0x11330, 0x0 }, | 949 | { 0x11330, 0x0 }, |
974 | { 0x11430, 0x0 }, | 950 | { 0x11430, 0x0 }, |
975 | { 0x11530, 0x0 }, | 951 | { 0x11530, 0x0 }, |
976 | { 0x11630, 0x0 }, | 952 | { 0x11630, 0x0 }, |
977 | { 0x11730, 0x0 }, | 953 | { 0x11730, 0x0 }, |
978 | { 0x11830, 0x0 }, | 954 | { 0x11830, 0x0 }, |
979 | { 0x12040, 0x0 }, | 955 | { 0x12040, 0x0 }, |
980 | { 0x12140, 0x0 }, | 956 | { 0x12140, 0x0 }, |
981 | { 0x12240, 0x0 }, | 957 | { 0x12240, 0x0 }, |
982 | { 0x12340, 0x0 }, | 958 | { 0x12340, 0x0 }, |
983 | { 0x12440, 0x0 }, | 959 | { 0x12440, 0x0 }, |
984 | { 0x12540, 0x0 }, | 960 | { 0x12540, 0x0 }, |
985 | { 0x12640, 0x0 }, | 961 | { 0x12640, 0x0 }, |
986 | { 0x12740, 0x0 }, | 962 | { 0x12740, 0x0 }, |
987 | { 0x12840, 0x0 }, | 963 | { 0x12840, 0x0 }, |
988 | { 0x12030, 0x0 }, | 964 | { 0x12030, 0x0 }, |
989 | { 0x12130, 0x0 }, | 965 | { 0x12130, 0x0 }, |
990 | { 0x12230, 0x0 }, | 966 | { 0x12230, 0x0 }, |
991 | { 0x12330, 0x0 }, | 967 | { 0x12330, 0x0 }, |
992 | { 0x12430, 0x0 }, | 968 | { 0x12430, 0x0 }, |
993 | { 0x12530, 0x0 }, | 969 | { 0x12530, 0x0 }, |
994 | { 0x12630, 0x0 }, | 970 | { 0x12630, 0x0 }, |
995 | { 0x12730, 0x0 }, | 971 | { 0x12730, 0x0 }, |
996 | { 0x12830, 0x0 }, | 972 | { 0x12830, 0x0 }, |
997 | { 0x13040, 0x0 }, | 973 | { 0x13040, 0x0 }, |
998 | { 0x13140, 0x0 }, | 974 | { 0x13140, 0x0 }, |
999 | { 0x13240, 0x0 }, | 975 | { 0x13240, 0x0 }, |
1000 | { 0x13340, 0x0 }, | 976 | { 0x13340, 0x0 }, |
1001 | { 0x13440, 0x0 }, | 977 | { 0x13440, 0x0 }, |
1002 | { 0x13540, 0x0 }, | 978 | { 0x13540, 0x0 }, |
1003 | { 0x13640, 0x0 }, | 979 | { 0x13640, 0x0 }, |
1004 | { 0x13740, 0x0 }, | 980 | { 0x13740, 0x0 }, |
1005 | { 0x13840, 0x0 }, | 981 | { 0x13840, 0x0 }, |
1006 | { 0x13030, 0x0 }, | 982 | { 0x13030, 0x0 }, |
1007 | { 0x13130, 0x0 }, | 983 | { 0x13130, 0x0 }, |
1008 | { 0x13230, 0x0 }, | 984 | { 0x13230, 0x0 }, |
1009 | { 0x13330, 0x0 }, | 985 | { 0x13330, 0x0 }, |
1010 | { 0x13430, 0x0 }, | 986 | { 0x13430, 0x0 }, |
1011 | { 0x13530, 0x0 }, | 987 | { 0x13530, 0x0 }, |
1012 | { 0x13630, 0x0 }, | 988 | { 0x13630, 0x0 }, |
1013 | { 0x13730, 0x0 }, | 989 | { 0x13730, 0x0 }, |
1014 | { 0x13830, 0x0 }, | 990 | { 0x13830, 0x0 }, |
1015 | }; | 991 | }; |
1016 | /* P0 message block paremeter for training firmware */ | 992 | /* P0 message block paremeter for training firmware */ |
1017 | struct dram_cfg_param ddr_fsp0_cfg[] = { | 993 | struct dram_cfg_param ddr_fsp0_cfg[] = { |
1018 | {0xd0000, 0x0}, | 994 | {0xd0000, 0x0}, |
1019 | {0x54003,0xc80}, | 995 | {0x54003,0xc80}, |
1020 | {0x54004,0x2}, | 996 | {0x54004,0x2}, |
1021 | {0x54005,0x2228}, | 997 | {0x54005,0x2228}, |
1022 | {0x54006,0x11}, | 998 | {0x54006,0x11}, |
1023 | {0x54008,0x131f}, | 999 | {0x54008,0x131f}, |
1024 | {0x54009,0xc8}, | 1000 | {0x54009,0xc8}, |
1025 | {0x5400b,0x2}, | 1001 | {0x5400b,0x2}, |
1026 | {0x5400d,0x100}, | 1002 | {0x5400d,0x100}, |
1027 | #ifdef CONFIG_IND | ||
1028 | {0x54012,0x110}, | ||
1029 | #else | ||
1030 | {0x54012,0x310}, | 1003 | {0x54012,0x310}, |
1031 | #endif | ||
1032 | {0x54019,0x2dd4}, | 1004 | {0x54019,0x2dd4}, |
1033 | {0x5401a,0x31}, | 1005 | {0x5401a,0x31}, |
1034 | {0x5401b,0x4a66}, | 1006 | {0x5401b,0x4a66}, |
1035 | {0x5401c,0x4a08}, | 1007 | {0x5401c,0x4a08}, |
1036 | {0x5401e,0x16}, | 1008 | {0x5401e,0x16}, |
1037 | {0x5401f,0x2dd4}, | 1009 | {0x5401f,0x2dd4}, |
1038 | {0x54020,0x31}, | 1010 | {0x54020,0x31}, |
1039 | {0x54021,0x4a66}, | 1011 | {0x54021,0x4a66}, |
1040 | {0x54022,0x4a08}, | 1012 | {0x54022,0x4a08}, |
1041 | {0x54024,0x16}, | 1013 | {0x54024,0x16}, |
1042 | {0x5402b,0x1000}, | 1014 | {0x5402b,0x1000}, |
1043 | #ifdef CONFIG_IND | ||
1044 | {0x5402c,0x1}, | ||
1045 | #else | ||
1046 | {0x5402c,0x3}, | 1015 | {0x5402c,0x3}, |
1047 | #endif | ||
1048 | {0x54032,0xd400}, | 1016 | {0x54032,0xd400}, |
1049 | {0x54033,0x312d}, | 1017 | {0x54033,0x312d}, |
1050 | {0x54034,0x6600}, | 1018 | {0x54034,0x6600}, |
1051 | {0x54035,0x84a}, | 1019 | {0x54035,0x84a}, |
1052 | {0x54036,0x4a}, | 1020 | {0x54036,0x4a}, |
1053 | {0x54037,0x1600}, | 1021 | {0x54037,0x1600}, |
1054 | {0x54038,0xd400}, | 1022 | {0x54038,0xd400}, |
1055 | {0x54039,0x312d}, | 1023 | {0x54039,0x312d}, |
1056 | {0x5403a,0x6600}, | 1024 | {0x5403a,0x6600}, |
1057 | {0x5403b,0x84a}, | 1025 | {0x5403b,0x84a}, |
1058 | {0x5403c,0x4a}, | 1026 | {0x5403c,0x4a}, |
1059 | {0x5403d,0x1600}, | 1027 | {0x5403d,0x1600}, |
1060 | {0xd0000, 0x1}, | 1028 | {0xd0000, 0x1}, |
1061 | }; | 1029 | }; |
1062 | 1030 | ||
1063 | 1031 | ||
1064 | /* P1 message block paremeter for training firmware */ | 1032 | /* P1 message block paremeter for training firmware */ |
1065 | struct dram_cfg_param ddr_fsp1_cfg[] = { | 1033 | struct dram_cfg_param ddr_fsp1_cfg[] = { |
1066 | {0xd0000, 0x0}, | 1034 | {0xd0000, 0x0}, |
1067 | {0x54002,0x1}, | 1035 | {0x54002,0x1}, |
1068 | {0x54003,0x29c}, | 1036 | {0x54003,0x29c}, |
1069 | {0x54004,0x2}, | 1037 | {0x54004,0x2}, |
1070 | {0x54005,0x2228}, | 1038 | {0x54005,0x2228}, |
1071 | {0x54006,0x11}, | 1039 | {0x54006,0x11}, |
1072 | {0x54008,0x121f}, | 1040 | {0x54008,0x121f}, |
1073 | {0x54009,0xc8}, | 1041 | {0x54009,0xc8}, |
1074 | {0x5400b,0x2}, | 1042 | {0x5400b,0x2}, |
1075 | {0x5400d,0x100}, | 1043 | {0x5400d,0x100}, |
1076 | #ifdef CONFIG_IND | ||
1077 | {0x54012,0x110}, | ||
1078 | #else | ||
1079 | {0x54012,0x310}, | 1044 | {0x54012,0x310}, |
1080 | #endif | ||
1081 | {0x54019,0x994}, | 1045 | {0x54019,0x994}, |
1082 | {0x5401a,0x31}, | 1046 | {0x5401a,0x31}, |
1083 | {0x5401b,0x4a66}, | 1047 | {0x5401b,0x4a66}, |
1084 | {0x5401c,0x4a08}, | 1048 | {0x5401c,0x4a08}, |
1085 | {0x5401e,0x16}, | 1049 | {0x5401e,0x16}, |
1086 | {0x5401f,0x994}, | 1050 | {0x5401f,0x994}, |
1087 | {0x54020,0x31}, | 1051 | {0x54020,0x31}, |
1088 | {0x54021,0x4a66}, | 1052 | {0x54021,0x4a66}, |
1089 | {0x54022,0x4a08}, | 1053 | {0x54022,0x4a08}, |
1090 | {0x54024,0x16}, | 1054 | {0x54024,0x16}, |
1091 | {0x5402b,0x1000}, | 1055 | {0x5402b,0x1000}, |
1092 | #ifdef CONFIG_IND | ||
1093 | {0x5402c,0x1}, | ||
1094 | #else | ||
1095 | {0x5402c,0x3}, | 1056 | {0x5402c,0x3}, |
1096 | #endif | ||
1097 | {0x54032,0x9400}, | 1057 | {0x54032,0x9400}, |
1098 | {0x54033,0x3109}, | 1058 | {0x54033,0x3109}, |
1099 | {0x54034,0x6600}, | 1059 | {0x54034,0x6600}, |
1100 | {0x54035,0x84a}, | 1060 | {0x54035,0x84a}, |
1101 | {0x54036,0x4a}, | 1061 | {0x54036,0x4a}, |
1102 | {0x54037,0x1600}, | 1062 | {0x54037,0x1600}, |
1103 | {0x54038,0x9400}, | 1063 | {0x54038,0x9400}, |
1104 | {0x54039,0x3109}, | 1064 | {0x54039,0x3109}, |
1105 | {0x5403a,0x6600}, | 1065 | {0x5403a,0x6600}, |
1106 | {0x5403b,0x84a}, | 1066 | {0x5403b,0x84a}, |
1107 | {0x5403c,0x4a}, | 1067 | {0x5403c,0x4a}, |
1108 | {0x5403d,0x1600}, | 1068 | {0x5403d,0x1600}, |
1109 | {0xd0000, 0x1}, | 1069 | {0xd0000, 0x1}, |
1110 | }; | 1070 | }; |
1111 | 1071 | ||
1112 | 1072 | ||
1113 | /* P0 2D message block paremeter for training firmware */ | 1073 | /* P0 2D message block paremeter for training firmware */ |
1114 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | 1074 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { |
1115 | {0xd0000, 0x0}, | 1075 | {0xd0000, 0x0}, |
1116 | {0x54003,0xc80}, | 1076 | {0x54003,0xc80}, |
1117 | {0x54004,0x2}, | 1077 | {0x54004,0x2}, |
1118 | {0x54005,0x2228}, | 1078 | {0x54005,0x2228}, |
1119 | {0x54006,0x11}, | 1079 | {0x54006,0x11}, |
1120 | {0x54008,0x61}, | 1080 | {0x54008,0x61}, |
1121 | {0x54009,0xc8}, | 1081 | {0x54009,0xc8}, |
1122 | {0x5400b,0x2}, | 1082 | {0x5400b,0x2}, |
1123 | {0x5400f,0x100}, | 1083 | {0x5400f,0x100}, |
1124 | {0x54010,0x1f7f}, | 1084 | {0x54010,0x1f7f}, |
1125 | #ifdef CONFIG_IND | ||
1126 | {0x54012,0x110}, | ||
1127 | #else | ||
1128 | {0x54012,0x310}, | 1085 | {0x54012,0x310}, |
1129 | #endif | ||
1130 | {0x54019,0x2dd4}, | 1086 | {0x54019,0x2dd4}, |
1131 | {0x5401a,0x31}, | 1087 | {0x5401a,0x31}, |
1132 | {0x5401b,0x4a66}, | 1088 | {0x5401b,0x4a66}, |
1133 | {0x5401c,0x4a08}, | 1089 | {0x5401c,0x4a08}, |
1134 | {0x5401e,0x16}, | 1090 | {0x5401e,0x16}, |
1135 | {0x5401f,0x2dd4}, | 1091 | {0x5401f,0x2dd4}, |
1136 | {0x54020,0x31}, | 1092 | {0x54020,0x31}, |
1137 | {0x54021,0x4a66}, | 1093 | {0x54021,0x4a66}, |
1138 | {0x54022,0x4a08}, | 1094 | {0x54022,0x4a08}, |
1139 | {0x54024,0x16}, | 1095 | {0x54024,0x16}, |
1140 | {0x5402b,0x1000}, | 1096 | {0x5402b,0x1000}, |
1141 | #ifdef CONFIG_IND | ||
1142 | {0x5402c,0x1}, | ||
1143 | #else | ||
1144 | {0x5402c,0x3}, | 1097 | {0x5402c,0x3}, |
1145 | #endif | ||
1146 | {0x54032,0xd400}, | 1098 | {0x54032,0xd400}, |
1147 | {0x54033,0x312d}, | 1099 | {0x54033,0x312d}, |
1148 | {0x54034,0x6600}, | 1100 | {0x54034,0x6600}, |
1149 | {0x54035,0x84a}, | 1101 | {0x54035,0x84a}, |
1150 | {0x54036,0x4a}, | 1102 | {0x54036,0x4a}, |
1151 | {0x54037,0x1600}, | 1103 | {0x54037,0x1600}, |
1152 | {0x54038,0xd400}, | 1104 | {0x54038,0xd400}, |
1153 | {0x54039,0x312d}, | 1105 | {0x54039,0x312d}, |
1154 | {0x5403a,0x6600}, | 1106 | {0x5403a,0x6600}, |
1155 | {0x5403b,0x84a}, | 1107 | {0x5403b,0x84a}, |
1156 | {0x5403c,0x4a}, | 1108 | {0x5403c,0x4a}, |
1157 | {0x5403d,0x1600}, | 1109 | {0x5403d,0x1600}, |
1158 | { 0xd0000, 0x1 }, | 1110 | { 0xd0000, 0x1 }, |
1159 | }; | 1111 | }; |
1160 | 1112 | ||
1161 | /* DRAM PHY init engine image */ | 1113 | /* DRAM PHY init engine image */ |
1162 | struct dram_cfg_param ddr_phy_pie[] = { | 1114 | struct dram_cfg_param ddr_phy_pie[] = { |
1163 | {0xd0000, 0x0}, | 1115 | {0xd0000, 0x0}, |
1164 | {0x90000,0x10}, | 1116 | {0x90000,0x10}, |
1165 | {0x90001,0x400}, | 1117 | {0x90001,0x400}, |
1166 | {0x90002,0x10e}, | 1118 | {0x90002,0x10e}, |
1167 | {0x90003,0x0}, | 1119 | {0x90003,0x0}, |
1168 | {0x90004,0x0}, | 1120 | {0x90004,0x0}, |
1169 | {0x90005,0x8}, | 1121 | {0x90005,0x8}, |
1170 | {0x90029,0xb}, | 1122 | {0x90029,0xb}, |
1171 | {0x9002a,0x480}, | 1123 | {0x9002a,0x480}, |
1172 | {0x9002b,0x109}, | 1124 | {0x9002b,0x109}, |
1173 | {0x9002c,0x8}, | 1125 | {0x9002c,0x8}, |
1174 | {0x9002d,0x448}, | 1126 | {0x9002d,0x448}, |
1175 | {0x9002e,0x139}, | 1127 | {0x9002e,0x139}, |
1176 | {0x9002f,0x8}, | 1128 | {0x9002f,0x8}, |
1177 | {0x90030,0x478}, | 1129 | {0x90030,0x478}, |
1178 | {0x90031,0x109}, | 1130 | {0x90031,0x109}, |
1179 | {0x90032,0x0}, | 1131 | {0x90032,0x0}, |
1180 | {0x90033,0xe8}, | 1132 | {0x90033,0xe8}, |
1181 | {0x90034,0x109}, | 1133 | {0x90034,0x109}, |
1182 | {0x90035,0x2}, | 1134 | {0x90035,0x2}, |
1183 | {0x90036,0x10}, | 1135 | {0x90036,0x10}, |
1184 | {0x90037,0x139}, | 1136 | {0x90037,0x139}, |
1185 | {0x90038,0xf}, | 1137 | {0x90038,0xf}, |
1186 | {0x90039,0x7c0}, | 1138 | {0x90039,0x7c0}, |
1187 | {0x9003a,0x139}, | 1139 | {0x9003a,0x139}, |
1188 | {0x9003b,0x44}, | 1140 | {0x9003b,0x44}, |
1189 | {0x9003c,0x630}, | 1141 | {0x9003c,0x630}, |
1190 | {0x9003d,0x159}, | 1142 | {0x9003d,0x159}, |
1191 | {0x9003e,0x14f}, | 1143 | {0x9003e,0x14f}, |
1192 | {0x9003f,0x630}, | 1144 | {0x9003f,0x630}, |
1193 | {0x90040,0x159}, | 1145 | {0x90040,0x159}, |
1194 | {0x90041,0x47}, | 1146 | {0x90041,0x47}, |
1195 | {0x90042,0x630}, | 1147 | {0x90042,0x630}, |
1196 | {0x90043,0x149}, | 1148 | {0x90043,0x149}, |
1197 | {0x90044,0x4f}, | 1149 | {0x90044,0x4f}, |
1198 | {0x90045,0x630}, | 1150 | {0x90045,0x630}, |
1199 | {0x90046,0x179}, | 1151 | {0x90046,0x179}, |
1200 | {0x90047,0x8}, | 1152 | {0x90047,0x8}, |
1201 | {0x90048,0xe0}, | 1153 | {0x90048,0xe0}, |
1202 | {0x90049,0x109}, | 1154 | {0x90049,0x109}, |
1203 | {0x9004a,0x0}, | 1155 | {0x9004a,0x0}, |
1204 | {0x9004b,0x7c8}, | 1156 | {0x9004b,0x7c8}, |
1205 | {0x9004c,0x109}, | 1157 | {0x9004c,0x109}, |
1206 | {0x9004d,0x0}, | 1158 | {0x9004d,0x0}, |
1207 | {0x9004e,0x1}, | 1159 | {0x9004e,0x1}, |
1208 | {0x9004f,0x8}, | 1160 | {0x9004f,0x8}, |
1209 | {0x90050,0x0}, | 1161 | {0x90050,0x0}, |
1210 | {0x90051,0x45a}, | 1162 | {0x90051,0x45a}, |
1211 | {0x90052,0x9}, | 1163 | {0x90052,0x9}, |
1212 | {0x90053,0x0}, | 1164 | {0x90053,0x0}, |
1213 | {0x90054,0x448}, | 1165 | {0x90054,0x448}, |
1214 | {0x90055,0x109}, | 1166 | {0x90055,0x109}, |
1215 | {0x90056,0x40}, | 1167 | {0x90056,0x40}, |
1216 | {0x90057,0x630}, | 1168 | {0x90057,0x630}, |
1217 | {0x90058,0x179}, | 1169 | {0x90058,0x179}, |
1218 | {0x90059,0x1}, | 1170 | {0x90059,0x1}, |
1219 | {0x9005a,0x618}, | 1171 | {0x9005a,0x618}, |
1220 | {0x9005b,0x109}, | 1172 | {0x9005b,0x109}, |
1221 | {0x9005c,0x40c0}, | 1173 | {0x9005c,0x40c0}, |
1222 | {0x9005d,0x630}, | 1174 | {0x9005d,0x630}, |
1223 | {0x9005e,0x149}, | 1175 | {0x9005e,0x149}, |
1224 | {0x9005f,0x8}, | 1176 | {0x9005f,0x8}, |
1225 | {0x90060,0x4}, | 1177 | {0x90060,0x4}, |
1226 | {0x90061,0x48}, | 1178 | {0x90061,0x48}, |
1227 | {0x90062,0x4040}, | 1179 | {0x90062,0x4040}, |
1228 | {0x90063,0x630}, | 1180 | {0x90063,0x630}, |
1229 | {0x90064,0x149}, | 1181 | {0x90064,0x149}, |
1230 | {0x90065,0x0}, | 1182 | {0x90065,0x0}, |
1231 | {0x90066,0x4}, | 1183 | {0x90066,0x4}, |
1232 | {0x90067,0x48}, | 1184 | {0x90067,0x48}, |
1233 | {0x90068,0x40}, | 1185 | {0x90068,0x40}, |
1234 | {0x90069,0x630}, | 1186 | {0x90069,0x630}, |
1235 | {0x9006a,0x149}, | 1187 | {0x9006a,0x149}, |
1236 | {0x9006b,0x10}, | 1188 | {0x9006b,0x10}, |
1237 | {0x9006c,0x4}, | 1189 | {0x9006c,0x4}, |
1238 | {0x9006d,0x18}, | 1190 | {0x9006d,0x18}, |
1239 | {0x9006e,0x0}, | 1191 | {0x9006e,0x0}, |
1240 | {0x9006f,0x4}, | 1192 | {0x9006f,0x4}, |
1241 | {0x90070,0x78}, | 1193 | {0x90070,0x78}, |
1242 | {0x90071,0x549}, | 1194 | {0x90071,0x549}, |
1243 | {0x90072,0x630}, | 1195 | {0x90072,0x630}, |
1244 | {0x90073,0x159}, | 1196 | {0x90073,0x159}, |
1245 | {0x90074,0xd49}, | 1197 | {0x90074,0xd49}, |
1246 | {0x90075,0x630}, | 1198 | {0x90075,0x630}, |
1247 | {0x90076,0x159}, | 1199 | {0x90076,0x159}, |
1248 | {0x90077,0x94a}, | 1200 | {0x90077,0x94a}, |
1249 | {0x90078,0x630}, | 1201 | {0x90078,0x630}, |
1250 | {0x90079,0x159}, | 1202 | {0x90079,0x159}, |
1251 | {0x9007a,0x441}, | 1203 | {0x9007a,0x441}, |
1252 | {0x9007b,0x630}, | 1204 | {0x9007b,0x630}, |
1253 | {0x9007c,0x149}, | 1205 | {0x9007c,0x149}, |
1254 | {0x9007d,0x42}, | 1206 | {0x9007d,0x42}, |
1255 | {0x9007e,0x630}, | 1207 | {0x9007e,0x630}, |
1256 | {0x9007f,0x149}, | 1208 | {0x9007f,0x149}, |
1257 | {0x90080,0x1}, | 1209 | {0x90080,0x1}, |
1258 | {0x90081,0x630}, | 1210 | {0x90081,0x630}, |
1259 | {0x90082,0x149}, | 1211 | {0x90082,0x149}, |
1260 | {0x90083,0x0}, | 1212 | {0x90083,0x0}, |
1261 | {0x90084,0xe0}, | 1213 | {0x90084,0xe0}, |
1262 | {0x90085,0x109}, | 1214 | {0x90085,0x109}, |
1263 | {0x90086,0xa}, | 1215 | {0x90086,0xa}, |
1264 | {0x90087,0x10}, | 1216 | {0x90087,0x10}, |
1265 | {0x90088,0x109}, | 1217 | {0x90088,0x109}, |
1266 | {0x90089,0x9}, | 1218 | {0x90089,0x9}, |
1267 | {0x9008a,0x3c0}, | 1219 | {0x9008a,0x3c0}, |
1268 | {0x9008b,0x149}, | 1220 | {0x9008b,0x149}, |
1269 | {0x9008c,0x9}, | 1221 | {0x9008c,0x9}, |
1270 | {0x9008d,0x3c0}, | 1222 | {0x9008d,0x3c0}, |
1271 | {0x9008e,0x159}, | 1223 | {0x9008e,0x159}, |
1272 | {0x9008f,0x18}, | 1224 | {0x9008f,0x18}, |
1273 | {0x90090,0x10}, | 1225 | {0x90090,0x10}, |
1274 | {0x90091,0x109}, | 1226 | {0x90091,0x109}, |
1275 | {0x90092,0x0}, | 1227 | {0x90092,0x0}, |
1276 | {0x90093,0x3c0}, | 1228 | {0x90093,0x3c0}, |
1277 | {0x90094,0x109}, | 1229 | {0x90094,0x109}, |
1278 | {0x90095,0x18}, | 1230 | {0x90095,0x18}, |
1279 | {0x90096,0x4}, | 1231 | {0x90096,0x4}, |
1280 | {0x90097,0x48}, | 1232 | {0x90097,0x48}, |
1281 | {0x90098,0x18}, | 1233 | {0x90098,0x18}, |
1282 | {0x90099,0x4}, | 1234 | {0x90099,0x4}, |
1283 | {0x9009a,0x58}, | 1235 | {0x9009a,0x58}, |
1284 | {0x9009b,0xa}, | 1236 | {0x9009b,0xa}, |
1285 | {0x9009c,0x10}, | 1237 | {0x9009c,0x10}, |
1286 | {0x9009d,0x109}, | 1238 | {0x9009d,0x109}, |
1287 | {0x9009e,0x2}, | 1239 | {0x9009e,0x2}, |
1288 | {0x9009f,0x10}, | 1240 | {0x9009f,0x10}, |
1289 | {0x900a0,0x109}, | 1241 | {0x900a0,0x109}, |
1290 | {0x900a1,0x5}, | 1242 | {0x900a1,0x5}, |
1291 | {0x900a2,0x7c0}, | 1243 | {0x900a2,0x7c0}, |
1292 | {0x900a3,0x109}, | 1244 | {0x900a3,0x109}, |
1293 | {0x900a4,0x10}, | 1245 | {0x900a4,0x10}, |
1294 | {0x900a5,0x10}, | 1246 | {0x900a5,0x10}, |
1295 | {0x900a6,0x109}, | 1247 | {0x900a6,0x109}, |
1296 | {0x40000,0x811}, | 1248 | {0x40000,0x811}, |
1297 | {0x40020,0x880}, | 1249 | {0x40020,0x880}, |
1298 | {0x40040,0x0}, | 1250 | {0x40040,0x0}, |
1299 | {0x40060,0x0}, | 1251 | {0x40060,0x0}, |
1300 | {0x40001,0x4008}, | 1252 | {0x40001,0x4008}, |
1301 | {0x40021,0x83}, | 1253 | {0x40021,0x83}, |
1302 | {0x40041,0x4f}, | 1254 | {0x40041,0x4f}, |
1303 | {0x40061,0x0}, | 1255 | {0x40061,0x0}, |
1304 | {0x40002,0x4040}, | 1256 | {0x40002,0x4040}, |
1305 | {0x40022,0x83}, | 1257 | {0x40022,0x83}, |
1306 | {0x40042,0x51}, | 1258 | {0x40042,0x51}, |
1307 | {0x40062,0x0}, | 1259 | {0x40062,0x0}, |
1308 | {0x40003,0x811}, | 1260 | {0x40003,0x811}, |
1309 | {0x40023,0x880}, | 1261 | {0x40023,0x880}, |
1310 | {0x40043,0x0}, | 1262 | {0x40043,0x0}, |
1311 | {0x40063,0x0}, | 1263 | {0x40063,0x0}, |
1312 | {0x40004,0x720}, | 1264 | {0x40004,0x720}, |
1313 | {0x40024,0xf}, | 1265 | {0x40024,0xf}, |
1314 | {0x40044,0x1740}, | 1266 | {0x40044,0x1740}, |
1315 | {0x40064,0x0}, | 1267 | {0x40064,0x0}, |
1316 | {0x40005,0x16}, | 1268 | {0x40005,0x16}, |
1317 | {0x40025,0x83}, | 1269 | {0x40025,0x83}, |
1318 | {0x40045,0x4b}, | 1270 | {0x40045,0x4b}, |
1319 | {0x40065,0x0}, | 1271 | {0x40065,0x0}, |
1320 | {0x40006,0x716}, | 1272 | {0x40006,0x716}, |
1321 | {0x40026,0xf}, | 1273 | {0x40026,0xf}, |
1322 | {0x40046,0x2001}, | 1274 | {0x40046,0x2001}, |
1323 | {0x40066,0x0}, | 1275 | {0x40066,0x0}, |
1324 | {0x40007,0x716}, | 1276 | {0x40007,0x716}, |
1325 | {0x40027,0xf}, | 1277 | {0x40027,0xf}, |
1326 | {0x40047,0x2800}, | 1278 | {0x40047,0x2800}, |
1327 | {0x40067,0x0}, | 1279 | {0x40067,0x0}, |
1328 | {0x40008,0x716}, | 1280 | {0x40008,0x716}, |
1329 | {0x40028,0xf}, | 1281 | {0x40028,0xf}, |
1330 | {0x40048,0xf00}, | 1282 | {0x40048,0xf00}, |
1331 | {0x40068,0x0}, | 1283 | {0x40068,0x0}, |
1332 | {0x40009,0x720}, | 1284 | {0x40009,0x720}, |
1333 | {0x40029,0xf}, | 1285 | {0x40029,0xf}, |
1334 | {0x40049,0x1400}, | 1286 | {0x40049,0x1400}, |
1335 | {0x40069,0x0}, | 1287 | {0x40069,0x0}, |
1336 | {0x4000a,0xe08}, | 1288 | {0x4000a,0xe08}, |
1337 | {0x4002a,0xc15}, | 1289 | {0x4002a,0xc15}, |
1338 | {0x4004a,0x0}, | 1290 | {0x4004a,0x0}, |
1339 | {0x4006a,0x0}, | 1291 | {0x4006a,0x0}, |
1340 | {0x4000b,0x623}, | 1292 | {0x4000b,0x623}, |
1341 | {0x4002b,0x15}, | 1293 | {0x4002b,0x15}, |
1342 | {0x4004b,0x0}, | 1294 | {0x4004b,0x0}, |
1343 | {0x4006b,0x0}, | 1295 | {0x4006b,0x0}, |
1344 | {0x4000c,0x4028}, | 1296 | {0x4000c,0x4028}, |
1345 | {0x4002c,0x80}, | 1297 | {0x4002c,0x80}, |
1346 | {0x4004c,0x0}, | 1298 | {0x4004c,0x0}, |
1347 | {0x4006c,0x0}, | 1299 | {0x4006c,0x0}, |
1348 | {0x4000d,0xe08}, | 1300 | {0x4000d,0xe08}, |
1349 | {0x4002d,0xc1a}, | 1301 | {0x4002d,0xc1a}, |
1350 | {0x4004d,0x0}, | 1302 | {0x4004d,0x0}, |
1351 | {0x4006d,0x0}, | 1303 | {0x4006d,0x0}, |
1352 | {0x4000e,0x623}, | 1304 | {0x4000e,0x623}, |
1353 | {0x4002e,0x1a}, | 1305 | {0x4002e,0x1a}, |
1354 | {0x4004e,0x0}, | 1306 | {0x4004e,0x0}, |
1355 | {0x4006e,0x0}, | 1307 | {0x4006e,0x0}, |
1356 | {0x4000f,0x4040}, | 1308 | {0x4000f,0x4040}, |
1357 | {0x4002f,0x80}, | 1309 | {0x4002f,0x80}, |
1358 | {0x4004f,0x0}, | 1310 | {0x4004f,0x0}, |
1359 | {0x4006f,0x0}, | 1311 | {0x4006f,0x0}, |
1360 | {0x40010,0x2604}, | 1312 | {0x40010,0x2604}, |
1361 | {0x40030,0x15}, | 1313 | {0x40030,0x15}, |
1362 | {0x40050,0x0}, | 1314 | {0x40050,0x0}, |
1363 | {0x40070,0x0}, | 1315 | {0x40070,0x0}, |
1364 | {0x40011,0x708}, | 1316 | {0x40011,0x708}, |
1365 | {0x40031,0x5}, | 1317 | {0x40031,0x5}, |
1366 | {0x40051,0x0}, | 1318 | {0x40051,0x0}, |
1367 | {0x40071,0x2002}, | 1319 | {0x40071,0x2002}, |
1368 | {0x40012,0x8}, | 1320 | {0x40012,0x8}, |
1369 | {0x40032,0x80}, | 1321 | {0x40032,0x80}, |
1370 | {0x40052,0x0}, | 1322 | {0x40052,0x0}, |
1371 | {0x40072,0x0}, | 1323 | {0x40072,0x0}, |
1372 | {0x40013,0x2604}, | 1324 | {0x40013,0x2604}, |
1373 | {0x40033,0x1a}, | 1325 | {0x40033,0x1a}, |
1374 | {0x40053,0x0}, | 1326 | {0x40053,0x0}, |
1375 | {0x40073,0x0}, | 1327 | {0x40073,0x0}, |
1376 | {0x40014,0x708}, | 1328 | {0x40014,0x708}, |
1377 | {0x40034,0xa}, | 1329 | {0x40034,0xa}, |
1378 | {0x40054,0x0}, | 1330 | {0x40054,0x0}, |
1379 | {0x40074,0x2002}, | 1331 | {0x40074,0x2002}, |
1380 | {0x40015,0x4040}, | 1332 | {0x40015,0x4040}, |
1381 | {0x40035,0x80}, | 1333 | {0x40035,0x80}, |
1382 | {0x40055,0x0}, | 1334 | {0x40055,0x0}, |
1383 | {0x40075,0x0}, | 1335 | {0x40075,0x0}, |
1384 | {0x40016,0x60a}, | 1336 | {0x40016,0x60a}, |
1385 | {0x40036,0x15}, | 1337 | {0x40036,0x15}, |
1386 | {0x40056,0x1200}, | 1338 | {0x40056,0x1200}, |
1387 | {0x40076,0x0}, | 1339 | {0x40076,0x0}, |
1388 | {0x40017,0x61a}, | 1340 | {0x40017,0x61a}, |
1389 | {0x40037,0x15}, | 1341 | {0x40037,0x15}, |
1390 | {0x40057,0x1300}, | 1342 | {0x40057,0x1300}, |
1391 | {0x40077,0x0}, | 1343 | {0x40077,0x0}, |
1392 | {0x40018,0x60a}, | 1344 | {0x40018,0x60a}, |
1393 | {0x40038,0x1a}, | 1345 | {0x40038,0x1a}, |
1394 | {0x40058,0x1200}, | 1346 | {0x40058,0x1200}, |
1395 | {0x40078,0x0}, | 1347 | {0x40078,0x0}, |
1396 | {0x40019,0x642}, | 1348 | {0x40019,0x642}, |
1397 | {0x40039,0x1a}, | 1349 | {0x40039,0x1a}, |
1398 | {0x40059,0x1300}, | 1350 | {0x40059,0x1300}, |
1399 | {0x40079,0x0}, | 1351 | {0x40079,0x0}, |
1400 | {0x4001a,0x4808}, | 1352 | {0x4001a,0x4808}, |
1401 | {0x4003a,0x880}, | 1353 | {0x4003a,0x880}, |
1402 | {0x4005a,0x0}, | 1354 | {0x4005a,0x0}, |
1403 | {0x4007a,0x0}, | 1355 | {0x4007a,0x0}, |
1404 | {0x900a7,0x0}, | 1356 | {0x900a7,0x0}, |
1405 | {0x900a8,0x790}, | 1357 | {0x900a8,0x790}, |
1406 | {0x900a9,0x11a}, | 1358 | {0x900a9,0x11a}, |
1407 | {0x900aa,0x8}, | 1359 | {0x900aa,0x8}, |
1408 | {0x900ab,0x7aa}, | 1360 | {0x900ab,0x7aa}, |
1409 | {0x900ac,0x2a}, | 1361 | {0x900ac,0x2a}, |
1410 | {0x900ad,0x10}, | 1362 | {0x900ad,0x10}, |
1411 | {0x900ae,0x7b2}, | 1363 | {0x900ae,0x7b2}, |
1412 | {0x900af,0x2a}, | 1364 | {0x900af,0x2a}, |
1413 | {0x900b0,0x0}, | 1365 | {0x900b0,0x0}, |
1414 | {0x900b1,0x7c8}, | 1366 | {0x900b1,0x7c8}, |
1415 | {0x900b2,0x109}, | 1367 | {0x900b2,0x109}, |
1416 | {0x900b3,0x10}, | 1368 | {0x900b3,0x10}, |
1417 | {0x900b4,0x2a8}, | 1369 | {0x900b4,0x2a8}, |
1418 | {0x900b5,0x129}, | 1370 | {0x900b5,0x129}, |
1419 | {0x900b6,0x8}, | 1371 | {0x900b6,0x8}, |
1420 | {0x900b7,0x370}, | 1372 | {0x900b7,0x370}, |
1421 | {0x900b8,0x129}, | 1373 | {0x900b8,0x129}, |
1422 | {0x900b9,0xa}, | 1374 | {0x900b9,0xa}, |
1423 | {0x900ba,0x3c8}, | 1375 | {0x900ba,0x3c8}, |
1424 | {0x900bb,0x1a9}, | 1376 | {0x900bb,0x1a9}, |
1425 | {0x900bc,0xc}, | 1377 | {0x900bc,0xc}, |
1426 | {0x900bd,0x408}, | 1378 | {0x900bd,0x408}, |
1427 | {0x900be,0x199}, | 1379 | {0x900be,0x199}, |
1428 | {0x900bf,0x14}, | 1380 | {0x900bf,0x14}, |
1429 | {0x900c0,0x790}, | 1381 | {0x900c0,0x790}, |
1430 | {0x900c1,0x11a}, | 1382 | {0x900c1,0x11a}, |
1431 | {0x900c2,0x8}, | 1383 | {0x900c2,0x8}, |
1432 | {0x900c3,0x4}, | 1384 | {0x900c3,0x4}, |
1433 | {0x900c4,0x18}, | 1385 | {0x900c4,0x18}, |
1434 | {0x900c5,0xe}, | 1386 | {0x900c5,0xe}, |
1435 | {0x900c6,0x408}, | 1387 | {0x900c6,0x408}, |
1436 | {0x900c7,0x199}, | 1388 | {0x900c7,0x199}, |
1437 | {0x900c8,0x8}, | 1389 | {0x900c8,0x8}, |
1438 | {0x900c9,0x8568}, | 1390 | {0x900c9,0x8568}, |
1439 | {0x900ca,0x108}, | 1391 | {0x900ca,0x108}, |
1440 | {0x900cb,0x18}, | 1392 | {0x900cb,0x18}, |
1441 | {0x900cc,0x790}, | 1393 | {0x900cc,0x790}, |
1442 | {0x900cd,0x16a}, | 1394 | {0x900cd,0x16a}, |
1443 | {0x900ce,0x8}, | 1395 | {0x900ce,0x8}, |
1444 | {0x900cf,0x1d8}, | 1396 | {0x900cf,0x1d8}, |
1445 | {0x900d0,0x169}, | 1397 | {0x900d0,0x169}, |
1446 | {0x900d1,0x10}, | 1398 | {0x900d1,0x10}, |
1447 | {0x900d2,0x8558}, | 1399 | {0x900d2,0x8558}, |
1448 | {0x900d3,0x168}, | 1400 | {0x900d3,0x168}, |
1449 | {0x900d4,0x70}, | 1401 | {0x900d4,0x70}, |
1450 | {0x900d5,0x788}, | 1402 | {0x900d5,0x788}, |
1451 | {0x900d6,0x16a}, | 1403 | {0x900d6,0x16a}, |
1452 | {0x900d7,0x1ff8}, | 1404 | {0x900d7,0x1ff8}, |
1453 | {0x900d8,0x85a8}, | 1405 | {0x900d8,0x85a8}, |
1454 | {0x900d9,0x1e8}, | 1406 | {0x900d9,0x1e8}, |
1455 | {0x900da,0x50}, | 1407 | {0x900da,0x50}, |
1456 | {0x900db,0x798}, | 1408 | {0x900db,0x798}, |
1457 | {0x900dc,0x16a}, | 1409 | {0x900dc,0x16a}, |
1458 | {0x900dd,0x60}, | 1410 | {0x900dd,0x60}, |
1459 | {0x900de,0x7a0}, | 1411 | {0x900de,0x7a0}, |
1460 | {0x900df,0x16a}, | 1412 | {0x900df,0x16a}, |
1461 | {0x900e0,0x8}, | 1413 | {0x900e0,0x8}, |
1462 | {0x900e1,0x8310}, | 1414 | {0x900e1,0x8310}, |
1463 | {0x900e2,0x168}, | 1415 | {0x900e2,0x168}, |
1464 | {0x900e3,0x8}, | 1416 | {0x900e3,0x8}, |
1465 | {0x900e4,0xa310}, | 1417 | {0x900e4,0xa310}, |
1466 | {0x900e5,0x168}, | 1418 | {0x900e5,0x168}, |
1467 | {0x900e6,0xa}, | 1419 | {0x900e6,0xa}, |
1468 | {0x900e7,0x408}, | 1420 | {0x900e7,0x408}, |
1469 | {0x900e8,0x169}, | 1421 | {0x900e8,0x169}, |
1470 | {0x900e9,0x6e}, | 1422 | {0x900e9,0x6e}, |
1471 | {0x900ea,0x0}, | 1423 | {0x900ea,0x0}, |
1472 | {0x900eb,0x68}, | 1424 | {0x900eb,0x68}, |
1473 | {0x900ec,0x0}, | 1425 | {0x900ec,0x0}, |
1474 | {0x900ed,0x408}, | 1426 | {0x900ed,0x408}, |
1475 | {0x900ee,0x169}, | 1427 | {0x900ee,0x169}, |
1476 | {0x900ef,0x0}, | 1428 | {0x900ef,0x0}, |
1477 | {0x900f0,0x8310}, | 1429 | {0x900f0,0x8310}, |
1478 | {0x900f1,0x168}, | 1430 | {0x900f1,0x168}, |
1479 | {0x900f2,0x0}, | 1431 | {0x900f2,0x0}, |
1480 | {0x900f3,0xa310}, | 1432 | {0x900f3,0xa310}, |
1481 | {0x900f4,0x168}, | 1433 | {0x900f4,0x168}, |
1482 | {0x900f5,0x1ff8}, | 1434 | {0x900f5,0x1ff8}, |
1483 | {0x900f6,0x85a8}, | 1435 | {0x900f6,0x85a8}, |
1484 | {0x900f7,0x1e8}, | 1436 | {0x900f7,0x1e8}, |
1485 | {0x900f8,0x68}, | 1437 | {0x900f8,0x68}, |
1486 | {0x900f9,0x798}, | 1438 | {0x900f9,0x798}, |
1487 | {0x900fa,0x16a}, | 1439 | {0x900fa,0x16a}, |
1488 | {0x900fb,0x78}, | 1440 | {0x900fb,0x78}, |
1489 | {0x900fc,0x7a0}, | 1441 | {0x900fc,0x7a0}, |
1490 | {0x900fd,0x16a}, | 1442 | {0x900fd,0x16a}, |
1491 | {0x900fe,0x68}, | 1443 | {0x900fe,0x68}, |
1492 | {0x900ff,0x790}, | 1444 | {0x900ff,0x790}, |
1493 | {0x90100,0x16a}, | 1445 | {0x90100,0x16a}, |
1494 | {0x90101,0x8}, | 1446 | {0x90101,0x8}, |
1495 | {0x90102,0x8b10}, | 1447 | {0x90102,0x8b10}, |
1496 | {0x90103,0x168}, | 1448 | {0x90103,0x168}, |
1497 | {0x90104,0x8}, | 1449 | {0x90104,0x8}, |
1498 | {0x90105,0xab10}, | 1450 | {0x90105,0xab10}, |
1499 | {0x90106,0x168}, | 1451 | {0x90106,0x168}, |
1500 | {0x90107,0xa}, | 1452 | {0x90107,0xa}, |
1501 | {0x90108,0x408}, | 1453 | {0x90108,0x408}, |
1502 | {0x90109,0x169}, | 1454 | {0x90109,0x169}, |
1503 | {0x9010a,0x58}, | 1455 | {0x9010a,0x58}, |
1504 | {0x9010b,0x0}, | 1456 | {0x9010b,0x0}, |
1505 | {0x9010c,0x68}, | 1457 | {0x9010c,0x68}, |
1506 | {0x9010d,0x0}, | 1458 | {0x9010d,0x0}, |
1507 | {0x9010e,0x408}, | 1459 | {0x9010e,0x408}, |
1508 | {0x9010f,0x169}, | 1460 | {0x9010f,0x169}, |
1509 | {0x90110,0x0}, | 1461 | {0x90110,0x0}, |
1510 | {0x90111,0x8b10}, | 1462 | {0x90111,0x8b10}, |
1511 | {0x90112,0x168}, | 1463 | {0x90112,0x168}, |
1512 | {0x90113,0x0}, | 1464 | {0x90113,0x0}, |
1513 | {0x90114,0xab10}, | 1465 | {0x90114,0xab10}, |
1514 | {0x90115,0x168}, | 1466 | {0x90115,0x168}, |
1515 | {0x90116,0x0}, | 1467 | {0x90116,0x0}, |
1516 | {0x90117,0x1d8}, | 1468 | {0x90117,0x1d8}, |
1517 | {0x90118,0x169}, | 1469 | {0x90118,0x169}, |
1518 | {0x90119,0x80}, | 1470 | {0x90119,0x80}, |
1519 | {0x9011a,0x790}, | 1471 | {0x9011a,0x790}, |
1520 | {0x9011b,0x16a}, | 1472 | {0x9011b,0x16a}, |
1521 | {0x9011c,0x18}, | 1473 | {0x9011c,0x18}, |
1522 | {0x9011d,0x7aa}, | 1474 | {0x9011d,0x7aa}, |
1523 | {0x9011e,0x6a}, | 1475 | {0x9011e,0x6a}, |
1524 | {0x9011f,0xa}, | 1476 | {0x9011f,0xa}, |
1525 | {0x90120,0x0}, | 1477 | {0x90120,0x0}, |
1526 | {0x90121,0x1e9}, | 1478 | {0x90121,0x1e9}, |
1527 | {0x90122,0x8}, | 1479 | {0x90122,0x8}, |
1528 | {0x90123,0x8080}, | 1480 | {0x90123,0x8080}, |
1529 | {0x90124,0x108}, | 1481 | {0x90124,0x108}, |
1530 | {0x90125,0xf}, | 1482 | {0x90125,0xf}, |
1531 | {0x90126,0x408}, | 1483 | {0x90126,0x408}, |
1532 | {0x90127,0x169}, | 1484 | {0x90127,0x169}, |
1533 | {0x90128,0xc}, | 1485 | {0x90128,0xc}, |
1534 | {0x90129,0x0}, | 1486 | {0x90129,0x0}, |
1535 | {0x9012a,0x68}, | 1487 | {0x9012a,0x68}, |
1536 | {0x9012b,0x9}, | 1488 | {0x9012b,0x9}, |
1537 | {0x9012c,0x0}, | 1489 | {0x9012c,0x0}, |
1538 | {0x9012d,0x1a9}, | 1490 | {0x9012d,0x1a9}, |
1539 | {0x9012e,0x0}, | 1491 | {0x9012e,0x0}, |
1540 | {0x9012f,0x408}, | 1492 | {0x9012f,0x408}, |
1541 | {0x90130,0x169}, | 1493 | {0x90130,0x169}, |
1542 | {0x90131,0x0}, | 1494 | {0x90131,0x0}, |
1543 | {0x90132,0x8080}, | 1495 | {0x90132,0x8080}, |
1544 | {0x90133,0x108}, | 1496 | {0x90133,0x108}, |
1545 | {0x90134,0x8}, | 1497 | {0x90134,0x8}, |
1546 | {0x90135,0x7aa}, | 1498 | {0x90135,0x7aa}, |
1547 | {0x90136,0x6a}, | 1499 | {0x90136,0x6a}, |
1548 | {0x90137,0x0}, | 1500 | {0x90137,0x0}, |
1549 | {0x90138,0x8568}, | 1501 | {0x90138,0x8568}, |
1550 | {0x90139,0x108}, | 1502 | {0x90139,0x108}, |
1551 | {0x9013a,0xb7}, | 1503 | {0x9013a,0xb7}, |
1552 | {0x9013b,0x790}, | 1504 | {0x9013b,0x790}, |
1553 | {0x9013c,0x16a}, | 1505 | {0x9013c,0x16a}, |
1554 | {0x9013d,0x1f}, | 1506 | {0x9013d,0x1f}, |
1555 | {0x9013e,0x0}, | 1507 | {0x9013e,0x0}, |
1556 | {0x9013f,0x68}, | 1508 | {0x9013f,0x68}, |
1557 | {0x90140,0x8}, | 1509 | {0x90140,0x8}, |
1558 | {0x90141,0x8558}, | 1510 | {0x90141,0x8558}, |
1559 | {0x90142,0x168}, | 1511 | {0x90142,0x168}, |
1560 | {0x90143,0xf}, | 1512 | {0x90143,0xf}, |
1561 | {0x90144,0x408}, | 1513 | {0x90144,0x408}, |
1562 | {0x90145,0x169}, | 1514 | {0x90145,0x169}, |
1563 | {0x90146,0xc}, | 1515 | {0x90146,0xc}, |
1564 | {0x90147,0x0}, | 1516 | {0x90147,0x0}, |
1565 | {0x90148,0x68}, | 1517 | {0x90148,0x68}, |
1566 | {0x90149,0x0}, | 1518 | {0x90149,0x0}, |
1567 | {0x9014a,0x408}, | 1519 | {0x9014a,0x408}, |
1568 | {0x9014b,0x169}, | 1520 | {0x9014b,0x169}, |
1569 | {0x9014c,0x0}, | 1521 | {0x9014c,0x0}, |
1570 | {0x9014d,0x8558}, | 1522 | {0x9014d,0x8558}, |
1571 | {0x9014e,0x168}, | 1523 | {0x9014e,0x168}, |
1572 | {0x9014f,0x8}, | 1524 | {0x9014f,0x8}, |
1573 | {0x90150,0x3c8}, | 1525 | {0x90150,0x3c8}, |
1574 | {0x90151,0x1a9}, | 1526 | {0x90151,0x1a9}, |
1575 | {0x90152,0x3}, | 1527 | {0x90152,0x3}, |
1576 | {0x90153,0x370}, | 1528 | {0x90153,0x370}, |
1577 | {0x90154,0x129}, | 1529 | {0x90154,0x129}, |
1578 | {0x90155,0x20}, | 1530 | {0x90155,0x20}, |
1579 | {0x90156,0x2aa}, | 1531 | {0x90156,0x2aa}, |
1580 | {0x90157,0x9}, | 1532 | {0x90157,0x9}, |
1581 | {0x90158,0x0}, | 1533 | {0x90158,0x0}, |
1582 | {0x90159,0x400}, | 1534 | {0x90159,0x400}, |
1583 | {0x9015a,0x10e}, | 1535 | {0x9015a,0x10e}, |
1584 | {0x9015b,0x8}, | 1536 | {0x9015b,0x8}, |
1585 | {0x9015c,0xe8}, | 1537 | {0x9015c,0xe8}, |
1586 | {0x9015d,0x109}, | 1538 | {0x9015d,0x109}, |
1587 | {0x9015e,0x0}, | 1539 | {0x9015e,0x0}, |
1588 | {0x9015f,0x8140}, | 1540 | {0x9015f,0x8140}, |
1589 | {0x90160,0x10c}, | 1541 | {0x90160,0x10c}, |
1590 | {0x90161,0x10}, | 1542 | {0x90161,0x10}, |
1591 | {0x90162,0x8138}, | 1543 | {0x90162,0x8138}, |
1592 | {0x90163,0x10c}, | 1544 | {0x90163,0x10c}, |
1593 | {0x90164,0x8}, | 1545 | {0x90164,0x8}, |
1594 | {0x90165,0x7c8}, | 1546 | {0x90165,0x7c8}, |
1595 | {0x90166,0x101}, | 1547 | {0x90166,0x101}, |
1596 | {0x90167,0x8}, | 1548 | {0x90167,0x8}, |
1597 | {0x90168,0x0}, | 1549 | {0x90168,0x0}, |
1598 | {0x90169,0x8}, | 1550 | {0x90169,0x8}, |
1599 | {0x9016a,0x8}, | 1551 | {0x9016a,0x8}, |
1600 | {0x9016b,0x448}, | 1552 | {0x9016b,0x448}, |
1601 | {0x9016c,0x109}, | 1553 | {0x9016c,0x109}, |
1602 | {0x9016d,0xf}, | 1554 | {0x9016d,0xf}, |
1603 | {0x9016e,0x7c0}, | 1555 | {0x9016e,0x7c0}, |
1604 | {0x9016f,0x109}, | 1556 | {0x9016f,0x109}, |
1605 | {0x90170,0x0}, | 1557 | {0x90170,0x0}, |
1606 | {0x90171,0xe8}, | 1558 | {0x90171,0xe8}, |
1607 | {0x90172,0x109}, | 1559 | {0x90172,0x109}, |
1608 | {0x90173,0x47}, | 1560 | {0x90173,0x47}, |
1609 | {0x90174,0x630}, | 1561 | {0x90174,0x630}, |
1610 | {0x90175,0x109}, | 1562 | {0x90175,0x109}, |
1611 | {0x90176,0x8}, | 1563 | {0x90176,0x8}, |
1612 | {0x90177,0x618}, | 1564 | {0x90177,0x618}, |
1613 | {0x90178,0x109}, | 1565 | {0x90178,0x109}, |
1614 | {0x90179,0x8}, | 1566 | {0x90179,0x8}, |
1615 | {0x9017a,0xe0}, | 1567 | {0x9017a,0xe0}, |
1616 | {0x9017b,0x109}, | 1568 | {0x9017b,0x109}, |
1617 | {0x9017c,0x0}, | 1569 | {0x9017c,0x0}, |
1618 | {0x9017d,0x7c8}, | 1570 | {0x9017d,0x7c8}, |
1619 | {0x9017e,0x109}, | 1571 | {0x9017e,0x109}, |
1620 | {0x9017f,0x8}, | 1572 | {0x9017f,0x8}, |
1621 | {0x90180,0x8140}, | 1573 | {0x90180,0x8140}, |
1622 | {0x90181,0x10c}, | 1574 | {0x90181,0x10c}, |
1623 | {0x90182,0x0}, | 1575 | {0x90182,0x0}, |
1624 | {0x90183,0x1}, | 1576 | {0x90183,0x1}, |
1625 | {0x90184,0x8}, | 1577 | {0x90184,0x8}, |
1626 | {0x90185,0x8}, | 1578 | {0x90185,0x8}, |
1627 | {0x90186,0x4}, | 1579 | {0x90186,0x4}, |
1628 | {0x90187,0x8}, | 1580 | {0x90187,0x8}, |
1629 | {0x90188,0x8}, | 1581 | {0x90188,0x8}, |
1630 | {0x90189,0x7c8}, | 1582 | {0x90189,0x7c8}, |
1631 | {0x9018a,0x101}, | 1583 | {0x9018a,0x101}, |
1632 | {0x90006,0x0}, | 1584 | {0x90006,0x0}, |
1633 | {0x90007,0x0}, | 1585 | {0x90007,0x0}, |
1634 | {0x90008,0x8}, | 1586 | {0x90008,0x8}, |
1635 | {0x90009,0x0}, | 1587 | {0x90009,0x0}, |
1636 | {0x9000a,0x0}, | 1588 | {0x9000a,0x0}, |
1637 | {0x9000b,0x0}, | 1589 | {0x9000b,0x0}, |
1638 | {0xd00e7,0x400}, | 1590 | {0xd00e7,0x400}, |
1639 | {0x90017,0x0}, | 1591 | {0x90017,0x0}, |
1640 | {0x9001f,0x2a}, | 1592 | {0x9001f,0x2a}, |
1641 | {0x90026,0x6a}, | 1593 | {0x90026,0x6a}, |
1642 | {0x400d0,0x0}, | 1594 | {0x400d0,0x0}, |
1643 | {0x400d1,0x101}, | 1595 | {0x400d1,0x101}, |
1644 | {0x400d2,0x105}, | 1596 | {0x400d2,0x105}, |
1645 | {0x400d3,0x107}, | 1597 | {0x400d3,0x107}, |
1646 | {0x400d4,0x10f}, | 1598 | {0x400d4,0x10f}, |
1647 | {0x400d5,0x202}, | 1599 | {0x400d5,0x202}, |
1648 | {0x400d6,0x20a}, | 1600 | {0x400d6,0x20a}, |
1649 | {0x400d7,0x20b}, | 1601 | {0x400d7,0x20b}, |
1650 | {0x2003a,0x2}, | 1602 | {0x2003a,0x2}, |
1651 | {0x2000b,0x64}, | 1603 | {0x2000b,0x64}, |
1652 | {0x2000c,0xc8}, | 1604 | {0x2000c,0xc8}, |
1653 | {0x2000d,0x7d0}, | 1605 | {0x2000d,0x7d0}, |
1654 | {0x2000e,0x2c}, | 1606 | {0x2000e,0x2c}, |
1655 | {0x12000b,0x14}, | 1607 | {0x12000b,0x14}, |
1656 | {0x12000c,0x29}, | 1608 | {0x12000c,0x29}, |
1657 | {0x12000d,0x1a1}, | 1609 | {0x12000d,0x1a1}, |
1658 | {0x12000e,0x10}, | 1610 | {0x12000e,0x10}, |
1659 | {0x9000c,0x0}, | 1611 | {0x9000c,0x0}, |
1660 | {0x9000d,0x173}, | 1612 | {0x9000d,0x173}, |
1661 | {0x9000e,0x60}, | 1613 | {0x9000e,0x60}, |
1662 | {0x9000f,0x6110}, | 1614 | {0x9000f,0x6110}, |
1663 | {0x90010,0x2152}, | 1615 | {0x90010,0x2152}, |
1664 | {0x90011,0xdfbd}, | 1616 | {0x90011,0xdfbd}, |
1665 | {0x90012,0x60}, | 1617 | {0x90012,0x60}, |
1666 | {0x90013,0x6152}, | 1618 | {0x90013,0x6152}, |
1667 | {0x20010,0x5a}, | 1619 | {0x20010,0x5a}, |
1668 | {0x20011,0x3}, | 1620 | {0x20011,0x3}, |
1669 | {0x120010,0x5a}, | 1621 | {0x120010,0x5a}, |
1670 | {0x120011,0x3}, | 1622 | {0x120011,0x3}, |
1671 | {0x40080,0xe0}, | 1623 | {0x40080,0xe0}, |
1672 | {0x40081,0x12}, | 1624 | {0x40081,0x12}, |
1673 | {0x40082,0xe0}, | 1625 | {0x40082,0xe0}, |
1674 | {0x40083,0x12}, | 1626 | {0x40083,0x12}, |
1675 | {0x40084,0xe0}, | 1627 | {0x40084,0xe0}, |
1676 | {0x40085,0x12}, | 1628 | {0x40085,0x12}, |
1677 | {0x140080,0xe0}, | 1629 | {0x140080,0xe0}, |
1678 | {0x140081,0x12}, | 1630 | {0x140081,0x12}, |
1679 | {0x140082,0xe0}, | 1631 | {0x140082,0xe0}, |
1680 | {0x140083,0x12}, | 1632 | {0x140083,0x12}, |
1681 | {0x140084,0xe0}, | 1633 | {0x140084,0xe0}, |
1682 | {0x140085,0x12}, | 1634 | {0x140085,0x12}, |
1683 | {0x400fd,0xf}, | 1635 | {0x400fd,0xf}, |
1684 | {0x10011,0x1}, | 1636 | {0x10011,0x1}, |
1685 | {0x10012,0x1}, | 1637 | {0x10012,0x1}, |
1686 | {0x10013,0x180}, | 1638 | {0x10013,0x180}, |
1687 | {0x10018,0x1}, | 1639 | {0x10018,0x1}, |
1688 | {0x10002,0x6209}, | 1640 | {0x10002,0x6209}, |
1689 | {0x100b2,0x1}, | 1641 | {0x100b2,0x1}, |
1690 | {0x101b4,0x1}, | 1642 | {0x101b4,0x1}, |
1691 | {0x102b4,0x1}, | 1643 | {0x102b4,0x1}, |
1692 | {0x103b4,0x1}, | 1644 | {0x103b4,0x1}, |
1693 | {0x104b4,0x1}, | 1645 | {0x104b4,0x1}, |
1694 | {0x105b4,0x1}, | 1646 | {0x105b4,0x1}, |
1695 | {0x106b4,0x1}, | 1647 | {0x106b4,0x1}, |
1696 | {0x107b4,0x1}, | 1648 | {0x107b4,0x1}, |
1697 | {0x108b4,0x1}, | 1649 | {0x108b4,0x1}, |
1698 | {0x11011,0x1}, | 1650 | {0x11011,0x1}, |
1699 | {0x11012,0x1}, | 1651 | {0x11012,0x1}, |
1700 | {0x11013,0x180}, | 1652 | {0x11013,0x180}, |
1701 | {0x11018,0x1}, | 1653 | {0x11018,0x1}, |
1702 | {0x11002,0x6209}, | 1654 | {0x11002,0x6209}, |
1703 | {0x110b2,0x1}, | 1655 | {0x110b2,0x1}, |
1704 | {0x111b4,0x1}, | 1656 | {0x111b4,0x1}, |
1705 | {0x112b4,0x1}, | 1657 | {0x112b4,0x1}, |
1706 | {0x113b4,0x1}, | 1658 | {0x113b4,0x1}, |
1707 | {0x114b4,0x1}, | 1659 | {0x114b4,0x1}, |
1708 | {0x115b4,0x1}, | 1660 | {0x115b4,0x1}, |
1709 | {0x116b4,0x1}, | 1661 | {0x116b4,0x1}, |
1710 | {0x117b4,0x1}, | 1662 | {0x117b4,0x1}, |
1711 | {0x118b4,0x1}, | 1663 | {0x118b4,0x1}, |
1712 | {0x12011,0x1}, | 1664 | {0x12011,0x1}, |
1713 | {0x12012,0x1}, | 1665 | {0x12012,0x1}, |
1714 | {0x12013,0x180}, | 1666 | {0x12013,0x180}, |
1715 | {0x12018,0x1}, | 1667 | {0x12018,0x1}, |
1716 | {0x12002,0x6209}, | 1668 | {0x12002,0x6209}, |
1717 | {0x120b2,0x1}, | 1669 | {0x120b2,0x1}, |
1718 | {0x121b4,0x1}, | 1670 | {0x121b4,0x1}, |
1719 | {0x122b4,0x1}, | 1671 | {0x122b4,0x1}, |
1720 | {0x123b4,0x1}, | 1672 | {0x123b4,0x1}, |
1721 | {0x124b4,0x1}, | 1673 | {0x124b4,0x1}, |
1722 | {0x125b4,0x1}, | 1674 | {0x125b4,0x1}, |
1723 | {0x126b4,0x1}, | 1675 | {0x126b4,0x1}, |
1724 | {0x127b4,0x1}, | 1676 | {0x127b4,0x1}, |
1725 | {0x128b4,0x1}, | 1677 | {0x128b4,0x1}, |
1726 | {0x13011,0x1}, | 1678 | {0x13011,0x1}, |
1727 | {0x13012,0x1}, | 1679 | {0x13012,0x1}, |
1728 | {0x13013,0x180}, | 1680 | {0x13013,0x180}, |
1729 | {0x13018,0x1}, | 1681 | {0x13018,0x1}, |
1730 | {0x13002,0x6209}, | 1682 | {0x13002,0x6209}, |
1731 | {0x130b2,0x1}, | 1683 | {0x130b2,0x1}, |
1732 | {0x131b4,0x1}, | 1684 | {0x131b4,0x1}, |
1733 | {0x132b4,0x1}, | 1685 | {0x132b4,0x1}, |
1734 | {0x133b4,0x1}, | 1686 | {0x133b4,0x1}, |
1735 | {0x134b4,0x1}, | 1687 | {0x134b4,0x1}, |
1736 | {0x135b4,0x1}, | 1688 | {0x135b4,0x1}, |
1737 | {0x136b4,0x1}, | 1689 | {0x136b4,0x1}, |
1738 | {0x137b4,0x1}, | 1690 | {0x137b4,0x1}, |
1739 | {0x138b4,0x1}, | 1691 | {0x138b4,0x1}, |
1740 | {0x2003a,0x2}, | 1692 | {0x2003a,0x2}, |
1741 | {0xc0080,0x2}, | 1693 | {0xc0080,0x2}, |
1742 | {0xd0000, 0x1} | 1694 | {0xd0000, 0x1} |
1743 | }; | 1695 | }; |
1744 | 1696 | ||
1745 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | 1697 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { |
1746 | { | 1698 | { |
1747 | /* P0 3200mts 1D */ | 1699 | /* P0 3200mts 1D */ |
1748 | .drate = 3200, | 1700 | .drate = 3200, |
1749 | .fw_type = FW_1D_IMAGE, | 1701 | .fw_type = FW_1D_IMAGE, |
1750 | .fsp_cfg = ddr_fsp0_cfg, | 1702 | .fsp_cfg = ddr_fsp0_cfg, |
1751 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | 1703 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), |
1752 | }, | 1704 | }, |
1753 | { | 1705 | { |
1754 | /* P1 667mts 1D */ | 1706 | /* P1 667mts 1D */ |
1755 | .drate = 667, | 1707 | .drate = 667, |
1756 | .fw_type = FW_1D_IMAGE, | 1708 | .fw_type = FW_1D_IMAGE, |
1757 | .fsp_cfg = ddr_fsp1_cfg, | 1709 | .fsp_cfg = ddr_fsp1_cfg, |
1758 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | 1710 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), |
1759 | }, | 1711 | }, |
1760 | { | 1712 | { |
1761 | /* P0 3200mts 2D */ | 1713 | /* P0 3200mts 2D */ |
1762 | .drate = 3200, | 1714 | .drate = 3200, |
1763 | .fw_type = FW_2D_IMAGE, | 1715 | .fw_type = FW_2D_IMAGE, |
1764 | .fsp_cfg = ddr_fsp0_2d_cfg, | 1716 | .fsp_cfg = ddr_fsp0_2d_cfg, |
1765 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | 1717 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), |
1766 | }, | 1718 | }, |
1767 | }; | 1719 | }; |
1768 | 1720 | ||
1769 | /* ddr timing config params */ | 1721 | /* ddr timing config params */ |
1770 | struct dram_timing_info dram_timing = { | 1722 | struct dram_timing_info dram_timing = { |
1771 | .ddrc_cfg = ddr_ddrc_cfg, | 1723 | .ddrc_cfg = ddr_ddrc_cfg, |
1772 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | 1724 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), |
1773 | .ddrphy_cfg = ddr_ddrphy_cfg, | 1725 | .ddrphy_cfg = ddr_ddrphy_cfg, |
1774 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | 1726 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), |
1775 | .fsp_msg = ddr_dram_fsp_msg, | 1727 | .fsp_msg = ddr_dram_fsp_msg, |
1776 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | 1728 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), |
1777 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | 1729 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, |
1778 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | 1730 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), |
1779 | .ddrphy_pie = ddr_phy_pie, | 1731 | .ddrphy_pie = ddr_phy_pie, |
1780 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | 1732 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), |
1781 | .fsp_table = { 3200, 667, }, | 1733 | .fsp_table = { 3200, 667, }, |
1782 | }; | 1734 | }; |
1735 | #elif defined(CONFIG_2GB_LPDDR4_IND) | ||
1736 | struct dram_cfg_param ddr_ddrc_cfg[] = { | ||
1737 | /** Initialize DDRC registers **/ | ||
1738 | {0x3d400304,0x1}, | ||
1739 | {0x3d400030,0x1}, | ||
1740 | {0x3d400000,0xa1080020}, | ||
1741 | {0x3d400028,0x0}, | ||
1742 | {0x3d400020,0x203}, | ||
1743 | {0x3d400024,0x3e800}, | ||
1744 | {0x3d400064,0x6100e0}, | ||
1745 | {0x3d4000d0,0xc003061c}, | ||
1746 | {0x3d4000d4,0x9e0000}, | ||
1747 | {0x3d4000dc,0xd4002d}, | ||
1748 | {0x3d4000e0,0x310008}, | ||
1749 | {0x3d4000e8,0x66004a}, | ||
1750 | {0x3d4000ec,0x16004a}, | ||
1751 | {0x3d400100,0x1a201b22}, | ||
1752 | {0x3d400104,0x60633}, | ||
1753 | {0x3d40010c,0xc0c000}, | ||
1754 | {0x3d400110,0xf04080f}, | ||
1755 | {0x3d400114,0x2040c0c}, | ||
1756 | {0x3d400118,0x1010007}, | ||
1757 | {0x3d40011c,0x401}, | ||
1758 | {0x3d400130,0x20600}, | ||
1759 | {0x3d400134,0xc100002}, | ||
1760 | {0x3d400138,0xe6}, | ||
1761 | {0x3d400144,0xa00050}, | ||
1762 | {0x3d400180,0xc3200018}, | ||
1763 | {0x3d400184,0x28061a8}, | ||
1764 | {0x3d400188,0x0}, | ||
1765 | {0x3d400190,0x497820a}, | ||
1766 | {0x3d400194,0x80303}, | ||
1767 | {0x3d4001a0,0xe0400018}, | ||
1768 | {0x3d4001a4,0xdf00e4}, | ||
1769 | {0x3d4001a8,0x80000000}, | ||
1770 | {0x3d4001b0,0x11}, | ||
1771 | {0x3d4001b4,0x170a}, | ||
1772 | {0x3d4001c0,0x1}, | ||
1773 | {0x3d4001c4,0x1}, | ||
1774 | {0x3d4000f4,0x639}, | ||
1775 | {0x3d400108,0x70e1617}, | ||
1776 | {0x3d400200,0x1f}, | ||
1777 | {0x3d40020c,0x0}, | ||
1778 | {0x3d400210,0x1f1f}, | ||
1779 | {0x3d400204,0x80808}, | ||
1780 | {0x3d400214,0x7070707}, | ||
1781 | {0x3d400218,0x7070707}, | ||
1782 | {0x3d402020,0x1}, | ||
1783 | {0x3d402024,0xd0c0}, | ||
1784 | {0x3d402050,0x20d040}, | ||
1785 | {0x3d402064,0x14002f}, | ||
1786 | {0x3d4020dc,0x940009}, | ||
1787 | {0x3d4020e0,0x310000}, | ||
1788 | {0x3d4020e8,0x66004a}, | ||
1789 | {0x3d4020ec,0x16004a}, | ||
1790 | {0x3d402100,0xb070508}, | ||
1791 | {0x3d402104,0x3040b}, | ||
1792 | {0x3d402108,0x305090c}, | ||
1793 | {0x3d40210c,0x505000}, | ||
1794 | {0x3d402110,0x4040204}, | ||
1795 | {0x3d402114,0x2030303}, | ||
1796 | {0x3d402118,0x1010004}, | ||
1797 | {0x3d40211c,0x301}, | ||
1798 | {0x3d402130,0x20300}, | ||
1799 | {0x3d402134,0xa100002}, | ||
1800 | {0x3d402138,0x31}, | ||
1801 | {0x3d402144,0x220011}, | ||
1802 | {0x3d402180,0xc0a70006}, | ||
1803 | {0x3d402190,0x3858202}, | ||
1804 | {0x3d402194,0x80303}, | ||
1805 | {0x3d4021b4,0x502}, | ||
1806 | {0x3d400244,0x0}, | ||
1807 | {0x3d400250,0x29001505}, | ||
1808 | {0x3d400254,0x2c}, | ||
1809 | {0x3d40025c,0x5900575b}, | ||
1810 | {0x3d400264,0x90000096}, | ||
1811 | {0x3d40026c,0x1000012c}, | ||
1812 | {0x3d400300,0x16}, | ||
1813 | {0x3d400304,0x0}, | ||
1814 | {0x3d40030c,0x0}, | ||
1815 | {0x3d400320,0x1}, | ||
1816 | {0x3d40036c,0x11}, | ||
1817 | {0x3d400400,0x111}, | ||
1818 | {0x3d400404,0x10f3}, | ||
1819 | {0x3d400408,0x72ff}, | ||
1820 | {0x3d400490,0x1}, | ||
1821 | {0x3d400494,0xe00}, | ||
1822 | {0x3d400498,0x62ffff}, | ||
1823 | {0x3d40049c,0xe00}, | ||
1824 | {0x3d4004a0,0xffff}, | ||
1825 | }; | ||
1783 | 1826 | ||
1827 | /* PHY Initialize Configuration */ | ||
1828 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | ||
1829 | {0x100a0,0x0}, | ||
1830 | {0x100a1,0x1}, | ||
1831 | {0x100a2,0x2}, | ||
1832 | {0x100a3,0x3}, | ||
1833 | {0x100a4,0x4}, | ||
1834 | {0x100a5,0x5}, | ||
1835 | {0x100a6,0x6}, | ||
1836 | {0x100a7,0x7}, | ||
1837 | {0x110a0,0x0}, | ||
1838 | {0x110a1,0x1}, | ||
1839 | {0x110a2,0x2}, | ||
1840 | {0x110a3,0x3}, | ||
1841 | {0x110a4,0x4}, | ||
1842 | {0x110a5,0x7}, | ||
1843 | {0x110a6,0x6}, | ||
1844 | {0x110a7,0x5}, | ||
1845 | {0x120a0,0x0}, | ||
1846 | {0x120a1,0x1}, | ||
1847 | {0x120a2,0x2}, | ||
1848 | {0x120a3,0x3}, | ||
1849 | {0x120a4,0x4}, | ||
1850 | {0x120a5,0x5}, | ||
1851 | {0x120a6,0x6}, | ||
1852 | {0x120a7,0x7}, | ||
1853 | {0x130a0,0x0}, | ||
1854 | {0x130a1,0x1}, | ||
1855 | {0x130a2,0x2}, | ||
1856 | {0x130a3,0x3}, | ||
1857 | {0x130a4,0x4}, | ||
1858 | {0x130a5,0x5}, | ||
1859 | {0x130a6,0x6}, | ||
1860 | {0x130a7,0x7}, | ||
1861 | {0x20110,0x2}, | ||
1862 | {0x20111,0x3}, | ||
1863 | {0x20112,0x4}, | ||
1864 | {0x20113,0x5}, | ||
1865 | {0x20114,0x0}, | ||
1866 | {0x20115,0x1}, | ||
1867 | {0x1005f,0x1ff}, | ||
1868 | {0x1015f,0x1ff}, | ||
1869 | {0x1105f,0x1ff}, | ||
1870 | {0x1115f,0x1ff}, | ||
1871 | {0x1205f,0x1ff}, | ||
1872 | {0x1215f,0x1ff}, | ||
1873 | {0x1305f,0x1ff}, | ||
1874 | {0x1315f,0x1ff}, | ||
1875 | {0x11005f,0x1ff}, | ||
1876 | {0x11015f,0x1ff}, | ||
1877 | {0x11105f,0x1ff}, | ||
1878 | {0x11115f,0x1ff}, | ||
1879 | {0x11205f,0x1ff}, | ||
1880 | {0x11215f,0x1ff}, | ||
1881 | {0x11305f,0x1ff}, | ||
1882 | {0x11315f,0x1ff}, | ||
1883 | {0x55,0x1ff}, | ||
1884 | {0x1055,0x1ff}, | ||
1885 | {0x2055,0x1ff}, | ||
1886 | {0x3055,0x1ff}, | ||
1887 | {0x4055,0x1ff}, | ||
1888 | {0x5055,0x1ff}, | ||
1889 | {0x6055,0x1ff}, | ||
1890 | {0x7055,0x1ff}, | ||
1891 | {0x8055,0x1ff}, | ||
1892 | {0x9055,0x1ff}, | ||
1893 | {0x200c5,0x19}, | ||
1894 | {0x1200c5,0x7}, | ||
1895 | {0x2002e,0x2}, | ||
1896 | {0x12002e,0x1}, | ||
1897 | {0x90204,0x0}, | ||
1898 | {0x190204,0x0}, | ||
1899 | {0x20024,0x1ab}, | ||
1900 | {0x2003a,0x0}, | ||
1901 | {0x120024,0x1ab}, | ||
1902 | {0x2003a,0x0}, | ||
1903 | {0x20056,0x3}, | ||
1904 | {0x120056,0xa}, | ||
1905 | {0x1004d,0xe00}, | ||
1906 | {0x1014d,0xe00}, | ||
1907 | {0x1104d,0xe00}, | ||
1908 | {0x1114d,0xe00}, | ||
1909 | {0x1204d,0xe00}, | ||
1910 | {0x1214d,0xe00}, | ||
1911 | {0x1304d,0xe00}, | ||
1912 | {0x1314d,0xe00}, | ||
1913 | {0x11004d,0xe00}, | ||
1914 | {0x11014d,0xe00}, | ||
1915 | {0x11104d,0xe00}, | ||
1916 | {0x11114d,0xe00}, | ||
1917 | {0x11204d,0xe00}, | ||
1918 | {0x11214d,0xe00}, | ||
1919 | {0x11304d,0xe00}, | ||
1920 | {0x11314d,0xe00}, | ||
1921 | {0x10049,0xeba}, | ||
1922 | {0x10149,0xeba}, | ||
1923 | {0x11049,0xeba}, | ||
1924 | {0x11149,0xeba}, | ||
1925 | {0x12049,0xeba}, | ||
1926 | {0x12149,0xeba}, | ||
1927 | {0x13049,0xeba}, | ||
1928 | {0x13149,0xeba}, | ||
1929 | {0x110049,0xeba}, | ||
1930 | {0x110149,0xeba}, | ||
1931 | {0x111049,0xeba}, | ||
1932 | {0x111149,0xeba}, | ||
1933 | {0x112049,0xeba}, | ||
1934 | {0x112149,0xeba}, | ||
1935 | {0x113049,0xeba}, | ||
1936 | {0x113149,0xeba}, | ||
1937 | {0x43,0x63}, | ||
1938 | {0x1043,0x63}, | ||
1939 | {0x2043,0x63}, | ||
1940 | {0x3043,0x63}, | ||
1941 | {0x4043,0x63}, | ||
1942 | {0x5043,0x63}, | ||
1943 | {0x6043,0x63}, | ||
1944 | {0x7043,0x63}, | ||
1945 | {0x8043,0x63}, | ||
1946 | {0x9043,0x63}, | ||
1947 | {0x20018,0x3}, | ||
1948 | {0x20075,0x4}, | ||
1949 | {0x20050,0x0}, | ||
1950 | {0x20008,0x320}, | ||
1951 | {0x120008,0xa7}, | ||
1952 | {0x20088,0x9}, | ||
1953 | {0x200b2,0xdc}, | ||
1954 | {0x10043,0x5a1}, | ||
1955 | {0x10143,0x5a1}, | ||
1956 | {0x11043,0x5a1}, | ||
1957 | {0x11143,0x5a1}, | ||
1958 | {0x12043,0x5a1}, | ||
1959 | {0x12143,0x5a1}, | ||
1960 | {0x13043,0x5a1}, | ||
1961 | {0x13143,0x5a1}, | ||
1962 | {0x1200b2,0xdc}, | ||
1963 | {0x110043,0x5a1}, | ||
1964 | {0x110143,0x5a1}, | ||
1965 | {0x111043,0x5a1}, | ||
1966 | {0x111143,0x5a1}, | ||
1967 | {0x112043,0x5a1}, | ||
1968 | {0x112143,0x5a1}, | ||
1969 | {0x113043,0x5a1}, | ||
1970 | {0x113143,0x5a1}, | ||
1971 | {0x200fa,0x1}, | ||
1972 | {0x1200fa,0x1}, | ||
1973 | {0x20019,0x1}, | ||
1974 | {0x120019,0x1}, | ||
1975 | {0x200f0,0x0}, | ||
1976 | {0x200f1,0x0}, | ||
1977 | {0x200f2,0x4444}, | ||
1978 | {0x200f3,0x8888}, | ||
1979 | {0x200f4,0x5555}, | ||
1980 | {0x200f5,0x0}, | ||
1981 | {0x200f6,0x0}, | ||
1982 | {0x200f7,0xf000}, | ||
1983 | {0x20025,0x0}, | ||
1984 | {0x2002d,0x0}, | ||
1985 | {0x12002d,0x0}, | ||
1986 | {0x200c7,0x80}, | ||
1987 | {0x1200c7,0x80}, | ||
1988 | {0x200ca,0x106}, | ||
1989 | {0x1200ca,0x106}, | ||
1990 | }; | ||
1991 | |||
1992 | /* ddr phy trained csr */ | ||
1993 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | ||
1994 | { 0x200b2, 0x0 }, | ||
1995 | { 0x1200b2, 0x0 }, | ||
1996 | { 0x2200b2, 0x0 }, | ||
1997 | { 0x200cb, 0x0 }, | ||
1998 | { 0x10043, 0x0 }, | ||
1999 | { 0x110043, 0x0 }, | ||
2000 | { 0x210043, 0x0 }, | ||
2001 | { 0x10143, 0x0 }, | ||
2002 | { 0x110143, 0x0 }, | ||
2003 | { 0x210143, 0x0 }, | ||
2004 | { 0x11043, 0x0 }, | ||
2005 | { 0x111043, 0x0 }, | ||
2006 | { 0x211043, 0x0 }, | ||
2007 | { 0x11143, 0x0 }, | ||
2008 | { 0x111143, 0x0 }, | ||
2009 | { 0x211143, 0x0 }, | ||
2010 | { 0x12043, 0x0 }, | ||
2011 | { 0x112043, 0x0 }, | ||
2012 | { 0x212043, 0x0 }, | ||
2013 | { 0x12143, 0x0 }, | ||
2014 | { 0x112143, 0x0 }, | ||
2015 | { 0x212143, 0x0 }, | ||
2016 | { 0x13043, 0x0 }, | ||
2017 | { 0x113043, 0x0 }, | ||
2018 | { 0x213043, 0x0 }, | ||
2019 | { 0x13143, 0x0 }, | ||
2020 | { 0x113143, 0x0 }, | ||
2021 | { 0x213143, 0x0 }, | ||
2022 | { 0x80, 0x0 }, | ||
2023 | { 0x100080, 0x0 }, | ||
2024 | { 0x200080, 0x0 }, | ||
2025 | { 0x1080, 0x0 }, | ||
2026 | { 0x101080, 0x0 }, | ||
2027 | { 0x201080, 0x0 }, | ||
2028 | { 0x2080, 0x0 }, | ||
2029 | { 0x102080, 0x0 }, | ||
2030 | { 0x202080, 0x0 }, | ||
2031 | { 0x3080, 0x0 }, | ||
2032 | { 0x103080, 0x0 }, | ||
2033 | { 0x203080, 0x0 }, | ||
2034 | { 0x4080, 0x0 }, | ||
2035 | { 0x104080, 0x0 }, | ||
2036 | { 0x204080, 0x0 }, | ||
2037 | { 0x5080, 0x0 }, | ||
2038 | { 0x105080, 0x0 }, | ||
2039 | { 0x205080, 0x0 }, | ||
2040 | { 0x6080, 0x0 }, | ||
2041 | { 0x106080, 0x0 }, | ||
2042 | { 0x206080, 0x0 }, | ||
2043 | { 0x7080, 0x0 }, | ||
2044 | { 0x107080, 0x0 }, | ||
2045 | { 0x207080, 0x0 }, | ||
2046 | { 0x8080, 0x0 }, | ||
2047 | { 0x108080, 0x0 }, | ||
2048 | { 0x208080, 0x0 }, | ||
2049 | { 0x9080, 0x0 }, | ||
2050 | { 0x109080, 0x0 }, | ||
2051 | { 0x209080, 0x0 }, | ||
2052 | { 0x10080, 0x0 }, | ||
2053 | { 0x110080, 0x0 }, | ||
2054 | { 0x210080, 0x0 }, | ||
2055 | { 0x10180, 0x0 }, | ||
2056 | { 0x110180, 0x0 }, | ||
2057 | { 0x210180, 0x0 }, | ||
2058 | { 0x11080, 0x0 }, | ||
2059 | { 0x111080, 0x0 }, | ||
2060 | { 0x211080, 0x0 }, | ||
2061 | { 0x11180, 0x0 }, | ||
2062 | { 0x111180, 0x0 }, | ||
2063 | { 0x211180, 0x0 }, | ||
2064 | { 0x12080, 0x0 }, | ||
2065 | { 0x112080, 0x0 }, | ||
2066 | { 0x212080, 0x0 }, | ||
2067 | { 0x12180, 0x0 }, | ||
2068 | { 0x112180, 0x0 }, | ||
2069 | { 0x212180, 0x0 }, | ||
2070 | { 0x13080, 0x0 }, | ||
2071 | { 0x113080, 0x0 }, | ||
2072 | { 0x213080, 0x0 }, | ||
2073 | { 0x13180, 0x0 }, | ||
2074 | { 0x113180, 0x0 }, | ||
2075 | { 0x213180, 0x0 }, | ||
2076 | { 0x10081, 0x0 }, | ||
2077 | { 0x110081, 0x0 }, | ||
2078 | { 0x210081, 0x0 }, | ||
2079 | { 0x10181, 0x0 }, | ||
2080 | { 0x110181, 0x0 }, | ||
2081 | { 0x210181, 0x0 }, | ||
2082 | { 0x11081, 0x0 }, | ||
2083 | { 0x111081, 0x0 }, | ||
2084 | { 0x211081, 0x0 }, | ||
2085 | { 0x11181, 0x0 }, | ||
2086 | { 0x111181, 0x0 }, | ||
2087 | { 0x211181, 0x0 }, | ||
2088 | { 0x12081, 0x0 }, | ||
2089 | { 0x112081, 0x0 }, | ||
2090 | { 0x212081, 0x0 }, | ||
2091 | { 0x12181, 0x0 }, | ||
2092 | { 0x112181, 0x0 }, | ||
2093 | { 0x212181, 0x0 }, | ||
2094 | { 0x13081, 0x0 }, | ||
2095 | { 0x113081, 0x0 }, | ||
2096 | { 0x213081, 0x0 }, | ||
2097 | { 0x13181, 0x0 }, | ||
2098 | { 0x113181, 0x0 }, | ||
2099 | { 0x213181, 0x0 }, | ||
2100 | { 0x100d0, 0x0 }, | ||
2101 | { 0x1100d0, 0x0 }, | ||
2102 | { 0x2100d0, 0x0 }, | ||
2103 | { 0x101d0, 0x0 }, | ||
2104 | { 0x1101d0, 0x0 }, | ||
2105 | { 0x2101d0, 0x0 }, | ||
2106 | { 0x110d0, 0x0 }, | ||
2107 | { 0x1110d0, 0x0 }, | ||
2108 | { 0x2110d0, 0x0 }, | ||
2109 | { 0x111d0, 0x0 }, | ||
2110 | { 0x1111d0, 0x0 }, | ||
2111 | { 0x2111d0, 0x0 }, | ||
2112 | { 0x120d0, 0x0 }, | ||
2113 | { 0x1120d0, 0x0 }, | ||
2114 | { 0x2120d0, 0x0 }, | ||
2115 | { 0x121d0, 0x0 }, | ||
2116 | { 0x1121d0, 0x0 }, | ||
2117 | { 0x2121d0, 0x0 }, | ||
2118 | { 0x130d0, 0x0 }, | ||
2119 | { 0x1130d0, 0x0 }, | ||
2120 | { 0x2130d0, 0x0 }, | ||
2121 | { 0x131d0, 0x0 }, | ||
2122 | { 0x1131d0, 0x0 }, | ||
2123 | { 0x2131d0, 0x0 }, | ||
2124 | { 0x100d1, 0x0 }, | ||
2125 | { 0x1100d1, 0x0 }, | ||
2126 | { 0x2100d1, 0x0 }, | ||
2127 | { 0x101d1, 0x0 }, | ||
2128 | { 0x1101d1, 0x0 }, | ||
2129 | { 0x2101d1, 0x0 }, | ||
2130 | { 0x110d1, 0x0 }, | ||
2131 | { 0x1110d1, 0x0 }, | ||
2132 | { 0x2110d1, 0x0 }, | ||
2133 | { 0x111d1, 0x0 }, | ||
2134 | { 0x1111d1, 0x0 }, | ||
2135 | { 0x2111d1, 0x0 }, | ||
2136 | { 0x120d1, 0x0 }, | ||
2137 | { 0x1120d1, 0x0 }, | ||
2138 | { 0x2120d1, 0x0 }, | ||
2139 | { 0x121d1, 0x0 }, | ||
2140 | { 0x1121d1, 0x0 }, | ||
2141 | { 0x2121d1, 0x0 }, | ||
2142 | { 0x130d1, 0x0 }, | ||
2143 | { 0x1130d1, 0x0 }, | ||
2144 | { 0x2130d1, 0x0 }, | ||
2145 | { 0x131d1, 0x0 }, | ||
2146 | { 0x1131d1, 0x0 }, | ||
2147 | { 0x2131d1, 0x0 }, | ||
2148 | { 0x10068, 0x0 }, | ||
2149 | { 0x10168, 0x0 }, | ||
2150 | { 0x10268, 0x0 }, | ||
2151 | { 0x10368, 0x0 }, | ||
2152 | { 0x10468, 0x0 }, | ||
2153 | { 0x10568, 0x0 }, | ||
2154 | { 0x10668, 0x0 }, | ||
2155 | { 0x10768, 0x0 }, | ||
2156 | { 0x10868, 0x0 }, | ||
2157 | { 0x11068, 0x0 }, | ||
2158 | { 0x11168, 0x0 }, | ||
2159 | { 0x11268, 0x0 }, | ||
2160 | { 0x11368, 0x0 }, | ||
2161 | { 0x11468, 0x0 }, | ||
2162 | { 0x11568, 0x0 }, | ||
2163 | { 0x11668, 0x0 }, | ||
2164 | { 0x11768, 0x0 }, | ||
2165 | { 0x11868, 0x0 }, | ||
2166 | { 0x12068, 0x0 }, | ||
2167 | { 0x12168, 0x0 }, | ||
2168 | { 0x12268, 0x0 }, | ||
2169 | { 0x12368, 0x0 }, | ||
2170 | { 0x12468, 0x0 }, | ||
2171 | { 0x12568, 0x0 }, | ||
2172 | { 0x12668, 0x0 }, | ||
2173 | { 0x12768, 0x0 }, | ||
2174 | { 0x12868, 0x0 }, | ||
2175 | { 0x13068, 0x0 }, | ||
2176 | { 0x13168, 0x0 }, | ||
2177 | { 0x13268, 0x0 }, | ||
2178 | { 0x13368, 0x0 }, | ||
2179 | { 0x13468, 0x0 }, | ||
2180 | { 0x13568, 0x0 }, | ||
2181 | { 0x13668, 0x0 }, | ||
2182 | { 0x13768, 0x0 }, | ||
2183 | { 0x13868, 0x0 }, | ||
2184 | { 0x10069, 0x0 }, | ||
2185 | { 0x10169, 0x0 }, | ||
2186 | { 0x10269, 0x0 }, | ||
2187 | { 0x10369, 0x0 }, | ||
2188 | { 0x10469, 0x0 }, | ||
2189 | { 0x10569, 0x0 }, | ||
2190 | { 0x10669, 0x0 }, | ||
2191 | { 0x10769, 0x0 }, | ||
2192 | { 0x10869, 0x0 }, | ||
2193 | { 0x11069, 0x0 }, | ||
2194 | { 0x11169, 0x0 }, | ||
2195 | { 0x11269, 0x0 }, | ||
2196 | { 0x11369, 0x0 }, | ||
2197 | { 0x11469, 0x0 }, | ||
2198 | { 0x11569, 0x0 }, | ||
2199 | { 0x11669, 0x0 }, | ||
2200 | { 0x11769, 0x0 }, | ||
2201 | { 0x11869, 0x0 }, | ||
2202 | { 0x12069, 0x0 }, | ||
2203 | { 0x12169, 0x0 }, | ||
2204 | { 0x12269, 0x0 }, | ||
2205 | { 0x12369, 0x0 }, | ||
2206 | { 0x12469, 0x0 }, | ||
2207 | { 0x12569, 0x0 }, | ||
2208 | { 0x12669, 0x0 }, | ||
2209 | { 0x12769, 0x0 }, | ||
2210 | { 0x12869, 0x0 }, | ||
2211 | { 0x13069, 0x0 }, | ||
2212 | { 0x13169, 0x0 }, | ||
2213 | { 0x13269, 0x0 }, | ||
2214 | { 0x13369, 0x0 }, | ||
2215 | { 0x13469, 0x0 }, | ||
2216 | { 0x13569, 0x0 }, | ||
2217 | { 0x13669, 0x0 }, | ||
2218 | { 0x13769, 0x0 }, | ||
2219 | { 0x13869, 0x0 }, | ||
2220 | { 0x1008c, 0x0 }, | ||
2221 | { 0x11008c, 0x0 }, | ||
2222 | { 0x21008c, 0x0 }, | ||
2223 | { 0x1018c, 0x0 }, | ||
2224 | { 0x11018c, 0x0 }, | ||
2225 | { 0x21018c, 0x0 }, | ||
2226 | { 0x1108c, 0x0 }, | ||
2227 | { 0x11108c, 0x0 }, | ||
2228 | { 0x21108c, 0x0 }, | ||
2229 | { 0x1118c, 0x0 }, | ||
2230 | { 0x11118c, 0x0 }, | ||
2231 | { 0x21118c, 0x0 }, | ||
2232 | { 0x1208c, 0x0 }, | ||
2233 | { 0x11208c, 0x0 }, | ||
2234 | { 0x21208c, 0x0 }, | ||
2235 | { 0x1218c, 0x0 }, | ||
2236 | { 0x11218c, 0x0 }, | ||
2237 | { 0x21218c, 0x0 }, | ||
2238 | { 0x1308c, 0x0 }, | ||
2239 | { 0x11308c, 0x0 }, | ||
2240 | { 0x21308c, 0x0 }, | ||
2241 | { 0x1318c, 0x0 }, | ||
2242 | { 0x11318c, 0x0 }, | ||
2243 | { 0x21318c, 0x0 }, | ||
2244 | { 0x1008d, 0x0 }, | ||
2245 | { 0x11008d, 0x0 }, | ||
2246 | { 0x21008d, 0x0 }, | ||
2247 | { 0x1018d, 0x0 }, | ||
2248 | { 0x11018d, 0x0 }, | ||
2249 | { 0x21018d, 0x0 }, | ||
2250 | { 0x1108d, 0x0 }, | ||
2251 | { 0x11108d, 0x0 }, | ||
2252 | { 0x21108d, 0x0 }, | ||
2253 | { 0x1118d, 0x0 }, | ||
2254 | { 0x11118d, 0x0 }, | ||
2255 | { 0x21118d, 0x0 }, | ||
2256 | { 0x1208d, 0x0 }, | ||
2257 | { 0x11208d, 0x0 }, | ||
2258 | { 0x21208d, 0x0 }, | ||
2259 | { 0x1218d, 0x0 }, | ||
2260 | { 0x11218d, 0x0 }, | ||
2261 | { 0x21218d, 0x0 }, | ||
2262 | { 0x1308d, 0x0 }, | ||
2263 | { 0x11308d, 0x0 }, | ||
2264 | { 0x21308d, 0x0 }, | ||
2265 | { 0x1318d, 0x0 }, | ||
2266 | { 0x11318d, 0x0 }, | ||
2267 | { 0x21318d, 0x0 }, | ||
2268 | { 0x100c0, 0x0 }, | ||
2269 | { 0x1100c0, 0x0 }, | ||
2270 | { 0x2100c0, 0x0 }, | ||
2271 | { 0x101c0, 0x0 }, | ||
2272 | { 0x1101c0, 0x0 }, | ||
2273 | { 0x2101c0, 0x0 }, | ||
2274 | { 0x102c0, 0x0 }, | ||
2275 | { 0x1102c0, 0x0 }, | ||
2276 | { 0x2102c0, 0x0 }, | ||
2277 | { 0x103c0, 0x0 }, | ||
2278 | { 0x1103c0, 0x0 }, | ||
2279 | { 0x2103c0, 0x0 }, | ||
2280 | { 0x104c0, 0x0 }, | ||
2281 | { 0x1104c0, 0x0 }, | ||
2282 | { 0x2104c0, 0x0 }, | ||
2283 | { 0x105c0, 0x0 }, | ||
2284 | { 0x1105c0, 0x0 }, | ||
2285 | { 0x2105c0, 0x0 }, | ||
2286 | { 0x106c0, 0x0 }, | ||
2287 | { 0x1106c0, 0x0 }, | ||
2288 | { 0x2106c0, 0x0 }, | ||
2289 | { 0x107c0, 0x0 }, | ||
2290 | { 0x1107c0, 0x0 }, | ||
2291 | { 0x2107c0, 0x0 }, | ||
2292 | { 0x108c0, 0x0 }, | ||
2293 | { 0x1108c0, 0x0 }, | ||
2294 | { 0x2108c0, 0x0 }, | ||
2295 | { 0x110c0, 0x0 }, | ||
2296 | { 0x1110c0, 0x0 }, | ||
2297 | { 0x2110c0, 0x0 }, | ||
2298 | { 0x111c0, 0x0 }, | ||
2299 | { 0x1111c0, 0x0 }, | ||
2300 | { 0x2111c0, 0x0 }, | ||
2301 | { 0x112c0, 0x0 }, | ||
2302 | { 0x1112c0, 0x0 }, | ||
2303 | { 0x2112c0, 0x0 }, | ||
2304 | { 0x113c0, 0x0 }, | ||
2305 | { 0x1113c0, 0x0 }, | ||
2306 | { 0x2113c0, 0x0 }, | ||
2307 | { 0x114c0, 0x0 }, | ||
2308 | { 0x1114c0, 0x0 }, | ||
2309 | { 0x2114c0, 0x0 }, | ||
2310 | { 0x115c0, 0x0 }, | ||
2311 | { 0x1115c0, 0x0 }, | ||
2312 | { 0x2115c0, 0x0 }, | ||
2313 | { 0x116c0, 0x0 }, | ||
2314 | { 0x1116c0, 0x0 }, | ||
2315 | { 0x2116c0, 0x0 }, | ||
2316 | { 0x117c0, 0x0 }, | ||
2317 | { 0x1117c0, 0x0 }, | ||
2318 | { 0x2117c0, 0x0 }, | ||
2319 | { 0x118c0, 0x0 }, | ||
2320 | { 0x1118c0, 0x0 }, | ||
2321 | { 0x2118c0, 0x0 }, | ||
2322 | { 0x120c0, 0x0 }, | ||
2323 | { 0x1120c0, 0x0 }, | ||
2324 | { 0x2120c0, 0x0 }, | ||
2325 | { 0x121c0, 0x0 }, | ||
2326 | { 0x1121c0, 0x0 }, | ||
2327 | { 0x2121c0, 0x0 }, | ||
2328 | { 0x122c0, 0x0 }, | ||
2329 | { 0x1122c0, 0x0 }, | ||
2330 | { 0x2122c0, 0x0 }, | ||
2331 | { 0x123c0, 0x0 }, | ||
2332 | { 0x1123c0, 0x0 }, | ||
2333 | { 0x2123c0, 0x0 }, | ||
2334 | { 0x124c0, 0x0 }, | ||
2335 | { 0x1124c0, 0x0 }, | ||
2336 | { 0x2124c0, 0x0 }, | ||
2337 | { 0x125c0, 0x0 }, | ||
2338 | { 0x1125c0, 0x0 }, | ||
2339 | { 0x2125c0, 0x0 }, | ||
2340 | { 0x126c0, 0x0 }, | ||
2341 | { 0x1126c0, 0x0 }, | ||
2342 | { 0x2126c0, 0x0 }, | ||
2343 | { 0x127c0, 0x0 }, | ||
2344 | { 0x1127c0, 0x0 }, | ||
2345 | { 0x2127c0, 0x0 }, | ||
2346 | { 0x128c0, 0x0 }, | ||
2347 | { 0x1128c0, 0x0 }, | ||
2348 | { 0x2128c0, 0x0 }, | ||
2349 | { 0x130c0, 0x0 }, | ||
2350 | { 0x1130c0, 0x0 }, | ||
2351 | { 0x2130c0, 0x0 }, | ||
2352 | { 0x131c0, 0x0 }, | ||
2353 | { 0x1131c0, 0x0 }, | ||
2354 | { 0x2131c0, 0x0 }, | ||
2355 | { 0x132c0, 0x0 }, | ||
2356 | { 0x1132c0, 0x0 }, | ||
2357 | { 0x2132c0, 0x0 }, | ||
2358 | { 0x133c0, 0x0 }, | ||
2359 | { 0x1133c0, 0x0 }, | ||
2360 | { 0x2133c0, 0x0 }, | ||
2361 | { 0x134c0, 0x0 }, | ||
2362 | { 0x1134c0, 0x0 }, | ||
2363 | { 0x2134c0, 0x0 }, | ||
2364 | { 0x135c0, 0x0 }, | ||
2365 | { 0x1135c0, 0x0 }, | ||
2366 | { 0x2135c0, 0x0 }, | ||
2367 | { 0x136c0, 0x0 }, | ||
2368 | { 0x1136c0, 0x0 }, | ||
2369 | { 0x2136c0, 0x0 }, | ||
2370 | { 0x137c0, 0x0 }, | ||
2371 | { 0x1137c0, 0x0 }, | ||
2372 | { 0x2137c0, 0x0 }, | ||
2373 | { 0x138c0, 0x0 }, | ||
2374 | { 0x1138c0, 0x0 }, | ||
2375 | { 0x2138c0, 0x0 }, | ||
2376 | { 0x100c1, 0x0 }, | ||
2377 | { 0x1100c1, 0x0 }, | ||
2378 | { 0x2100c1, 0x0 }, | ||
2379 | { 0x101c1, 0x0 }, | ||
2380 | { 0x1101c1, 0x0 }, | ||
2381 | { 0x2101c1, 0x0 }, | ||
2382 | { 0x102c1, 0x0 }, | ||
2383 | { 0x1102c1, 0x0 }, | ||
2384 | { 0x2102c1, 0x0 }, | ||
2385 | { 0x103c1, 0x0 }, | ||
2386 | { 0x1103c1, 0x0 }, | ||
2387 | { 0x2103c1, 0x0 }, | ||
2388 | { 0x104c1, 0x0 }, | ||
2389 | { 0x1104c1, 0x0 }, | ||
2390 | { 0x2104c1, 0x0 }, | ||
2391 | { 0x105c1, 0x0 }, | ||
2392 | { 0x1105c1, 0x0 }, | ||
2393 | { 0x2105c1, 0x0 }, | ||
2394 | { 0x106c1, 0x0 }, | ||
2395 | { 0x1106c1, 0x0 }, | ||
2396 | { 0x2106c1, 0x0 }, | ||
2397 | { 0x107c1, 0x0 }, | ||
2398 | { 0x1107c1, 0x0 }, | ||
2399 | { 0x2107c1, 0x0 }, | ||
2400 | { 0x108c1, 0x0 }, | ||
2401 | { 0x1108c1, 0x0 }, | ||
2402 | { 0x2108c1, 0x0 }, | ||
2403 | { 0x110c1, 0x0 }, | ||
2404 | { 0x1110c1, 0x0 }, | ||
2405 | { 0x2110c1, 0x0 }, | ||
2406 | { 0x111c1, 0x0 }, | ||
2407 | { 0x1111c1, 0x0 }, | ||
2408 | { 0x2111c1, 0x0 }, | ||
2409 | { 0x112c1, 0x0 }, | ||
2410 | { 0x1112c1, 0x0 }, | ||
2411 | { 0x2112c1, 0x0 }, | ||
2412 | { 0x113c1, 0x0 }, | ||
2413 | { 0x1113c1, 0x0 }, | ||
2414 | { 0x2113c1, 0x0 }, | ||
2415 | { 0x114c1, 0x0 }, | ||
2416 | { 0x1114c1, 0x0 }, | ||
2417 | { 0x2114c1, 0x0 }, | ||
2418 | { 0x115c1, 0x0 }, | ||
2419 | { 0x1115c1, 0x0 }, | ||
2420 | { 0x2115c1, 0x0 }, | ||
2421 | { 0x116c1, 0x0 }, | ||
2422 | { 0x1116c1, 0x0 }, | ||
2423 | { 0x2116c1, 0x0 }, | ||
2424 | { 0x117c1, 0x0 }, | ||
2425 | { 0x1117c1, 0x0 }, | ||
2426 | { 0x2117c1, 0x0 }, | ||
2427 | { 0x118c1, 0x0 }, | ||
2428 | { 0x1118c1, 0x0 }, | ||
2429 | { 0x2118c1, 0x0 }, | ||
2430 | { 0x120c1, 0x0 }, | ||
2431 | { 0x1120c1, 0x0 }, | ||
2432 | { 0x2120c1, 0x0 }, | ||
2433 | { 0x121c1, 0x0 }, | ||
2434 | { 0x1121c1, 0x0 }, | ||
2435 | { 0x2121c1, 0x0 }, | ||
2436 | { 0x122c1, 0x0 }, | ||
2437 | { 0x1122c1, 0x0 }, | ||
2438 | { 0x2122c1, 0x0 }, | ||
2439 | { 0x123c1, 0x0 }, | ||
2440 | { 0x1123c1, 0x0 }, | ||
2441 | { 0x2123c1, 0x0 }, | ||
2442 | { 0x124c1, 0x0 }, | ||
2443 | { 0x1124c1, 0x0 }, | ||
2444 | { 0x2124c1, 0x0 }, | ||
2445 | { 0x125c1, 0x0 }, | ||
2446 | { 0x1125c1, 0x0 }, | ||
2447 | { 0x2125c1, 0x0 }, | ||
2448 | { 0x126c1, 0x0 }, | ||
2449 | { 0x1126c1, 0x0 }, | ||
2450 | { 0x2126c1, 0x0 }, | ||
2451 | { 0x127c1, 0x0 }, | ||
2452 | { 0x1127c1, 0x0 }, | ||
2453 | { 0x2127c1, 0x0 }, | ||
2454 | { 0x128c1, 0x0 }, | ||
2455 | { 0x1128c1, 0x0 }, | ||
2456 | { 0x2128c1, 0x0 }, | ||
2457 | { 0x130c1, 0x0 }, | ||
2458 | { 0x1130c1, 0x0 }, | ||
2459 | { 0x2130c1, 0x0 }, | ||
2460 | { 0x131c1, 0x0 }, | ||
2461 | { 0x1131c1, 0x0 }, | ||
2462 | { 0x2131c1, 0x0 }, | ||
2463 | { 0x132c1, 0x0 }, | ||
2464 | { 0x1132c1, 0x0 }, | ||
2465 | { 0x2132c1, 0x0 }, | ||
2466 | { 0x133c1, 0x0 }, | ||
2467 | { 0x1133c1, 0x0 }, | ||
2468 | { 0x2133c1, 0x0 }, | ||
2469 | { 0x134c1, 0x0 }, | ||
2470 | { 0x1134c1, 0x0 }, | ||
2471 | { 0x2134c1, 0x0 }, | ||
2472 | { 0x135c1, 0x0 }, | ||
2473 | { 0x1135c1, 0x0 }, | ||
2474 | { 0x2135c1, 0x0 }, | ||
2475 | { 0x136c1, 0x0 }, | ||
2476 | { 0x1136c1, 0x0 }, | ||
2477 | { 0x2136c1, 0x0 }, | ||
2478 | { 0x137c1, 0x0 }, | ||
2479 | { 0x1137c1, 0x0 }, | ||
2480 | { 0x2137c1, 0x0 }, | ||
2481 | { 0x138c1, 0x0 }, | ||
2482 | { 0x1138c1, 0x0 }, | ||
2483 | { 0x2138c1, 0x0 }, | ||
2484 | { 0x10020, 0x0 }, | ||
2485 | { 0x110020, 0x0 }, | ||
2486 | { 0x210020, 0x0 }, | ||
2487 | { 0x11020, 0x0 }, | ||
2488 | { 0x111020, 0x0 }, | ||
2489 | { 0x211020, 0x0 }, | ||
2490 | { 0x12020, 0x0 }, | ||
2491 | { 0x112020, 0x0 }, | ||
2492 | { 0x212020, 0x0 }, | ||
2493 | { 0x13020, 0x0 }, | ||
2494 | { 0x113020, 0x0 }, | ||
2495 | { 0x213020, 0x0 }, | ||
2496 | { 0x20072, 0x0 }, | ||
2497 | { 0x20073, 0x0 }, | ||
2498 | { 0x20074, 0x0 }, | ||
2499 | { 0x100aa, 0x0 }, | ||
2500 | { 0x110aa, 0x0 }, | ||
2501 | { 0x120aa, 0x0 }, | ||
2502 | { 0x130aa, 0x0 }, | ||
2503 | { 0x20010, 0x0 }, | ||
2504 | { 0x120010, 0x0 }, | ||
2505 | { 0x220010, 0x0 }, | ||
2506 | { 0x20011, 0x0 }, | ||
2507 | { 0x120011, 0x0 }, | ||
2508 | { 0x220011, 0x0 }, | ||
2509 | { 0x100ae, 0x0 }, | ||
2510 | { 0x1100ae, 0x0 }, | ||
2511 | { 0x2100ae, 0x0 }, | ||
2512 | { 0x100af, 0x0 }, | ||
2513 | { 0x1100af, 0x0 }, | ||
2514 | { 0x2100af, 0x0 }, | ||
2515 | { 0x110ae, 0x0 }, | ||
2516 | { 0x1110ae, 0x0 }, | ||
2517 | { 0x2110ae, 0x0 }, | ||
2518 | { 0x110af, 0x0 }, | ||
2519 | { 0x1110af, 0x0 }, | ||
2520 | { 0x2110af, 0x0 }, | ||
2521 | { 0x120ae, 0x0 }, | ||
2522 | { 0x1120ae, 0x0 }, | ||
2523 | { 0x2120ae, 0x0 }, | ||
2524 | { 0x120af, 0x0 }, | ||
2525 | { 0x1120af, 0x0 }, | ||
2526 | { 0x2120af, 0x0 }, | ||
2527 | { 0x130ae, 0x0 }, | ||
2528 | { 0x1130ae, 0x0 }, | ||
2529 | { 0x2130ae, 0x0 }, | ||
2530 | { 0x130af, 0x0 }, | ||
2531 | { 0x1130af, 0x0 }, | ||
2532 | { 0x2130af, 0x0 }, | ||
2533 | { 0x20020, 0x0 }, | ||
2534 | { 0x120020, 0x0 }, | ||
2535 | { 0x220020, 0x0 }, | ||
2536 | { 0x100a0, 0x0 }, | ||
2537 | { 0x100a1, 0x0 }, | ||
2538 | { 0x100a2, 0x0 }, | ||
2539 | { 0x100a3, 0x0 }, | ||
2540 | { 0x100a4, 0x0 }, | ||
2541 | { 0x100a5, 0x0 }, | ||
2542 | { 0x100a6, 0x0 }, | ||
2543 | { 0x100a7, 0x0 }, | ||
2544 | { 0x110a0, 0x0 }, | ||
2545 | { 0x110a1, 0x0 }, | ||
2546 | { 0x110a2, 0x0 }, | ||
2547 | { 0x110a3, 0x0 }, | ||
2548 | { 0x110a4, 0x0 }, | ||
2549 | { 0x110a5, 0x0 }, | ||
2550 | { 0x110a6, 0x0 }, | ||
2551 | { 0x110a7, 0x0 }, | ||
2552 | { 0x120a0, 0x0 }, | ||
2553 | { 0x120a1, 0x0 }, | ||
2554 | { 0x120a2, 0x0 }, | ||
2555 | { 0x120a3, 0x0 }, | ||
2556 | { 0x120a4, 0x0 }, | ||
2557 | { 0x120a5, 0x0 }, | ||
2558 | { 0x120a6, 0x0 }, | ||
2559 | { 0x120a7, 0x0 }, | ||
2560 | { 0x130a0, 0x0 }, | ||
2561 | { 0x130a1, 0x0 }, | ||
2562 | { 0x130a2, 0x0 }, | ||
2563 | { 0x130a3, 0x0 }, | ||
2564 | { 0x130a4, 0x0 }, | ||
2565 | { 0x130a5, 0x0 }, | ||
2566 | { 0x130a6, 0x0 }, | ||
2567 | { 0x130a7, 0x0 }, | ||
2568 | { 0x2007c, 0x0 }, | ||
2569 | { 0x12007c, 0x0 }, | ||
2570 | { 0x22007c, 0x0 }, | ||
2571 | { 0x2007d, 0x0 }, | ||
2572 | { 0x12007d, 0x0 }, | ||
2573 | { 0x22007d, 0x0 }, | ||
2574 | { 0x400fd, 0x0 }, | ||
2575 | { 0x400c0, 0x0 }, | ||
2576 | { 0x90201, 0x0 }, | ||
2577 | { 0x190201, 0x0 }, | ||
2578 | { 0x290201, 0x0 }, | ||
2579 | { 0x90202, 0x0 }, | ||
2580 | { 0x190202, 0x0 }, | ||
2581 | { 0x290202, 0x0 }, | ||
2582 | { 0x90203, 0x0 }, | ||
2583 | { 0x190203, 0x0 }, | ||
2584 | { 0x290203, 0x0 }, | ||
2585 | { 0x90204, 0x0 }, | ||
2586 | { 0x190204, 0x0 }, | ||
2587 | { 0x290204, 0x0 }, | ||
2588 | { 0x90205, 0x0 }, | ||
2589 | { 0x190205, 0x0 }, | ||
2590 | { 0x290205, 0x0 }, | ||
2591 | { 0x90206, 0x0 }, | ||
2592 | { 0x190206, 0x0 }, | ||
2593 | { 0x290206, 0x0 }, | ||
2594 | { 0x90207, 0x0 }, | ||
2595 | { 0x190207, 0x0 }, | ||
2596 | { 0x290207, 0x0 }, | ||
2597 | { 0x90208, 0x0 }, | ||
2598 | { 0x190208, 0x0 }, | ||
2599 | { 0x290208, 0x0 }, | ||
2600 | { 0x10062, 0x0 }, | ||
2601 | { 0x10162, 0x0 }, | ||
2602 | { 0x10262, 0x0 }, | ||
2603 | { 0x10362, 0x0 }, | ||
2604 | { 0x10462, 0x0 }, | ||
2605 | { 0x10562, 0x0 }, | ||
2606 | { 0x10662, 0x0 }, | ||
2607 | { 0x10762, 0x0 }, | ||
2608 | { 0x10862, 0x0 }, | ||
2609 | { 0x11062, 0x0 }, | ||
2610 | { 0x11162, 0x0 }, | ||
2611 | { 0x11262, 0x0 }, | ||
2612 | { 0x11362, 0x0 }, | ||
2613 | { 0x11462, 0x0 }, | ||
2614 | { 0x11562, 0x0 }, | ||
2615 | { 0x11662, 0x0 }, | ||
2616 | { 0x11762, 0x0 }, | ||
2617 | { 0x11862, 0x0 }, | ||
2618 | { 0x12062, 0x0 }, | ||
2619 | { 0x12162, 0x0 }, | ||
2620 | { 0x12262, 0x0 }, | ||
2621 | { 0x12362, 0x0 }, | ||
2622 | { 0x12462, 0x0 }, | ||
2623 | { 0x12562, 0x0 }, | ||
2624 | { 0x12662, 0x0 }, | ||
2625 | { 0x12762, 0x0 }, | ||
2626 | { 0x12862, 0x0 }, | ||
2627 | { 0x13062, 0x0 }, | ||
2628 | { 0x13162, 0x0 }, | ||
2629 | { 0x13262, 0x0 }, | ||
2630 | { 0x13362, 0x0 }, | ||
2631 | { 0x13462, 0x0 }, | ||
2632 | { 0x13562, 0x0 }, | ||
2633 | { 0x13662, 0x0 }, | ||
2634 | { 0x13762, 0x0 }, | ||
2635 | { 0x13862, 0x0 }, | ||
2636 | { 0x20077, 0x0 }, | ||
2637 | { 0x10001, 0x0 }, | ||
2638 | { 0x11001, 0x0 }, | ||
2639 | { 0x12001, 0x0 }, | ||
2640 | { 0x13001, 0x0 }, | ||
2641 | { 0x10040, 0x0 }, | ||
2642 | { 0x10140, 0x0 }, | ||
2643 | { 0x10240, 0x0 }, | ||
2644 | { 0x10340, 0x0 }, | ||
2645 | { 0x10440, 0x0 }, | ||
2646 | { 0x10540, 0x0 }, | ||
2647 | { 0x10640, 0x0 }, | ||
2648 | { 0x10740, 0x0 }, | ||
2649 | { 0x10840, 0x0 }, | ||
2650 | { 0x10030, 0x0 }, | ||
2651 | { 0x10130, 0x0 }, | ||
2652 | { 0x10230, 0x0 }, | ||
2653 | { 0x10330, 0x0 }, | ||
2654 | { 0x10430, 0x0 }, | ||
2655 | { 0x10530, 0x0 }, | ||
2656 | { 0x10630, 0x0 }, | ||
2657 | { 0x10730, 0x0 }, | ||
2658 | { 0x10830, 0x0 }, | ||
2659 | { 0x11040, 0x0 }, | ||
2660 | { 0x11140, 0x0 }, | ||
2661 | { 0x11240, 0x0 }, | ||
2662 | { 0x11340, 0x0 }, | ||
2663 | { 0x11440, 0x0 }, | ||
2664 | { 0x11540, 0x0 }, | ||
2665 | { 0x11640, 0x0 }, | ||
2666 | { 0x11740, 0x0 }, | ||
2667 | { 0x11840, 0x0 }, | ||
2668 | { 0x11030, 0x0 }, | ||
2669 | { 0x11130, 0x0 }, | ||
2670 | { 0x11230, 0x0 }, | ||
2671 | { 0x11330, 0x0 }, | ||
2672 | { 0x11430, 0x0 }, | ||
2673 | { 0x11530, 0x0 }, | ||
2674 | { 0x11630, 0x0 }, | ||
2675 | { 0x11730, 0x0 }, | ||
2676 | { 0x11830, 0x0 }, | ||
2677 | { 0x12040, 0x0 }, | ||
2678 | { 0x12140, 0x0 }, | ||
2679 | { 0x12240, 0x0 }, | ||
2680 | { 0x12340, 0x0 }, | ||
2681 | { 0x12440, 0x0 }, | ||
2682 | { 0x12540, 0x0 }, | ||
2683 | { 0x12640, 0x0 }, | ||
2684 | { 0x12740, 0x0 }, | ||
2685 | { 0x12840, 0x0 }, | ||
2686 | { 0x12030, 0x0 }, | ||
2687 | { 0x12130, 0x0 }, | ||
2688 | { 0x12230, 0x0 }, | ||
2689 | { 0x12330, 0x0 }, | ||
2690 | { 0x12430, 0x0 }, | ||
2691 | { 0x12530, 0x0 }, | ||
2692 | { 0x12630, 0x0 }, | ||
2693 | { 0x12730, 0x0 }, | ||
2694 | { 0x12830, 0x0 }, | ||
2695 | { 0x13040, 0x0 }, | ||
2696 | { 0x13140, 0x0 }, | ||
2697 | { 0x13240, 0x0 }, | ||
2698 | { 0x13340, 0x0 }, | ||
2699 | { 0x13440, 0x0 }, | ||
2700 | { 0x13540, 0x0 }, | ||
2701 | { 0x13640, 0x0 }, | ||
2702 | { 0x13740, 0x0 }, | ||
2703 | { 0x13840, 0x0 }, | ||
2704 | { 0x13030, 0x0 }, | ||
2705 | { 0x13130, 0x0 }, | ||
2706 | { 0x13230, 0x0 }, | ||
2707 | { 0x13330, 0x0 }, | ||
2708 | { 0x13430, 0x0 }, | ||
2709 | { 0x13530, 0x0 }, | ||
2710 | { 0x13630, 0x0 }, | ||
2711 | { 0x13730, 0x0 }, | ||
2712 | { 0x13830, 0x0 }, | ||
2713 | }; | ||
2714 | /* P0 message block paremeter for training firmware */ | ||
2715 | struct dram_cfg_param ddr_fsp0_cfg[] = { | ||
2716 | {0xd0000, 0x0}, | ||
2717 | {0x54003,0xc80}, | ||
2718 | {0x54004,0x2}, | ||
2719 | {0x54005,0x2228}, | ||
2720 | {0x54006,0x11}, | ||
2721 | {0x54008,0x131f}, | ||
2722 | {0x54009,0xc8}, | ||
2723 | {0x5400b,0x2}, | ||
2724 | {0x5400d,0x100}, | ||
2725 | {0x54012,0x110}, | ||
2726 | {0x54019,0x2dd4}, | ||
2727 | {0x5401a,0x31}, | ||
2728 | {0x5401b,0x4a66}, | ||
2729 | {0x5401c,0x4a08}, | ||
2730 | {0x5401e,0x16}, | ||
2731 | {0x5401f,0x2dd4}, | ||
2732 | {0x54020,0x31}, | ||
2733 | {0x54021,0x4a66}, | ||
2734 | {0x54022,0x4a08}, | ||
2735 | {0x54024,0x16}, | ||
2736 | {0x5402b,0x1000}, | ||
2737 | {0x5402c,0x1}, | ||
2738 | {0x54032,0xd400}, | ||
2739 | {0x54033,0x312d}, | ||
2740 | {0x54034,0x6600}, | ||
2741 | {0x54035,0x84a}, | ||
2742 | {0x54036,0x4a}, | ||
2743 | {0x54037,0x1600}, | ||
2744 | {0x54038,0xd400}, | ||
2745 | {0x54039,0x312d}, | ||
2746 | {0x5403a,0x6600}, | ||
2747 | {0x5403b,0x84a}, | ||
2748 | {0x5403c,0x4a}, | ||
2749 | {0x5403d,0x1600}, | ||
2750 | {0xd0000, 0x1}, | ||
2751 | }; | ||
2752 | |||
2753 | |||
2754 | /* P1 message block paremeter for training firmware */ | ||
2755 | struct dram_cfg_param ddr_fsp1_cfg[] = { | ||
2756 | {0xd0000, 0x0}, | ||
2757 | {0x54002,0x1}, | ||
2758 | {0x54003,0x29c}, | ||
2759 | {0x54004,0x2}, | ||
2760 | {0x54005,0x2228}, | ||
2761 | {0x54006,0x11}, | ||
2762 | {0x54008,0x121f}, | ||
2763 | {0x54009,0xc8}, | ||
2764 | {0x5400b,0x2}, | ||
2765 | {0x5400d,0x100}, | ||
2766 | {0x54012,0x110}, | ||
2767 | {0x54019,0x994}, | ||
2768 | {0x5401a,0x31}, | ||
2769 | {0x5401b,0x4a66}, | ||
2770 | {0x5401c,0x4a08}, | ||
2771 | {0x5401e,0x16}, | ||
2772 | {0x5401f,0x994}, | ||
2773 | {0x54020,0x31}, | ||
2774 | {0x54021,0x4a66}, | ||
2775 | {0x54022,0x4a08}, | ||
2776 | {0x54024,0x16}, | ||
2777 | {0x5402b,0x1000}, | ||
2778 | {0x5402c,0x1}, | ||
2779 | {0x54032,0x9400}, | ||
2780 | {0x54033,0x3109}, | ||
2781 | {0x54034,0x6600}, | ||
2782 | {0x54035,0x84a}, | ||
2783 | {0x54036,0x4a}, | ||
2784 | {0x54037,0x1600}, | ||
2785 | {0x54038,0x9400}, | ||
2786 | {0x54039,0x3109}, | ||
2787 | {0x5403a,0x6600}, | ||
2788 | {0x5403b,0x84a}, | ||
2789 | {0x5403c,0x4a}, | ||
2790 | {0x5403d,0x1600}, | ||
2791 | {0xd0000, 0x1}, | ||
2792 | }; | ||
2793 | |||
2794 | |||
2795 | /* P0 2D message block paremeter for training firmware */ | ||
2796 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | ||
2797 | {0xd0000, 0x0}, | ||
2798 | {0x54003,0xc80}, | ||
2799 | {0x54004,0x2}, | ||
2800 | {0x54005,0x2228}, | ||
2801 | {0x54006,0x11}, | ||
2802 | {0x54008,0x61}, | ||
2803 | {0x54009,0xc8}, | ||
2804 | {0x5400b,0x2}, | ||
2805 | {0x5400f,0x100}, | ||
2806 | {0x54010,0x1f7f}, | ||
2807 | {0x54012,0x110}, | ||
2808 | {0x54019,0x2dd4}, | ||
2809 | {0x5401a,0x31}, | ||
2810 | {0x5401b,0x4a66}, | ||
2811 | {0x5401c,0x4a08}, | ||
2812 | {0x5401e,0x16}, | ||
2813 | {0x5401f,0x2dd4}, | ||
2814 | {0x54020,0x31}, | ||
2815 | {0x54021,0x4a66}, | ||
2816 | {0x54022,0x4a08}, | ||
2817 | {0x54024,0x16}, | ||
2818 | {0x5402b,0x1000}, | ||
2819 | {0x5402c,0x1}, | ||
2820 | {0x54032,0xd400}, | ||
2821 | {0x54033,0x312d}, | ||
2822 | {0x54034,0x6600}, | ||
2823 | {0x54035,0x84a}, | ||
2824 | {0x54036,0x4a}, | ||
2825 | {0x54037,0x1600}, | ||
2826 | {0x54038,0xd400}, | ||
2827 | {0x54039,0x312d}, | ||
2828 | {0x5403a,0x6600}, | ||
2829 | {0x5403b,0x84a}, | ||
2830 | {0x5403c,0x4a}, | ||
2831 | {0x5403d,0x1600}, | ||
2832 | { 0xd0000, 0x1 }, | ||
2833 | }; | ||
2834 | |||
2835 | /* DRAM PHY init engine image */ | ||
2836 | struct dram_cfg_param ddr_phy_pie[] = { | ||
2837 | {0xd0000, 0x0}, | ||
2838 | {0x90000,0x10}, | ||
2839 | {0x90001,0x400}, | ||
2840 | {0x90002,0x10e}, | ||
2841 | {0x90003,0x0}, | ||
2842 | {0x90004,0x0}, | ||
2843 | {0x90005,0x8}, | ||
2844 | {0x90029,0xb}, | ||
2845 | {0x9002a,0x480}, | ||
2846 | {0x9002b,0x109}, | ||
2847 | {0x9002c,0x8}, | ||
2848 | {0x9002d,0x448}, | ||
2849 | {0x9002e,0x139}, | ||
2850 | {0x9002f,0x8}, | ||
2851 | {0x90030,0x478}, | ||
2852 | {0x90031,0x109}, | ||
2853 | {0x90032,0x0}, | ||
2854 | {0x90033,0xe8}, | ||
2855 | {0x90034,0x109}, | ||
2856 | {0x90035,0x2}, | ||
2857 | {0x90036,0x10}, | ||
2858 | {0x90037,0x139}, | ||
2859 | {0x90038,0xf}, | ||
2860 | {0x90039,0x7c0}, | ||
2861 | {0x9003a,0x139}, | ||
2862 | {0x9003b,0x44}, | ||
2863 | {0x9003c,0x630}, | ||
2864 | {0x9003d,0x159}, | ||
2865 | {0x9003e,0x14f}, | ||
2866 | {0x9003f,0x630}, | ||
2867 | {0x90040,0x159}, | ||
2868 | {0x90041,0x47}, | ||
2869 | {0x90042,0x630}, | ||
2870 | {0x90043,0x149}, | ||
2871 | {0x90044,0x4f}, | ||
2872 | {0x90045,0x630}, | ||
2873 | {0x90046,0x179}, | ||
2874 | {0x90047,0x8}, | ||
2875 | {0x90048,0xe0}, | ||
2876 | {0x90049,0x109}, | ||
2877 | {0x9004a,0x0}, | ||
2878 | {0x9004b,0x7c8}, | ||
2879 | {0x9004c,0x109}, | ||
2880 | {0x9004d,0x0}, | ||
2881 | {0x9004e,0x1}, | ||
2882 | {0x9004f,0x8}, | ||
2883 | {0x90050,0x0}, | ||
2884 | {0x90051,0x45a}, | ||
2885 | {0x90052,0x9}, | ||
2886 | {0x90053,0x0}, | ||
2887 | {0x90054,0x448}, | ||
2888 | {0x90055,0x109}, | ||
2889 | {0x90056,0x40}, | ||
2890 | {0x90057,0x630}, | ||
2891 | {0x90058,0x179}, | ||
2892 | {0x90059,0x1}, | ||
2893 | {0x9005a,0x618}, | ||
2894 | {0x9005b,0x109}, | ||
2895 | {0x9005c,0x40c0}, | ||
2896 | {0x9005d,0x630}, | ||
2897 | {0x9005e,0x149}, | ||
2898 | {0x9005f,0x8}, | ||
2899 | {0x90060,0x4}, | ||
2900 | {0x90061,0x48}, | ||
2901 | {0x90062,0x4040}, | ||
2902 | {0x90063,0x630}, | ||
2903 | {0x90064,0x149}, | ||
2904 | {0x90065,0x0}, | ||
2905 | {0x90066,0x4}, | ||
2906 | {0x90067,0x48}, | ||
2907 | {0x90068,0x40}, | ||
2908 | {0x90069,0x630}, | ||
2909 | {0x9006a,0x149}, | ||
2910 | {0x9006b,0x10}, | ||
2911 | {0x9006c,0x4}, | ||
2912 | {0x9006d,0x18}, | ||
2913 | {0x9006e,0x0}, | ||
2914 | {0x9006f,0x4}, | ||
2915 | {0x90070,0x78}, | ||
2916 | {0x90071,0x549}, | ||
2917 | {0x90072,0x630}, | ||
2918 | {0x90073,0x159}, | ||
2919 | {0x90074,0xd49}, | ||
2920 | {0x90075,0x630}, | ||
2921 | {0x90076,0x159}, | ||
2922 | {0x90077,0x94a}, | ||
2923 | {0x90078,0x630}, | ||
2924 | {0x90079,0x159}, | ||
2925 | {0x9007a,0x441}, | ||
2926 | {0x9007b,0x630}, | ||
2927 | {0x9007c,0x149}, | ||
2928 | {0x9007d,0x42}, | ||
2929 | {0x9007e,0x630}, | ||
2930 | {0x9007f,0x149}, | ||
2931 | {0x90080,0x1}, | ||
2932 | {0x90081,0x630}, | ||
2933 | {0x90082,0x149}, | ||
2934 | {0x90083,0x0}, | ||
2935 | {0x90084,0xe0}, | ||
2936 | {0x90085,0x109}, | ||
2937 | {0x90086,0xa}, | ||
2938 | {0x90087,0x10}, | ||
2939 | {0x90088,0x109}, | ||
2940 | {0x90089,0x9}, | ||
2941 | {0x9008a,0x3c0}, | ||
2942 | {0x9008b,0x149}, | ||
2943 | {0x9008c,0x9}, | ||
2944 | {0x9008d,0x3c0}, | ||
2945 | {0x9008e,0x159}, | ||
2946 | {0x9008f,0x18}, | ||
2947 | {0x90090,0x10}, | ||
2948 | {0x90091,0x109}, | ||
2949 | {0x90092,0x0}, | ||
2950 | {0x90093,0x3c0}, | ||
2951 | {0x90094,0x109}, | ||
2952 | {0x90095,0x18}, | ||
2953 | {0x90096,0x4}, | ||
2954 | {0x90097,0x48}, | ||
2955 | {0x90098,0x18}, | ||
2956 | {0x90099,0x4}, | ||
2957 | {0x9009a,0x58}, | ||
2958 | {0x9009b,0xa}, | ||
2959 | {0x9009c,0x10}, | ||
2960 | {0x9009d,0x109}, | ||
2961 | {0x9009e,0x2}, | ||
2962 | {0x9009f,0x10}, | ||
2963 | {0x900a0,0x109}, | ||
2964 | {0x900a1,0x5}, | ||
2965 | {0x900a2,0x7c0}, | ||
2966 | {0x900a3,0x109}, | ||
2967 | {0x900a4,0x10}, | ||
2968 | {0x900a5,0x10}, | ||
2969 | {0x900a6,0x109}, | ||
2970 | {0x40000,0x811}, | ||
2971 | {0x40020,0x880}, | ||
2972 | {0x40040,0x0}, | ||
2973 | {0x40060,0x0}, | ||
2974 | {0x40001,0x4008}, | ||
2975 | {0x40021,0x83}, | ||
2976 | {0x40041,0x4f}, | ||
2977 | {0x40061,0x0}, | ||
2978 | {0x40002,0x4040}, | ||
2979 | {0x40022,0x83}, | ||
2980 | {0x40042,0x51}, | ||
2981 | {0x40062,0x0}, | ||
2982 | {0x40003,0x811}, | ||
2983 | {0x40023,0x880}, | ||
2984 | {0x40043,0x0}, | ||
2985 | {0x40063,0x0}, | ||
2986 | {0x40004,0x720}, | ||
2987 | {0x40024,0xf}, | ||
2988 | {0x40044,0x1740}, | ||
2989 | {0x40064,0x0}, | ||
2990 | {0x40005,0x16}, | ||
2991 | {0x40025,0x83}, | ||
2992 | {0x40045,0x4b}, | ||
2993 | {0x40065,0x0}, | ||
2994 | {0x40006,0x716}, | ||
2995 | {0x40026,0xf}, | ||
2996 | {0x40046,0x2001}, | ||
2997 | {0x40066,0x0}, | ||
2998 | {0x40007,0x716}, | ||
2999 | {0x40027,0xf}, | ||
3000 | {0x40047,0x2800}, | ||
3001 | {0x40067,0x0}, | ||
3002 | {0x40008,0x716}, | ||
3003 | {0x40028,0xf}, | ||
3004 | {0x40048,0xf00}, | ||
3005 | {0x40068,0x0}, | ||
3006 | {0x40009,0x720}, | ||
3007 | {0x40029,0xf}, | ||
3008 | {0x40049,0x1400}, | ||
3009 | {0x40069,0x0}, | ||
3010 | {0x4000a,0xe08}, | ||
3011 | {0x4002a,0xc15}, | ||
3012 | {0x4004a,0x0}, | ||
3013 | {0x4006a,0x0}, | ||
3014 | {0x4000b,0x623}, | ||
3015 | {0x4002b,0x15}, | ||
3016 | {0x4004b,0x0}, | ||
3017 | {0x4006b,0x0}, | ||
3018 | {0x4000c,0x4028}, | ||
3019 | {0x4002c,0x80}, | ||
3020 | {0x4004c,0x0}, | ||
3021 | {0x4006c,0x0}, | ||
3022 | {0x4000d,0xe08}, | ||
3023 | {0x4002d,0xc1a}, | ||
3024 | {0x4004d,0x0}, | ||
3025 | {0x4006d,0x0}, | ||
3026 | {0x4000e,0x623}, | ||
3027 | {0x4002e,0x1a}, | ||
3028 | {0x4004e,0x0}, | ||
3029 | {0x4006e,0x0}, | ||
3030 | {0x4000f,0x4040}, | ||
3031 | {0x4002f,0x80}, | ||
3032 | {0x4004f,0x0}, | ||
3033 | {0x4006f,0x0}, | ||
3034 | {0x40010,0x2604}, | ||
3035 | {0x40030,0x15}, | ||
3036 | {0x40050,0x0}, | ||
3037 | {0x40070,0x0}, | ||
3038 | {0x40011,0x708}, | ||
3039 | {0x40031,0x5}, | ||
3040 | {0x40051,0x0}, | ||
3041 | {0x40071,0x2002}, | ||
3042 | {0x40012,0x8}, | ||
3043 | {0x40032,0x80}, | ||
3044 | {0x40052,0x0}, | ||
3045 | {0x40072,0x0}, | ||
3046 | {0x40013,0x2604}, | ||
3047 | {0x40033,0x1a}, | ||
3048 | {0x40053,0x0}, | ||
3049 | {0x40073,0x0}, | ||
3050 | {0x40014,0x708}, | ||
3051 | {0x40034,0xa}, | ||
3052 | {0x40054,0x0}, | ||
3053 | {0x40074,0x2002}, | ||
3054 | {0x40015,0x4040}, | ||
3055 | {0x40035,0x80}, | ||
3056 | {0x40055,0x0}, | ||
3057 | {0x40075,0x0}, | ||
3058 | {0x40016,0x60a}, | ||
3059 | {0x40036,0x15}, | ||
3060 | {0x40056,0x1200}, | ||
3061 | {0x40076,0x0}, | ||
3062 | {0x40017,0x61a}, | ||
3063 | {0x40037,0x15}, | ||
3064 | {0x40057,0x1300}, | ||
3065 | {0x40077,0x0}, | ||
3066 | {0x40018,0x60a}, | ||
3067 | {0x40038,0x1a}, | ||
3068 | {0x40058,0x1200}, | ||
3069 | {0x40078,0x0}, | ||
3070 | {0x40019,0x642}, | ||
3071 | {0x40039,0x1a}, | ||
3072 | {0x40059,0x1300}, | ||
3073 | {0x40079,0x0}, | ||
3074 | {0x4001a,0x4808}, | ||
3075 | {0x4003a,0x880}, | ||
3076 | {0x4005a,0x0}, | ||
3077 | {0x4007a,0x0}, | ||
3078 | {0x900a7,0x0}, | ||
3079 | {0x900a8,0x790}, | ||
3080 | {0x900a9,0x11a}, | ||
3081 | {0x900aa,0x8}, | ||
3082 | {0x900ab,0x7aa}, | ||
3083 | {0x900ac,0x2a}, | ||
3084 | {0x900ad,0x10}, | ||
3085 | {0x900ae,0x7b2}, | ||
3086 | {0x900af,0x2a}, | ||
3087 | {0x900b0,0x0}, | ||
3088 | {0x900b1,0x7c8}, | ||
3089 | {0x900b2,0x109}, | ||
3090 | {0x900b3,0x10}, | ||
3091 | {0x900b4,0x2a8}, | ||
3092 | {0x900b5,0x129}, | ||
3093 | {0x900b6,0x8}, | ||
3094 | {0x900b7,0x370}, | ||
3095 | {0x900b8,0x129}, | ||
3096 | {0x900b9,0xa}, | ||
3097 | {0x900ba,0x3c8}, | ||
3098 | {0x900bb,0x1a9}, | ||
3099 | {0x900bc,0xc}, | ||
3100 | {0x900bd,0x408}, | ||
3101 | {0x900be,0x199}, | ||
3102 | {0x900bf,0x14}, | ||
3103 | {0x900c0,0x790}, | ||
3104 | {0x900c1,0x11a}, | ||
3105 | {0x900c2,0x8}, | ||
3106 | {0x900c3,0x4}, | ||
3107 | {0x900c4,0x18}, | ||
3108 | {0x900c5,0xe}, | ||
3109 | {0x900c6,0x408}, | ||
3110 | {0x900c7,0x199}, | ||
3111 | {0x900c8,0x8}, | ||
3112 | {0x900c9,0x8568}, | ||
3113 | {0x900ca,0x108}, | ||
3114 | {0x900cb,0x18}, | ||
3115 | {0x900cc,0x790}, | ||
3116 | {0x900cd,0x16a}, | ||
3117 | {0x900ce,0x8}, | ||
3118 | {0x900cf,0x1d8}, | ||
3119 | {0x900d0,0x169}, | ||
3120 | {0x900d1,0x10}, | ||
3121 | {0x900d2,0x8558}, | ||
3122 | {0x900d3,0x168}, | ||
3123 | {0x900d4,0x70}, | ||
3124 | {0x900d5,0x788}, | ||
3125 | {0x900d6,0x16a}, | ||
3126 | {0x900d7,0x1ff8}, | ||
3127 | {0x900d8,0x85a8}, | ||
3128 | {0x900d9,0x1e8}, | ||
3129 | {0x900da,0x50}, | ||
3130 | {0x900db,0x798}, | ||
3131 | {0x900dc,0x16a}, | ||
3132 | {0x900dd,0x60}, | ||
3133 | {0x900de,0x7a0}, | ||
3134 | {0x900df,0x16a}, | ||
3135 | {0x900e0,0x8}, | ||
3136 | {0x900e1,0x8310}, | ||
3137 | {0x900e2,0x168}, | ||
3138 | {0x900e3,0x8}, | ||
3139 | {0x900e4,0xa310}, | ||
3140 | {0x900e5,0x168}, | ||
3141 | {0x900e6,0xa}, | ||
3142 | {0x900e7,0x408}, | ||
3143 | {0x900e8,0x169}, | ||
3144 | {0x900e9,0x6e}, | ||
3145 | {0x900ea,0x0}, | ||
3146 | {0x900eb,0x68}, | ||
3147 | {0x900ec,0x0}, | ||
3148 | {0x900ed,0x408}, | ||
3149 | {0x900ee,0x169}, | ||
3150 | {0x900ef,0x0}, | ||
3151 | {0x900f0,0x8310}, | ||
3152 | {0x900f1,0x168}, | ||
3153 | {0x900f2,0x0}, | ||
3154 | {0x900f3,0xa310}, | ||
3155 | {0x900f4,0x168}, | ||
3156 | {0x900f5,0x1ff8}, | ||
3157 | {0x900f6,0x85a8}, | ||
3158 | {0x900f7,0x1e8}, | ||
3159 | {0x900f8,0x68}, | ||
3160 | {0x900f9,0x798}, | ||
3161 | {0x900fa,0x16a}, | ||
3162 | {0x900fb,0x78}, | ||
3163 | {0x900fc,0x7a0}, | ||
3164 | {0x900fd,0x16a}, | ||
3165 | {0x900fe,0x68}, | ||
3166 | {0x900ff,0x790}, | ||
3167 | {0x90100,0x16a}, | ||
3168 | {0x90101,0x8}, | ||
3169 | {0x90102,0x8b10}, | ||
3170 | {0x90103,0x168}, | ||
3171 | {0x90104,0x8}, | ||
3172 | {0x90105,0xab10}, | ||
3173 | {0x90106,0x168}, | ||
3174 | {0x90107,0xa}, | ||
3175 | {0x90108,0x408}, | ||
3176 | {0x90109,0x169}, | ||
3177 | {0x9010a,0x58}, | ||
3178 | {0x9010b,0x0}, | ||
3179 | {0x9010c,0x68}, | ||
3180 | {0x9010d,0x0}, | ||
3181 | {0x9010e,0x408}, | ||
3182 | {0x9010f,0x169}, | ||
3183 | {0x90110,0x0}, | ||
3184 | {0x90111,0x8b10}, | ||
3185 | {0x90112,0x168}, | ||
3186 | {0x90113,0x0}, | ||
3187 | {0x90114,0xab10}, | ||
3188 | {0x90115,0x168}, | ||
3189 | {0x90116,0x0}, | ||
3190 | {0x90117,0x1d8}, | ||
3191 | {0x90118,0x169}, | ||
3192 | {0x90119,0x80}, | ||
3193 | {0x9011a,0x790}, | ||
3194 | {0x9011b,0x16a}, | ||
3195 | {0x9011c,0x18}, | ||
3196 | {0x9011d,0x7aa}, | ||
3197 | {0x9011e,0x6a}, | ||
3198 | {0x9011f,0xa}, | ||
3199 | {0x90120,0x0}, | ||
3200 | {0x90121,0x1e9}, | ||
3201 | {0x90122,0x8}, | ||
3202 | {0x90123,0x8080}, | ||
3203 | {0x90124,0x108}, | ||
3204 | {0x90125,0xf}, | ||
3205 | {0x90126,0x408}, | ||
3206 | {0x90127,0x169}, | ||
3207 | {0x90128,0xc}, | ||
3208 | {0x90129,0x0}, | ||
3209 | {0x9012a,0x68}, | ||
3210 | {0x9012b,0x9}, | ||
3211 | {0x9012c,0x0}, | ||
3212 | {0x9012d,0x1a9}, | ||
3213 | {0x9012e,0x0}, | ||
3214 | {0x9012f,0x408}, | ||
3215 | {0x90130,0x169}, | ||
3216 | {0x90131,0x0}, | ||
3217 | {0x90132,0x8080}, | ||
3218 | {0x90133,0x108}, | ||
3219 | {0x90134,0x8}, | ||
3220 | {0x90135,0x7aa}, | ||
3221 | {0x90136,0x6a}, | ||
3222 | {0x90137,0x0}, | ||
3223 | {0x90138,0x8568}, | ||
3224 | {0x90139,0x108}, | ||
3225 | {0x9013a,0xb7}, | ||
3226 | {0x9013b,0x790}, | ||
3227 | {0x9013c,0x16a}, | ||
3228 | {0x9013d,0x1f}, | ||
3229 | {0x9013e,0x0}, | ||
3230 | {0x9013f,0x68}, | ||
3231 | {0x90140,0x8}, | ||
3232 | {0x90141,0x8558}, | ||
3233 | {0x90142,0x168}, | ||
3234 | {0x90143,0xf}, | ||
3235 | {0x90144,0x408}, | ||
3236 | {0x90145,0x169}, | ||
3237 | {0x90146,0xc}, | ||
3238 | {0x90147,0x0}, | ||
3239 | {0x90148,0x68}, | ||
3240 | {0x90149,0x0}, | ||
3241 | {0x9014a,0x408}, | ||
3242 | {0x9014b,0x169}, | ||
3243 | {0x9014c,0x0}, | ||
3244 | {0x9014d,0x8558}, | ||
3245 | {0x9014e,0x168}, | ||
3246 | {0x9014f,0x8}, | ||
3247 | {0x90150,0x3c8}, | ||
3248 | {0x90151,0x1a9}, | ||
3249 | {0x90152,0x3}, | ||
3250 | {0x90153,0x370}, | ||
3251 | {0x90154,0x129}, | ||
3252 | {0x90155,0x20}, | ||
3253 | {0x90156,0x2aa}, | ||
3254 | {0x90157,0x9}, | ||
3255 | {0x90158,0x0}, | ||
3256 | {0x90159,0x400}, | ||
3257 | {0x9015a,0x10e}, | ||
3258 | {0x9015b,0x8}, | ||
3259 | {0x9015c,0xe8}, | ||
3260 | {0x9015d,0x109}, | ||
3261 | {0x9015e,0x0}, | ||
3262 | {0x9015f,0x8140}, | ||
3263 | {0x90160,0x10c}, | ||
3264 | {0x90161,0x10}, | ||
3265 | {0x90162,0x8138}, | ||
3266 | {0x90163,0x10c}, | ||
3267 | {0x90164,0x8}, | ||
3268 | {0x90165,0x7c8}, | ||
3269 | {0x90166,0x101}, | ||
3270 | {0x90167,0x8}, | ||
3271 | {0x90168,0x0}, | ||
3272 | {0x90169,0x8}, | ||
3273 | {0x9016a,0x8}, | ||
3274 | {0x9016b,0x448}, | ||
3275 | {0x9016c,0x109}, | ||
3276 | {0x9016d,0xf}, | ||
3277 | {0x9016e,0x7c0}, | ||
3278 | {0x9016f,0x109}, | ||
3279 | {0x90170,0x0}, | ||
3280 | {0x90171,0xe8}, | ||
3281 | {0x90172,0x109}, | ||
3282 | {0x90173,0x47}, | ||
3283 | {0x90174,0x630}, | ||
3284 | {0x90175,0x109}, | ||
3285 | {0x90176,0x8}, | ||
3286 | {0x90177,0x618}, | ||
3287 | {0x90178,0x109}, | ||
3288 | {0x90179,0x8}, | ||
3289 | {0x9017a,0xe0}, | ||
3290 | {0x9017b,0x109}, | ||
3291 | {0x9017c,0x0}, | ||
3292 | {0x9017d,0x7c8}, | ||
3293 | {0x9017e,0x109}, | ||
3294 | {0x9017f,0x8}, | ||
3295 | {0x90180,0x8140}, | ||
3296 | {0x90181,0x10c}, | ||
3297 | {0x90182,0x0}, | ||
3298 | {0x90183,0x1}, | ||
3299 | {0x90184,0x8}, | ||
3300 | {0x90185,0x8}, | ||
3301 | {0x90186,0x4}, | ||
3302 | {0x90187,0x8}, | ||
3303 | {0x90188,0x8}, | ||
3304 | {0x90189,0x7c8}, | ||
3305 | {0x9018a,0x101}, | ||
3306 | {0x90006,0x0}, | ||
3307 | {0x90007,0x0}, | ||
3308 | {0x90008,0x8}, | ||
3309 | {0x90009,0x0}, | ||
3310 | {0x9000a,0x0}, | ||
3311 | {0x9000b,0x0}, | ||
3312 | {0xd00e7,0x400}, | ||
3313 | {0x90017,0x0}, | ||
3314 | {0x9001f,0x2a}, | ||
3315 | {0x90026,0x6a}, | ||
3316 | {0x400d0,0x0}, | ||
3317 | {0x400d1,0x101}, | ||
3318 | {0x400d2,0x105}, | ||
3319 | {0x400d3,0x107}, | ||
3320 | {0x400d4,0x10f}, | ||
3321 | {0x400d5,0x202}, | ||
3322 | {0x400d6,0x20a}, | ||
3323 | {0x400d7,0x20b}, | ||
3324 | {0x2003a,0x2}, | ||
3325 | {0x2000b,0x64}, | ||
3326 | {0x2000c,0xc8}, | ||
3327 | {0x2000d,0x7d0}, | ||
3328 | {0x2000e,0x2c}, | ||
3329 | {0x12000b,0x14}, | ||
3330 | {0x12000c,0x29}, | ||
3331 | {0x12000d,0x1a1}, | ||
3332 | {0x12000e,0x10}, | ||
3333 | {0x9000c,0x0}, | ||
3334 | {0x9000d,0x173}, | ||
3335 | {0x9000e,0x60}, | ||
3336 | {0x9000f,0x6110}, | ||
3337 | {0x90010,0x2152}, | ||
3338 | {0x90011,0xdfbd}, | ||
3339 | {0x90012,0x60}, | ||
3340 | {0x90013,0x6152}, | ||
3341 | {0x20010,0x5a}, | ||
3342 | {0x20011,0x3}, | ||
3343 | {0x120010,0x5a}, | ||
3344 | {0x120011,0x3}, | ||
3345 | {0x40080,0xe0}, | ||
3346 | {0x40081,0x12}, | ||
3347 | {0x40082,0xe0}, | ||
3348 | {0x40083,0x12}, | ||
3349 | {0x40084,0xe0}, | ||
3350 | {0x40085,0x12}, | ||
3351 | {0x140080,0xe0}, | ||
3352 | {0x140081,0x12}, | ||
3353 | {0x140082,0xe0}, | ||
3354 | {0x140083,0x12}, | ||
3355 | {0x140084,0xe0}, | ||
3356 | {0x140085,0x12}, | ||
3357 | {0x400fd,0xf}, | ||
3358 | {0x10011,0x1}, | ||
3359 | {0x10012,0x1}, | ||
3360 | {0x10013,0x180}, | ||
3361 | {0x10018,0x1}, | ||
3362 | {0x10002,0x6209}, | ||
3363 | {0x100b2,0x1}, | ||
3364 | {0x101b4,0x1}, | ||
3365 | {0x102b4,0x1}, | ||
3366 | {0x103b4,0x1}, | ||
3367 | {0x104b4,0x1}, | ||
3368 | {0x105b4,0x1}, | ||
3369 | {0x106b4,0x1}, | ||
3370 | {0x107b4,0x1}, | ||
3371 | {0x108b4,0x1}, | ||
3372 | {0x11011,0x1}, | ||
3373 | {0x11012,0x1}, | ||
3374 | {0x11013,0x180}, | ||
3375 | {0x11018,0x1}, | ||
3376 | {0x11002,0x6209}, | ||
3377 | {0x110b2,0x1}, | ||
3378 | {0x111b4,0x1}, | ||
3379 | {0x112b4,0x1}, | ||
3380 | {0x113b4,0x1}, | ||
3381 | {0x114b4,0x1}, | ||
3382 | {0x115b4,0x1}, | ||
3383 | {0x116b4,0x1}, | ||
3384 | {0x117b4,0x1}, | ||
3385 | {0x118b4,0x1}, | ||
3386 | {0x12011,0x1}, | ||
3387 | {0x12012,0x1}, | ||
3388 | {0x12013,0x180}, | ||
3389 | {0x12018,0x1}, | ||
3390 | {0x12002,0x6209}, | ||
3391 | {0x120b2,0x1}, | ||
3392 | {0x121b4,0x1}, | ||
3393 | {0x122b4,0x1}, | ||
3394 | {0x123b4,0x1}, | ||
3395 | {0x124b4,0x1}, | ||
3396 | {0x125b4,0x1}, | ||
3397 | {0x126b4,0x1}, | ||
3398 | {0x127b4,0x1}, | ||
3399 | {0x128b4,0x1}, | ||
3400 | {0x13011,0x1}, | ||
3401 | {0x13012,0x1}, | ||
3402 | {0x13013,0x180}, | ||
3403 | {0x13018,0x1}, | ||
3404 | {0x13002,0x6209}, | ||
3405 | {0x130b2,0x1}, | ||
3406 | {0x131b4,0x1}, | ||
3407 | {0x132b4,0x1}, | ||
3408 | {0x133b4,0x1}, | ||
3409 | {0x134b4,0x1}, | ||
3410 | {0x135b4,0x1}, | ||
3411 | {0x136b4,0x1}, | ||
3412 | {0x137b4,0x1}, | ||
3413 | {0x138b4,0x1}, | ||
3414 | {0x2003a,0x2}, | ||
3415 | {0xc0080,0x2}, | ||
3416 | {0xd0000, 0x1} | ||
3417 | }; | ||
3418 | |||
3419 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | ||
3420 | { | ||
3421 | /* P0 3200mts 1D */ | ||
3422 | .drate = 3200, | ||
3423 | .fw_type = FW_1D_IMAGE, | ||
3424 | .fsp_cfg = ddr_fsp0_cfg, | ||
3425 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | ||
3426 | }, | ||
3427 | { | ||
3428 | /* P1 667mts 1D */ | ||
3429 | .drate = 667, | ||
3430 | .fw_type = FW_1D_IMAGE, | ||
3431 | .fsp_cfg = ddr_fsp1_cfg, | ||
3432 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | ||
3433 | }, | ||
3434 | { | ||
3435 | /* P0 3200mts 2D */ | ||
3436 | .drate = 3200, | ||
3437 | .fw_type = FW_2D_IMAGE, | ||
3438 | .fsp_cfg = ddr_fsp0_2d_cfg, | ||
3439 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | ||
3440 | }, | ||
3441 | }; | ||
3442 | |||
3443 | /* ddr timing config params */ | ||
3444 | struct dram_timing_info dram_timing = { | ||
3445 | .ddrc_cfg = ddr_ddrc_cfg, | ||
3446 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | ||
3447 | .ddrphy_cfg = ddr_ddrphy_cfg, | ||
3448 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | ||
3449 | .fsp_msg = ddr_dram_fsp_msg, | ||
3450 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | ||
3451 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | ||
3452 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | ||
3453 | .ddrphy_pie = ddr_phy_pie, | ||
3454 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | ||
3455 | .fsp_table = { 3200, 667, }, | ||
3456 | }; | ||
3457 | #elif defined(CONFIG_4GB_LPDDR4) | ||
3458 | struct dram_cfg_param ddr_ddrc_cfg[] = { | ||
3459 | /** Initialize DDRC registers **/ | ||
3460 | {0x3d400304,0x1}, | ||
3461 | {0x3d400030,0x1}, | ||
3462 | {0x3d400000,0xa3080020}, | ||
3463 | {0x3d400028,0x0}, | ||
3464 | {0x3d400020,0x203}, | ||
3465 | {0x3d400024,0x3e800}, | ||
3466 | {0x3d400064,0x6100e0}, | ||
3467 | {0x3d4000d0,0xc003061c}, | ||
3468 | {0x3d4000d4,0x9e0000}, | ||
3469 | {0x3d4000dc,0xd4002d}, | ||
3470 | {0x3d4000e0,0x310008}, | ||
3471 | {0x3d4000e8,0x66004a}, | ||
3472 | {0x3d4000ec,0x16004a}, | ||
3473 | {0x3d400100,0x1a201b22}, | ||
3474 | {0x3d400104,0x60633}, | ||
3475 | {0x3d40010c,0xc0c000}, | ||
3476 | {0x3d400110,0xf04080f}, | ||
3477 | {0x3d400114,0x2040c0c}, | ||
3478 | {0x3d400118,0x1010007}, | ||
3479 | {0x3d40011c,0x401}, | ||
3480 | {0x3d400130,0x20600}, | ||
3481 | {0x3d400134,0xc100002}, | ||
3482 | {0x3d400138,0xe6}, | ||
3483 | {0x3d400144,0xa00050}, | ||
3484 | {0x3d400180,0xc3200018}, | ||
3485 | {0x3d400184,0x28061a8}, | ||
3486 | {0x3d400188,0x0}, | ||
3487 | {0x3d400190,0x497820a}, | ||
3488 | {0x3d400194,0x80303}, | ||
3489 | {0x3d4001a0,0xe0400018}, | ||
3490 | {0x3d4001a4,0xdf00e4}, | ||
3491 | {0x3d4001a8,0x80000000}, | ||
3492 | {0x3d4001b0,0x11}, | ||
3493 | {0x3d4001b4,0x170a}, | ||
3494 | {0x3d4001c0,0x1}, | ||
3495 | {0x3d4001c4,0x1}, | ||
3496 | {0x3d4000f4,0x639}, | ||
3497 | {0x3d400108,0x70e1617}, | ||
3498 | {0x3d400200,0x17}, | ||
3499 | {0x3d40020c,0x0}, | ||
3500 | {0x3d400210,0x1f1f}, | ||
3501 | {0x3d400204,0x80808}, | ||
3502 | {0x3d400214,0x7070707}, | ||
3503 | {0x3d400218,0x7070707}, | ||
3504 | {0x3d402020,0x1}, | ||
3505 | {0x3d402024,0xd0c0}, | ||
3506 | {0x3d402050,0x20d040}, | ||
3507 | {0x3d402064,0x14002f}, | ||
3508 | {0x3d4020dc,0x940009}, | ||
3509 | {0x3d4020e0,0x310000}, | ||
3510 | {0x3d4020e8,0x66004a}, | ||
3511 | {0x3d4020ec,0x16004a}, | ||
3512 | {0x3d402100,0xb070508}, | ||
3513 | {0x3d402104,0x3040b}, | ||
3514 | {0x3d402108,0x305090c}, | ||
3515 | {0x3d40210c,0x505000}, | ||
3516 | {0x3d402110,0x4040204}, | ||
3517 | {0x3d402114,0x2030303}, | ||
3518 | {0x3d402118,0x1010004}, | ||
3519 | {0x3d40211c,0x301}, | ||
3520 | {0x3d402130,0x20300}, | ||
3521 | {0x3d402134,0xa100002}, | ||
3522 | {0x3d402138,0x31}, | ||
3523 | {0x3d402144,0x220011}, | ||
3524 | {0x3d402180,0xc0a70006}, | ||
3525 | {0x3d402190,0x3858202}, | ||
3526 | {0x3d402194,0x80303}, | ||
3527 | {0x3d4021b4,0x502}, | ||
3528 | {0x3d400244,0x0}, | ||
3529 | {0x3d400250,0x29001505}, | ||
3530 | {0x3d400254,0x2c}, | ||
3531 | {0x3d40025c,0x5900575b}, | ||
3532 | {0x3d400264,0x90000096}, | ||
3533 | {0x3d40026c,0x1000012c}, | ||
3534 | {0x3d400300,0x16}, | ||
3535 | {0x3d400304,0x0}, | ||
3536 | {0x3d40030c,0x0}, | ||
3537 | {0x3d400320,0x1}, | ||
3538 | {0x3d40036c,0x11}, | ||
3539 | {0x3d400400,0x111}, | ||
3540 | {0x3d400404,0x10f3}, | ||
3541 | {0x3d400408,0x72ff}, | ||
3542 | {0x3d400490,0x1}, | ||
3543 | {0x3d400494,0xe00}, | ||
3544 | {0x3d400498,0x62ffff}, | ||
3545 | {0x3d40049c,0xe00}, | ||
3546 | {0x3d4004a0,0xffff}, | ||
3547 | }; | ||
3548 | |||
3549 | /* PHY Initialize Configuration */ | ||
3550 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | ||
3551 | {0x100a0,0x0}, | ||
3552 | {0x100a1,0x1}, | ||
3553 | {0x100a2,0x2}, | ||
3554 | {0x100a3,0x3}, | ||
3555 | {0x100a4,0x4}, | ||
3556 | {0x100a5,0x5}, | ||
3557 | {0x100a6,0x6}, | ||
3558 | {0x100a7,0x7}, | ||
3559 | {0x110a0,0x0}, | ||
3560 | {0x110a1,0x1}, | ||
3561 | {0x110a2,0x2}, | ||
3562 | {0x110a3,0x3}, | ||
3563 | {0x110a4,0x4}, | ||
3564 | {0x110a5,0x7}, | ||
3565 | {0x110a6,0x6}, | ||
3566 | {0x110a7,0x5}, | ||
3567 | {0x120a0,0x0}, | ||
3568 | {0x120a1,0x1}, | ||
3569 | {0x120a2,0x2}, | ||
3570 | {0x120a3,0x3}, | ||
3571 | {0x120a4,0x4}, | ||
3572 | {0x120a5,0x5}, | ||
3573 | {0x120a6,0x6}, | ||
3574 | {0x120a7,0x7}, | ||
3575 | {0x130a0,0x0}, | ||
3576 | {0x130a1,0x1}, | ||
3577 | {0x130a2,0x2}, | ||
3578 | {0x130a3,0x3}, | ||
3579 | {0x130a4,0x4}, | ||
3580 | {0x130a5,0x5}, | ||
3581 | {0x130a6,0x6}, | ||
3582 | {0x130a7,0x7}, | ||
3583 | {0x20110,0x2}, | ||
3584 | {0x20111,0x3}, | ||
3585 | {0x20112,0x4}, | ||
3586 | {0x20113,0x5}, | ||
3587 | {0x20114,0x0}, | ||
3588 | {0x20115,0x1}, | ||
3589 | {0x1005f,0x1ff}, | ||
3590 | {0x1015f,0x1ff}, | ||
3591 | {0x1105f,0x1ff}, | ||
3592 | {0x1115f,0x1ff}, | ||
3593 | {0x1205f,0x1ff}, | ||
3594 | {0x1215f,0x1ff}, | ||
3595 | {0x1305f,0x1ff}, | ||
3596 | {0x1315f,0x1ff}, | ||
3597 | {0x11005f,0x1ff}, | ||
3598 | {0x11015f,0x1ff}, | ||
3599 | {0x11105f,0x1ff}, | ||
3600 | {0x11115f,0x1ff}, | ||
3601 | {0x11205f,0x1ff}, | ||
3602 | {0x11215f,0x1ff}, | ||
3603 | {0x11305f,0x1ff}, | ||
3604 | {0x11315f,0x1ff}, | ||
3605 | {0x55,0x1ff}, | ||
3606 | {0x1055,0x1ff}, | ||
3607 | {0x2055,0x1ff}, | ||
3608 | {0x3055,0x1ff}, | ||
3609 | {0x4055,0x1ff}, | ||
3610 | {0x5055,0x1ff}, | ||
3611 | {0x6055,0x1ff}, | ||
3612 | {0x7055,0x1ff}, | ||
3613 | {0x8055,0x1ff}, | ||
3614 | {0x9055,0x1ff}, | ||
3615 | {0x200c5,0x19}, | ||
3616 | {0x1200c5,0x7}, | ||
3617 | {0x2002e,0x2}, | ||
3618 | {0x12002e,0x1}, | ||
3619 | {0x90204,0x0}, | ||
3620 | {0x190204,0x0}, | ||
3621 | {0x20024,0x1ab}, | ||
3622 | {0x2003a,0x0}, | ||
3623 | {0x120024,0x1ab}, | ||
3624 | {0x2003a,0x0}, | ||
3625 | {0x20056,0x3}, | ||
3626 | {0x120056,0xa}, | ||
3627 | {0x1004d,0xe00}, | ||
3628 | {0x1014d,0xe00}, | ||
3629 | {0x1104d,0xe00}, | ||
3630 | {0x1114d,0xe00}, | ||
3631 | {0x1204d,0xe00}, | ||
3632 | {0x1214d,0xe00}, | ||
3633 | {0x1304d,0xe00}, | ||
3634 | {0x1314d,0xe00}, | ||
3635 | {0x11004d,0xe00}, | ||
3636 | {0x11014d,0xe00}, | ||
3637 | {0x11104d,0xe00}, | ||
3638 | {0x11114d,0xe00}, | ||
3639 | {0x11204d,0xe00}, | ||
3640 | {0x11214d,0xe00}, | ||
3641 | {0x11304d,0xe00}, | ||
3642 | {0x11314d,0xe00}, | ||
3643 | {0x10049,0xeba}, | ||
3644 | {0x10149,0xeba}, | ||
3645 | {0x11049,0xeba}, | ||
3646 | {0x11149,0xeba}, | ||
3647 | {0x12049,0xeba}, | ||
3648 | {0x12149,0xeba}, | ||
3649 | {0x13049,0xeba}, | ||
3650 | {0x13149,0xeba}, | ||
3651 | {0x110049,0xeba}, | ||
3652 | {0x110149,0xeba}, | ||
3653 | {0x111049,0xeba}, | ||
3654 | {0x111149,0xeba}, | ||
3655 | {0x112049,0xeba}, | ||
3656 | {0x112149,0xeba}, | ||
3657 | {0x113049,0xeba}, | ||
3658 | {0x113149,0xeba}, | ||
3659 | {0x43,0x63}, | ||
3660 | {0x1043,0x63}, | ||
3661 | {0x2043,0x63}, | ||
3662 | {0x3043,0x63}, | ||
3663 | {0x4043,0x63}, | ||
3664 | {0x5043,0x63}, | ||
3665 | {0x6043,0x63}, | ||
3666 | {0x7043,0x63}, | ||
3667 | {0x8043,0x63}, | ||
3668 | {0x9043,0x63}, | ||
3669 | {0x20018,0x3}, | ||
3670 | {0x20075,0x4}, | ||
3671 | {0x20050,0x0}, | ||
3672 | {0x20008,0x320}, | ||
3673 | {0x120008,0xa7}, | ||
3674 | {0x20088,0x9}, | ||
3675 | {0x200b2,0xdc}, | ||
3676 | {0x10043,0x5a1}, | ||
3677 | {0x10143,0x5a1}, | ||
3678 | {0x11043,0x5a1}, | ||
3679 | {0x11143,0x5a1}, | ||
3680 | {0x12043,0x5a1}, | ||
3681 | {0x12143,0x5a1}, | ||
3682 | {0x13043,0x5a1}, | ||
3683 | {0x13143,0x5a1}, | ||
3684 | {0x1200b2,0xdc}, | ||
3685 | {0x110043,0x5a1}, | ||
3686 | {0x110143,0x5a1}, | ||
3687 | {0x111043,0x5a1}, | ||
3688 | {0x111143,0x5a1}, | ||
3689 | {0x112043,0x5a1}, | ||
3690 | {0x112143,0x5a1}, | ||
3691 | {0x113043,0x5a1}, | ||
3692 | {0x113143,0x5a1}, | ||
3693 | {0x200fa,0x1}, | ||
3694 | {0x1200fa,0x1}, | ||
3695 | {0x20019,0x1}, | ||
3696 | {0x120019,0x1}, | ||
3697 | {0x200f0,0x0}, | ||
3698 | {0x200f1,0x0}, | ||
3699 | {0x200f2,0x4444}, | ||
3700 | {0x200f3,0x8888}, | ||
3701 | {0x200f4,0x5555}, | ||
3702 | {0x200f5,0x0}, | ||
3703 | {0x200f6,0x0}, | ||
3704 | {0x200f7,0xf000}, | ||
3705 | {0x20025,0x0}, | ||
3706 | {0x2002d,0x0}, | ||
3707 | {0x12002d,0x0}, | ||
3708 | {0x200c7,0x80}, | ||
3709 | {0x1200c7,0x80}, | ||
3710 | {0x200ca,0x106}, | ||
3711 | {0x1200ca,0x106}, | ||
3712 | }; | ||
3713 | |||
3714 | /* ddr phy trained csr */ | ||
3715 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | ||
3716 | { 0x200b2, 0x0 }, | ||
3717 | { 0x1200b2, 0x0 }, | ||
3718 | { 0x2200b2, 0x0 }, | ||
3719 | { 0x200cb, 0x0 }, | ||
3720 | { 0x10043, 0x0 }, | ||
3721 | { 0x110043, 0x0 }, | ||
3722 | { 0x210043, 0x0 }, | ||
3723 | { 0x10143, 0x0 }, | ||
3724 | { 0x110143, 0x0 }, | ||
3725 | { 0x210143, 0x0 }, | ||
3726 | { 0x11043, 0x0 }, | ||
3727 | { 0x111043, 0x0 }, | ||
3728 | { 0x211043, 0x0 }, | ||
3729 | { 0x11143, 0x0 }, | ||
3730 | { 0x111143, 0x0 }, | ||
3731 | { 0x211143, 0x0 }, | ||
3732 | { 0x12043, 0x0 }, | ||
3733 | { 0x112043, 0x0 }, | ||
3734 | { 0x212043, 0x0 }, | ||
3735 | { 0x12143, 0x0 }, | ||
3736 | { 0x112143, 0x0 }, | ||
3737 | { 0x212143, 0x0 }, | ||
3738 | { 0x13043, 0x0 }, | ||
3739 | { 0x113043, 0x0 }, | ||
3740 | { 0x213043, 0x0 }, | ||
3741 | { 0x13143, 0x0 }, | ||
3742 | { 0x113143, 0x0 }, | ||
3743 | { 0x213143, 0x0 }, | ||
3744 | { 0x80, 0x0 }, | ||
3745 | { 0x100080, 0x0 }, | ||
3746 | { 0x200080, 0x0 }, | ||
3747 | { 0x1080, 0x0 }, | ||
3748 | { 0x101080, 0x0 }, | ||
3749 | { 0x201080, 0x0 }, | ||
3750 | { 0x2080, 0x0 }, | ||
3751 | { 0x102080, 0x0 }, | ||
3752 | { 0x202080, 0x0 }, | ||
3753 | { 0x3080, 0x0 }, | ||
3754 | { 0x103080, 0x0 }, | ||
3755 | { 0x203080, 0x0 }, | ||
3756 | { 0x4080, 0x0 }, | ||
3757 | { 0x104080, 0x0 }, | ||
3758 | { 0x204080, 0x0 }, | ||
3759 | { 0x5080, 0x0 }, | ||
3760 | { 0x105080, 0x0 }, | ||
3761 | { 0x205080, 0x0 }, | ||
3762 | { 0x6080, 0x0 }, | ||
3763 | { 0x106080, 0x0 }, | ||
3764 | { 0x206080, 0x0 }, | ||
3765 | { 0x7080, 0x0 }, | ||
3766 | { 0x107080, 0x0 }, | ||
3767 | { 0x207080, 0x0 }, | ||
3768 | { 0x8080, 0x0 }, | ||
3769 | { 0x108080, 0x0 }, | ||
3770 | { 0x208080, 0x0 }, | ||
3771 | { 0x9080, 0x0 }, | ||
3772 | { 0x109080, 0x0 }, | ||
3773 | { 0x209080, 0x0 }, | ||
3774 | { 0x10080, 0x0 }, | ||
3775 | { 0x110080, 0x0 }, | ||
3776 | { 0x210080, 0x0 }, | ||
3777 | { 0x10180, 0x0 }, | ||
3778 | { 0x110180, 0x0 }, | ||
3779 | { 0x210180, 0x0 }, | ||
3780 | { 0x11080, 0x0 }, | ||
3781 | { 0x111080, 0x0 }, | ||
3782 | { 0x211080, 0x0 }, | ||
3783 | { 0x11180, 0x0 }, | ||
3784 | { 0x111180, 0x0 }, | ||
3785 | { 0x211180, 0x0 }, | ||
3786 | { 0x12080, 0x0 }, | ||
3787 | { 0x112080, 0x0 }, | ||
3788 | { 0x212080, 0x0 }, | ||
3789 | { 0x12180, 0x0 }, | ||
3790 | { 0x112180, 0x0 }, | ||
3791 | { 0x212180, 0x0 }, | ||
3792 | { 0x13080, 0x0 }, | ||
3793 | { 0x113080, 0x0 }, | ||
3794 | { 0x213080, 0x0 }, | ||
3795 | { 0x13180, 0x0 }, | ||
3796 | { 0x113180, 0x0 }, | ||
3797 | { 0x213180, 0x0 }, | ||
3798 | { 0x10081, 0x0 }, | ||
3799 | { 0x110081, 0x0 }, | ||
3800 | { 0x210081, 0x0 }, | ||
3801 | { 0x10181, 0x0 }, | ||
3802 | { 0x110181, 0x0 }, | ||
3803 | { 0x210181, 0x0 }, | ||
3804 | { 0x11081, 0x0 }, | ||
3805 | { 0x111081, 0x0 }, | ||
3806 | { 0x211081, 0x0 }, | ||
3807 | { 0x11181, 0x0 }, | ||
3808 | { 0x111181, 0x0 }, | ||
3809 | { 0x211181, 0x0 }, | ||
3810 | { 0x12081, 0x0 }, | ||
3811 | { 0x112081, 0x0 }, | ||
3812 | { 0x212081, 0x0 }, | ||
3813 | { 0x12181, 0x0 }, | ||
3814 | { 0x112181, 0x0 }, | ||
3815 | { 0x212181, 0x0 }, | ||
3816 | { 0x13081, 0x0 }, | ||
3817 | { 0x113081, 0x0 }, | ||
3818 | { 0x213081, 0x0 }, | ||
3819 | { 0x13181, 0x0 }, | ||
3820 | { 0x113181, 0x0 }, | ||
3821 | { 0x213181, 0x0 }, | ||
3822 | { 0x100d0, 0x0 }, | ||
3823 | { 0x1100d0, 0x0 }, | ||
3824 | { 0x2100d0, 0x0 }, | ||
3825 | { 0x101d0, 0x0 }, | ||
3826 | { 0x1101d0, 0x0 }, | ||
3827 | { 0x2101d0, 0x0 }, | ||
3828 | { 0x110d0, 0x0 }, | ||
3829 | { 0x1110d0, 0x0 }, | ||
3830 | { 0x2110d0, 0x0 }, | ||
3831 | { 0x111d0, 0x0 }, | ||
3832 | { 0x1111d0, 0x0 }, | ||
3833 | { 0x2111d0, 0x0 }, | ||
3834 | { 0x120d0, 0x0 }, | ||
3835 | { 0x1120d0, 0x0 }, | ||
3836 | { 0x2120d0, 0x0 }, | ||
3837 | { 0x121d0, 0x0 }, | ||
3838 | { 0x1121d0, 0x0 }, | ||
3839 | { 0x2121d0, 0x0 }, | ||
3840 | { 0x130d0, 0x0 }, | ||
3841 | { 0x1130d0, 0x0 }, | ||
3842 | { 0x2130d0, 0x0 }, | ||
3843 | { 0x131d0, 0x0 }, | ||
3844 | { 0x1131d0, 0x0 }, | ||
3845 | { 0x2131d0, 0x0 }, | ||
3846 | { 0x100d1, 0x0 }, | ||
3847 | { 0x1100d1, 0x0 }, | ||
3848 | { 0x2100d1, 0x0 }, | ||
3849 | { 0x101d1, 0x0 }, | ||
3850 | { 0x1101d1, 0x0 }, | ||
3851 | { 0x2101d1, 0x0 }, | ||
3852 | { 0x110d1, 0x0 }, | ||
3853 | { 0x1110d1, 0x0 }, | ||
3854 | { 0x2110d1, 0x0 }, | ||
3855 | { 0x111d1, 0x0 }, | ||
3856 | { 0x1111d1, 0x0 }, | ||
3857 | { 0x2111d1, 0x0 }, | ||
3858 | { 0x120d1, 0x0 }, | ||
3859 | { 0x1120d1, 0x0 }, | ||
3860 | { 0x2120d1, 0x0 }, | ||
3861 | { 0x121d1, 0x0 }, | ||
3862 | { 0x1121d1, 0x0 }, | ||
3863 | { 0x2121d1, 0x0 }, | ||
3864 | { 0x130d1, 0x0 }, | ||
3865 | { 0x1130d1, 0x0 }, | ||
3866 | { 0x2130d1, 0x0 }, | ||
3867 | { 0x131d1, 0x0 }, | ||
3868 | { 0x1131d1, 0x0 }, | ||
3869 | { 0x2131d1, 0x0 }, | ||
3870 | { 0x10068, 0x0 }, | ||
3871 | { 0x10168, 0x0 }, | ||
3872 | { 0x10268, 0x0 }, | ||
3873 | { 0x10368, 0x0 }, | ||
3874 | { 0x10468, 0x0 }, | ||
3875 | { 0x10568, 0x0 }, | ||
3876 | { 0x10668, 0x0 }, | ||
3877 | { 0x10768, 0x0 }, | ||
3878 | { 0x10868, 0x0 }, | ||
3879 | { 0x11068, 0x0 }, | ||
3880 | { 0x11168, 0x0 }, | ||
3881 | { 0x11268, 0x0 }, | ||
3882 | { 0x11368, 0x0 }, | ||
3883 | { 0x11468, 0x0 }, | ||
3884 | { 0x11568, 0x0 }, | ||
3885 | { 0x11668, 0x0 }, | ||
3886 | { 0x11768, 0x0 }, | ||
3887 | { 0x11868, 0x0 }, | ||
3888 | { 0x12068, 0x0 }, | ||
3889 | { 0x12168, 0x0 }, | ||
3890 | { 0x12268, 0x0 }, | ||
3891 | { 0x12368, 0x0 }, | ||
3892 | { 0x12468, 0x0 }, | ||
3893 | { 0x12568, 0x0 }, | ||
3894 | { 0x12668, 0x0 }, | ||
3895 | { 0x12768, 0x0 }, | ||
3896 | { 0x12868, 0x0 }, | ||
3897 | { 0x13068, 0x0 }, | ||
3898 | { 0x13168, 0x0 }, | ||
3899 | { 0x13268, 0x0 }, | ||
3900 | { 0x13368, 0x0 }, | ||
3901 | { 0x13468, 0x0 }, | ||
3902 | { 0x13568, 0x0 }, | ||
3903 | { 0x13668, 0x0 }, | ||
3904 | { 0x13768, 0x0 }, | ||
3905 | { 0x13868, 0x0 }, | ||
3906 | { 0x10069, 0x0 }, | ||
3907 | { 0x10169, 0x0 }, | ||
3908 | { 0x10269, 0x0 }, | ||
3909 | { 0x10369, 0x0 }, | ||
3910 | { 0x10469, 0x0 }, | ||
3911 | { 0x10569, 0x0 }, | ||
3912 | { 0x10669, 0x0 }, | ||
3913 | { 0x10769, 0x0 }, | ||
3914 | { 0x10869, 0x0 }, | ||
3915 | { 0x11069, 0x0 }, | ||
3916 | { 0x11169, 0x0 }, | ||
3917 | { 0x11269, 0x0 }, | ||
3918 | { 0x11369, 0x0 }, | ||
3919 | { 0x11469, 0x0 }, | ||
3920 | { 0x11569, 0x0 }, | ||
3921 | { 0x11669, 0x0 }, | ||
3922 | { 0x11769, 0x0 }, | ||
3923 | { 0x11869, 0x0 }, | ||
3924 | { 0x12069, 0x0 }, | ||
3925 | { 0x12169, 0x0 }, | ||
3926 | { 0x12269, 0x0 }, | ||
3927 | { 0x12369, 0x0 }, | ||
3928 | { 0x12469, 0x0 }, | ||
3929 | { 0x12569, 0x0 }, | ||
3930 | { 0x12669, 0x0 }, | ||
3931 | { 0x12769, 0x0 }, | ||
3932 | { 0x12869, 0x0 }, | ||
3933 | { 0x13069, 0x0 }, | ||
3934 | { 0x13169, 0x0 }, | ||
3935 | { 0x13269, 0x0 }, | ||
3936 | { 0x13369, 0x0 }, | ||
3937 | { 0x13469, 0x0 }, | ||
3938 | { 0x13569, 0x0 }, | ||
3939 | { 0x13669, 0x0 }, | ||
3940 | { 0x13769, 0x0 }, | ||
3941 | { 0x13869, 0x0 }, | ||
3942 | { 0x1008c, 0x0 }, | ||
3943 | { 0x11008c, 0x0 }, | ||
3944 | { 0x21008c, 0x0 }, | ||
3945 | { 0x1018c, 0x0 }, | ||
3946 | { 0x11018c, 0x0 }, | ||
3947 | { 0x21018c, 0x0 }, | ||
3948 | { 0x1108c, 0x0 }, | ||
3949 | { 0x11108c, 0x0 }, | ||
3950 | { 0x21108c, 0x0 }, | ||
3951 | { 0x1118c, 0x0 }, | ||
3952 | { 0x11118c, 0x0 }, | ||
3953 | { 0x21118c, 0x0 }, | ||
3954 | { 0x1208c, 0x0 }, | ||
3955 | { 0x11208c, 0x0 }, | ||
3956 | { 0x21208c, 0x0 }, | ||
3957 | { 0x1218c, 0x0 }, | ||
3958 | { 0x11218c, 0x0 }, | ||
3959 | { 0x21218c, 0x0 }, | ||
3960 | { 0x1308c, 0x0 }, | ||
3961 | { 0x11308c, 0x0 }, | ||
3962 | { 0x21308c, 0x0 }, | ||
3963 | { 0x1318c, 0x0 }, | ||
3964 | { 0x11318c, 0x0 }, | ||
3965 | { 0x21318c, 0x0 }, | ||
3966 | { 0x1008d, 0x0 }, | ||
3967 | { 0x11008d, 0x0 }, | ||
3968 | { 0x21008d, 0x0 }, | ||
3969 | { 0x1018d, 0x0 }, | ||
3970 | { 0x11018d, 0x0 }, | ||
3971 | { 0x21018d, 0x0 }, | ||
3972 | { 0x1108d, 0x0 }, | ||
3973 | { 0x11108d, 0x0 }, | ||
3974 | { 0x21108d, 0x0 }, | ||
3975 | { 0x1118d, 0x0 }, | ||
3976 | { 0x11118d, 0x0 }, | ||
3977 | { 0x21118d, 0x0 }, | ||
3978 | { 0x1208d, 0x0 }, | ||
3979 | { 0x11208d, 0x0 }, | ||
3980 | { 0x21208d, 0x0 }, | ||
3981 | { 0x1218d, 0x0 }, | ||
3982 | { 0x11218d, 0x0 }, | ||
3983 | { 0x21218d, 0x0 }, | ||
3984 | { 0x1308d, 0x0 }, | ||
3985 | { 0x11308d, 0x0 }, | ||
3986 | { 0x21308d, 0x0 }, | ||
3987 | { 0x1318d, 0x0 }, | ||
3988 | { 0x11318d, 0x0 }, | ||
3989 | { 0x21318d, 0x0 }, | ||
3990 | { 0x100c0, 0x0 }, | ||
3991 | { 0x1100c0, 0x0 }, | ||
3992 | { 0x2100c0, 0x0 }, | ||
3993 | { 0x101c0, 0x0 }, | ||
3994 | { 0x1101c0, 0x0 }, | ||
3995 | { 0x2101c0, 0x0 }, | ||
3996 | { 0x102c0, 0x0 }, | ||
3997 | { 0x1102c0, 0x0 }, | ||
3998 | { 0x2102c0, 0x0 }, | ||
3999 | { 0x103c0, 0x0 }, | ||
4000 | { 0x1103c0, 0x0 }, | ||
4001 | { 0x2103c0, 0x0 }, | ||
4002 | { 0x104c0, 0x0 }, | ||
4003 | { 0x1104c0, 0x0 }, | ||
4004 | { 0x2104c0, 0x0 }, | ||
4005 | { 0x105c0, 0x0 }, | ||
4006 | { 0x1105c0, 0x0 }, | ||
4007 | { 0x2105c0, 0x0 }, | ||
4008 | { 0x106c0, 0x0 }, | ||
4009 | { 0x1106c0, 0x0 }, | ||
4010 | { 0x2106c0, 0x0 }, | ||
4011 | { 0x107c0, 0x0 }, | ||
4012 | { 0x1107c0, 0x0 }, | ||
4013 | { 0x2107c0, 0x0 }, | ||
4014 | { 0x108c0, 0x0 }, | ||
4015 | { 0x1108c0, 0x0 }, | ||
4016 | { 0x2108c0, 0x0 }, | ||
4017 | { 0x110c0, 0x0 }, | ||
4018 | { 0x1110c0, 0x0 }, | ||
4019 | { 0x2110c0, 0x0 }, | ||
4020 | { 0x111c0, 0x0 }, | ||
4021 | { 0x1111c0, 0x0 }, | ||
4022 | { 0x2111c0, 0x0 }, | ||
4023 | { 0x112c0, 0x0 }, | ||
4024 | { 0x1112c0, 0x0 }, | ||
4025 | { 0x2112c0, 0x0 }, | ||
4026 | { 0x113c0, 0x0 }, | ||
4027 | { 0x1113c0, 0x0 }, | ||
4028 | { 0x2113c0, 0x0 }, | ||
4029 | { 0x114c0, 0x0 }, | ||
4030 | { 0x1114c0, 0x0 }, | ||
4031 | { 0x2114c0, 0x0 }, | ||
4032 | { 0x115c0, 0x0 }, | ||
4033 | { 0x1115c0, 0x0 }, | ||
4034 | { 0x2115c0, 0x0 }, | ||
4035 | { 0x116c0, 0x0 }, | ||
4036 | { 0x1116c0, 0x0 }, | ||
4037 | { 0x2116c0, 0x0 }, | ||
4038 | { 0x117c0, 0x0 }, | ||
4039 | { 0x1117c0, 0x0 }, | ||
4040 | { 0x2117c0, 0x0 }, | ||
4041 | { 0x118c0, 0x0 }, | ||
4042 | { 0x1118c0, 0x0 }, | ||
4043 | { 0x2118c0, 0x0 }, | ||
4044 | { 0x120c0, 0x0 }, | ||
4045 | { 0x1120c0, 0x0 }, | ||
4046 | { 0x2120c0, 0x0 }, | ||
4047 | { 0x121c0, 0x0 }, | ||
4048 | { 0x1121c0, 0x0 }, | ||
4049 | { 0x2121c0, 0x0 }, | ||
4050 | { 0x122c0, 0x0 }, | ||
4051 | { 0x1122c0, 0x0 }, | ||
4052 | { 0x2122c0, 0x0 }, | ||
4053 | { 0x123c0, 0x0 }, | ||
4054 | { 0x1123c0, 0x0 }, | ||
4055 | { 0x2123c0, 0x0 }, | ||
4056 | { 0x124c0, 0x0 }, | ||
4057 | { 0x1124c0, 0x0 }, | ||
4058 | { 0x2124c0, 0x0 }, | ||
4059 | { 0x125c0, 0x0 }, | ||
4060 | { 0x1125c0, 0x0 }, | ||
4061 | { 0x2125c0, 0x0 }, | ||
4062 | { 0x126c0, 0x0 }, | ||
4063 | { 0x1126c0, 0x0 }, | ||
4064 | { 0x2126c0, 0x0 }, | ||
4065 | { 0x127c0, 0x0 }, | ||
4066 | { 0x1127c0, 0x0 }, | ||
4067 | { 0x2127c0, 0x0 }, | ||
4068 | { 0x128c0, 0x0 }, | ||
4069 | { 0x1128c0, 0x0 }, | ||
4070 | { 0x2128c0, 0x0 }, | ||
4071 | { 0x130c0, 0x0 }, | ||
4072 | { 0x1130c0, 0x0 }, | ||
4073 | { 0x2130c0, 0x0 }, | ||
4074 | { 0x131c0, 0x0 }, | ||
4075 | { 0x1131c0, 0x0 }, | ||
4076 | { 0x2131c0, 0x0 }, | ||
4077 | { 0x132c0, 0x0 }, | ||
4078 | { 0x1132c0, 0x0 }, | ||
4079 | { 0x2132c0, 0x0 }, | ||
4080 | { 0x133c0, 0x0 }, | ||
4081 | { 0x1133c0, 0x0 }, | ||
4082 | { 0x2133c0, 0x0 }, | ||
4083 | { 0x134c0, 0x0 }, | ||
4084 | { 0x1134c0, 0x0 }, | ||
4085 | { 0x2134c0, 0x0 }, | ||
4086 | { 0x135c0, 0x0 }, | ||
4087 | { 0x1135c0, 0x0 }, | ||
4088 | { 0x2135c0, 0x0 }, | ||
4089 | { 0x136c0, 0x0 }, | ||
4090 | { 0x1136c0, 0x0 }, | ||
4091 | { 0x2136c0, 0x0 }, | ||
4092 | { 0x137c0, 0x0 }, | ||
4093 | { 0x1137c0, 0x0 }, | ||
4094 | { 0x2137c0, 0x0 }, | ||
4095 | { 0x138c0, 0x0 }, | ||
4096 | { 0x1138c0, 0x0 }, | ||
4097 | { 0x2138c0, 0x0 }, | ||
4098 | { 0x100c1, 0x0 }, | ||
4099 | { 0x1100c1, 0x0 }, | ||
4100 | { 0x2100c1, 0x0 }, | ||
4101 | { 0x101c1, 0x0 }, | ||
4102 | { 0x1101c1, 0x0 }, | ||
4103 | { 0x2101c1, 0x0 }, | ||
4104 | { 0x102c1, 0x0 }, | ||
4105 | { 0x1102c1, 0x0 }, | ||
4106 | { 0x2102c1, 0x0 }, | ||
4107 | { 0x103c1, 0x0 }, | ||
4108 | { 0x1103c1, 0x0 }, | ||
4109 | { 0x2103c1, 0x0 }, | ||
4110 | { 0x104c1, 0x0 }, | ||
4111 | { 0x1104c1, 0x0 }, | ||
4112 | { 0x2104c1, 0x0 }, | ||
4113 | { 0x105c1, 0x0 }, | ||
4114 | { 0x1105c1, 0x0 }, | ||
4115 | { 0x2105c1, 0x0 }, | ||
4116 | { 0x106c1, 0x0 }, | ||
4117 | { 0x1106c1, 0x0 }, | ||
4118 | { 0x2106c1, 0x0 }, | ||
4119 | { 0x107c1, 0x0 }, | ||
4120 | { 0x1107c1, 0x0 }, | ||
4121 | { 0x2107c1, 0x0 }, | ||
4122 | { 0x108c1, 0x0 }, | ||
4123 | { 0x1108c1, 0x0 }, | ||
4124 | { 0x2108c1, 0x0 }, | ||
4125 | { 0x110c1, 0x0 }, | ||
4126 | { 0x1110c1, 0x0 }, | ||
4127 | { 0x2110c1, 0x0 }, | ||
4128 | { 0x111c1, 0x0 }, | ||
4129 | { 0x1111c1, 0x0 }, | ||
4130 | { 0x2111c1, 0x0 }, | ||
4131 | { 0x112c1, 0x0 }, | ||
4132 | { 0x1112c1, 0x0 }, | ||
4133 | { 0x2112c1, 0x0 }, | ||
4134 | { 0x113c1, 0x0 }, | ||
4135 | { 0x1113c1, 0x0 }, | ||
4136 | { 0x2113c1, 0x0 }, | ||
4137 | { 0x114c1, 0x0 }, | ||
4138 | { 0x1114c1, 0x0 }, | ||
4139 | { 0x2114c1, 0x0 }, | ||
4140 | { 0x115c1, 0x0 }, | ||
4141 | { 0x1115c1, 0x0 }, | ||
4142 | { 0x2115c1, 0x0 }, | ||
4143 | { 0x116c1, 0x0 }, | ||
4144 | { 0x1116c1, 0x0 }, | ||
4145 | { 0x2116c1, 0x0 }, | ||
4146 | { 0x117c1, 0x0 }, | ||
4147 | { 0x1117c1, 0x0 }, | ||
4148 | { 0x2117c1, 0x0 }, | ||
4149 | { 0x118c1, 0x0 }, | ||
4150 | { 0x1118c1, 0x0 }, | ||
4151 | { 0x2118c1, 0x0 }, | ||
4152 | { 0x120c1, 0x0 }, | ||
4153 | { 0x1120c1, 0x0 }, | ||
4154 | { 0x2120c1, 0x0 }, | ||
4155 | { 0x121c1, 0x0 }, | ||
4156 | { 0x1121c1, 0x0 }, | ||
4157 | { 0x2121c1, 0x0 }, | ||
4158 | { 0x122c1, 0x0 }, | ||
4159 | { 0x1122c1, 0x0 }, | ||
4160 | { 0x2122c1, 0x0 }, | ||
4161 | { 0x123c1, 0x0 }, | ||
4162 | { 0x1123c1, 0x0 }, | ||
4163 | { 0x2123c1, 0x0 }, | ||
4164 | { 0x124c1, 0x0 }, | ||
4165 | { 0x1124c1, 0x0 }, | ||
4166 | { 0x2124c1, 0x0 }, | ||
4167 | { 0x125c1, 0x0 }, | ||
4168 | { 0x1125c1, 0x0 }, | ||
4169 | { 0x2125c1, 0x0 }, | ||
4170 | { 0x126c1, 0x0 }, | ||
4171 | { 0x1126c1, 0x0 }, | ||
4172 | { 0x2126c1, 0x0 }, | ||
4173 | { 0x127c1, 0x0 }, | ||
4174 | { 0x1127c1, 0x0 }, | ||
4175 | { 0x2127c1, 0x0 }, | ||
4176 | { 0x128c1, 0x0 }, | ||
4177 | { 0x1128c1, 0x0 }, | ||
4178 | { 0x2128c1, 0x0 }, | ||
4179 | { 0x130c1, 0x0 }, | ||
4180 | { 0x1130c1, 0x0 }, | ||
4181 | { 0x2130c1, 0x0 }, | ||
4182 | { 0x131c1, 0x0 }, | ||
4183 | { 0x1131c1, 0x0 }, | ||
4184 | { 0x2131c1, 0x0 }, | ||
4185 | { 0x132c1, 0x0 }, | ||
4186 | { 0x1132c1, 0x0 }, | ||
4187 | { 0x2132c1, 0x0 }, | ||
4188 | { 0x133c1, 0x0 }, | ||
4189 | { 0x1133c1, 0x0 }, | ||
4190 | { 0x2133c1, 0x0 }, | ||
4191 | { 0x134c1, 0x0 }, | ||
4192 | { 0x1134c1, 0x0 }, | ||
4193 | { 0x2134c1, 0x0 }, | ||
4194 | { 0x135c1, 0x0 }, | ||
4195 | { 0x1135c1, 0x0 }, | ||
4196 | { 0x2135c1, 0x0 }, | ||
4197 | { 0x136c1, 0x0 }, | ||
4198 | { 0x1136c1, 0x0 }, | ||
4199 | { 0x2136c1, 0x0 }, | ||
4200 | { 0x137c1, 0x0 }, | ||
4201 | { 0x1137c1, 0x0 }, | ||
4202 | { 0x2137c1, 0x0 }, | ||
4203 | { 0x138c1, 0x0 }, | ||
4204 | { 0x1138c1, 0x0 }, | ||
4205 | { 0x2138c1, 0x0 }, | ||
4206 | { 0x10020, 0x0 }, | ||
4207 | { 0x110020, 0x0 }, | ||
4208 | { 0x210020, 0x0 }, | ||
4209 | { 0x11020, 0x0 }, | ||
4210 | { 0x111020, 0x0 }, | ||
4211 | { 0x211020, 0x0 }, | ||
4212 | { 0x12020, 0x0 }, | ||
4213 | { 0x112020, 0x0 }, | ||
4214 | { 0x212020, 0x0 }, | ||
4215 | { 0x13020, 0x0 }, | ||
4216 | { 0x113020, 0x0 }, | ||
4217 | { 0x213020, 0x0 }, | ||
4218 | { 0x20072, 0x0 }, | ||
4219 | { 0x20073, 0x0 }, | ||
4220 | { 0x20074, 0x0 }, | ||
4221 | { 0x100aa, 0x0 }, | ||
4222 | { 0x110aa, 0x0 }, | ||
4223 | { 0x120aa, 0x0 }, | ||
4224 | { 0x130aa, 0x0 }, | ||
4225 | { 0x20010, 0x0 }, | ||
4226 | { 0x120010, 0x0 }, | ||
4227 | { 0x220010, 0x0 }, | ||
4228 | { 0x20011, 0x0 }, | ||
4229 | { 0x120011, 0x0 }, | ||
4230 | { 0x220011, 0x0 }, | ||
4231 | { 0x100ae, 0x0 }, | ||
4232 | { 0x1100ae, 0x0 }, | ||
4233 | { 0x2100ae, 0x0 }, | ||
4234 | { 0x100af, 0x0 }, | ||
4235 | { 0x1100af, 0x0 }, | ||
4236 | { 0x2100af, 0x0 }, | ||
4237 | { 0x110ae, 0x0 }, | ||
4238 | { 0x1110ae, 0x0 }, | ||
4239 | { 0x2110ae, 0x0 }, | ||
4240 | { 0x110af, 0x0 }, | ||
4241 | { 0x1110af, 0x0 }, | ||
4242 | { 0x2110af, 0x0 }, | ||
4243 | { 0x120ae, 0x0 }, | ||
4244 | { 0x1120ae, 0x0 }, | ||
4245 | { 0x2120ae, 0x0 }, | ||
4246 | { 0x120af, 0x0 }, | ||
4247 | { 0x1120af, 0x0 }, | ||
4248 | { 0x2120af, 0x0 }, | ||
4249 | { 0x130ae, 0x0 }, | ||
4250 | { 0x1130ae, 0x0 }, | ||
4251 | { 0x2130ae, 0x0 }, | ||
4252 | { 0x130af, 0x0 }, | ||
4253 | { 0x1130af, 0x0 }, | ||
4254 | { 0x2130af, 0x0 }, | ||
4255 | { 0x20020, 0x0 }, | ||
4256 | { 0x120020, 0x0 }, | ||
4257 | { 0x220020, 0x0 }, | ||
4258 | { 0x100a0, 0x0 }, | ||
4259 | { 0x100a1, 0x0 }, | ||
4260 | { 0x100a2, 0x0 }, | ||
4261 | { 0x100a3, 0x0 }, | ||
4262 | { 0x100a4, 0x0 }, | ||
4263 | { 0x100a5, 0x0 }, | ||
4264 | { 0x100a6, 0x0 }, | ||
4265 | { 0x100a7, 0x0 }, | ||
4266 | { 0x110a0, 0x0 }, | ||
4267 | { 0x110a1, 0x0 }, | ||
4268 | { 0x110a2, 0x0 }, | ||
4269 | { 0x110a3, 0x0 }, | ||
4270 | { 0x110a4, 0x0 }, | ||
4271 | { 0x110a5, 0x0 }, | ||
4272 | { 0x110a6, 0x0 }, | ||
4273 | { 0x110a7, 0x0 }, | ||
4274 | { 0x120a0, 0x0 }, | ||
4275 | { 0x120a1, 0x0 }, | ||
4276 | { 0x120a2, 0x0 }, | ||
4277 | { 0x120a3, 0x0 }, | ||
4278 | { 0x120a4, 0x0 }, | ||
4279 | { 0x120a5, 0x0 }, | ||
4280 | { 0x120a6, 0x0 }, | ||
4281 | { 0x120a7, 0x0 }, | ||
4282 | { 0x130a0, 0x0 }, | ||
4283 | { 0x130a1, 0x0 }, | ||
4284 | { 0x130a2, 0x0 }, | ||
4285 | { 0x130a3, 0x0 }, | ||
4286 | { 0x130a4, 0x0 }, | ||
4287 | { 0x130a5, 0x0 }, | ||
4288 | { 0x130a6, 0x0 }, | ||
4289 | { 0x130a7, 0x0 }, | ||
4290 | { 0x2007c, 0x0 }, | ||
4291 | { 0x12007c, 0x0 }, | ||
4292 | { 0x22007c, 0x0 }, | ||
4293 | { 0x2007d, 0x0 }, | ||
4294 | { 0x12007d, 0x0 }, | ||
4295 | { 0x22007d, 0x0 }, | ||
4296 | { 0x400fd, 0x0 }, | ||
4297 | { 0x400c0, 0x0 }, | ||
4298 | { 0x90201, 0x0 }, | ||
4299 | { 0x190201, 0x0 }, | ||
4300 | { 0x290201, 0x0 }, | ||
4301 | { 0x90202, 0x0 }, | ||
4302 | { 0x190202, 0x0 }, | ||
4303 | { 0x290202, 0x0 }, | ||
4304 | { 0x90203, 0x0 }, | ||
4305 | { 0x190203, 0x0 }, | ||
4306 | { 0x290203, 0x0 }, | ||
4307 | { 0x90204, 0x0 }, | ||
4308 | { 0x190204, 0x0 }, | ||
4309 | { 0x290204, 0x0 }, | ||
4310 | { 0x90205, 0x0 }, | ||
4311 | { 0x190205, 0x0 }, | ||
4312 | { 0x290205, 0x0 }, | ||
4313 | { 0x90206, 0x0 }, | ||
4314 | { 0x190206, 0x0 }, | ||
4315 | { 0x290206, 0x0 }, | ||
4316 | { 0x90207, 0x0 }, | ||
4317 | { 0x190207, 0x0 }, | ||
4318 | { 0x290207, 0x0 }, | ||
4319 | { 0x90208, 0x0 }, | ||
4320 | { 0x190208, 0x0 }, | ||
4321 | { 0x290208, 0x0 }, | ||
4322 | { 0x10062, 0x0 }, | ||
4323 | { 0x10162, 0x0 }, | ||
4324 | { 0x10262, 0x0 }, | ||
4325 | { 0x10362, 0x0 }, | ||
4326 | { 0x10462, 0x0 }, | ||
4327 | { 0x10562, 0x0 }, | ||
4328 | { 0x10662, 0x0 }, | ||
4329 | { 0x10762, 0x0 }, | ||
4330 | { 0x10862, 0x0 }, | ||
4331 | { 0x11062, 0x0 }, | ||
4332 | { 0x11162, 0x0 }, | ||
4333 | { 0x11262, 0x0 }, | ||
4334 | { 0x11362, 0x0 }, | ||
4335 | { 0x11462, 0x0 }, | ||
4336 | { 0x11562, 0x0 }, | ||
4337 | { 0x11662, 0x0 }, | ||
4338 | { 0x11762, 0x0 }, | ||
4339 | { 0x11862, 0x0 }, | ||
4340 | { 0x12062, 0x0 }, | ||
4341 | { 0x12162, 0x0 }, | ||
4342 | { 0x12262, 0x0 }, | ||
4343 | { 0x12362, 0x0 }, | ||
4344 | { 0x12462, 0x0 }, | ||
4345 | { 0x12562, 0x0 }, | ||
4346 | { 0x12662, 0x0 }, | ||
4347 | { 0x12762, 0x0 }, | ||
4348 | { 0x12862, 0x0 }, | ||
4349 | { 0x13062, 0x0 }, | ||
4350 | { 0x13162, 0x0 }, | ||
4351 | { 0x13262, 0x0 }, | ||
4352 | { 0x13362, 0x0 }, | ||
4353 | { 0x13462, 0x0 }, | ||
4354 | { 0x13562, 0x0 }, | ||
4355 | { 0x13662, 0x0 }, | ||
4356 | { 0x13762, 0x0 }, | ||
4357 | { 0x13862, 0x0 }, | ||
4358 | { 0x20077, 0x0 }, | ||
4359 | { 0x10001, 0x0 }, | ||
4360 | { 0x11001, 0x0 }, | ||
4361 | { 0x12001, 0x0 }, | ||
4362 | { 0x13001, 0x0 }, | ||
4363 | { 0x10040, 0x0 }, | ||
4364 | { 0x10140, 0x0 }, | ||
4365 | { 0x10240, 0x0 }, | ||
4366 | { 0x10340, 0x0 }, | ||
4367 | { 0x10440, 0x0 }, | ||
4368 | { 0x10540, 0x0 }, | ||
4369 | { 0x10640, 0x0 }, | ||
4370 | { 0x10740, 0x0 }, | ||
4371 | { 0x10840, 0x0 }, | ||
4372 | { 0x10030, 0x0 }, | ||
4373 | { 0x10130, 0x0 }, | ||
4374 | { 0x10230, 0x0 }, | ||
4375 | { 0x10330, 0x0 }, | ||
4376 | { 0x10430, 0x0 }, | ||
4377 | { 0x10530, 0x0 }, | ||
4378 | { 0x10630, 0x0 }, | ||
4379 | { 0x10730, 0x0 }, | ||
4380 | { 0x10830, 0x0 }, | ||
4381 | { 0x11040, 0x0 }, | ||
4382 | { 0x11140, 0x0 }, | ||
4383 | { 0x11240, 0x0 }, | ||
4384 | { 0x11340, 0x0 }, | ||
4385 | { 0x11440, 0x0 }, | ||
4386 | { 0x11540, 0x0 }, | ||
4387 | { 0x11640, 0x0 }, | ||
4388 | { 0x11740, 0x0 }, | ||
4389 | { 0x11840, 0x0 }, | ||
4390 | { 0x11030, 0x0 }, | ||
4391 | { 0x11130, 0x0 }, | ||
4392 | { 0x11230, 0x0 }, | ||
4393 | { 0x11330, 0x0 }, | ||
4394 | { 0x11430, 0x0 }, | ||
4395 | { 0x11530, 0x0 }, | ||
4396 | { 0x11630, 0x0 }, | ||
4397 | { 0x11730, 0x0 }, | ||
4398 | { 0x11830, 0x0 }, | ||
4399 | { 0x12040, 0x0 }, | ||
4400 | { 0x12140, 0x0 }, | ||
4401 | { 0x12240, 0x0 }, | ||
4402 | { 0x12340, 0x0 }, | ||
4403 | { 0x12440, 0x0 }, | ||
4404 | { 0x12540, 0x0 }, | ||
4405 | { 0x12640, 0x0 }, | ||
4406 | { 0x12740, 0x0 }, | ||
4407 | { 0x12840, 0x0 }, | ||
4408 | { 0x12030, 0x0 }, | ||
4409 | { 0x12130, 0x0 }, | ||
4410 | { 0x12230, 0x0 }, | ||
4411 | { 0x12330, 0x0 }, | ||
4412 | { 0x12430, 0x0 }, | ||
4413 | { 0x12530, 0x0 }, | ||
4414 | { 0x12630, 0x0 }, | ||
4415 | { 0x12730, 0x0 }, | ||
4416 | { 0x12830, 0x0 }, | ||
4417 | { 0x13040, 0x0 }, | ||
4418 | { 0x13140, 0x0 }, | ||
4419 | { 0x13240, 0x0 }, | ||
4420 | { 0x13340, 0x0 }, | ||
4421 | { 0x13440, 0x0 }, | ||
4422 | { 0x13540, 0x0 }, | ||
4423 | { 0x13640, 0x0 }, | ||
4424 | { 0x13740, 0x0 }, | ||
4425 | { 0x13840, 0x0 }, | ||
4426 | { 0x13030, 0x0 }, | ||
4427 | { 0x13130, 0x0 }, | ||
4428 | { 0x13230, 0x0 }, | ||
4429 | { 0x13330, 0x0 }, | ||
4430 | { 0x13430, 0x0 }, | ||
4431 | { 0x13530, 0x0 }, | ||
4432 | { 0x13630, 0x0 }, | ||
4433 | { 0x13730, 0x0 }, | ||
4434 | { 0x13830, 0x0 }, | ||
4435 | }; | ||
4436 | /* P0 message block paremeter for training firmware */ | ||
4437 | struct dram_cfg_param ddr_fsp0_cfg[] = { | ||
4438 | {0xd0000, 0x0}, | ||
4439 | {0x54003,0xc80}, | ||
4440 | {0x54004,0x2}, | ||
4441 | {0x54005,0x2228}, | ||
4442 | {0x54006,0x11}, | ||
4443 | {0x54008,0x131f}, | ||
4444 | {0x54009,0xc8}, | ||
4445 | {0x5400b,0x2}, | ||
4446 | {0x5400d,0x100}, | ||
4447 | {0x54012,0x310}, | ||
4448 | {0x54019,0x2dd4}, | ||
4449 | {0x5401a,0x31}, | ||
4450 | {0x5401b,0x4a66}, | ||
4451 | {0x5401c,0x4a08}, | ||
4452 | {0x5401e,0x16}, | ||
4453 | {0x5401f,0x2dd4}, | ||
4454 | {0x54020,0x31}, | ||
4455 | {0x54021,0x4a66}, | ||
4456 | {0x54022,0x4a08}, | ||
4457 | {0x54024,0x16}, | ||
4458 | {0x5402b,0x1000}, | ||
4459 | {0x5402c,0x3}, | ||
4460 | {0x54032,0xd400}, | ||
4461 | {0x54033,0x312d}, | ||
4462 | {0x54034,0x6600}, | ||
4463 | {0x54035,0x84a}, | ||
4464 | {0x54036,0x4a}, | ||
4465 | {0x54037,0x1600}, | ||
4466 | {0x54038,0xd400}, | ||
4467 | {0x54039,0x312d}, | ||
4468 | {0x5403a,0x6600}, | ||
4469 | {0x5403b,0x84a}, | ||
4470 | {0x5403c,0x4a}, | ||
4471 | {0x5403d,0x1600}, | ||
4472 | {0xd0000, 0x1}, | ||
4473 | }; | ||
4474 | |||
4475 | |||
4476 | /* P1 message block paremeter for training firmware */ | ||
4477 | struct dram_cfg_param ddr_fsp1_cfg[] = { | ||
4478 | {0xd0000, 0x0}, | ||
4479 | {0x54002,0x1}, | ||
4480 | {0x54003,0x29c}, | ||
4481 | {0x54004,0x2}, | ||
4482 | {0x54005,0x2228}, | ||
4483 | {0x54006,0x11}, | ||
4484 | {0x54008,0x121f}, | ||
4485 | {0x54009,0xc8}, | ||
4486 | {0x5400b,0x2}, | ||
4487 | {0x5400d,0x100}, | ||
4488 | {0x54012,0x310}, | ||
4489 | {0x54019,0x994}, | ||
4490 | {0x5401a,0x31}, | ||
4491 | {0x5401b,0x4a66}, | ||
4492 | {0x5401c,0x4a08}, | ||
4493 | {0x5401e,0x16}, | ||
4494 | {0x5401f,0x994}, | ||
4495 | {0x54020,0x31}, | ||
4496 | {0x54021,0x4a66}, | ||
4497 | {0x54022,0x4a08}, | ||
4498 | {0x54024,0x16}, | ||
4499 | {0x5402b,0x1000}, | ||
4500 | {0x5402c,0x3}, | ||
4501 | {0x54032,0x9400}, | ||
4502 | {0x54033,0x3109}, | ||
4503 | {0x54034,0x6600}, | ||
4504 | {0x54035,0x84a}, | ||
4505 | {0x54036,0x4a}, | ||
4506 | {0x54037,0x1600}, | ||
4507 | {0x54038,0x9400}, | ||
4508 | {0x54039,0x3109}, | ||
4509 | {0x5403a,0x6600}, | ||
4510 | {0x5403b,0x84a}, | ||
4511 | {0x5403c,0x4a}, | ||
4512 | {0x5403d,0x1600}, | ||
4513 | {0xd0000, 0x1}, | ||
4514 | }; | ||
4515 | |||
4516 | |||
4517 | /* P0 2D message block paremeter for training firmware */ | ||
4518 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | ||
4519 | {0xd0000, 0x0}, | ||
4520 | {0x54003,0xc80}, | ||
4521 | {0x54004,0x2}, | ||
4522 | {0x54005,0x2228}, | ||
4523 | {0x54006,0x11}, | ||
4524 | {0x54008,0x61}, | ||
4525 | {0x54009,0xc8}, | ||
4526 | {0x5400b,0x2}, | ||
4527 | {0x5400f,0x100}, | ||
4528 | {0x54010,0x1f7f}, | ||
4529 | {0x54012,0x310}, | ||
4530 | {0x54019,0x2dd4}, | ||
4531 | {0x5401a,0x31}, | ||
4532 | {0x5401b,0x4a66}, | ||
4533 | {0x5401c,0x4a08}, | ||
4534 | {0x5401e,0x16}, | ||
4535 | {0x5401f,0x2dd4}, | ||
4536 | {0x54020,0x31}, | ||
4537 | {0x54021,0x4a66}, | ||
4538 | {0x54022,0x4a08}, | ||
4539 | {0x54024,0x16}, | ||
4540 | {0x5402b,0x1000}, | ||
4541 | {0x5402c,0x3}, | ||
4542 | {0x54032,0xd400}, | ||
4543 | {0x54033,0x312d}, | ||
4544 | {0x54034,0x6600}, | ||
4545 | {0x54035,0x84a}, | ||
4546 | {0x54036,0x4a}, | ||
4547 | {0x54037,0x1600}, | ||
4548 | {0x54038,0xd400}, | ||
4549 | {0x54039,0x312d}, | ||
4550 | {0x5403a,0x6600}, | ||
4551 | {0x5403b,0x84a}, | ||
4552 | {0x5403c,0x4a}, | ||
4553 | {0x5403d,0x1600}, | ||
4554 | { 0xd0000, 0x1 }, | ||
4555 | }; | ||
4556 | |||
4557 | /* DRAM PHY init engine image */ | ||
4558 | struct dram_cfg_param ddr_phy_pie[] = { | ||
4559 | {0xd0000, 0x0}, | ||
4560 | {0x90000,0x10}, | ||
4561 | {0x90001,0x400}, | ||
4562 | {0x90002,0x10e}, | ||
4563 | {0x90003,0x0}, | ||
4564 | {0x90004,0x0}, | ||
4565 | {0x90005,0x8}, | ||
4566 | {0x90029,0xb}, | ||
4567 | {0x9002a,0x480}, | ||
4568 | {0x9002b,0x109}, | ||
4569 | {0x9002c,0x8}, | ||
4570 | {0x9002d,0x448}, | ||
4571 | {0x9002e,0x139}, | ||
4572 | {0x9002f,0x8}, | ||
4573 | {0x90030,0x478}, | ||
4574 | {0x90031,0x109}, | ||
4575 | {0x90032,0x0}, | ||
4576 | {0x90033,0xe8}, | ||
4577 | {0x90034,0x109}, | ||
4578 | {0x90035,0x2}, | ||
4579 | {0x90036,0x10}, | ||
4580 | {0x90037,0x139}, | ||
4581 | {0x90038,0xf}, | ||
4582 | {0x90039,0x7c0}, | ||
4583 | {0x9003a,0x139}, | ||
4584 | {0x9003b,0x44}, | ||
4585 | {0x9003c,0x630}, | ||
4586 | {0x9003d,0x159}, | ||
4587 | {0x9003e,0x14f}, | ||
4588 | {0x9003f,0x630}, | ||
4589 | {0x90040,0x159}, | ||
4590 | {0x90041,0x47}, | ||
4591 | {0x90042,0x630}, | ||
4592 | {0x90043,0x149}, | ||
4593 | {0x90044,0x4f}, | ||
4594 | {0x90045,0x630}, | ||
4595 | {0x90046,0x179}, | ||
4596 | {0x90047,0x8}, | ||
4597 | {0x90048,0xe0}, | ||
4598 | {0x90049,0x109}, | ||
4599 | {0x9004a,0x0}, | ||
4600 | {0x9004b,0x7c8}, | ||
4601 | {0x9004c,0x109}, | ||
4602 | {0x9004d,0x0}, | ||
4603 | {0x9004e,0x1}, | ||
4604 | {0x9004f,0x8}, | ||
4605 | {0x90050,0x0}, | ||
4606 | {0x90051,0x45a}, | ||
4607 | {0x90052,0x9}, | ||
4608 | {0x90053,0x0}, | ||
4609 | {0x90054,0x448}, | ||
4610 | {0x90055,0x109}, | ||
4611 | {0x90056,0x40}, | ||
4612 | {0x90057,0x630}, | ||
4613 | {0x90058,0x179}, | ||
4614 | {0x90059,0x1}, | ||
4615 | {0x9005a,0x618}, | ||
4616 | {0x9005b,0x109}, | ||
4617 | {0x9005c,0x40c0}, | ||
4618 | {0x9005d,0x630}, | ||
4619 | {0x9005e,0x149}, | ||
4620 | {0x9005f,0x8}, | ||
4621 | {0x90060,0x4}, | ||
4622 | {0x90061,0x48}, | ||
4623 | {0x90062,0x4040}, | ||
4624 | {0x90063,0x630}, | ||
4625 | {0x90064,0x149}, | ||
4626 | {0x90065,0x0}, | ||
4627 | {0x90066,0x4}, | ||
4628 | {0x90067,0x48}, | ||
4629 | {0x90068,0x40}, | ||
4630 | {0x90069,0x630}, | ||
4631 | {0x9006a,0x149}, | ||
4632 | {0x9006b,0x10}, | ||
4633 | {0x9006c,0x4}, | ||
4634 | {0x9006d,0x18}, | ||
4635 | {0x9006e,0x0}, | ||
4636 | {0x9006f,0x4}, | ||
4637 | {0x90070,0x78}, | ||
4638 | {0x90071,0x549}, | ||
4639 | {0x90072,0x630}, | ||
4640 | {0x90073,0x159}, | ||
4641 | {0x90074,0xd49}, | ||
4642 | {0x90075,0x630}, | ||
4643 | {0x90076,0x159}, | ||
4644 | {0x90077,0x94a}, | ||
4645 | {0x90078,0x630}, | ||
4646 | {0x90079,0x159}, | ||
4647 | {0x9007a,0x441}, | ||
4648 | {0x9007b,0x630}, | ||
4649 | {0x9007c,0x149}, | ||
4650 | {0x9007d,0x42}, | ||
4651 | {0x9007e,0x630}, | ||
4652 | {0x9007f,0x149}, | ||
4653 | {0x90080,0x1}, | ||
4654 | {0x90081,0x630}, | ||
4655 | {0x90082,0x149}, | ||
4656 | {0x90083,0x0}, | ||
4657 | {0x90084,0xe0}, | ||
4658 | {0x90085,0x109}, | ||
4659 | {0x90086,0xa}, | ||
4660 | {0x90087,0x10}, | ||
4661 | {0x90088,0x109}, | ||
4662 | {0x90089,0x9}, | ||
4663 | {0x9008a,0x3c0}, | ||
4664 | {0x9008b,0x149}, | ||
4665 | {0x9008c,0x9}, | ||
4666 | {0x9008d,0x3c0}, | ||
4667 | {0x9008e,0x159}, | ||
4668 | {0x9008f,0x18}, | ||
4669 | {0x90090,0x10}, | ||
4670 | {0x90091,0x109}, | ||
4671 | {0x90092,0x0}, | ||
4672 | {0x90093,0x3c0}, | ||
4673 | {0x90094,0x109}, | ||
4674 | {0x90095,0x18}, | ||
4675 | {0x90096,0x4}, | ||
4676 | {0x90097,0x48}, | ||
4677 | {0x90098,0x18}, | ||
4678 | {0x90099,0x4}, | ||
4679 | {0x9009a,0x58}, | ||
4680 | {0x9009b,0xa}, | ||
4681 | {0x9009c,0x10}, | ||
4682 | {0x9009d,0x109}, | ||
4683 | {0x9009e,0x2}, | ||
4684 | {0x9009f,0x10}, | ||
4685 | {0x900a0,0x109}, | ||
4686 | {0x900a1,0x5}, | ||
4687 | {0x900a2,0x7c0}, | ||
4688 | {0x900a3,0x109}, | ||
4689 | {0x900a4,0x10}, | ||
4690 | {0x900a5,0x10}, | ||
4691 | {0x900a6,0x109}, | ||
4692 | {0x40000,0x811}, | ||
4693 | {0x40020,0x880}, | ||
4694 | {0x40040,0x0}, | ||
4695 | {0x40060,0x0}, | ||
4696 | {0x40001,0x4008}, | ||
4697 | {0x40021,0x83}, | ||
4698 | {0x40041,0x4f}, | ||
4699 | {0x40061,0x0}, | ||
4700 | {0x40002,0x4040}, | ||
4701 | {0x40022,0x83}, | ||
4702 | {0x40042,0x51}, | ||
4703 | {0x40062,0x0}, | ||
4704 | {0x40003,0x811}, | ||
4705 | {0x40023,0x880}, | ||
4706 | {0x40043,0x0}, | ||
4707 | {0x40063,0x0}, | ||
4708 | {0x40004,0x720}, | ||
4709 | {0x40024,0xf}, | ||
4710 | {0x40044,0x1740}, | ||
4711 | {0x40064,0x0}, | ||
4712 | {0x40005,0x16}, | ||
4713 | {0x40025,0x83}, | ||
4714 | {0x40045,0x4b}, | ||
4715 | {0x40065,0x0}, | ||
4716 | {0x40006,0x716}, | ||
4717 | {0x40026,0xf}, | ||
4718 | {0x40046,0x2001}, | ||
4719 | {0x40066,0x0}, | ||
4720 | {0x40007,0x716}, | ||
4721 | {0x40027,0xf}, | ||
4722 | {0x40047,0x2800}, | ||
4723 | {0x40067,0x0}, | ||
4724 | {0x40008,0x716}, | ||
4725 | {0x40028,0xf}, | ||
4726 | {0x40048,0xf00}, | ||
4727 | {0x40068,0x0}, | ||
4728 | {0x40009,0x720}, | ||
4729 | {0x40029,0xf}, | ||
4730 | {0x40049,0x1400}, | ||
4731 | {0x40069,0x0}, | ||
4732 | {0x4000a,0xe08}, | ||
4733 | {0x4002a,0xc15}, | ||
4734 | {0x4004a,0x0}, | ||
4735 | {0x4006a,0x0}, | ||
4736 | {0x4000b,0x623}, | ||
4737 | {0x4002b,0x15}, | ||
4738 | {0x4004b,0x0}, | ||
4739 | {0x4006b,0x0}, | ||
4740 | {0x4000c,0x4028}, | ||
4741 | {0x4002c,0x80}, | ||
4742 | {0x4004c,0x0}, | ||
4743 | {0x4006c,0x0}, | ||
4744 | {0x4000d,0xe08}, | ||
4745 | {0x4002d,0xc1a}, | ||
4746 | {0x4004d,0x0}, | ||
4747 | {0x4006d,0x0}, | ||
4748 | {0x4000e,0x623}, | ||
4749 | {0x4002e,0x1a}, | ||
4750 | {0x4004e,0x0}, | ||
4751 | {0x4006e,0x0}, | ||
4752 | {0x4000f,0x4040}, | ||
4753 | {0x4002f,0x80}, | ||
4754 | {0x4004f,0x0}, | ||
4755 | {0x4006f,0x0}, | ||
4756 | {0x40010,0x2604}, | ||
4757 | {0x40030,0x15}, | ||
4758 | {0x40050,0x0}, | ||
4759 | {0x40070,0x0}, | ||
4760 | {0x40011,0x708}, | ||
4761 | {0x40031,0x5}, | ||
4762 | {0x40051,0x0}, | ||
4763 | {0x40071,0x2002}, | ||
4764 | {0x40012,0x8}, | ||
4765 | {0x40032,0x80}, | ||
4766 | {0x40052,0x0}, | ||
4767 | {0x40072,0x0}, | ||
4768 | {0x40013,0x2604}, | ||
4769 | {0x40033,0x1a}, | ||
4770 | {0x40053,0x0}, | ||
4771 | {0x40073,0x0}, | ||
4772 | {0x40014,0x708}, | ||
4773 | {0x40034,0xa}, | ||
4774 | {0x40054,0x0}, | ||
4775 | {0x40074,0x2002}, | ||
4776 | {0x40015,0x4040}, | ||
4777 | {0x40035,0x80}, | ||
4778 | {0x40055,0x0}, | ||
4779 | {0x40075,0x0}, | ||
4780 | {0x40016,0x60a}, | ||
4781 | {0x40036,0x15}, | ||
4782 | {0x40056,0x1200}, | ||
4783 | {0x40076,0x0}, | ||
4784 | {0x40017,0x61a}, | ||
4785 | {0x40037,0x15}, | ||
4786 | {0x40057,0x1300}, | ||
4787 | {0x40077,0x0}, | ||
4788 | {0x40018,0x60a}, | ||
4789 | {0x40038,0x1a}, | ||
4790 | {0x40058,0x1200}, | ||
4791 | {0x40078,0x0}, | ||
4792 | {0x40019,0x642}, | ||
4793 | {0x40039,0x1a}, | ||
4794 | {0x40059,0x1300}, | ||
4795 | {0x40079,0x0}, | ||
4796 | {0x4001a,0x4808}, | ||
4797 | {0x4003a,0x880}, | ||
4798 | {0x4005a,0x0}, | ||
4799 | {0x4007a,0x0}, | ||
4800 | {0x900a7,0x0}, | ||
4801 | {0x900a8,0x790}, | ||
4802 | {0x900a9,0x11a}, | ||
4803 | {0x900aa,0x8}, | ||
4804 | {0x900ab,0x7aa}, | ||
4805 | {0x900ac,0x2a}, | ||
4806 | {0x900ad,0x10}, | ||
4807 | {0x900ae,0x7b2}, | ||
4808 | {0x900af,0x2a}, | ||
4809 | {0x900b0,0x0}, | ||
4810 | {0x900b1,0x7c8}, | ||
4811 | {0x900b2,0x109}, | ||
4812 | {0x900b3,0x10}, | ||
4813 | {0x900b4,0x2a8}, | ||
4814 | {0x900b5,0x129}, | ||
4815 | {0x900b6,0x8}, | ||
4816 | {0x900b7,0x370}, | ||
4817 | {0x900b8,0x129}, | ||
4818 | {0x900b9,0xa}, | ||
4819 | {0x900ba,0x3c8}, | ||
4820 | {0x900bb,0x1a9}, | ||
4821 | {0x900bc,0xc}, | ||
4822 | {0x900bd,0x408}, | ||
4823 | {0x900be,0x199}, | ||
4824 | {0x900bf,0x14}, | ||
4825 | {0x900c0,0x790}, | ||
4826 | {0x900c1,0x11a}, | ||
4827 | {0x900c2,0x8}, | ||
4828 | {0x900c3,0x4}, | ||
4829 | {0x900c4,0x18}, | ||
4830 | {0x900c5,0xe}, | ||
4831 | {0x900c6,0x408}, | ||
4832 | {0x900c7,0x199}, | ||
4833 | {0x900c8,0x8}, | ||
4834 | {0x900c9,0x8568}, | ||
4835 | {0x900ca,0x108}, | ||
4836 | {0x900cb,0x18}, | ||
4837 | {0x900cc,0x790}, | ||
4838 | {0x900cd,0x16a}, | ||
4839 | {0x900ce,0x8}, | ||
4840 | {0x900cf,0x1d8}, | ||
4841 | {0x900d0,0x169}, | ||
4842 | {0x900d1,0x10}, | ||
4843 | {0x900d2,0x8558}, | ||
4844 | {0x900d3,0x168}, | ||
4845 | {0x900d4,0x70}, | ||
4846 | {0x900d5,0x788}, | ||
4847 | {0x900d6,0x16a}, | ||
4848 | {0x900d7,0x1ff8}, | ||
4849 | {0x900d8,0x85a8}, | ||
4850 | {0x900d9,0x1e8}, | ||
4851 | {0x900da,0x50}, | ||
4852 | {0x900db,0x798}, | ||
4853 | {0x900dc,0x16a}, | ||
4854 | {0x900dd,0x60}, | ||
4855 | {0x900de,0x7a0}, | ||
4856 | {0x900df,0x16a}, | ||
4857 | {0x900e0,0x8}, | ||
4858 | {0x900e1,0x8310}, | ||
4859 | {0x900e2,0x168}, | ||
4860 | {0x900e3,0x8}, | ||
4861 | {0x900e4,0xa310}, | ||
4862 | {0x900e5,0x168}, | ||
4863 | {0x900e6,0xa}, | ||
4864 | {0x900e7,0x408}, | ||
4865 | {0x900e8,0x169}, | ||
4866 | {0x900e9,0x6e}, | ||
4867 | {0x900ea,0x0}, | ||
4868 | {0x900eb,0x68}, | ||
4869 | {0x900ec,0x0}, | ||
4870 | {0x900ed,0x408}, | ||
4871 | {0x900ee,0x169}, | ||
4872 | {0x900ef,0x0}, | ||
4873 | {0x900f0,0x8310}, | ||
4874 | {0x900f1,0x168}, | ||
4875 | {0x900f2,0x0}, | ||
4876 | {0x900f3,0xa310}, | ||
4877 | {0x900f4,0x168}, | ||
4878 | {0x900f5,0x1ff8}, | ||
4879 | {0x900f6,0x85a8}, | ||
4880 | {0x900f7,0x1e8}, | ||
4881 | {0x900f8,0x68}, | ||
4882 | {0x900f9,0x798}, | ||
4883 | {0x900fa,0x16a}, | ||
4884 | {0x900fb,0x78}, | ||
4885 | {0x900fc,0x7a0}, | ||
4886 | {0x900fd,0x16a}, | ||
4887 | {0x900fe,0x68}, | ||
4888 | {0x900ff,0x790}, | ||
4889 | {0x90100,0x16a}, | ||
4890 | {0x90101,0x8}, | ||
4891 | {0x90102,0x8b10}, | ||
4892 | {0x90103,0x168}, | ||
4893 | {0x90104,0x8}, | ||
4894 | {0x90105,0xab10}, | ||
4895 | {0x90106,0x168}, | ||
4896 | {0x90107,0xa}, | ||
4897 | {0x90108,0x408}, | ||
4898 | {0x90109,0x169}, | ||
4899 | {0x9010a,0x58}, | ||
4900 | {0x9010b,0x0}, | ||
4901 | {0x9010c,0x68}, | ||
4902 | {0x9010d,0x0}, | ||
4903 | {0x9010e,0x408}, | ||
4904 | {0x9010f,0x169}, | ||
4905 | {0x90110,0x0}, | ||
4906 | {0x90111,0x8b10}, | ||
4907 | {0x90112,0x168}, | ||
4908 | {0x90113,0x0}, | ||
4909 | {0x90114,0xab10}, | ||
4910 | {0x90115,0x168}, | ||
4911 | {0x90116,0x0}, | ||
4912 | {0x90117,0x1d8}, | ||
4913 | {0x90118,0x169}, | ||
4914 | {0x90119,0x80}, | ||
4915 | {0x9011a,0x790}, | ||
4916 | {0x9011b,0x16a}, | ||
4917 | {0x9011c,0x18}, | ||
4918 | {0x9011d,0x7aa}, | ||
4919 | {0x9011e,0x6a}, | ||
4920 | {0x9011f,0xa}, | ||
4921 | {0x90120,0x0}, | ||
4922 | {0x90121,0x1e9}, | ||
4923 | {0x90122,0x8}, | ||
4924 | {0x90123,0x8080}, | ||
4925 | {0x90124,0x108}, | ||
4926 | {0x90125,0xf}, | ||
4927 | {0x90126,0x408}, | ||
4928 | {0x90127,0x169}, | ||
4929 | {0x90128,0xc}, | ||
4930 | {0x90129,0x0}, | ||
4931 | {0x9012a,0x68}, | ||
4932 | {0x9012b,0x9}, | ||
4933 | {0x9012c,0x0}, | ||
4934 | {0x9012d,0x1a9}, | ||
4935 | {0x9012e,0x0}, | ||
4936 | {0x9012f,0x408}, | ||
4937 | {0x90130,0x169}, | ||
4938 | {0x90131,0x0}, | ||
4939 | {0x90132,0x8080}, | ||
4940 | {0x90133,0x108}, | ||
4941 | {0x90134,0x8}, | ||
4942 | {0x90135,0x7aa}, | ||
4943 | {0x90136,0x6a}, | ||
4944 | {0x90137,0x0}, | ||
4945 | {0x90138,0x8568}, | ||
4946 | {0x90139,0x108}, | ||
4947 | {0x9013a,0xb7}, | ||
4948 | {0x9013b,0x790}, | ||
4949 | {0x9013c,0x16a}, | ||
4950 | {0x9013d,0x1f}, | ||
4951 | {0x9013e,0x0}, | ||
4952 | {0x9013f,0x68}, | ||
4953 | {0x90140,0x8}, | ||
4954 | {0x90141,0x8558}, | ||
4955 | {0x90142,0x168}, | ||
4956 | {0x90143,0xf}, | ||
4957 | {0x90144,0x408}, | ||
4958 | {0x90145,0x169}, | ||
4959 | {0x90146,0xc}, | ||
4960 | {0x90147,0x0}, | ||
4961 | {0x90148,0x68}, | ||
4962 | {0x90149,0x0}, | ||
4963 | {0x9014a,0x408}, | ||
4964 | {0x9014b,0x169}, | ||
4965 | {0x9014c,0x0}, | ||
4966 | {0x9014d,0x8558}, | ||
4967 | {0x9014e,0x168}, | ||
4968 | {0x9014f,0x8}, | ||
4969 | {0x90150,0x3c8}, | ||
4970 | {0x90151,0x1a9}, | ||
4971 | {0x90152,0x3}, | ||
4972 | {0x90153,0x370}, | ||
4973 | {0x90154,0x129}, | ||
4974 | {0x90155,0x20}, | ||
4975 | {0x90156,0x2aa}, | ||
4976 | {0x90157,0x9}, | ||
4977 | {0x90158,0x0}, | ||
4978 | {0x90159,0x400}, | ||
4979 | {0x9015a,0x10e}, | ||
4980 | {0x9015b,0x8}, | ||
4981 | {0x9015c,0xe8}, | ||
4982 | {0x9015d,0x109}, | ||
4983 | {0x9015e,0x0}, | ||
4984 | {0x9015f,0x8140}, | ||
4985 | {0x90160,0x10c}, | ||
4986 | {0x90161,0x10}, | ||
4987 | {0x90162,0x8138}, | ||
4988 | {0x90163,0x10c}, | ||
4989 | {0x90164,0x8}, | ||
4990 | {0x90165,0x7c8}, | ||
4991 | {0x90166,0x101}, | ||
4992 | {0x90167,0x8}, | ||
4993 | {0x90168,0x0}, | ||
4994 | {0x90169,0x8}, | ||
4995 | {0x9016a,0x8}, | ||
4996 | {0x9016b,0x448}, | ||
4997 | {0x9016c,0x109}, | ||
4998 | {0x9016d,0xf}, | ||
4999 | {0x9016e,0x7c0}, | ||
5000 | {0x9016f,0x109}, | ||
5001 | {0x90170,0x0}, | ||
5002 | {0x90171,0xe8}, | ||
5003 | {0x90172,0x109}, | ||
5004 | {0x90173,0x47}, | ||
5005 | {0x90174,0x630}, | ||
5006 | {0x90175,0x109}, | ||
5007 | {0x90176,0x8}, | ||
5008 | {0x90177,0x618}, | ||
5009 | {0x90178,0x109}, | ||
5010 | {0x90179,0x8}, | ||
5011 | {0x9017a,0xe0}, | ||
5012 | {0x9017b,0x109}, | ||
5013 | {0x9017c,0x0}, | ||
5014 | {0x9017d,0x7c8}, | ||
5015 | {0x9017e,0x109}, | ||
5016 | {0x9017f,0x8}, | ||
5017 | {0x90180,0x8140}, | ||
5018 | {0x90181,0x10c}, | ||
5019 | {0x90182,0x0}, | ||
5020 | {0x90183,0x1}, | ||
5021 | {0x90184,0x8}, | ||
5022 | {0x90185,0x8}, | ||
5023 | {0x90186,0x4}, | ||
5024 | {0x90187,0x8}, | ||
5025 | {0x90188,0x8}, | ||
5026 | {0x90189,0x7c8}, | ||
5027 | {0x9018a,0x101}, | ||
5028 | {0x90006,0x0}, | ||
5029 | {0x90007,0x0}, | ||
5030 | {0x90008,0x8}, | ||
5031 | {0x90009,0x0}, | ||
5032 | {0x9000a,0x0}, | ||
5033 | {0x9000b,0x0}, | ||
5034 | {0xd00e7,0x400}, | ||
5035 | {0x90017,0x0}, | ||
5036 | {0x9001f,0x2a}, | ||
5037 | {0x90026,0x6a}, | ||
5038 | {0x400d0,0x0}, | ||
5039 | {0x400d1,0x101}, | ||
5040 | {0x400d2,0x105}, | ||
5041 | {0x400d3,0x107}, | ||
5042 | {0x400d4,0x10f}, | ||
5043 | {0x400d5,0x202}, | ||
5044 | {0x400d6,0x20a}, | ||
5045 | {0x400d7,0x20b}, | ||
5046 | {0x2003a,0x2}, | ||
5047 | {0x2000b,0x64}, | ||
5048 | {0x2000c,0xc8}, | ||
5049 | {0x2000d,0x7d0}, | ||
5050 | {0x2000e,0x2c}, | ||
5051 | {0x12000b,0x14}, | ||
5052 | {0x12000c,0x29}, | ||
5053 | {0x12000d,0x1a1}, | ||
5054 | {0x12000e,0x10}, | ||
5055 | {0x9000c,0x0}, | ||
5056 | {0x9000d,0x173}, | ||
5057 | {0x9000e,0x60}, | ||
5058 | {0x9000f,0x6110}, | ||
5059 | {0x90010,0x2152}, | ||
5060 | {0x90011,0xdfbd}, | ||
5061 | {0x90012,0x60}, | ||
5062 | {0x90013,0x6152}, | ||
5063 | {0x20010,0x5a}, | ||
5064 | {0x20011,0x3}, | ||
5065 | {0x120010,0x5a}, | ||
5066 | {0x120011,0x3}, | ||
5067 | {0x40080,0xe0}, | ||
5068 | {0x40081,0x12}, | ||
5069 | {0x40082,0xe0}, | ||
5070 | {0x40083,0x12}, | ||
5071 | {0x40084,0xe0}, | ||
5072 | {0x40085,0x12}, | ||
5073 | {0x140080,0xe0}, | ||
5074 | {0x140081,0x12}, | ||
5075 | {0x140082,0xe0}, | ||
5076 | {0x140083,0x12}, | ||
5077 | {0x140084,0xe0}, | ||
5078 | {0x140085,0x12}, | ||
5079 | {0x400fd,0xf}, | ||
5080 | {0x10011,0x1}, | ||
5081 | {0x10012,0x1}, | ||
5082 | {0x10013,0x180}, | ||
5083 | {0x10018,0x1}, | ||
5084 | {0x10002,0x6209}, | ||
5085 | {0x100b2,0x1}, | ||
5086 | {0x101b4,0x1}, | ||
5087 | {0x102b4,0x1}, | ||
5088 | {0x103b4,0x1}, | ||
5089 | {0x104b4,0x1}, | ||
5090 | {0x105b4,0x1}, | ||
5091 | {0x106b4,0x1}, | ||
5092 | {0x107b4,0x1}, | ||
5093 | {0x108b4,0x1}, | ||
5094 | {0x11011,0x1}, | ||
5095 | {0x11012,0x1}, | ||
5096 | {0x11013,0x180}, | ||
5097 | {0x11018,0x1}, | ||
5098 | {0x11002,0x6209}, | ||
5099 | {0x110b2,0x1}, | ||
5100 | {0x111b4,0x1}, | ||
5101 | {0x112b4,0x1}, | ||
5102 | {0x113b4,0x1}, | ||
5103 | {0x114b4,0x1}, | ||
5104 | {0x115b4,0x1}, | ||
5105 | {0x116b4,0x1}, | ||
5106 | {0x117b4,0x1}, | ||
5107 | {0x118b4,0x1}, | ||
5108 | {0x12011,0x1}, | ||
5109 | {0x12012,0x1}, | ||
5110 | {0x12013,0x180}, | ||
5111 | {0x12018,0x1}, | ||
5112 | {0x12002,0x6209}, | ||
5113 | {0x120b2,0x1}, | ||
5114 | {0x121b4,0x1}, | ||
5115 | {0x122b4,0x1}, | ||
5116 | {0x123b4,0x1}, | ||
5117 | {0x124b4,0x1}, | ||
5118 | {0x125b4,0x1}, | ||
5119 | {0x126b4,0x1}, | ||
5120 | {0x127b4,0x1}, | ||
5121 | {0x128b4,0x1}, | ||
5122 | {0x13011,0x1}, | ||
5123 | {0x13012,0x1}, | ||
5124 | {0x13013,0x180}, | ||
5125 | {0x13018,0x1}, | ||
5126 | {0x13002,0x6209}, | ||
5127 | {0x130b2,0x1}, | ||
5128 | {0x131b4,0x1}, | ||
5129 | {0x132b4,0x1}, | ||
5130 | {0x133b4,0x1}, | ||
5131 | {0x134b4,0x1}, | ||
5132 | {0x135b4,0x1}, | ||
5133 | {0x136b4,0x1}, |
configs/smarcimx8mq_2g_ser0_ind_android_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER0=y | 9 | CONFIG_CONSOLE_SER0=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | CONFIG_NOT_UUU_BUILD=y | 81 | CONFIG_NOT_UUU_BUILD=y |
82 | CONFIG_APPEND_BOOTARGS=y | 82 | CONFIG_APPEND_BOOTARGS=y |
83 | 83 |
configs/smarcimx8mq_2g_ser0_ind_android_uuu_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER0=y | 9 | CONFIG_CONSOLE_SER0=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | 81 |
configs/smarcimx8mq_2g_ser0_ind_androidthings_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_THINGS_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_THINGS_SUPPORT" |
9 | CONFIG_CONSOLE_SER0=y | 9 | CONFIG_CONSOLE_SER0=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_USB_FUNCTION_FASTBOOT=y | 55 | CONFIG_USB_FUNCTION_FASTBOOT=y |
56 | CONFIG_FSL_FASTBOOT=y | 56 | CONFIG_FSL_FASTBOOT=y |
57 | CONFIG_BCB_SUPPORT=y | 57 | CONFIG_BCB_SUPPORT=y |
58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
59 | CONFIG_SPL_ENV_SUPPORT=y | 59 | CONFIG_SPL_ENV_SUPPORT=y |
60 | CONFIG_CMD_FASTBOOT=y | 60 | CONFIG_CMD_FASTBOOT=y |
61 | CONFIG_ANDROID_BOOT_IMAGE=y | 61 | CONFIG_ANDROID_BOOT_IMAGE=y |
62 | CONFIG_EFI_PARTITION=y | 62 | CONFIG_EFI_PARTITION=y |
63 | CONFIG_SDP_LOADADDR=0x40400000 | 63 | CONFIG_SDP_LOADADDR=0x40400000 |
64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
67 | CONFIG_USB_GADGET_DOWNLOAD=y | 67 | CONFIG_USB_GADGET_DOWNLOAD=y |
68 | CONFIG_SPL_USB_HOST_SUPPORT=y | 68 | CONFIG_SPL_USB_HOST_SUPPORT=y |
69 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 69 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
70 | CONFIG_SPL_USB_SDP_SUPPORT=y | 70 | CONFIG_SPL_USB_SDP_SUPPORT=y |
71 | CONFIG_USB_XHCI_HCD=y | 71 | CONFIG_USB_XHCI_HCD=y |
72 | CONFIG_USB_XHCI_IMX8M=y | 72 | CONFIG_USB_XHCI_IMX8M=y |
73 | CONFIG_USB_XHCI_DWC3=y | 73 | CONFIG_USB_XHCI_DWC3=y |
74 | CONFIG_USB_DWC3=y | 74 | CONFIG_USB_DWC3=y |
75 | CONFIG_USB_DWC3_GADGET=y | 75 | CONFIG_USB_DWC3_GADGET=y |
76 | CONFIG_SPL_LIBDISK_SUPPORT=y | 76 | CONFIG_SPL_LIBDISK_SUPPORT=y |
77 | CONFIG_DUAL_BOOTLOADER=y | 77 | CONFIG_DUAL_BOOTLOADER=y |
78 | 78 |
configs/smarcimx8mq_2g_ser0_ind_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND" |
9 | CONFIG_CONSOLE_SER0=y | 9 | CONFIG_CONSOLE_SER0=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_FASTBOOT=y | 55 | CONFIG_FASTBOOT=y |
56 | CONFIG_USB_FUNCTION_FASTBOOT=y | 56 | CONFIG_USB_FUNCTION_FASTBOOT=y |
57 | CONFIG_CMD_FASTBOOT=y | 57 | CONFIG_CMD_FASTBOOT=y |
58 | CONFIG_ANDROID_BOOT_IMAGE=y | 58 | CONFIG_ANDROID_BOOT_IMAGE=y |
59 | CONFIG_FSL_FASTBOOT=y | 59 | CONFIG_FSL_FASTBOOT=y |
60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
62 | CONFIG_FASTBOOT_FLASH=y | 62 | CONFIG_FASTBOOT_FLASH=y |
63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
64 | CONFIG_EFI_PARTITION=y | 64 | CONFIG_EFI_PARTITION=y |
65 | CONFIG_SDP_LOADADDR=0x40400000 | 65 | CONFIG_SDP_LOADADDR=0x40400000 |
66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
69 | CONFIG_USB_GADGET_DOWNLOAD=y | 69 | CONFIG_USB_GADGET_DOWNLOAD=y |
70 | CONFIG_SPL_USB_HOST_SUPPORT=y | 70 | CONFIG_SPL_USB_HOST_SUPPORT=y |
71 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 71 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
72 | CONFIG_SPL_USB_SDP_SUPPORT=y | 72 | CONFIG_SPL_USB_SDP_SUPPORT=y |
73 | CONFIG_USB_XHCI_HCD=y | 73 | CONFIG_USB_XHCI_HCD=y |
74 | CONFIG_USB_XHCI_IMX8M=y | 74 | CONFIG_USB_XHCI_IMX8M=y |
75 | CONFIG_USB_XHCI_DWC3=y | 75 | CONFIG_USB_XHCI_DWC3=y |
76 | CONFIG_USB_DWC3=y | 76 | CONFIG_USB_DWC3=y |
77 | CONFIG_USB_DWC3_GADGET=y | 77 | CONFIG_USB_DWC3_GADGET=y |
78 | 78 |
configs/smarcimx8mq_2g_ser1_ind_android_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER3=y | 9 | CONFIG_CONSOLE_SER3=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | CONFIG_NOT_UUU_BUILD=y | 81 | CONFIG_NOT_UUU_BUILD=y |
82 | CONFIG_APPEND_BOOTARGS=y | 82 | CONFIG_APPEND_BOOTARGS=y |
83 | 83 |
configs/smarcimx8mq_2g_ser1_ind_android_uuu_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER1=y | 9 | CONFIG_CONSOLE_SER1=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | 81 |
configs/smarcimx8mq_2g_ser1_ind_androidthings_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_THINGS_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_THINGS_SUPPORT" |
9 | CONFIG_CONSOLE_SER1=y | 9 | CONFIG_CONSOLE_SER1=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_USB_FUNCTION_FASTBOOT=y | 55 | CONFIG_USB_FUNCTION_FASTBOOT=y |
56 | CONFIG_FSL_FASTBOOT=y | 56 | CONFIG_FSL_FASTBOOT=y |
57 | CONFIG_BCB_SUPPORT=y | 57 | CONFIG_BCB_SUPPORT=y |
58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
59 | CONFIG_SPL_ENV_SUPPORT=y | 59 | CONFIG_SPL_ENV_SUPPORT=y |
60 | CONFIG_CMD_FASTBOOT=y | 60 | CONFIG_CMD_FASTBOOT=y |
61 | CONFIG_ANDROID_BOOT_IMAGE=y | 61 | CONFIG_ANDROID_BOOT_IMAGE=y |
62 | CONFIG_EFI_PARTITION=y | 62 | CONFIG_EFI_PARTITION=y |
63 | CONFIG_SDP_LOADADDR=0x40400000 | 63 | CONFIG_SDP_LOADADDR=0x40400000 |
64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
67 | CONFIG_USB_GADGET_DOWNLOAD=y | 67 | CONFIG_USB_GADGET_DOWNLOAD=y |
68 | CONFIG_SPL_USB_HOST_SUPPORT=y | 68 | CONFIG_SPL_USB_HOST_SUPPORT=y |
69 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 69 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
70 | CONFIG_SPL_USB_SDP_SUPPORT=y | 70 | CONFIG_SPL_USB_SDP_SUPPORT=y |
71 | CONFIG_USB_XHCI_HCD=y | 71 | CONFIG_USB_XHCI_HCD=y |
72 | CONFIG_USB_XHCI_IMX8M=y | 72 | CONFIG_USB_XHCI_IMX8M=y |
73 | CONFIG_USB_XHCI_DWC3=y | 73 | CONFIG_USB_XHCI_DWC3=y |
74 | CONFIG_USB_DWC3=y | 74 | CONFIG_USB_DWC3=y |
75 | CONFIG_USB_DWC3_GADGET=y | 75 | CONFIG_USB_DWC3_GADGET=y |
76 | CONFIG_SPL_LIBDISK_SUPPORT=y | 76 | CONFIG_SPL_LIBDISK_SUPPORT=y |
77 | CONFIG_DUAL_BOOTLOADER=y | 77 | CONFIG_DUAL_BOOTLOADER=y |
78 | 78 |
configs/smarcimx8mq_2g_ser1_ind_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND" |
9 | CONFIG_CONSOLE_SER1=y | 9 | CONFIG_CONSOLE_SER1=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_FASTBOOT=y | 55 | CONFIG_FASTBOOT=y |
56 | CONFIG_USB_FUNCTION_FASTBOOT=y | 56 | CONFIG_USB_FUNCTION_FASTBOOT=y |
57 | CONFIG_CMD_FASTBOOT=y | 57 | CONFIG_CMD_FASTBOOT=y |
58 | CONFIG_ANDROID_BOOT_IMAGE=y | 58 | CONFIG_ANDROID_BOOT_IMAGE=y |
59 | CONFIG_FSL_FASTBOOT=y | 59 | CONFIG_FSL_FASTBOOT=y |
60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
62 | CONFIG_FASTBOOT_FLASH=y | 62 | CONFIG_FASTBOOT_FLASH=y |
63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
64 | CONFIG_EFI_PARTITION=y | 64 | CONFIG_EFI_PARTITION=y |
65 | CONFIG_SDP_LOADADDR=0x40400000 | 65 | CONFIG_SDP_LOADADDR=0x40400000 |
66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
69 | CONFIG_USB_GADGET_DOWNLOAD=y | 69 | CONFIG_USB_GADGET_DOWNLOAD=y |
70 | CONFIG_SPL_USB_HOST_SUPPORT=y | 70 | CONFIG_SPL_USB_HOST_SUPPORT=y |
71 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 71 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
72 | CONFIG_SPL_USB_SDP_SUPPORT=y | 72 | CONFIG_SPL_USB_SDP_SUPPORT=y |
73 | CONFIG_USB_XHCI_HCD=y | 73 | CONFIG_USB_XHCI_HCD=y |
74 | CONFIG_USB_XHCI_IMX8M=y | 74 | CONFIG_USB_XHCI_IMX8M=y |
75 | CONFIG_USB_XHCI_DWC3=y | 75 | CONFIG_USB_XHCI_DWC3=y |
76 | CONFIG_USB_DWC3=y | 76 | CONFIG_USB_DWC3=y |
77 | CONFIG_USB_DWC3_GADGET=y | 77 | CONFIG_USB_DWC3_GADGET=y |
78 | 78 |
configs/smarcimx8mq_2g_ser2_ind_android_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER1=y | 9 | CONFIG_CONSOLE_SER1=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | CONFIG_NOT_UUU_BUILD=y | 81 | CONFIG_NOT_UUU_BUILD=y |
82 | CONFIG_APPEND_BOOTARGS=y | 82 | CONFIG_APPEND_BOOTARGS=y |
83 | 83 |
configs/smarcimx8mq_2g_ser2_ind_android_uuu_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER2=y | 9 | CONFIG_CONSOLE_SER2=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | 81 |
configs/smarcimx8mq_2g_ser2_ind_androidthings_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_THINGS_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_THINGS_SUPPORT" |
9 | CONFIG_CONSOLE_SER2=y | 9 | CONFIG_CONSOLE_SER2=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_USB_FUNCTION_FASTBOOT=y | 55 | CONFIG_USB_FUNCTION_FASTBOOT=y |
56 | CONFIG_FSL_FASTBOOT=y | 56 | CONFIG_FSL_FASTBOOT=y |
57 | CONFIG_BCB_SUPPORT=y | 57 | CONFIG_BCB_SUPPORT=y |
58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
59 | CONFIG_SPL_ENV_SUPPORT=y | 59 | CONFIG_SPL_ENV_SUPPORT=y |
60 | CONFIG_CMD_FASTBOOT=y | 60 | CONFIG_CMD_FASTBOOT=y |
61 | CONFIG_ANDROID_BOOT_IMAGE=y | 61 | CONFIG_ANDROID_BOOT_IMAGE=y |
62 | CONFIG_EFI_PARTITION=y | 62 | CONFIG_EFI_PARTITION=y |
63 | CONFIG_SDP_LOADADDR=0x40400000 | 63 | CONFIG_SDP_LOADADDR=0x40400000 |
64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
67 | CONFIG_USB_GADGET_DOWNLOAD=y | 67 | CONFIG_USB_GADGET_DOWNLOAD=y |
68 | CONFIG_SPL_USB_HOST_SUPPORT=y | 68 | CONFIG_SPL_USB_HOST_SUPPORT=y |
69 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 69 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
70 | CONFIG_SPL_USB_SDP_SUPPORT=y | 70 | CONFIG_SPL_USB_SDP_SUPPORT=y |
71 | CONFIG_USB_XHCI_HCD=y | 71 | CONFIG_USB_XHCI_HCD=y |
72 | CONFIG_USB_XHCI_IMX8M=y | 72 | CONFIG_USB_XHCI_IMX8M=y |
73 | CONFIG_USB_XHCI_DWC3=y | 73 | CONFIG_USB_XHCI_DWC3=y |
74 | CONFIG_USB_DWC3=y | 74 | CONFIG_USB_DWC3=y |
75 | CONFIG_USB_DWC3_GADGET=y | 75 | CONFIG_USB_DWC3_GADGET=y |
76 | CONFIG_SPL_LIBDISK_SUPPORT=y | 76 | CONFIG_SPL_LIBDISK_SUPPORT=y |
77 | CONFIG_DUAL_BOOTLOADER=y | 77 | CONFIG_DUAL_BOOTLOADER=y |
78 | 78 |
configs/smarcimx8mq_2g_ser2_ind_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND" |
9 | CONFIG_CONSOLE_SER2=y | 9 | CONFIG_CONSOLE_SER2=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_FASTBOOT=y | 55 | CONFIG_FASTBOOT=y |
56 | CONFIG_USB_FUNCTION_FASTBOOT=y | 56 | CONFIG_USB_FUNCTION_FASTBOOT=y |
57 | CONFIG_CMD_FASTBOOT=y | 57 | CONFIG_CMD_FASTBOOT=y |
58 | CONFIG_ANDROID_BOOT_IMAGE=y | 58 | CONFIG_ANDROID_BOOT_IMAGE=y |
59 | CONFIG_FSL_FASTBOOT=y | 59 | CONFIG_FSL_FASTBOOT=y |
60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
62 | CONFIG_FASTBOOT_FLASH=y | 62 | CONFIG_FASTBOOT_FLASH=y |
63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
64 | CONFIG_EFI_PARTITION=y | 64 | CONFIG_EFI_PARTITION=y |
65 | CONFIG_SDP_LOADADDR=0x40400000 | 65 | CONFIG_SDP_LOADADDR=0x40400000 |
66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
69 | CONFIG_USB_GADGET_DOWNLOAD=y | 69 | CONFIG_USB_GADGET_DOWNLOAD=y |
70 | CONFIG_SPL_USB_HOST_SUPPORT=y | 70 | CONFIG_SPL_USB_HOST_SUPPORT=y |
71 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 71 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
72 | CONFIG_SPL_USB_SDP_SUPPORT=y | 72 | CONFIG_SPL_USB_SDP_SUPPORT=y |
73 | CONFIG_USB_XHCI_HCD=y | 73 | CONFIG_USB_XHCI_HCD=y |
74 | CONFIG_USB_XHCI_IMX8M=y | 74 | CONFIG_USB_XHCI_IMX8M=y |
75 | CONFIG_USB_XHCI_DWC3=y | 75 | CONFIG_USB_XHCI_DWC3=y |
76 | CONFIG_USB_DWC3=y | 76 | CONFIG_USB_DWC3=y |
77 | CONFIG_USB_DWC3_GADGET=y | 77 | CONFIG_USB_DWC3_GADGET=y |
78 | 78 |
configs/smarcimx8mq_2g_ser3_ind_android_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER3=y | 9 | CONFIG_CONSOLE_SER3=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | CONFIG_NOT_UUU_BUILD=y | 81 | CONFIG_NOT_UUU_BUILD=y |
82 | CONFIG_APPEND_BOOTARGS=y | 82 | CONFIG_APPEND_BOOTARGS=y |
83 | 83 |
configs/smarcimx8mq_2g_ser3_ind_android_uuu_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_SUPPORT" |
9 | CONFIG_CONSOLE_SER3=y | 9 | CONFIG_CONSOLE_SER3=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_LZ4=y | 54 | CONFIG_LZ4=y |
55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 55 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
56 | CONFIG_USB_GADGET=y | 56 | CONFIG_USB_GADGET=y |
57 | CONFIG_FASTBOOT=y | 57 | CONFIG_FASTBOOT=y |
58 | CONFIG_USB_FUNCTION_FASTBOOT=y | 58 | CONFIG_USB_FUNCTION_FASTBOOT=y |
59 | CONFIG_CMD_FASTBOOT=y | 59 | CONFIG_CMD_FASTBOOT=y |
60 | CONFIG_ANDROID_BOOT_IMAGE=y | 60 | CONFIG_ANDROID_BOOT_IMAGE=y |
61 | CONFIG_FSL_FASTBOOT=y | 61 | CONFIG_FSL_FASTBOOT=y |
62 | CONFIG_BCB_SUPPORT=y | 62 | CONFIG_BCB_SUPPORT=y |
63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 63 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 64 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
65 | CONFIG_FASTBOOT_FLASH=y | 65 | CONFIG_FASTBOOT_FLASH=y |
66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 66 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
67 | CONFIG_EFI_PARTITION=y | 67 | CONFIG_EFI_PARTITION=y |
68 | CONFIG_SDP_LOADADDR=0x40400000 | 68 | CONFIG_SDP_LOADADDR=0x40400000 |
69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 69 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 70 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 71 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
72 | CONFIG_USB_GADGET_DOWNLOAD=y | 72 | CONFIG_USB_GADGET_DOWNLOAD=y |
73 | CONFIG_SPL_USB_HOST_SUPPORT=y | 73 | CONFIG_SPL_USB_HOST_SUPPORT=y |
74 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 74 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
75 | CONFIG_SPL_USB_SDP_SUPPORT=y | 75 | CONFIG_SPL_USB_SDP_SUPPORT=y |
76 | CONFIG_USB_XHCI_HCD=y | 76 | CONFIG_USB_XHCI_HCD=y |
77 | CONFIG_USB_XHCI_IMX8M=y | 77 | CONFIG_USB_XHCI_IMX8M=y |
78 | CONFIG_USB_XHCI_DWC3=y | 78 | CONFIG_USB_XHCI_DWC3=y |
79 | CONFIG_USB_DWC3=y | 79 | CONFIG_USB_DWC3=y |
80 | CONFIG_USB_DWC3_GADGET=y | 80 | CONFIG_USB_DWC3_GADGET=y |
81 | 81 |
configs/smarcimx8mq_2g_ser3_ind_androidthings_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND,ANDROID_THINGS_SUPPORT" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND,ANDROID_THINGS_SUPPORT" |
9 | CONFIG_CONSOLE_SER3=y | 9 | CONFIG_CONSOLE_SER3=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_USB_FUNCTION_FASTBOOT=y | 55 | CONFIG_USB_FUNCTION_FASTBOOT=y |
56 | CONFIG_FSL_FASTBOOT=y | 56 | CONFIG_FSL_FASTBOOT=y |
57 | CONFIG_BCB_SUPPORT=y | 57 | CONFIG_BCB_SUPPORT=y |
58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 58 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
59 | CONFIG_SPL_ENV_SUPPORT=y | 59 | CONFIG_SPL_ENV_SUPPORT=y |
60 | CONFIG_CMD_FASTBOOT=y | 60 | CONFIG_CMD_FASTBOOT=y |
61 | CONFIG_ANDROID_BOOT_IMAGE=y | 61 | CONFIG_ANDROID_BOOT_IMAGE=y |
62 | CONFIG_EFI_PARTITION=y | 62 | CONFIG_EFI_PARTITION=y |
63 | CONFIG_SDP_LOADADDR=0x40400000 | 63 | CONFIG_SDP_LOADADDR=0x40400000 |
64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 64 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 65 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 66 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
67 | CONFIG_USB_GADGET_DOWNLOAD=y | 67 | CONFIG_USB_GADGET_DOWNLOAD=y |
68 | CONFIG_SPL_USB_HOST_SUPPORT=y | 68 | CONFIG_SPL_USB_HOST_SUPPORT=y |
69 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 69 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
70 | CONFIG_SPL_USB_SDP_SUPPORT=y | 70 | CONFIG_SPL_USB_SDP_SUPPORT=y |
71 | CONFIG_USB_XHCI_HCD=y | 71 | CONFIG_USB_XHCI_HCD=y |
72 | CONFIG_USB_XHCI_IMX8M=y | 72 | CONFIG_USB_XHCI_IMX8M=y |
73 | CONFIG_USB_XHCI_DWC3=y | 73 | CONFIG_USB_XHCI_DWC3=y |
74 | CONFIG_USB_DWC3=y | 74 | CONFIG_USB_DWC3=y |
75 | CONFIG_USB_DWC3_GADGET=y | 75 | CONFIG_USB_DWC3_GADGET=y |
76 | CONFIG_SPL_LIBDISK_SUPPORT=y | 76 | CONFIG_SPL_LIBDISK_SUPPORT=y |
77 | CONFIG_DUAL_BOOTLOADER=y | 77 | CONFIG_DUAL_BOOTLOADER=y |
78 | 78 |
configs/smarcimx8mq_2g_ser3_ind_defconfig
1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | 2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
5 | CONFIG_BOOTDELAY=1 | 5 | CONFIG_BOOTDELAY=1 |
6 | CONFIG_TARGET_SMARCIMX8MQ=y | 6 | CONFIG_TARGET_SMARCIMX8MQ=y |
7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | 7 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,IND" | 8 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4_IND" |
9 | CONFIG_CONSOLE_SER3=y | 9 | CONFIG_CONSOLE_SER3=y |
10 | CONFIG_ARCH_MISC_INIT=y | 10 | CONFIG_ARCH_MISC_INIT=y |
11 | CONFIG_SPL=y | 11 | CONFIG_SPL=y |
12 | CONFIG_SPL_BOARD_INIT=y | 12 | CONFIG_SPL_BOARD_INIT=y |
13 | CONFIG_HUSH_PARSER=y | 13 | CONFIG_HUSH_PARSER=y |
14 | CONFIG_OF_LIBFDT=y | 14 | CONFIG_OF_LIBFDT=y |
15 | CONFIG_FS_FAT=y | 15 | CONFIG_FS_FAT=y |
16 | CONFIG_CMD_CACHE=y | 16 | CONFIG_CMD_CACHE=y |
17 | CONFIG_CMD_EXT2=y | 17 | CONFIG_CMD_EXT2=y |
18 | CONFIG_CMD_EXT4=y | 18 | CONFIG_CMD_EXT4=y |
19 | CONFIG_CMD_EXT4_WRITE=y | 19 | CONFIG_CMD_EXT4_WRITE=y |
20 | CONFIG_CMD_FAT=y | 20 | CONFIG_CMD_FAT=y |
21 | CONFIG_CMD_MEMTEST=y | 21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" | 22 | CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq" |
23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" | 23 | CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb" |
24 | CONFIG_ENV_IS_IN_MMC=y | 24 | CONFIG_ENV_IS_IN_MMC=y |
25 | CONFIG_OF_CONTROL=y | 25 | CONFIG_OF_CONTROL=y |
26 | CONFIG_PINCTRL=y | 26 | CONFIG_PINCTRL=y |
27 | CONFIG_PINCTRL_IMX8M=y | 27 | CONFIG_PINCTRL_IMX8M=y |
28 | CONFIG_SYS_I2C_MXC=y | 28 | CONFIG_SYS_I2C_MXC=y |
29 | CONFIG_CMD_I2C=y | 29 | CONFIG_CMD_I2C=y |
30 | CONFIG_DM_I2C=y | 30 | CONFIG_DM_I2C=y |
31 | CONFIG_DM_GPIO=y | 31 | CONFIG_DM_GPIO=y |
32 | CONFIG_CMD_GPIO=y | 32 | CONFIG_CMD_GPIO=y |
33 | CONFIG_CMD_GPT=y | 33 | CONFIG_CMD_GPT=y |
34 | CONFIG_CMD_TIME=y | 34 | CONFIG_CMD_TIME=y |
35 | CONFIG_DM_MMC=y | 35 | CONFIG_DM_MMC=y |
36 | CONFIG_CMD_REGULATOR=y | 36 | CONFIG_CMD_REGULATOR=y |
37 | CONFIG_DM_PMIC=y | 37 | CONFIG_DM_PMIC=y |
38 | CONFIG_DM_PMIC_PFUZE100=y | 38 | CONFIG_DM_PMIC_PFUZE100=y |
39 | CONFIG_DM_REGULATOR=y | 39 | CONFIG_DM_REGULATOR=y |
40 | CONFIG_DM_REGULATOR_PFUZE100=y | 40 | CONFIG_DM_REGULATOR_PFUZE100=y |
41 | CONFIG_DM_REGULATOR_FIXED=y | 41 | CONFIG_DM_REGULATOR_FIXED=y |
42 | CONFIG_DM_REGULATOR_GPIO=y | 42 | CONFIG_DM_REGULATOR_GPIO=y |
43 | CONFIG_DM_ETH=y | 43 | CONFIG_DM_ETH=y |
44 | CONFIG_CMD_PMIC=y | 44 | CONFIG_CMD_PMIC=y |
45 | CONFIG_NXP_TMU=y | 45 | CONFIG_NXP_TMU=y |
46 | CONFIG_DM_THERMAL=y | 46 | CONFIG_DM_THERMAL=y |
47 | CONFIG_FIT=y | 47 | CONFIG_FIT=y |
48 | CONFIG_SPL_FIT=y | 48 | CONFIG_SPL_FIT=y |
49 | CONFIG_SPL_LOAD_FIT=y | 49 | CONFIG_SPL_LOAD_FIT=y |
50 | CONFIG_USB=y | 50 | CONFIG_USB=y |
51 | CONFIG_DM_USB=y | 51 | CONFIG_DM_USB=y |
52 | CONFIG_VIDEO=y | 52 | CONFIG_VIDEO=y |
53 | CONFIG_VIDEO_IMX8_HDMI=y | 53 | CONFIG_VIDEO_IMX8_HDMI=y |
54 | CONFIG_USB_GADGET=y | 54 | CONFIG_USB_GADGET=y |
55 | CONFIG_FASTBOOT=y | 55 | CONFIG_FASTBOOT=y |
56 | CONFIG_USB_FUNCTION_FASTBOOT=y | 56 | CONFIG_USB_FUNCTION_FASTBOOT=y |
57 | CONFIG_CMD_FASTBOOT=y | 57 | CONFIG_CMD_FASTBOOT=y |
58 | CONFIG_ANDROID_BOOT_IMAGE=y | 58 | CONFIG_ANDROID_BOOT_IMAGE=y |
59 | CONFIG_FSL_FASTBOOT=y | 59 | CONFIG_FSL_FASTBOOT=y |
60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 60 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 61 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
62 | CONFIG_FASTBOOT_FLASH=y | 62 | CONFIG_FASTBOOT_FLASH=y |
63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | 63 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
64 | CONFIG_EFI_PARTITION=y | 64 | CONFIG_EFI_PARTITION=y |
65 | CONFIG_SDP_LOADADDR=0x40400000 | 65 | CONFIG_SDP_LOADADDR=0x40400000 |
66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 66 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 67 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 68 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
69 | CONFIG_USB_GADGET_DOWNLOAD=y | 69 | CONFIG_USB_GADGET_DOWNLOAD=y |
70 | CONFIG_SPL_USB_HOST_SUPPORT=y | 70 | CONFIG_SPL_USB_HOST_SUPPORT=y |
71 | CONFIG_SPL_USB_GADGET_SUPPORT=y | 71 | CONFIG_SPL_USB_GADGET_SUPPORT=y |
72 | CONFIG_SPL_USB_SDP_SUPPORT=y | 72 | CONFIG_SPL_USB_SDP_SUPPORT=y |
73 | CONFIG_USB_XHCI_HCD=y | 73 | CONFIG_USB_XHCI_HCD=y |
74 | CONFIG_USB_XHCI_IMX8M=y | 74 | CONFIG_USB_XHCI_IMX8M=y |
75 | CONFIG_USB_XHCI_DWC3=y | 75 | CONFIG_USB_XHCI_DWC3=y |
76 | CONFIG_USB_DWC3=y | 76 | CONFIG_USB_DWC3=y |
77 | CONFIG_USB_DWC3_GADGET=y | 77 | CONFIG_USB_DWC3_GADGET=y |
78 | 78 |
drivers/ram/Kconfig
1 | config RAM | 1 | config RAM |
2 | bool "Enable RAM drivers using Driver Model" | 2 | bool "Enable RAM drivers using Driver Model" |
3 | depends on DM | 3 | depends on DM |
4 | help | 4 | help |
5 | This allows drivers to be provided for SDRAM and other RAM | 5 | This allows drivers to be provided for SDRAM and other RAM |
6 | controllers and their type to be specified in the board's device | 6 | controllers and their type to be specified in the board's device |
7 | tree. Generally some parameters are required to set up the RAM and | 7 | tree. Generally some parameters are required to set up the RAM and |
8 | the RAM size can either be statically defined or dynamically | 8 | the RAM size can either be statically defined or dynamically |
9 | detected. | 9 | detected. |
10 | 10 | ||
11 | config SPL_RAM | 11 | config SPL_RAM |
12 | bool "Enable RAM support in SPL" | 12 | bool "Enable RAM support in SPL" |
13 | depends on RAM && SPL_DM | 13 | depends on RAM && SPL_DM |
14 | help | 14 | help |
15 | The RAM subsystem adds a small amount of overhead to the image. | 15 | The RAM subsystem adds a small amount of overhead to the image. |
16 | If this is acceptable and you have a need to use RAM drivers in | 16 | If this is acceptable and you have a need to use RAM drivers in |
17 | SPL, enable this option. It might provide a cleaner interface to | 17 | SPL, enable this option. It might provide a cleaner interface to |
18 | setting up RAM (e.g. SDRAM / DDR) within SPL. | 18 | setting up RAM (e.g. SDRAM / DDR) within SPL. |
19 | 19 | ||
20 | config 2GB_LPDDR4 | 20 | config 2GB_LPDDR4 |
21 | bool "SMARC-iMX8M with 16Gb LPDDR4 Memory" | 21 | bool "SMARC-iMX8M with 16Gb LPDDR4 Memory" |
22 | help | 22 | help |
23 | Select this if the board is SMARC-iMX8M-D/L/Q-2G | 23 | Select this if the board is SMARC-iMX8M-D/L/Q-2G |
24 | 24 | ||
25 | config 4GB_LPDDR4 | 25 | config 4GB_LPDDR4 |
26 | bool "SMARC-iMX8M with 32Gb LPDDR4 Memory" | 26 | bool "SMARC-iMX8M with 32Gb LPDDR4 Memory" |
27 | help | 27 | help |
28 | Select this if the board is SMARC-iMX8M-D/L/Q-4G | 28 | Select this if the board is SMARC-iMX8M-D/L/Q-4G |
29 | 29 | ||
30 | config IND | 30 | config 2GB_LPDDR4_IND |
31 | bool "SMARC-iMX8M with 16Gb LPDDR4 Memory in industrial temperature range" | 31 | bool "SMARC-iMX8M with 16Gb LPDDR4 Memory in industrial temperature range" |
32 | help | 32 | help |
33 | Select this if the board is SMARC-iMX8M-D/L/Q-2G-I | 33 | Select this if the board is SMARC-iMX8M-D/L/Q-2G-I |
34 | 34 | ||
35 | config TPL_RAM | 35 | config TPL_RAM |
36 | bool "Enable RAM support in TPL" | 36 | bool "Enable RAM support in TPL" |
37 | depends on RAM && TPL_DM | 37 | depends on RAM && TPL_DM |
38 | help | 38 | help |
39 | The RAM subsystem adds a small amount of overhead to the image. | 39 | The RAM subsystem adds a small amount of overhead to the image. |
40 | If this is acceptable and you have a need to use RAM drivers in | 40 | If this is acceptable and you have a need to use RAM drivers in |
41 | TPL, enable this option. It might provide a cleaner interface to | 41 | TPL, enable this option. It might provide a cleaner interface to |
42 | setting up RAM (e.g. SDRAM / DDR) within TPL. | 42 | setting up RAM (e.g. SDRAM / DDR) within TPL. |
43 | 43 | ||
44 | config STM32_SDRAM | 44 | config STM32_SDRAM |
45 | bool "Enable STM32 SDRAM support" | 45 | bool "Enable STM32 SDRAM support" |
46 | depends on RAM | 46 | depends on RAM |
47 | help | 47 | help |
48 | STM32F7 family devices support flexible memory controller(FMC) to | 48 | STM32F7 family devices support flexible memory controller(FMC) to |
49 | support external memories like sdram, psram & nand. | 49 | support external memories like sdram, psram & nand. |
50 | This driver is for the sdram memory interface with the FMC. | 50 | This driver is for the sdram memory interface with the FMC. |
51 | 51 |
include/configs/smarcimx8mq.h
1 | /* | 1 | /* |
2 | * Copyright 2017-2018 NXP | 2 | * Copyright 2017-2018 NXP |
3 | * | 3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #ifndef __SMARCIMX8MQ_H | 7 | #ifndef __SMARCIMX8MQ_H |
8 | #define __SMARCIMX8MQ_H | 8 | #define __SMARCIMX8MQ_H |
9 | 9 | ||
10 | #include <linux/sizes.h> | 10 | #include <linux/sizes.h> |
11 | #include <asm/arch/imx-regs.h> | 11 | #include <asm/arch/imx-regs.h> |
12 | #include "imx_env.h" | 12 | #include "imx_env.h" |
13 | 13 | ||
14 | #ifdef CONFIG_SECURE_BOOT | 14 | #ifdef CONFIG_SECURE_BOOT |
15 | #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ | 15 | #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ |
16 | #endif | 16 | #endif |
17 | 17 | ||
18 | #define CONFIG_SPL_TEXT_BASE 0x7E1000 | 18 | #define CONFIG_SPL_TEXT_BASE 0x7E1000 |
19 | #define CONFIG_SPL_MAX_SIZE (148 * 1024) | 19 | #define CONFIG_SPL_MAX_SIZE (148 * 1024) |
20 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | 20 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
21 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR | 21 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR |
22 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 | 22 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 |
23 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | 23 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
24 | 24 | ||
25 | #ifdef CONFIG_SPL_BUILD | 25 | #ifdef CONFIG_SPL_BUILD |
26 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ | 26 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ |
27 | #define CONFIG_SPL_WATCHDOG_SUPPORT | 27 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
28 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | 28 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT |
29 | #define CONFIG_SPL_POWER_SUPPORT | 29 | #define CONFIG_SPL_POWER_SUPPORT |
30 | #define CONFIG_SPL_I2C_SUPPORT | 30 | #define CONFIG_SPL_I2C_SUPPORT |
31 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | 31 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
32 | #define CONFIG_SPL_STACK 0x187FF0 | 32 | #define CONFIG_SPL_STACK 0x187FF0 |
33 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | 33 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
34 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | 34 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
35 | #define CONFIG_SPL_SERIAL_SUPPORT | 35 | #define CONFIG_SPL_SERIAL_SUPPORT |
36 | #define CONFIG_SPL_GPIO_SUPPORT | 36 | #define CONFIG_SPL_GPIO_SUPPORT |
37 | #define CONFIG_SPL_MMC_SUPPORT | 37 | #define CONFIG_SPL_MMC_SUPPORT |
38 | #define CONFIG_SPL_BSS_START_ADDR 0x00180000 | 38 | #define CONFIG_SPL_BSS_START_ADDR 0x00180000 |
39 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ | 39 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ |
40 | #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 | 40 | #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 |
41 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ | 41 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ |
42 | #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 | 42 | #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 |
43 | #define CONFIG_SYS_ICACHE_OFF | 43 | #define CONFIG_SYS_ICACHE_OFF |
44 | #define CONFIG_SYS_DCACHE_OFF | 44 | #define CONFIG_SYS_DCACHE_OFF |
45 | 45 | ||
46 | #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ | 46 | #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
47 | 47 | ||
48 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ | 48 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ |
49 | 49 | ||
50 | #undef CONFIG_DM_MMC | 50 | #undef CONFIG_DM_MMC |
51 | #undef CONFIG_DM_PMIC | 51 | #undef CONFIG_DM_PMIC |
52 | #undef CONFIG_DM_PMIC_PFUZE100 | 52 | #undef CONFIG_DM_PMIC_PFUZE100 |
53 | 53 | ||
54 | #define CONFIG_SYS_I2C | 54 | #define CONFIG_SYS_I2C |
55 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | 55 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
56 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | 56 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
57 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | 57 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
58 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ | 58 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ |
59 | 59 | ||
60 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | 60 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
61 | 61 | ||
62 | #define CONFIG_POWER | 62 | #define CONFIG_POWER |
63 | #define CONFIG_POWER_I2C | 63 | #define CONFIG_POWER_I2C |
64 | #define CONFIG_POWER_PFUZE100 | 64 | #define CONFIG_POWER_PFUZE100 |
65 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | 65 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 |
66 | #endif | 66 | #endif |
67 | 67 | ||
68 | #define CONFIG_REMAKE_ELF | 68 | #define CONFIG_REMAKE_ELF |
69 | 69 | ||
70 | #define CONFIG_BOARD_EARLY_INIT_F | 70 | #define CONFIG_BOARD_EARLY_INIT_F |
71 | #define CONFIG_BOARD_POSTCLK_INIT | 71 | #define CONFIG_BOARD_POSTCLK_INIT |
72 | #define CONFIG_BOARD_LATE_INIT | 72 | #define CONFIG_BOARD_LATE_INIT |
73 | 73 | ||
74 | /* Flat Device Tree Definitions */ | 74 | /* Flat Device Tree Definitions */ |
75 | #define CONFIG_OF_BOARD_SETUP | 75 | #define CONFIG_OF_BOARD_SETUP |
76 | 76 | ||
77 | #undef CONFIG_CMD_EXPORTENV | 77 | #undef CONFIG_CMD_EXPORTENV |
78 | #undef CONFIG_CMD_IMLS | 78 | #undef CONFIG_CMD_IMLS |
79 | 79 | ||
80 | #undef CONFIG_CMD_CRC32 | 80 | #undef CONFIG_CMD_CRC32 |
81 | #undef CONFIG_BOOTM_NETBSD | 81 | #undef CONFIG_BOOTM_NETBSD |
82 | 82 | ||
83 | /* ENET Config */ | 83 | /* ENET Config */ |
84 | /* ENET1 */ | 84 | /* ENET1 */ |
85 | #if defined(CONFIG_CMD_NET) | 85 | #if defined(CONFIG_CMD_NET) |
86 | #define CONFIG_CMD_PING | 86 | #define CONFIG_CMD_PING |
87 | #define CONFIG_CMD_DHCP | 87 | #define CONFIG_CMD_DHCP |
88 | #define CONFIG_CMD_MII | 88 | #define CONFIG_CMD_MII |
89 | #define CONFIG_MII | 89 | #define CONFIG_MII |
90 | #define CONFIG_ETHPRIME "FEC" | 90 | #define CONFIG_ETHPRIME "FEC" |
91 | 91 | ||
92 | #define CONFIG_FEC_MXC | 92 | #define CONFIG_FEC_MXC |
93 | #define CONFIG_FEC_XCV_TYPE RGMII | 93 | #define CONFIG_FEC_XCV_TYPE RGMII |
94 | #define CONFIG_FEC_MXC_PHYADDR 6 | 94 | #define CONFIG_FEC_MXC_PHYADDR 6 |
95 | #define FEC_QUIRK_ENET_MAC | 95 | #define FEC_QUIRK_ENET_MAC |
96 | 96 | ||
97 | #define CONFIG_PHY_GIGE | 97 | #define CONFIG_PHY_GIGE |
98 | #define IMX_FEC_BASE 0x30BE0000 | 98 | #define IMX_FEC_BASE 0x30BE0000 |
99 | 99 | ||
100 | #define CONFIG_PHYLIB | 100 | #define CONFIG_PHYLIB |
101 | #define CONFIG_PHY_ATHEROS | 101 | #define CONFIG_PHY_ATHEROS |
102 | #endif | 102 | #endif |
103 | 103 | ||
104 | /* | 104 | /* |
105 | * Another approach is add the clocks for inmates into clks_init_on | 105 | * Another approach is add the clocks for inmates into clks_init_on |
106 | * in clk-imx8mq.c, then clk_ingore_unused could be removed. | 106 | * in clk-imx8mq.c, then clk_ingore_unused could be removed. |
107 | */ | 107 | */ |
108 | #define JAILHOUSE_ENV \ | 108 | #define JAILHOUSE_ENV \ |
109 | "jh_clk= \0 " \ | 109 | "jh_clk= \0 " \ |
110 | "jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \ | 110 | "jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \ |
111 | "setenv jh_clk clk_ignore_unused; " \ | 111 | "setenv jh_clk clk_ignore_unused; " \ |
112 | "if run loadimage; then " \ | 112 | "if run loadimage; then " \ |
113 | "run mmcboot; " \ | 113 | "run mmcboot; " \ |
114 | "else run jh_netboot; fi; \0" \ | 114 | "else run jh_netboot; fi; \0" \ |
115 | "jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " | 115 | "jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " |
116 | 116 | ||
117 | #define CONFIG_MFG_ENV_SETTINGS \ | 117 | #define CONFIG_MFG_ENV_SETTINGS \ |
118 | CONFIG_MFG_ENV_SETTINGS_DEFAULT \ | 118 | CONFIG_MFG_ENV_SETTINGS_DEFAULT \ |
119 | "initrd_addr=0x43800000\0" \ | 119 | "initrd_addr=0x43800000\0" \ |
120 | "initrd_high=0xffffffffffffffff\0" \ | 120 | "initrd_high=0xffffffffffffffff\0" \ |
121 | "emmc_dev=0\0"\ | 121 | "emmc_dev=0\0"\ |
122 | "sd_dev=1\0" \ | 122 | "sd_dev=1\0" \ |
123 | 123 | ||
124 | /* Initial environment variables */ | 124 | /* Initial environment variables */ |
125 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 125 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
126 | CONFIG_MFG_ENV_SETTINGS \ | 126 | CONFIG_MFG_ENV_SETTINGS \ |
127 | JAILHOUSE_ENV \ | 127 | JAILHOUSE_ENV \ |
128 | "script=boot.scr\0" \ | 128 | "script=boot.scr\0" \ |
129 | "image=Image\0" \ | 129 | "image=Image\0" \ |
130 | "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ | 130 | "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ |
131 | "fdt_addr=0x43000000\0" \ | 131 | "fdt_addr=0x43000000\0" \ |
132 | "fdt_high=0xffffffffffffffff\0" \ | 132 | "fdt_high=0xffffffffffffffff\0" \ |
133 | "boot_fdt=try\0" \ | 133 | "boot_fdt=try\0" \ |
134 | "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ | 134 | "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
135 | "initrd_addr=0x43800000\0" \ | 135 | "initrd_addr=0x43800000\0" \ |
136 | "initrd_high=0xffffffffffffffff\0" \ | 136 | "initrd_high=0xffffffffffffffff\0" \ |
137 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | 137 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ |
138 | "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ | 138 | "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ |
139 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | 139 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
140 | "usbroot=/dev/sda2 rootwait ro\0" \ | 140 | "usbroot=/dev/sda2 rootwait ro\0" \ |
141 | "mmcrootfstype=ext4 rootwait\0" \ | 141 | "mmcrootfstype=ext4 rootwait\0" \ |
142 | "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ | 142 | "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ |
143 | "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \ | 143 | "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \ |
144 | "mmcautodetect=yes\0" \ | 144 | "mmcautodetect=yes\0" \ |
145 | "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ | 145 | "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ |
146 | "env import -t $loadaddr $filesize\0" \ | 146 | "env import -t $loadaddr $filesize\0" \ |
147 | "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \ | 147 | "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \ |
148 | "env import -t $loadaddr $filesize\0" \ | 148 | "env import -t $loadaddr $filesize\0" \ |
149 | "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ | 149 | "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ |
150 | "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \ | 150 | "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \ |
151 | "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ | 151 | "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ |
152 | "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \ | 152 | "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \ |
153 | "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | 153 | "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
154 | "bootscript=echo Running bootscript from mmc ...; " \ | 154 | "bootscript=echo Running bootscript from mmc ...; " \ |
155 | "source\0" \ | 155 | "source\0" \ |
156 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | 156 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
157 | "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \ | 157 | "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \ |
158 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ | 158 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ |
159 | "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \ | 159 | "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \ |
160 | "mmcboot=echo Booting from mmc ...; " \ | 160 | "mmcboot=echo Booting from mmc ...; " \ |
161 | "run mmcargs; " \ | 161 | "run mmcargs; " \ |
162 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | 162 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
163 | "if run loadfdt; then " \ | 163 | "if run loadfdt; then " \ |
164 | "booti ${loadaddr} - ${fdt_addr}; " \ | 164 | "booti ${loadaddr} - ${fdt_addr}; " \ |
165 | "else " \ | 165 | "else " \ |
166 | "echo WARN: Cannot load the DT; " \ | 166 | "echo WARN: Cannot load the DT; " \ |
167 | "fi; " \ | 167 | "fi; " \ |
168 | "else " \ | 168 | "else " \ |
169 | "echo wait for boot; " \ | 169 | "echo wait for boot; " \ |
170 | "fi;\0" \ | 170 | "fi;\0" \ |
171 | "usbboot=echo Booting from USB ...; " \ | 171 | "usbboot=echo Booting from USB ...; " \ |
172 | "run usbargs; " \ | 172 | "run usbargs; " \ |
173 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | 173 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
174 | "if run loadusbfdt; then " \ | 174 | "if run loadusbfdt; then " \ |
175 | "booti ${loadaddr} - ${fdt_addr}; " \ | 175 | "booti ${loadaddr} - ${fdt_addr}; " \ |
176 | "else " \ | 176 | "else " \ |
177 | "echo WARN: Cannot load the DT; " \ | 177 | "echo WARN: Cannot load the DT; " \ |
178 | "fi; " \ | 178 | "fi; " \ |
179 | "else " \ | 179 | "else " \ |
180 | "echo wait for boot; " \ | 180 | "echo wait for boot; " \ |
181 | "fi;\0" \ | 181 | "fi;\0" \ |
182 | "netargs=setenv bootargs ${jh_clk} console=${console} " \ | 182 | "netargs=setenv bootargs ${jh_clk} console=${console} " \ |
183 | "root=/dev/nfs " \ | 183 | "root=/dev/nfs " \ |
184 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | 184 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ |
185 | "netboot=echo Booting from net ...; " \ | 185 | "netboot=echo Booting from net ...; " \ |
186 | "run netargs; " \ | 186 | "run netargs; " \ |
187 | "if test ${ip_dyn} = yes; then " \ | 187 | "if test ${ip_dyn} = yes; then " \ |
188 | "setenv get_cmd dhcp; " \ | 188 | "setenv get_cmd dhcp; " \ |
189 | "else " \ | 189 | "else " \ |
190 | "setenv get_cmd tftp; " \ | 190 | "setenv get_cmd tftp; " \ |
191 | "fi; " \ | 191 | "fi; " \ |
192 | "${get_cmd} ${loadaddr} ${image}; " \ | 192 | "${get_cmd} ${loadaddr} ${image}; " \ |
193 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | 193 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
194 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | 194 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ |
195 | "booti ${loadaddr} - ${fdt_addr}; " \ | 195 | "booti ${loadaddr} - ${fdt_addr}; " \ |
196 | "else " \ | 196 | "else " \ |
197 | "echo WARN: Cannot load the DT; " \ | 197 | "echo WARN: Cannot load the DT; " \ |
198 | "fi; " \ | 198 | "fi; " \ |
199 | "else " \ | 199 | "else " \ |
200 | "booti; " \ | 200 | "booti; " \ |
201 | "fi;\0" | 201 | "fi;\0" |
202 | 202 | ||
203 | #define CONFIG_BOOTCOMMAND \ | 203 | #define CONFIG_BOOTCOMMAND \ |
204 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | 204 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
205 | "echo Checking for: uEnv.txt ...; " \ | 205 | "echo Checking for: uEnv.txt ...; " \ |
206 | "if test -e mmc ${bootpart} /uEnv.txt; then " \ | 206 | "if test -e mmc ${bootpart} /uEnv.txt; then " \ |
207 | "if run loadbootenv; then " \ | 207 | "if run loadbootenv; then " \ |
208 | "echo Loaded environment from uEnv.txt;" \ | 208 | "echo Loaded environment from uEnv.txt;" \ |
209 | "run importbootenv;" \ | 209 | "run importbootenv;" \ |
210 | "fi;" \ | 210 | "fi;" \ |
211 | "echo Checking if uenvcmd is set ...;" \ | 211 | "echo Checking if uenvcmd is set ...;" \ |
212 | "if test -n ${uenvcmd}; then " \ | 212 | "if test -n ${uenvcmd}; then " \ |
213 | "echo Running uenvcmd ...;" \ | 213 | "echo Running uenvcmd ...;" \ |
214 | "run uenvcmd;" \ | 214 | "run uenvcmd;" \ |
215 | "fi;" \ | 215 | "fi;" \ |
216 | "fi; " \ | 216 | "fi; " \ |
217 | "if run loadimage; then " \ | 217 | "if run loadimage; then " \ |
218 | "run mmcboot; " \ | 218 | "run mmcboot; " \ |
219 | "else run netboot; " \ | 219 | "else run netboot; " \ |
220 | "fi; " \ | 220 | "fi; " \ |
221 | "booti ${loadaddr} - ${fdt_addr}; fi;" | 221 | "booti ${loadaddr} - ${fdt_addr}; fi;" |
222 | 222 | ||
223 | /* Link Definitions */ | 223 | /* Link Definitions */ |
224 | #define CONFIG_LOADADDR 0x40480000 | 224 | #define CONFIG_LOADADDR 0x40480000 |
225 | 225 | ||
226 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | 226 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
227 | 227 | ||
228 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | 228 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
229 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | 229 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 |
230 | #define CONFIG_SYS_INIT_SP_OFFSET \ | 230 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
231 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | 231 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
232 | #define CONFIG_SYS_INIT_SP_ADDR \ | 232 | #define CONFIG_SYS_INIT_SP_ADDR \ |
233 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | 233 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
234 | 234 | ||
235 | #define CONFIG_ENV_OVERWRITE | 235 | #define CONFIG_ENV_OVERWRITE |
236 | #define CONFIG_ENV_OFFSET (64 * SZ_64K) | 236 | #define CONFIG_ENV_OFFSET (64 * SZ_64K) |
237 | #define CONFIG_ENV_SIZE 0x1000 | 237 | #define CONFIG_ENV_SIZE 0x1000 |
238 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ | 238 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ |
239 | #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ | 239 | #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ |
240 | 240 | ||
241 | /* Size of malloc() pool */ | 241 | /* Size of malloc() pool */ |
242 | #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) | 242 | #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) |
243 | 243 | ||
244 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | 244 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
245 | #define PHYS_SDRAM 0x40000000 | 245 | #define PHYS_SDRAM 0x40000000 |
246 | #ifdef CONFIG_2GB_LPDDR4 | 246 | #ifdef CONFIG_2GB_LPDDR4 |
247 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ | 247 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ |
248 | #elif CONFIG_2GB_LPDDR4_IND | ||
249 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ | ||
248 | #else | 250 | #else |
249 | #define PHYS_SDRAM_SIZE 0xc0000000 /* 4GB DDR, temporary workaround */ | 251 | #define PHYS_SDRAM_SIZE 0xc0000000 /* 4GB DDR, temporary workaround */ |
250 | #endif | 252 | #endif |
251 | #define CONFIG_NR_DRAM_BANKS 1 | 253 | #define CONFIG_NR_DRAM_BANKS 1 |
252 | 254 | ||
253 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | 255 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
254 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) | 256 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) |
255 | 257 | ||
256 | #define CONFIG_BAUDRATE 115200 | 258 | #define CONFIG_BAUDRATE 115200 |
257 | 259 | ||
258 | #define CONFIG_MXC_UART | 260 | #define CONFIG_MXC_UART |
259 | 261 | ||
260 | #ifdef CONFIG_CONSOLE_SER0 | 262 | #ifdef CONFIG_CONSOLE_SER0 |
261 | #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR | 263 | #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR |
262 | #define CONSOLE_DEV "ttymxc3" | 264 | #define CONSOLE_DEV "ttymxc3" |
263 | #endif | 265 | #endif |
264 | 266 | ||
265 | #ifdef CONFIG_CONSOLE_SER1 | 267 | #ifdef CONFIG_CONSOLE_SER1 |
266 | #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR | 268 | #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR |
267 | #define CONSOLE_DEV "ttymxc2" | 269 | #define CONSOLE_DEV "ttymxc2" |
268 | #endif | 270 | #endif |
269 | 271 | ||
270 | #ifdef CONFIG_CONSOLE_SER2 | 272 | #ifdef CONFIG_CONSOLE_SER2 |
271 | #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR | 273 | #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR |
272 | #define CONSOLE_DEV "ttymxc1" | 274 | #define CONSOLE_DEV "ttymxc1" |
273 | #endif | 275 | #endif |
274 | 276 | ||
275 | #ifdef CONFIG_CONSOLE_SER3 | 277 | #ifdef CONFIG_CONSOLE_SER3 |
276 | #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR | 278 | #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR |
277 | #define CONSOLE_DEV "ttymxc0" | 279 | #define CONSOLE_DEV "ttymxc0" |
278 | #endif | 280 | #endif |
279 | 281 | ||
280 | /* Monitor Command Prompt */ | 282 | /* Monitor Command Prompt */ |
281 | #undef CONFIG_SYS_PROMPT | 283 | #undef CONFIG_SYS_PROMPT |
282 | #define CONFIG_SYS_PROMPT "u-boot$ " | 284 | #define CONFIG_SYS_PROMPT "u-boot$ " |
283 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | 285 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
284 | #define CONFIG_SYS_CBSIZE 2048 | 286 | #define CONFIG_SYS_CBSIZE 2048 |
285 | #define CONFIG_SYS_MAXARGS 64 | 287 | #define CONFIG_SYS_MAXARGS 64 |
286 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | 288 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
287 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | 289 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
288 | sizeof(CONFIG_SYS_PROMPT) + 16) | 290 | sizeof(CONFIG_SYS_PROMPT) + 16) |
289 | 291 | ||
290 | #define CONFIG_IMX_BOOTAUX | 292 | #define CONFIG_IMX_BOOTAUX |
291 | 293 | ||
292 | #define CONFIG_CMD_MMC | 294 | #define CONFIG_CMD_MMC |
293 | #define CONFIG_FSL_ESDHC | 295 | #define CONFIG_FSL_ESDHC |
294 | #define CONFIG_FSL_USDHC | 296 | #define CONFIG_FSL_USDHC |
295 | 297 | ||
296 | #define CONFIG_SYS_FSL_USDHC_NUM 2 | 298 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
297 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | 299 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
298 | 300 | ||
299 | #define CONFIG_CMD_PART | 301 | #define CONFIG_CMD_PART |
300 | #define CONFIG_CMD_FS_GENERIC | 302 | #define CONFIG_CMD_FS_GENERIC |
301 | 303 | ||
302 | #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ | 304 | #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ |
303 | #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 | 305 | #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
304 | 306 | ||
305 | #define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ | 307 | #define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ |
306 | #ifdef CONFIG_FSL_QSPI | 308 | #ifdef CONFIG_FSL_QSPI |
307 | #define CONFIG_CMD_SF | 309 | #define CONFIG_CMD_SF |
308 | #define CONFIG_SPI_FLASH | 310 | #define CONFIG_SPI_FLASH |
309 | #define CONFIG_SPI_FLASH_STMICRO | 311 | #define CONFIG_SPI_FLASH_STMICRO |
310 | #define CONFIG_SPI_FLASH_BAR | 312 | #define CONFIG_SPI_FLASH_BAR |
311 | #define CONFIG_SF_DEFAULT_BUS 0 | 313 | #define CONFIG_SF_DEFAULT_BUS 0 |
312 | #define CONFIG_SF_DEFAULT_CS 0 | 314 | #define CONFIG_SF_DEFAULT_CS 0 |
313 | #define CONFIG_SF_DEFAULT_SPEED 40000000 | 315 | #define CONFIG_SF_DEFAULT_SPEED 40000000 |
314 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | 316 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
315 | 317 | ||
316 | #define FSL_QSPI_FLASH_SIZE (SZ_32M) | 318 | #define FSL_QSPI_FLASH_SIZE (SZ_32M) |
317 | #define FSL_QSPI_FLASH_NUM 1 | 319 | #define FSL_QSPI_FLASH_NUM 1 |
318 | #endif | 320 | #endif |
319 | 321 | ||
320 | #define CONFIG_MXC_GPIO | 322 | #define CONFIG_MXC_GPIO |
321 | 323 | ||
322 | #define CONFIG_MXC_OCOTP | 324 | #define CONFIG_MXC_OCOTP |
323 | #define CONFIG_CMD_FUSE | 325 | #define CONFIG_CMD_FUSE |
324 | 326 | ||
325 | /* I2C Configs */ | 327 | /* I2C Configs */ |
326 | #define CONFIG_SYS_I2C_SPEED 100000 | 328 | #define CONFIG_SYS_I2C_SPEED 100000 |
327 | 329 | ||
328 | /* USB configs */ | 330 | /* USB configs */ |
329 | #ifndef CONFIG_SPL_BUILD | 331 | #ifndef CONFIG_SPL_BUILD |
330 | #define CONFIG_HAS_FSL_XHCI_USB | 332 | #define CONFIG_HAS_FSL_XHCI_USB |
331 | 333 | ||
332 | #ifdef CONFIG_HAS_FSL_XHCI_USB | 334 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
333 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | 335 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
334 | #endif | 336 | #endif |
335 | 337 | ||
336 | #define CONFIG_CMD_USB | 338 | #define CONFIG_CMD_USB |
337 | #define CONFIG_USB_STORAGE | 339 | #define CONFIG_USB_STORAGE |
338 | 340 | ||
339 | #define CONFIG_USBD_HS | 341 | #define CONFIG_USBD_HS |
340 | 342 | ||
341 | #define CONFIG_CMD_USB_MASS_STORAGE | 343 | #define CONFIG_CMD_USB_MASS_STORAGE |
342 | #define CONFIG_USB_GADGET_MASS_STORAGE | 344 | #define CONFIG_USB_GADGET_MASS_STORAGE |
343 | #define CONFIG_USB_FUNCTION_MASS_STORAGE | 345 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
344 | 346 | ||
345 | #define CONFIG_CMD_READ | 347 | #define CONFIG_CMD_READ |
346 | #endif | 348 | #endif |
347 | 349 | ||
348 | #define CONFIG_SERIAL_TAG | 350 | #define CONFIG_SERIAL_TAG |
349 | #define CONFIG_FASTBOOT_USB_DEV 0 | 351 | #define CONFIG_FASTBOOT_USB_DEV 0 |
350 | 352 | ||
351 | 353 | ||
352 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | 354 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
353 | 355 | ||
354 | #define CONFIG_USBD_HS | 356 | #define CONFIG_USBD_HS |
355 | #define CONFIG_USB_GADGET_VBUS_DRAW 2 | 357 | #define CONFIG_USB_GADGET_VBUS_DRAW 2 |
356 | 358 | ||
357 | #define CONFIG_OF_SYSTEM_SETUP | 359 | #define CONFIG_OF_SYSTEM_SETUP |
358 | 360 | ||
359 | /* Framebuffer */ | 361 | /* Framebuffer */ |
360 | #ifdef CONFIG_VIDEO | 362 | #ifdef CONFIG_VIDEO |
361 | #define CONFIG_VIDEO_IMXDCSS | 363 | #define CONFIG_VIDEO_IMXDCSS |
362 | #define CONFIG_VIDEO_BMP_RLE8 | 364 | #define CONFIG_VIDEO_BMP_RLE8 |
363 | #define CONFIG_SPLASH_SCREEN | 365 | #define CONFIG_SPLASH_SCREEN |
364 | #define CONFIG_SPLASH_SCREEN_ALIGN | 366 | #define CONFIG_SPLASH_SCREEN_ALIGN |
365 | #define CONFIG_BMP_16BPP | 367 | #define CONFIG_BMP_16BPP |
366 | #define CONFIG_VIDEO_LOGO | 368 | #define CONFIG_VIDEO_LOGO |
367 | #define CONFIG_VIDEO_BMP_LOGO | 369 | #define CONFIG_VIDEO_BMP_LOGO |
368 | #define CONFIG_IMX_VIDEO_SKIP | 370 | #define CONFIG_IMX_VIDEO_SKIP |
369 | #endif | 371 | #endif |
370 | 372 | ||
371 | #if defined(CONFIG_ANDROID_SUPPORT) | 373 | #if defined(CONFIG_ANDROID_SUPPORT) |
372 | #include "smarcimx8mq_android.h" | 374 | #include "smarcimx8mq_android.h" |
373 | #elif defined (CONFIG_ANDROID_THINGS_SUPPORT) | 375 | #elif defined (CONFIG_ANDROID_THINGS_SUPPORT) |
374 | #include "smarcimx8mq_androidthings.h" | 376 | #include "smarcimx8mq_androidthings.h" |
375 | #endif | 377 | #endif |
376 | #endif | 378 | #endif |
377 | 379 |