Commit f49638e9f9b8c3fe282c2305a8272944b5debe33
Committed by
Tom Rini
Tom Rini
1 parent
9a41746f84
Exists in
smarc_8mq_lf_v2020.04
and in
20 other branches
board: p212: use common ethernet init function
Switch P212 Ethernet init to the common Ethernet init function. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Showing 1 changed file with 2 additions and 12 deletions Inline Diff
board/amlogic/p212/p212.c
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2016 BayLibre, SAS | 2 | * Copyright (C) 2016 BayLibre, SAS |
| 3 | * Author: Neil Armstrong <narmstrong@baylibre.com> | 3 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 4 | * | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <common.h> | 8 | #include <common.h> |
| 9 | #include <dm.h> | 9 | #include <dm.h> |
| 10 | #include <asm/io.h> | 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/gxbb.h> | 11 | #include <asm/arch/gxbb.h> |
| 12 | #include <asm/arch/sm.h> | 12 | #include <asm/arch/sm.h> |
| 13 | #include <phy.h> | 13 | #include <asm/arch/eth.h> |
| 14 | 14 | ||
| 15 | #define EFUSE_SN_OFFSET 20 | 15 | #define EFUSE_SN_OFFSET 20 |
| 16 | #define EFUSE_SN_SIZE 16 | 16 | #define EFUSE_SN_SIZE 16 |
| 17 | #define EFUSE_MAC_OFFSET 52 | 17 | #define EFUSE_MAC_OFFSET 52 |
| 18 | #define EFUSE_MAC_SIZE 6 | 18 | #define EFUSE_MAC_SIZE 6 |
| 19 | 19 | ||
| 20 | int board_init(void) | 20 | int board_init(void) |
| 21 | { | 21 | { |
| 22 | return 0; | 22 | return 0; |
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | int misc_init_r(void) | 25 | int misc_init_r(void) |
| 26 | { | 26 | { |
| 27 | u8 mac_addr[EFUSE_MAC_SIZE]; | 27 | u8 mac_addr[EFUSE_MAC_SIZE]; |
| 28 | char serial[EFUSE_SN_SIZE]; | 28 | char serial[EFUSE_SN_SIZE]; |
| 29 | ssize_t len; | 29 | ssize_t len; |
| 30 | 30 | ||
| 31 | /* Set RMII mode */ | 31 | meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, 0); |
| 32 | out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | | ||
| 33 | GXBB_ETH_REG_0_CLK_EN); | ||
| 34 | |||
| 35 | /* Use Internal PHY */ | ||
| 36 | out_le32(GXBB_ETH_REG_2, 0x10110181); | ||
| 37 | out_le32(GXBB_ETH_REG_3, 0xe40908ff); | ||
| 38 | |||
| 39 | /* Enable power and clock gate */ | ||
| 40 | setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); | ||
| 41 | clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); | ||
| 42 | 32 | ||
| 43 | if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { | 33 | if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { |
| 44 | len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, | 34 | len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, |
| 45 | mac_addr, EFUSE_MAC_SIZE); | 35 | mac_addr, EFUSE_MAC_SIZE); |
| 46 | if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) | 36 | if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) |
| 47 | eth_env_set_enetaddr("ethaddr", mac_addr); | 37 | eth_env_set_enetaddr("ethaddr", mac_addr); |
| 48 | } | 38 | } |
| 49 | 39 | ||
| 50 | if (!env_get("serial#")) { | 40 | if (!env_get("serial#")) { |
| 51 | len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, | 41 | len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, |
| 52 | EFUSE_SN_SIZE); | 42 | EFUSE_SN_SIZE); |
| 53 | if (len == EFUSE_SN_SIZE) | 43 | if (len == EFUSE_SN_SIZE) |
| 54 | env_set("serial#", serial); | 44 | env_set("serial#", serial); |
| 55 | } | 45 | } |
| 56 | 46 | ||
| 57 | return 0; | 47 | return 0; |
| 58 | } | 48 | } |
| 59 | 49 |