Eric Lee / smarc-uboot | Embedian Git Server

Commit f54fe87acedbbad7d29ad18cab31d2b323717514

Authored by Kumar Gala 2010-04-20 23:21:25 +0800

Exists in master and in 54 other branches

85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled

On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.

Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 3 changed files with 26 additions and 13 deletions Inline Diff

arch/powerpc/cpu/mpc85xx/cpu_init.c
board/freescale/mpc8536ds/mpc8536ds.c
drivers/block/fsl_sata.c

arch/powerpc/cpu/mpc85xx/cpu_init.c

Diff comments View file @ f54fe87

 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao@motorola.com
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <ioports.h>
+#include <sata.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
 #include "mp.h"
 DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_MPC8536
 extern void fsl_serdes_init(void);
 #endif
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 				int open_drain, int assign);
 extern void qe_init(uint qe_base);
 extern void qe_reset(void);
 static void config_qe_ioports(void)
 {
 	u8      port, pin;
 	int     dir, open_drain, assign;
 	int     i;
 	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 		port		= qe_iop_conf_tab[i].port;
 		pin		= qe_iop_conf_tab[i].pin;
 		dir		= qe_iop_conf_tab[i].dir;
 		open_drain	= qe_iop_conf_tab[i].open_drain;
 		assign		= qe_iop_conf_tab[i].assign;
 		qe_config_iopin(port, pin, dir, open_drain, assign);
 	}
 }
 #endif
 #ifdef CONFIG_CPM2
 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 {
 	int portnum;
 	for (portnum = 0; portnum < 4; portnum++) {
 		uint pmsk = 0,
 		     ppar = 0,
 		     psor = 0,
 		     pdir = 0,
 		     podr = 0,
 		     pdat = 0;
 		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 		iop_conf_t *eiopc = iopc + 32;
 		uint msk = 1;
 		/*
 		 * NOTE:
 		 * index 0 refers to pin 31,
 		 * index 31 refers to pin 0
 		 */
 		while (iopc < eiopc) {
 			if (iopc->conf) {
 				pmsk |= msk;
 				if (iopc->ppar)
 					ppar |= msk;
 				if (iopc->psor)
 					psor |= msk;
 				if (iopc->pdir)
 					pdir |= msk;
 				if (iopc->podr)
 					podr |= msk;
 				if (iopc->pdat)
 					pdat |= msk;
 			}
 			msk <<= 1;
 			iopc++;
 		}
 		if (pmsk != 0) {
 			volatile ioport_t *iop = ioport_addr (cpm, portnum);
 			uint tpmsk = ~pmsk;
 			/*
 			 * the (somewhat confused) paragraph at the
 			 * bottom of page 35-5 warns that there might
 			 * be "unknown behaviour" when programming
 			 * PSORx and PDIRx, if PPARx = 1, so I
 			 * decided this meant I had to disable the
 			 * dedicated function first, and enable it
 			 * last.
 			 */
 			iop->ppar &= tpmsk;
 			iop->psor = (iop->psor & tpmsk) | psor;
 			iop->podr = (iop->podr & tpmsk) | podr;
 			iop->pdat = (iop->pdat & tpmsk) | pdat;
 			iop->pdir = (iop->pdir & tpmsk) | pdir;
 			iop->ppar |= ppar;
 		}
 	}
 }
 #endif
 /*
  * Breathe some life into the CPU...
  *
  * Set up the memory map
  * initialize a bunch of registers
  */
 #ifdef CONFIG_FSL_CORENET
 static void corenet_tb_init(void)
 {
 	volatile ccsr_rcpm_t *rcpm =
 		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	volatile ccsr_pic_t *pic =
 		(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
 	u32 whoami = in_be32(&pic->whoami);
 	/* Enable the timebase register for this core */
 	out_be32(&rcpm->ctbenrl, (1 << whoami));
 }
 #endif
 void cpu_init_f (void)
 {
 	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	extern void m8560_cpm_reset (void);
 #ifdef CONFIG_MPC8548
 	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	uint svr = get_svr();
 	/*
 	 * CPU2 errata workaround: A core hang possible while executing
 	 * a msync instruction and a snoopable transaction from an I/O
 	 * master tagged to make quick forward progress is present.
 	 * Fixed in silicon rev 2.1.
 	 */
 	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 #endif
 	disable_tlb(14);
 	disable_tlb(15);
 #ifdef CONFIG_CPM2
 	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 #endif
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined
 	 */
 #if defined(CONFIG_SYS_OR0_REMAP)
 	out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
 #endif
 #if defined(CONFIG_SYS_OR1_REMAP)
 	out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
 #endif
 	/* now restrict to preliminary range */
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (! memctl->br1 & 1) {
 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
 		out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
 		out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 		out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
 		out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
 #endif
 	}
 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 	out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
 	out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 	out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
 	out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 	out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
 	out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 	out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
 	out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 	out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
 	out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
 #endif
 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 	out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
 	out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
 #endif
 #if defined(CONFIG_CPM2)
 	m8560_cpm_reset();
 #endif
 #ifdef CONFIG_QE
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
 #if defined(CONFIG_MPC8536)
 	fsl_serdes_init();
 #endif
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif
 #ifdef CONFIG_FSL_CORENET
 	corenet_tb_init();
 #endif
 	init_used_tlb_cams();
 }
 /*
  * Initialize L2 as cache.
  *
  * The newer 8548, etc, parts have twice as much cache, but
  * use the same bit-encoding as the older 8555, etc, parts.
  *
  */
 int cpu_init_r(void)
 {
 #ifdef CONFIG_SYS_LBC_LCRR
 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 #endif
 	puts ("L2:    ");
 #if defined(CONFIG_L2_CACHE)
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint svr, ver;
 	uint l2srbar;
 	u32 l2siz_field;
 	svr = get_svr();
 	ver = SVR_SOC_VER(svr);
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	if (cache_ctl & MPC85xx_L2CTL_L2E) {
 		/* Clear L2 SRAM memory-mapped base address */
 		out_be32(&l2cache->l2srbar0, 0x0);
 		out_be32(&l2cache->l2srbar1, 0x0);
 		/* set MBECCDIS=0, SBECCDIS=0 */
 		clrbits_be32(&l2cache->l2errdis,
 				(MPC85xx_L2ERRDIS_MBECC |
 				 MPC85xx_L2ERRDIS_SBECC));
 		/* set L2E=0, L2SRAM=0 */
 		clrbits_be32(&l2cache->l2ctl,
 				(MPC85xx_L2CTL_L2E |
 				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
 	}
 #endif
 	l2siz_field = (cache_ctl >> 28) & 0x3;
 	switch (l2siz_field) {
 	case 0x0:
 		printf(" unknown size (0x%08x)\n", cache_ctl);
 		return -1;
 		break;
 	case 0x1:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8541_E ||
 		    ver == SVR_8555 || ver == SVR_8555_E) {
 			puts("128 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 			cache_ctl = 0xc4000000;
 		} else {
 			puts("256 KB ");
 			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 		}
 		break;
 	case 0x2:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8541_E ||
 		    ver == SVR_8555 || ver == SVR_8555_E) {
 			puts("256 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 			cache_ctl = 0xc8000000;
 		} else {
 			puts ("512 KB ");
 			/* set L2E=1, L2I=1, & L2SRAM=0 */
 			cache_ctl = 0xc0000000;
 		}
 		break;
 	case 0x3:
 		puts("1024 KB ");
 		/* set L2E=1, L2I=1, & L2SRAM=0 */
 		cache_ctl = 0xc0000000;
 		break;
 	}
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
 		l2srbar = l2cache->l2srbar0;
 #ifdef CONFIG_SYS_INIT_L2_ADDR
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
 			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
 			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 		}
 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 		puts("\n");
 	} else {
 		asm("msync;isync");
 		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 		asm("msync;isync");
 		puts("enabled\n");
 	}
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 	/* invalidate the L2 cache */
 	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 		;
 #ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
 	mtspr(SPRN_L2CSR1, (32 + 1));
 #endif
 	/* enable the cache */
 	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 			;
 		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 	}
 #else
 	puts("disabled\n");
 #endif
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 	qe_init(qe_base);
 	qe_reset();
 #endif
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing
 	 * speed for NOR flash.
 	 */
 	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
 #endif
 	return 0;
 }
 extern void setup_ivors(void);
 void arch_preboot_os(void)
 {
 	u32 msr;
 	/*
 	 * We are changing interrupt offsets and are about to boot the OS so
 	 * we need to make sure we disable all async interrupts. EE is already
 	 * disabled by the time we get called.
 	 */
 	msr = mfmsr();
 	msr &= ~(MSR_ME|MSR_CE|MSR_DE);
 	mtmsr(msr);
 	setup_ivors();
 }
+#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
+int sata_initialize(void)
+{
+	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
+		return __sata_initialize();
+	return 1;
+}
+#endif

board/freescale/mpc8536ds/mpc8536ds.c

Diff comments View file @ f54fe87

 /*
  * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <spd.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <spd_sdram.h>
 #include <fdt_support.h>
 #include <tsec.h>
 #include <netdev.h>
 #include <sata.h>
 #include "../common/sgmii_riser.h"
 phys_size_t fixed_sdram(void);
 int board_early_init_f (void)
 {
 #ifdef CONFIG_MMC
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	setbits_be32(&gur->pmuxcr,
 			(MPC85xx_PMUXCR_SD_DATA |
 			 MPC85xx_PMUXCR_SDHC_CD |
 			 MPC85xx_PMUXCR_SDHC_WP));
 #endif
 	return 0;
 }
 int checkboard (void)
 {
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	puts("Board: MPC8536DS ");
 #ifdef CONFIG_PHYS_64BIT
 	puts("(36-bit addrmap) ");
 #endif
 	printf ("Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
 	vboot = in_8(pixis_base + PIXIS_VBOOT);
 	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
 		case PIXIS_VBOOT_LBMAP_NOR0:
 			puts ("vBank: 0\n");
 			break;
 		case PIXIS_VBOOT_LBMAP_NOR1:
 			puts ("vBank: 1\n");
 			break;
 		case PIXIS_VBOOT_LBMAP_NOR2:
 			puts ("vBank: 2\n");
 			break;
 		case PIXIS_VBOOT_LBMAP_NOR3:
 			puts ("vBank: 3\n");
 			break;
 		case PIXIS_VBOOT_LBMAP_PJET:
 			puts ("Promjet\n");
 			break;
 		case PIXIS_VBOOT_LBMAP_NAND:
 			puts ("NAND\n");
 			break;
 	}
 	return 0;
 }
 phys_size_t
 initdram(int board_type)
 {
 	phys_size_t dram_size = 0;
 	puts("Initializing....");
 #ifdef CONFIG_SPD_EEPROM
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
 #endif
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 	puts("    DDR: ");
 	return dram_size;
 }
 #if !defined(CONFIG_SPD_EEPROM)
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
 phys_size_t fixed_sdram (void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 	uint d_init;
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 #if defined (CONFIG_DDR_ECC)
 	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 #endif
 	asm("sync;isync");
 	udelay(500);
 	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	d_init = 1;
 	debug("DDR - 1st controller: memory initializing\n");
 	/*
 	 * Poll until memory is initialized.
 	 * 512 Meg at 400 might hit this 200 times or so.
 	 */
 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 		udelay(1000);
 	}
 	debug("DDR: memory initialized\n\n");
 	asm("sync; isync");
 	udelay(500);
 #endif
 	return 512 * 1024 * 1024;
 }
 #endif
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
 #ifdef CONFIG_PCIE1
 static struct pci_controller pcie1_hose;
 #endif
 #ifdef CONFIG_PCIE2
 static struct pci_controller pcie2_hose;
 #endif
 #ifdef CONFIG_PCIE3
 static struct pci_controller pcie3_hose;
 #endif
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	struct fsl_pci_info pci_info[4];
 	u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 	int first_free_busno = 0;
 	int num = 0;
 	int pcie_ep, pcie_configured;
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
 	porpllsr = in_be32(&gur->porpllsr);
 	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
 	debug("   pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
 		devdisr, sdrs2_io_sel, io_sel);
 	if (sdrs2_io_sel == 7)
 		printf("    Serdes2 disalbed\n");
 	else if (sdrs2_io_sel == 4) {
 		printf("    eTSEC1 is in sgmii mode.\n");
 		printf("    eTSEC3 is in sgmii mode.\n");
 	} else if (sdrs2_io_sel == 6)
 		printf("    eTSEC1 is in sgmii mode.\n");
 	puts("\n");
 #ifdef CONFIG_PCIE3
 	pcie_configured = is_serdes_configured(PCIE3);
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
 				LAW_TRGT_IF_PCIE_3);
 		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
 				LAW_TRGT_IF_PCIE_3);
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
 			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie3_hose, first_free_busno);
 	} else {
 		printf ("    PCIE3: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 #endif
 #ifdef CONFIG_PCIE1
 	pcie_configured = is_serdes_configured(PCIE1);
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
 				LAW_TRGT_IF_PCIE_1);
 		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
 				LAW_TRGT_IF_PCIE_1);
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
 			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE1: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 #endif
 #ifdef CONFIG_PCIE2
 	pcie_configured = is_serdes_configured(PCIE2);
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
 				LAW_TRGT_IF_PCIE_2);
 		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
 				LAW_TRGT_IF_PCIE_2);
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
 			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
 	} else {
 		printf ("    PCIE2: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 #endif
 #ifdef CONFIG_PCI1
 	pci_speed = 66666000;
 	pci_32 = 1;
 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
 				LAW_TRGT_IF_PCI);
 		set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
 				LAW_TRGT_IF_PCI);
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
 			(pci_speed == 66666000) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pci1_hose, first_free_busno);
 	} else {
 		printf ("    PCI: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 }
 #endif
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
 	 * so that flash can be erased properly.
 	 */
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
 	flush_dcache();
 	invalidate_icache();
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
 	return 0;
 }
 #ifdef CONFIG_GET_CLK_FROM_ICS307
 /* decode S[0-2] to Output Divider (OD) */
 static unsigned char
 ics307_S_to_OD[] = {
 	10, 2, 8, 4, 5, 7, 3, 6
 };
 /* Calculate frequency being generated by ICS307-02 clock chip based upon
  * the control bytes being programmed into it. */
 /* XXX: This function should probably go into a common library */
 static unsigned long
 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 {
 	const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 	unsigned long RDW = cw2 & 0x7F;
 	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 	unsigned long freq;
 	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 	 *
 	 * R6:R0 = Reference Divider Word (RDW)
 	 * V8:V0 = VCO Divider Word (VDW)
 	 * S2:S0 = Output Divider Select (OD)
 	 * F1:F0 = Function of CLK2 Output
 	 * TTL = duty cycle
 	 * C1:C0 = internal load capacitance for cyrstal
 	 */
 	/* Adding 1 to get a "nicely" rounded number, but this needs
 	 * more tweaking to get a "properly" rounded number. */
 	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 		freq);
 	return freq;
 }
 unsigned long
 get_board_sys_clk(ulong dummy)
 {
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	return ics307_clk_freq (
 	    in_8(pixis_base + PIXIS_VSYSCLK0),
 	    in_8(pixis_base + PIXIS_VSYSCLK1),
 	    in_8(pixis_base + PIXIS_VSYSCLK2)
 	);
 }
 unsigned long
 get_board_ddr_clk(ulong dummy)
 {
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	return ics307_clk_freq (
 	    in_8(pixis_base + PIXIS_VDDRCLK0),
 	    in_8(pixis_base + PIXIS_VDDRCLK1),
 	    in_8(pixis_base + PIXIS_VDDRCLK2)
 	);
 }
 #else
 unsigned long
 get_board_sys_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x07;
 	switch (i) {
 	case 0:
 		val = 33333333;
 		break;
 	case 1:
 		val = 40000000;
 		break;
 	case 2:
 		val = 50000000;
 		break;
 	case 3:
 		val = 66666666;
 		break;
 	case 4:
 		val = 83333333;
 		break;
 	case 5:
 		val = 100000000;
 		break;
 	case 6:
 		val = 133333333;
 		break;
 	case 7:
 		val = 166666666;
 		break;
 	}
 	return val;
 }
 unsigned long
 get_board_ddr_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x38;
 	i >>= 3;
 	switch (i) {
 	case 0:
 		val = 33333333;
 		break;
 	case 1:
 		val = 40000000;
 		break;
 	case 2:
 		val = 50000000;
 		break;
 	case 3:
 		val = 66666666;
 		break;
 	case 4:
 		val = 83333333;
 		break;
 	case 5:
 		val = 100000000;
 		break;
 	case 6:
 		val = 133333333;
 		break;
 	case 7:
 		val = 166666666;
 		break;
 	}
 	return val;
 }
 #endif
-int sata_initialize(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint sdrs2_io_sel =
-		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
-	if (sdrs2_io_sel & 0x04)
-		return 1;
-	return __sata_initialize();
-}
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_TSEC_ENET
 	struct tsec_info_struct tsec_info[2];
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int num = 0;
 	uint sdrs2_io_sel =
 		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
 	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
 		tsec_info[num].phyaddr = 0;
 		tsec_info[num].flags |= TSEC_SGMII;
 	}
 	num++;
 #endif
 #ifdef CONFIG_TSEC3
 	SET_STD_TSEC_INFO(tsec_info[num], 3);
 	if (sdrs2_io_sel == 4) {
 		tsec_info[num].phyaddr = 1;
 		tsec_info[num].flags |= TSEC_SGMII;
 	}
 	num++;
 #endif
 	if (!num) {
 		printf("No TSECs initialized\n");
 		return 0;
 	}
 #ifdef CONFIG_FSL_SGMII_RISER
 	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
 		fsl_sgmii_riser_init(tsec_info, num);
 #endif
 	tsec_eth_init(bis, tsec_info, num);
 #endif
 	return pci_eth_init(bis);
 }
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI1
 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 #else
 	ft_fsl_pci_setup(blob, "pci0", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 #else
 	ft_fsl_pci_setup(blob, "pci1", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 #else
 	ft_fsl_pci_setup(blob, "pci2", NULL);
 #endif
 #ifdef CONFIG_PCIE1
 	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
 #else
 	ft_fsl_pci_setup(blob, "pci3", NULL);
 #endif
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif
 }
 #endif

drivers/block/fsl_sata.c

Diff comments View file @ f54fe87

 /*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  *		Dave Liu <daveliu@freescale.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/fsl_serdes.h>
 #include <malloc.h>
 #include <libata.h>
 #include <fis.h>
 #include "fsl_sata.h"
 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
 #ifndef CONFIG_SYS_SATA1_FLAGS
 	#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
 #endif
 #ifndef CONFIG_SYS_SATA2_FLAGS
 	#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
 #endif
 static struct fsl_sata_info fsl_sata_info[] = {
 #ifdef CONFIG_SATA1
 	{CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
 #else
 	{0, 0},
 #endif
 #ifdef CONFIG_SATA2
 	{CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
 #else
 	{0, 0},
 #endif
 };
 static inline void mdelay(unsigned long msec)
 {
 	unsigned long i;
 	for (i = 0; i < msec; i++)
 		udelay(1000);
 }
 static inline void sdelay(unsigned long sec)
 {
 	unsigned long i;
 	for (i = 0; i < sec; i++)
 		mdelay(1000);
 }
 void dprint_buffer(unsigned char *buf, int len)
 {
 	int i, j;
 	i = 0;
 	j = 0;
 	printf("\n\r");
 	for (i = 0; i < len; i++) {
 		printf("%02x ", *buf++);
 		j++;
 		if (j == 16) {
 			printf("\n\r");
 			j = 0;
 		}
 	}
 	printf("\n\r");
 }
 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
 {
 	printf("Status FIS dump:\n\r");
 	printf("fis_type:		%02x\n\r", s->fis_type);
 	printf("pm_port_i:		%02x\n\r", s->pm_port_i);
 	printf("status:			%02x\n\r", s->status);
 	printf("error:			%02x\n\r", s->error);
 	printf("lba_low:		%02x\n\r", s->lba_low);
 	printf("lba_mid:		%02x\n\r", s->lba_mid);
 	printf("lba_high:		%02x\n\r", s->lba_high);
 	printf("device:			%02x\n\r", s->device);
 	printf("lba_low_exp:		%02x\n\r", s->lba_low_exp);
 	printf("lba_mid_exp:		%02x\n\r", s->lba_mid_exp);
 	printf("lba_high_exp:		%02x\n\r", s->lba_high_exp);
 	printf("res1:			%02x\n\r", s->res1);
 	printf("sector_count:		%02x\n\r", s->sector_count);
 	printf("sector_count_exp:	%02x\n\r", s->sector_count_exp);
 }
 static int ata_wait_register(volatile unsigned *addr, u32 mask,
 			 u32 val, u32 timeout_msec)
 {
 	int i;
 	u32 temp;
 	for (i = 0; (((temp = in_le32(addr)) & mask) != val)
 			 && i < timeout_msec; i++)
 		mdelay(1);
 	return (i < timeout_msec) ? 0 : -1;
 }
 int init_sata(int dev)
 {
 	u32 length, align;
 	cmd_hdr_tbl_t *cmd_hdr;
 	u32 cda;
 	u32 val32;
 	fsl_sata_reg_t *reg;
 	u32 sig;
 	int i;
 	fsl_sata_t *sata;
 	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
 		printf("the sata index %d is out of ranges\n\r", dev);
 		return -1;
 	}
+#ifdef CONFIG_MPC85xx
+	if ((dev == 0) && (!is_serdes_configured(SATA1))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
+		return -1;
+	}
+	if ((dev == 1) && (!is_serdes_configured(SATA2))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
+		return -1;
+	}
+#endif
 	/* Allocate SATA device driver struct */
 	sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
 	if (!sata) {
 		printf("alloc the sata device struct failed\n\r");
 		return -1;
 	}
 	/* Zero all of the device driver struct */
 	memset((void *)sata, 0, sizeof(fsl_sata_t));
 	/* Save the private struct to block device struct */
 	sata_dev_desc[dev].priv = (void *)sata;
 	sprintf(sata->name, "SATA%d", dev);
 	/* Set the controller register base address to device struct */
 	reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
 	sata->reg_base = reg;
 	/* Allocate the command header table, 4 bytes aligned */
 	length = sizeof(struct cmd_hdr_tbl);
 	align = SATA_HC_CMD_HDR_TBL_ALIGN;
 	sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
 	if (!sata) {
 		printf("alloc the command header failed\n\r");
 		return -1;
 	}
 	cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
 						& ~(align - 1));
 	sata->cmd_hdr = cmd_hdr;
 	/* Zero all of the command header table */
 	memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
 	/* Allocate command descriptor for all command */
 	length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
 	align = SATA_HC_CMD_DESC_ALIGN;
 	sata->cmd_desc_offset = (void *)malloc(length + align);
 	if (!sata->cmd_desc_offset) {
 		printf("alloc the command descriptor failed\n\r");
 		return -1;
 	}
 	sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
 						& ~(align - 1));
 	/* Zero all of command descriptor */
 	memset((void *)sata->cmd_desc_offset, 0, length + align);
 	/* Link the command descriptor to command header */
 	for (i = 0; i < SATA_HC_MAX_CMD; i++) {
 		cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
 					 & ~(CMD_HDR_CDA_ALIGN - 1);
 		cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
 	}
 	/* To have safe state, force the controller offline */
 	val32 = in_le32(&reg->hcontrol);
 	val32 &= ~HCONTROL_ONOFF;
 	val32 |= HCONTROL_FORCE_OFFLINE;
 	out_le32(&reg->hcontrol, val32);
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 	/*
 	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
 	 * controller is configured in legacy mode instead of the
 	 * expected enterprise mode. software needs to clear bit[28]
 	 * of HControl register to change to enterprise mode from
 	 * legacy mode.
 	 */
 	{
 		u32 svr = get_svr();
 		if (IS_SVR_REV(svr, 1, 0) &&
 		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
 		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
 		     (SVR_SOC_VER(svr) == SVR_P1013) ||
 		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
 			out_le32(&reg->hstatus, 0x20000000);
 			out_le32(&reg->hcontrol, 0x00000100);
 		}
 	}
 #endif
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
 	/* Snoop for the command header */
 	val32 = in_le32(&reg->hcontrol);
 	val32 |= HCONTROL_HDR_SNOOP;
 	out_le32(&reg->hcontrol, val32);
 	/* Disable all of interrupts */
 	val32 = in_le32(&reg->hcontrol);
 	val32 &= ~HCONTROL_INT_EN_ALL;
 	out_le32(&reg->hcontrol, val32);
 	/* Clear all of interrupts */
 	val32 = in_le32(&reg->hstatus);
 	out_le32(&reg->hstatus, val32);
 	/* Set the ICC, no interrupt coalescing */
 	out_le32(&reg->icc, 0x01000000);
 	/* No PM attatched, the SATA device direct connect */
 	out_le32(&reg->cqpmp, 0);
 	/* Clear SError register */
 	val32 = in_le32(&reg->serror);
 	out_le32(&reg->serror, val32);
 	/* Clear CER register */
 	val32 = in_le32(&reg->cer);
 	out_le32(&reg->cer, val32);
 	/* Clear DER register */
 	val32 = in_le32(&reg->der);
 	out_le32(&reg->der, val32);
 	/* No device detection or initialization action requested */
 	out_le32(&reg->scontrol, 0x00000300);
 	/* Configure the transport layer, default value */
 	out_le32(&reg->transcfg, 0x08000016);
 	/* Configure the link layer, default value */
 	out_le32(&reg->linkcfg, 0x0000ff34);
 	/* Bring the controller online */
 	val32 = in_le32(&reg->hcontrol);
 	val32 |= HCONTROL_ONOFF;
 	out_le32(&reg->hcontrol, val32);
 	mdelay(100);
 	/* print sata device name */
 	if (!dev)
 		printf("%s ", sata->name);
 	else
 		printf("       %s ", sata->name);
 	/* Wait PHY RDY signal changed for 500ms */
 	ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
 			  HSTATUS_PHY_RDY, 500);
 	/* Check PHYRDY */
 	val32 = in_le32(&reg->hstatus);
 	if (val32 & HSTATUS_PHY_RDY) {
 		sata->link = 1;
 	} else {
 		sata->link = 0;
 		printf("(No RDY)\n\r");
 		return -1;
 	}
 	/* Wait for signature updated, which is 1st D2H */
 	ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
 			  HSTATUS_SIGNATURE, 10000);
 	if (val32 & HSTATUS_SIGNATURE) {
 		sig = in_le32(&reg->sig);
 		debug("Signature updated, the sig =%08x\n\r", sig);
 		sata->ata_device_type = ata_dev_classify(sig);
 	}
 	/* Check the speed */
 	val32 = in_le32(&reg->sstatus);
 	if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
 		printf("(1.5 Gbps)\n\r");
 	else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
 		printf("(3 Gbps)\n\r");
 	return 0;
 }
 /* Hardware reset, like Power-on and COMRESET */
 void fsl_sata_hardware_reset(u32 reg_base)
 {
 	fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
 	u32 scontrol;
 	/* Disable the SATA interface and put PHY offline */
 	scontrol = in_le32(&reg->scontrol);
 	scontrol = (scontrol & 0x0f0) | 0x304;
 	out_le32(&reg->scontrol, scontrol);
 	/* No speed strict */
 	scontrol = in_le32(&reg->scontrol);
 	scontrol = scontrol & ~0x0f0;
 	out_le32(&reg->scontrol, scontrol);
 	/* Issue PHY wake/reset, Hardware_reset_asserted */
 	scontrol = in_le32(&reg->scontrol);
 	scontrol = (scontrol & 0x0f0) | 0x301;
 	out_le32(&reg->scontrol, scontrol);
 	mdelay(100);
 	/* Resume PHY, COMRESET negated, the device initialize hardware
 	 * and execute diagnostics, send good status-signature to host,
 	 * which is D2H register FIS, and then the device enter idle state.
 	 */
 	scontrol = in_le32(&reg->scontrol);
 	scontrol = (scontrol & 0x0f0) | 0x300;
 	out_le32(&reg->scontrol, scontrol);
 	mdelay(100);
 	return;
 }
 static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
 {
 	printf("\n\rSATA:           %08x\n\r", (u32)reg);
 	printf("CQR:            %08x\n\r", in_le32(&reg->cqr));
 	printf("CAR:            %08x\n\r", in_le32(&reg->car));
 	printf("CCR:            %08x\n\r", in_le32(&reg->ccr));
 	printf("CER:            %08x\n\r", in_le32(&reg->cer));
 	printf("CQR:            %08x\n\r", in_le32(&reg->cqr));
 	printf("DER:            %08x\n\r", in_le32(&reg->der));
 	printf("CHBA:           %08x\n\r", in_le32(&reg->chba));
 	printf("HStatus:        %08x\n\r", in_le32(&reg->hstatus));
 	printf("HControl:       %08x\n\r", in_le32(&reg->hcontrol));
 	printf("CQPMP:          %08x\n\r", in_le32(&reg->cqpmp));
 	printf("SIG:            %08x\n\r", in_le32(&reg->sig));
 	printf("ICC:            %08x\n\r", in_le32(&reg->icc));
 	printf("SStatus:        %08x\n\r", in_le32(&reg->sstatus));
 	printf("SError:         %08x\n\r", in_le32(&reg->serror));
 	printf("SControl:       %08x\n\r", in_le32(&reg->scontrol));
 	printf("SNotification:  %08x\n\r", in_le32(&reg->snotification));
 	printf("TransCfg:       %08x\n\r", in_le32(&reg->transcfg));
 	printf("TransStatus:    %08x\n\r", in_le32(&reg->transstatus));
 	printf("LinkCfg:        %08x\n\r", in_le32(&reg->linkcfg));
 	printf("LinkCfg1:       %08x\n\r", in_le32(&reg->linkcfg1));
 	printf("LinkCfg2:       %08x\n\r", in_le32(&reg->linkcfg2));
 	printf("LinkStatus:     %08x\n\r", in_le32(&reg->linkstatus));
 	printf("LinkStatus1:    %08x\n\r", in_le32(&reg->linkstatus1));
 	printf("PhyCtrlCfg:     %08x\n\r", in_le32(&reg->phyctrlcfg));
 	printf("SYSPR:          %08x\n\r", in_be32(&reg->syspr));
 }
 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
 				int is_ncq, int tag, u8 *buffer, u32 len)
 {
 	cmd_hdr_entry_t *cmd_hdr;
 	cmd_desc_t *cmd_desc;
 	sata_fis_h2d_t *h2d;
 	prd_entry_t *prde;
 	u32 ext_c_ddc;
 	u32 prde_count;
 	u32 val32;
 	u32 ttl;
 	fsl_sata_reg_t *reg = sata->reg_base;
 	int i;
 	/* Check xfer length */
 	if (len > SATA_HC_MAX_XFER_LEN) {
 		printf("max transfer length is 64MB\n\r");
 		return 0;
 	}
 	/* Setup the command descriptor */
 	cmd_desc = sata->cmd_desc + tag;
 	/* Get the pointer cfis of command descriptor */
 	h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
 	/* Zero the cfis of command descriptor */
 	memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
 	/* Copy the cfis from user to command descriptor */
 	h2d->fis_type = cfis->fis_type;
 	h2d->pm_port_c = cfis->pm_port_c;
 	h2d->command = cfis->command;
 	h2d->features = cfis->features;
 	h2d->features_exp = cfis->features_exp;
 	h2d->lba_low = cfis->lba_low;
 	h2d->lba_mid = cfis->lba_mid;
 	h2d->lba_high = cfis->lba_high;
 	h2d->lba_low_exp = cfis->lba_low_exp;
 	h2d->lba_mid_exp = cfis->lba_mid_exp;
 	h2d->lba_high_exp = cfis->lba_high_exp;
 	if (!is_ncq) {
 		h2d->sector_count = cfis->sector_count;
 		h2d->sector_count_exp = cfis->sector_count_exp;
 	} else { /* NCQ */
 		h2d->sector_count = (u8)(tag << 3);
 	}
 	h2d->device = cfis->device;
 	h2d->control = cfis->control;
 	/* Setup the PRD table */
 	prde = (prd_entry_t *)cmd_desc->prdt;
 	memset((void *)prde, 0, sizeof(struct prdt));
 	prde_count = 0;
 	ttl = len;
 	for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
 		if (!len)
 			break;
 		prde->dba = cpu_to_le32((u32)buffer & ~0x3);
 		debug("dba = %08x\n\r", (u32)buffer);
 		if (len < PRD_ENTRY_MAX_XFER_SZ) {
 			ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
 			debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
 			prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
 			prde_count++;
 			prde++;
 			break;
 		} else {
 			ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
 			debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
 			prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
 			buffer += PRD_ENTRY_MAX_XFER_SZ;
 			len -= PRD_ENTRY_MAX_XFER_SZ;
 			prde_count++;
 			prde++;
 		}
 	}
 	/* Setup the command slot of cmd hdr */
 	cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
 	cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
 	val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
 	val32 |= sizeof(sata_fis_h2d_t);
 	cmd_hdr->prde_fis_len = cpu_to_le32(val32);
 	cmd_hdr->ttl = cpu_to_le32(ttl);
 	if (!is_ncq) {
 		val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
 	} else {
 		val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
 	}
 	tag &= CMD_HDR_ATTR_TAG;
 	val32 |= tag;
 	debug("attribute = %08x\n\r", val32);
 	cmd_hdr->attribute = cpu_to_le32(val32);
 	/* Make sure cmd desc and cmd slot valid before commmand issue */
 	sync();
 	/* PMP*/
 	val32 = (u32)(h2d->pm_port_c & 0x0f);
 	out_le32(&reg->cqpmp, val32);
 	/* Wait no active */
 	if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
 		printf("Wait no active time out\n\r");
 	/* Issue command */
 	if (!(in_le32(&reg->cqr) & (1 << tag))) {
 		val32 = 1 << tag;
 		out_le32(&reg->cqr, val32);
 	}
 	/* Wait command completed for 10s */
 	if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
 		if (!is_ncq)
 			printf("Non-NCQ command time out\n\r");
 		else
 			printf("NCQ command time out\n\r");
 	}
 	val32 = in_le32(&reg->cer);
 	if (val32) {
 		u32 der;
 		fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
 		printf("CE at device\n\r");
 		fsl_sata_dump_regs(reg);
 		der = in_le32(&reg->der);
 		out_le32(&reg->cer, val32);
 		out_le32(&reg->der, der);
 	}
 	/* Clear complete flags */
 	val32 = in_le32(&reg->ccr);
 	out_le32(&reg->ccr, val32);
 	return len;
 }
 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
 				 int tag, u8 *buffer, u32 len)
 {
 	return 0;
 }
 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
 		 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
 {
 	int rc;
 	if (tag > SATA_HC_MAX_CMD || tag < 0) {
 		printf("tag is out of range, tag=%d\n\r", tag);
 		return -1;
 	}
 	switch (command_type) {
 	case CMD_ATA:
 		rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
 		return rc;
 	case CMD_RESET:
 		rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
 		return rc;
 	case CMD_NCQ:
 		rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
 		return rc;
 	case CMD_ATAPI:
 	case CMD_VENDOR_BIST:
 	case CMD_BIST:
 		printf("not support now\n\r");
 		return -1;
 	default:
 		break;
 	}
 	return -1;
 }
 static void fsl_sata_identify(int dev, u16 *id)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = ATA_CMD_ID_ATA;
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
 	ata_swap_buf_le16(id, ATA_ID_WORDS);
 }
 static void fsl_sata_xfer_mode(int dev, u16 *id)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	sata->pio = id[ATA_ID_PIO_MODES];
 	sata->mwdma = id[ATA_ID_MWDMA_MODES];
 	sata->udma = id[ATA_ID_UDMA_MODES];
 	debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
 }
 static void fsl_sata_set_features(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	u8 udma_cap;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = ATA_CMD_SET_FEATURES;
 	cfis->features = SETFEATURES_XFER;
 	/* First check the device capablity */
 	udma_cap = (u8)(sata->udma & 0xff);
 	debug("udma_cap %02x\n\r", udma_cap);
 	if (udma_cap == ATA_UDMA6)
 		cfis->sector_count = XFER_UDMA_6;
 	if (udma_cap == ATA_UDMA5)
 		cfis->sector_count = XFER_UDMA_5;
 	if (udma_cap == ATA_UDMA4)
 		cfis->sector_count = XFER_UDMA_4;
 	if (udma_cap == ATA_UDMA3)
 		cfis->sector_count = XFER_UDMA_3;
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
 }
 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	u32 block;
 	block = start;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
 	cfis->device = ATA_LBA;
 	cfis->device |= (block >> 24) & 0xf;
 	cfis->lba_high = (block >> 16) & 0xff;
 	cfis->lba_mid = (block >> 8) & 0xff;
 	cfis->lba_low = block & 0xff;
 	cfis->sector_count = (u8)(blkcnt & 0xff);
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
 	return blkcnt;
 }
 void fsl_sata_flush_cache(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = ATA_CMD_FLUSH;
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
 }
 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	u64 block;
 	block = (u64)start;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
 				 : ATA_CMD_READ_EXT;
 	cfis->lba_high_exp = (block >> 40) & 0xff;
 	cfis->lba_mid_exp = (block >> 32) & 0xff;
 	cfis->lba_low_exp = (block >> 24) & 0xff;
 	cfis->lba_high = (block >> 16) & 0xff;
 	cfis->lba_mid = (block >> 8) & 0xff;
 	cfis->lba_low = block & 0xff;
 	cfis->device = ATA_LBA;
 	cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
 	cfis->sector_count = blkcnt & 0xff;
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
 	return blkcnt;
 }
 u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	int ncq_channel;
 	u64 block;
 	if (sata_dev_desc[dev].lba48 != 1) {
 		printf("execute FPDMA command on non-LBA48 hard disk\n\r");
 		return -1;
 	}
 	block = (u64)start;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
 				 : ATA_CMD_FPDMA_READ;
 	cfis->lba_high_exp = (block >> 40) & 0xff;
 	cfis->lba_mid_exp = (block >> 32) & 0xff;
 	cfis->lba_low_exp = (block >> 24) & 0xff;
 	cfis->lba_high = (block >> 16) & 0xff;
 	cfis->lba_mid = (block >> 8) & 0xff;
 	cfis->lba_low = block & 0xff;
 	cfis->device = ATA_LBA;
 	cfis->features_exp = (blkcnt >> 8) & 0xff;
 	cfis->features = blkcnt & 0xff;
 	if (sata->queue_depth >= SATA_HC_MAX_CMD)
 		ncq_channel = SATA_HC_MAX_CMD - 1;
 	else
 		ncq_channel = sata->queue_depth - 1;
 	/* Use the latest queue */
 	fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
 	return blkcnt;
 }
 void fsl_sata_flush_cache_ext(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	struct sata_fis_h2d h2d, *cfis = &h2d;
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 	cfis->pm_port_c = 0x80; /* is command */
 	cfis->command = ATA_CMD_FLUSH_EXT;
 	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
 }
 /* Software reset, set SRST of the Device Control register */
 void fsl_sata_software_reset(int dev)
 {
 	return;
 }
 static void fsl_sata_init_wcache(int dev, u16 *id)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 		sata->wcache = 1;
 	if (ata_id_has_flush(id))
 		sata->flush = 1;
 	if (ata_id_has_flush_ext(id))
 		sata->flush_ext = 1;
 }
 static int fsl_sata_get_wcache(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	return sata->wcache;
 }
 static int fsl_sata_get_flush(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	return sata->flush;
 }
 static int fsl_sata_get_flush_ext(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	return sata->flush_ext;
 }
 u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
 {
 	u32 start, blks;
 	u8 *addr;
 	int max_blks;
 	start = blknr;
 	blks = blkcnt;
 	addr = (u8 *)buffer;
 	max_blks = ATA_MAX_SECTORS_LBA48;
 	do {
 		if (blks > max_blks) {
 			if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
 				fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
 			else
 				fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
 			start += max_blks;
 			blks -= max_blks;
 			addr += ATA_SECT_SIZE * max_blks;
 		} else {
 			if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
 				fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
 			else
 				fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
 			start += blks;
 			blks = 0;
 			addr += ATA_SECT_SIZE * blks;
 		}
 	} while (blks != 0);
 	return blkcnt;
 }
 u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
 {
 	u32 start, blks;
 	u8 *addr;
 	int max_blks;
 	start = blknr;
 	blks = blkcnt;
 	addr = (u8 *)buffer;
 	max_blks = ATA_MAX_SECTORS;
 	do {
 		if (blks > max_blks) {
 			fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
 			start += max_blks;
 			blks -= max_blks;
 			addr += ATA_SECT_SIZE * max_blks;
 		} else {
 			fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
 			start += blks;
 			blks = 0;
 			addr += ATA_SECT_SIZE * blks;
 		}
 	} while (blks != 0);
 	return blkcnt;
 }
 /*
  * SATA interface between low level driver and command layer
  */
 ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
 {
 	u32 rc;
 	if (sata_dev_desc[dev].lba48)
 		rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
 	else
 		rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
 	return rc;
 }
 ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
 {
 	u32 rc;
 	if (sata_dev_desc[dev].lba48) {
 		rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
 		if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
 			fsl_sata_flush_cache_ext(dev);
 	} else {
 		rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
 		if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
 			fsl_sata_flush_cache(dev);
 	}
 	return rc;
 }
 int scan_sata(int dev)
 {
 	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
 	unsigned char serial[ATA_ID_SERNO_LEN + 1];
 	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
 	unsigned char product[ATA_ID_PROD_LEN + 1];
 	u16 *id;
 	u64 n_sectors;
 	/* if no detected link */
 	if (!sata->link)
 		return -1;
 	id = (u16 *)malloc(ATA_ID_WORDS * 2);
 	if (!id) {
 		printf("id malloc failed\n\r");
 		return -1;
 	}
 	/* Identify device to get information */
 	fsl_sata_identify(dev, id);
 	/* Serial number */
 	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 	memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
 	/* Firmware version */
 	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 	memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
 	/* Product model */
 	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 	memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
 	/* Totoal sectors */
 	n_sectors = ata_id_n_sectors(id);
 	sata_dev_desc[dev].lba = (u32)n_sectors;
 	/* Check if support LBA48 */
 	if (ata_id_has_lba48(id)) {
 		sata_dev_desc[dev].lba48 = 1;
 		debug("Device support LBA48\n\r");
 	}
 	/* Get the NCQ queue depth from device */
 	sata->queue_depth = ata_id_queue_depth(id);
 	/* Get the xfer mode from device */
 	fsl_sata_xfer_mode(dev, id);
 	/* Get the write cache status from device */
 	fsl_sata_init_wcache(dev, id);
 	/* Set the xfer mode to highest speed */
 	fsl_sata_set_features(dev);
 #ifdef DEBUG
 	fsl_sata_identify(dev, id);
 	ata_dump_id(id);
 #endif
 	free((void *)id);
 	return 0;
 }