Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f5bf23d8278b2fdfb9ce41fa36369cebc882ab02

Authored by Santan Kumar
Committed by York Sun
1 parent 8104deb2d6
Exists in smarc_8mq_lf_v2020.04 and in 19 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-boot 

This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below

Image				Flash Offset
RCW+PBI				0x00000000
Boot firmware (U-Boot)		0x00100000
Boot firmware Environment	0x00300000
PPA firmware			0x00400000
PHY firmware			0x00980000
DPAA2 MC			0x00A00000
DPAA2 DPL			0x00D00000
DPAA2 DPC			0x00E00000
Kernel.itb			0x01000000

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 6 changed files with 40 additions and 15 deletions Inline Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ f5bf23d
1 config ARCH_LS1012A 1 config ARCH_LS1012A
2 bool 2 bool
3 select ARMV8_SET_SMPEN 3 select ARMV8_SET_SMPEN
4 select FSL_LSCH2 4 select FSL_LSCH2
5 select SYS_FSL_DDR_BE 5 select SYS_FSL_DDR_BE
6 select SYS_FSL_MMDC 6 select SYS_FSL_MMDC
7 select SYS_FSL_ERRATUM_A010315 7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R 8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F 9 select BOARD_EARLY_INIT_F
10 10
11 config ARCH_LS1043A 11 config ARCH_LS1043A
12 bool 12 bool
13 select ARMV8_SET_SMPEN 13 select ARMV8_SET_SMPEN
14 select FSL_LSCH2 14 select FSL_LSCH2
15 select SYS_FSL_DDR 15 select SYS_FSL_DDR
16 select SYS_FSL_DDR_BE 16 select SYS_FSL_DDR_BE
17 select SYS_FSL_DDR_VER_50 17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850 18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660 19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663 20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929 21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942 22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315 23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539 24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3 25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4 26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R 27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F 28 select BOARD_EARLY_INIT_F
29 29
30 config ARCH_LS1046A 30 config ARCH_LS1046A
31 bool 31 bool
32 select ARMV8_SET_SMPEN 32 select ARMV8_SET_SMPEN
33 select FSL_LSCH2 33 select FSL_LSCH2
34 select SYS_FSL_DDR 34 select SYS_FSL_DDR
35 select SYS_FSL_DDR_BE 35 select SYS_FSL_DDR_BE
36 select SYS_FSL_DDR_VER_50 36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336 37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511 38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A008850 39 select SYS_FSL_ERRATUM_A008850
40 select SYS_FSL_ERRATUM_A009801 40 select SYS_FSL_ERRATUM_A009801
41 select SYS_FSL_ERRATUM_A009803 41 select SYS_FSL_ERRATUM_A009803
42 select SYS_FSL_ERRATUM_A009942 42 select SYS_FSL_ERRATUM_A009942
43 select SYS_FSL_ERRATUM_A010165 43 select SYS_FSL_ERRATUM_A010165
44 select SYS_FSL_ERRATUM_A010539 44 select SYS_FSL_ERRATUM_A010539
45 select SYS_FSL_HAS_DDR4 45 select SYS_FSL_HAS_DDR4
46 select SYS_FSL_SRDS_2 46 select SYS_FSL_SRDS_2
47 select ARCH_EARLY_INIT_R 47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F 48 select BOARD_EARLY_INIT_F
49 49
50 config ARCH_LS2080A 50 config ARCH_LS2080A
51 bool 51 bool
52 select ARMV8_SET_SMPEN 52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_826974 53 select ARM_ERRATA_826974
54 select ARM_ERRATA_828024 54 select ARM_ERRATA_828024
55 select ARM_ERRATA_829520 55 select ARM_ERRATA_829520
56 select ARM_ERRATA_833471 56 select ARM_ERRATA_833471
57 select FSL_LSCH3 57 select FSL_LSCH3
58 select SYS_FSL_DDR 58 select SYS_FSL_DDR
59 select SYS_FSL_DDR_LE 59 select SYS_FSL_DDR_LE
60 select SYS_FSL_DDR_VER_50 60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_HAS_DP_DDR 61 select SYS_FSL_HAS_DP_DDR
62 select SYS_FSL_HAS_SEC 62 select SYS_FSL_HAS_SEC
63 select SYS_FSL_HAS_DDR4 63 select SYS_FSL_HAS_DDR4
64 select SYS_FSL_SEC_COMPAT_5 64 select SYS_FSL_SEC_COMPAT_5
65 select SYS_FSL_SEC_LE 65 select SYS_FSL_SEC_LE
66 select SYS_FSL_SRDS_2 66 select SYS_FSL_SRDS_2
67 select FSL_TZASC_1 67 select FSL_TZASC_1
68 select FSL_TZASC_2 68 select FSL_TZASC_2
69 select SYS_FSL_ERRATUM_A008336 69 select SYS_FSL_ERRATUM_A008336
70 select SYS_FSL_ERRATUM_A008511 70 select SYS_FSL_ERRATUM_A008511
71 select SYS_FSL_ERRATUM_A008514 71 select SYS_FSL_ERRATUM_A008514
72 select SYS_FSL_ERRATUM_A008585 72 select SYS_FSL_ERRATUM_A008585
73 select SYS_FSL_ERRATUM_A009635 73 select SYS_FSL_ERRATUM_A009635
74 select SYS_FSL_ERRATUM_A009663 74 select SYS_FSL_ERRATUM_A009663
75 select SYS_FSL_ERRATUM_A009801 75 select SYS_FSL_ERRATUM_A009801
76 select SYS_FSL_ERRATUM_A009803 76 select SYS_FSL_ERRATUM_A009803
77 select SYS_FSL_ERRATUM_A009942 77 select SYS_FSL_ERRATUM_A009942
78 select SYS_FSL_ERRATUM_A010165 78 select SYS_FSL_ERRATUM_A010165
79 select SYS_FSL_ERRATUM_A009203 79 select SYS_FSL_ERRATUM_A009203
80 select ARCH_EARLY_INIT_R 80 select ARCH_EARLY_INIT_R
81 select BOARD_EARLY_INIT_F 81 select BOARD_EARLY_INIT_F
82 82
83 config FSL_LSCH2 83 config FSL_LSCH2
84 bool 84 bool
85 select SYS_FSL_HAS_SEC 85 select SYS_FSL_HAS_SEC
86 select SYS_FSL_SEC_COMPAT_5 86 select SYS_FSL_SEC_COMPAT_5
87 select SYS_FSL_SEC_BE 87 select SYS_FSL_SEC_BE
88 select SYS_FSL_SRDS_1 88 select SYS_FSL_SRDS_1
89 select SYS_HAS_SERDES 89 select SYS_HAS_SERDES
90 90
91 config FSL_LSCH3 91 config FSL_LSCH3
92 bool 92 bool
93 select SYS_FSL_SRDS_1 93 select SYS_FSL_SRDS_1
94 select SYS_HAS_SERDES 94 select SYS_HAS_SERDES
95 95
96 config FSL_MC_ENET 96 config FSL_MC_ENET
97 bool "Management Complex network" 97 bool "Management Complex network"
98 depends on ARCH_LS2080A 98 depends on ARCH_LS2080A
99 default y 99 default y
100 select RESV_RAM 100 select RESV_RAM
101 help 101 help
102 Enable Management Complex (MC) network 102 Enable Management Complex (MC) network
103 103
104 menu "Layerscape architecture" 104 menu "Layerscape architecture"
105 depends on FSL_LSCH2 || FSL_LSCH3 105 depends on FSL_LSCH2 || FSL_LSCH3
106 106
107 config FSL_PCIE_COMPAT 107 config FSL_PCIE_COMPAT
108 string "PCIe compatible of Kernel DT" 108 string "PCIe compatible of Kernel DT"
109 depends on PCIE_LAYERSCAPE 109 depends on PCIE_LAYERSCAPE
110 default "fsl,ls1012a-pcie" if ARCH_LS1012A 110 default "fsl,ls1012a-pcie" if ARCH_LS1012A
111 default "fsl,ls1043a-pcie" if ARCH_LS1043A 111 default "fsl,ls1043a-pcie" if ARCH_LS1043A
112 default "fsl,ls1046a-pcie" if ARCH_LS1046A 112 default "fsl,ls1046a-pcie" if ARCH_LS1046A
113 default "fsl,ls2080a-pcie" if ARCH_LS2080A 113 default "fsl,ls2080a-pcie" if ARCH_LS2080A
114 help 114 help
115 This compatible is used to find pci controller node in Kernel DT 115 This compatible is used to find pci controller node in Kernel DT
116 to complete fixup. 116 to complete fixup.
117 117
118 config HAS_FEATURE_GIC64K_ALIGN 118 config HAS_FEATURE_GIC64K_ALIGN
119 bool 119 bool
120 default y if ARCH_LS1043A 120 default y if ARCH_LS1043A
121 121
122 config HAS_FEATURE_ENHANCED_MSI 122 config HAS_FEATURE_ENHANCED_MSI
123 bool 123 bool
124 default y if ARCH_LS1043A 124 default y if ARCH_LS1043A
125 125
126 menu "Layerscape PPA" 126 menu "Layerscape PPA"
127 config FSL_LS_PPA 127 config FSL_LS_PPA
128 bool "FSL Layerscape PPA firmware support" 128 bool "FSL Layerscape PPA firmware support"
129 depends on !ARMV8_PSCI 129 depends on !ARMV8_PSCI
130 select ARMV8_SEC_FIRMWARE_SUPPORT 130 select ARMV8_SEC_FIRMWARE_SUPPORT
131 select SEC_FIRMWARE_ARMV8_PSCI 131 select SEC_FIRMWARE_ARMV8_PSCI
132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
133 help 133 help
134 The FSL Primary Protected Application (PPA) is a software component 134 The FSL Primary Protected Application (PPA) is a software component
135 which is loaded during boot stage, and then remains resident in RAM 135 which is loaded during boot stage, and then remains resident in RAM
136 and runs in the TrustZone after boot. 136 and runs in the TrustZone after boot.
137 Say y to enable it. 137 Say y to enable it.
138 choice 138 choice
139 prompt "FSL Layerscape PPA firmware loading-media select" 139 prompt "FSL Layerscape PPA firmware loading-media select"
140 depends on FSL_LS_PPA 140 depends on FSL_LS_PPA
141 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 141 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
142 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 142 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
143 default SYS_LS_PPA_FW_IN_XIP 143 default SYS_LS_PPA_FW_IN_XIP
144 144
145 config SYS_LS_PPA_FW_IN_XIP 145 config SYS_LS_PPA_FW_IN_XIP
146 bool "XIP" 146 bool "XIP"
147 help 147 help
148 Say Y here if the PPA firmware locate at XIP flash, such 148 Say Y here if the PPA firmware locate at XIP flash, such
149 as NOR or QSPI flash. 149 as NOR or QSPI flash.
150 150
151 config SYS_LS_PPA_FW_IN_MMC 151 config SYS_LS_PPA_FW_IN_MMC
152 bool "eMMC or SD Card" 152 bool "eMMC or SD Card"
153 help 153 help
154 Say Y here if the PPA firmware locate at eMMC/SD card. 154 Say Y here if the PPA firmware locate at eMMC/SD card.
155 155
156 config SYS_LS_PPA_FW_IN_NAND 156 config SYS_LS_PPA_FW_IN_NAND
157 bool "NAND" 157 bool "NAND"
158 help 158 help
159 Say Y here if the PPA firmware locate at NAND flash. 159 Say Y here if the PPA firmware locate at NAND flash.
160 160
161 endchoice 161 endchoice
162 162
163 config SYS_LS_PPA_FW_ADDR 163 config SYS_LS_PPA_FW_ADDR
164 hex "Address of PPA firmware loading from" 164 hex "Address of PPA firmware loading from"
165 depends on FSL_LS_PPA 165 depends on FSL_LS_PPA
166 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 166 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
167 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 167 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
168 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 168 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
169 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 169 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
170 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 170 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
171 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 171 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
172 172
173 help 173 help
174 If the PPA firmware locate at XIP flash, such as NOR or 174 If the PPA firmware locate at XIP flash, such as NOR or
175 QSPI flash, this address is a directly memory-mapped. 175 QSPI flash, this address is a directly memory-mapped.
176 If it is in a serial accessed flash, such as NAND and SD 176 If it is in a serial accessed flash, such as NAND and SD
177 card, it is a byte offset. 177 card, it is a byte offset.
178 178
179 config SYS_LS_PPA_ESBC_ADDR 179 config SYS_LS_PPA_ESBC_ADDR
180 hex "hdr address of PPA firmware loading from" 180 hex "hdr address of PPA firmware loading from"
181 depends on FSL_LS_PPA && CHAIN_OF_TRUST 181 depends on FSL_LS_PPA && CHAIN_OF_TRUST
182 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 182 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
183 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 183 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
184 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 184 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
185 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 185 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
186 default 0x700000 if SYS_LS_PPA_FW_IN_MMC 186 default 0x700000 if SYS_LS_PPA_FW_IN_MMC
187 default 0x700000 if SYS_LS_PPA_FW_IN_NAND 187 default 0x700000 if SYS_LS_PPA_FW_IN_NAND
188 help 188 help
189 If the PPA header firmware locate at XIP flash, such as NOR or 189 If the PPA header firmware locate at XIP flash, such as NOR or
190 QSPI flash, this address is a directly memory-mapped. 190 QSPI flash, this address is a directly memory-mapped.
191 If it is in a serial accessed flash, such as NAND and SD 191 If it is in a serial accessed flash, such as NAND and SD
192 card, it is a byte offset. 192 card, it is a byte offset.
193 193
194 config LS_PPA_ESBC_HDR_SIZE 194 config LS_PPA_ESBC_HDR_SIZE
195 hex "Length of PPA ESBC header" 195 hex "Length of PPA ESBC header"
196 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 196 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
197 default 0x2000 197 default 0x2000
198 help 198 help
199 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 199 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
200 NAND to memory to validate PPA image. 200 NAND to memory to validate PPA image.
201 201
202 endmenu 202 endmenu
203 203
204 config SYS_FSL_ERRATUM_A010315 204 config SYS_FSL_ERRATUM_A010315
205 bool "Workaround for PCIe erratum A010315" 205 bool "Workaround for PCIe erratum A010315"
206 206
207 config SYS_FSL_ERRATUM_A010539 207 config SYS_FSL_ERRATUM_A010539
208 bool "Workaround for PIN MUX erratum A010539" 208 bool "Workaround for PIN MUX erratum A010539"
209 209
210 config MAX_CPUS 210 config MAX_CPUS
211 int "Maximum number of CPUs permitted for Layerscape" 211 int "Maximum number of CPUs permitted for Layerscape"
212 default 4 if ARCH_LS1043A 212 default 4 if ARCH_LS1043A
213 default 4 if ARCH_LS1046A 213 default 4 if ARCH_LS1046A
214 default 16 if ARCH_LS2080A 214 default 16 if ARCH_LS2080A
215 default 1 215 default 1
216 help 216 help
217 Set this number to the maximum number of possible CPUs in the SoC. 217 Set this number to the maximum number of possible CPUs in the SoC.
218 SoCs may have multiple clusters with each cluster may have multiple 218 SoCs may have multiple clusters with each cluster may have multiple
219 ports. If some ports are reserved but higher ports are used for 219 ports. If some ports are reserved but higher ports are used for
220 cores, count the reserved ports. This will allocate enough memory 220 cores, count the reserved ports. This will allocate enough memory
221 in spin table to properly handle all cores. 221 in spin table to properly handle all cores.
222 222
223 config SECURE_BOOT 223 config SECURE_BOOT
224 bool "Secure Boot" 224 bool "Secure Boot"
225 help 225 help
226 Enable Freescale Secure Boot feature 226 Enable Freescale Secure Boot feature
227 227
228 config QSPI_AHB_INIT 228 config QSPI_AHB_INIT
229 bool "Init the QSPI AHB bus" 229 bool "Init the QSPI AHB bus"
230 help 230 help
231 The default setting for QSPI AHB bus just support 3bytes addressing. 231 The default setting for QSPI AHB bus just support 3bytes addressing.
232 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 232 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
233 bus for those flashes to support the full QSPI flash size. 233 bus for those flashes to support the full QSPI flash size.
234 234
235 config SYS_FSL_IFC_BANK_COUNT 235 config SYS_FSL_IFC_BANK_COUNT
236 int "Maximum banks of Integrated flash controller" 236 int "Maximum banks of Integrated flash controller"
237 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 237 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
238 default 4 if ARCH_LS1043A 238 default 4 if ARCH_LS1043A
239 default 4 if ARCH_LS1046A 239 default 4 if ARCH_LS1046A
240 default 8 if ARCH_LS2080A 240 default 8 if ARCH_LS2080A
241 241
242 config SYS_FSL_HAS_DP_DDR 242 config SYS_FSL_HAS_DP_DDR
243 bool 243 bool
244 244
245 config SYS_FSL_SRDS_1 245 config SYS_FSL_SRDS_1
246 bool 246 bool
247 247
248 config SYS_FSL_SRDS_2 248 config SYS_FSL_SRDS_2
249 bool 249 bool
250 250
251 config SYS_HAS_SERDES 251 config SYS_HAS_SERDES
252 bool 252 bool
253 253
254 config FSL_TZASC_1 254 config FSL_TZASC_1
255 bool 255 bool
256 256
257 config FSL_TZASC_2 257 config FSL_TZASC_2
258 bool 258 bool
259 259
260 endmenu 260 endmenu
261 261
262 menu "Layerscape clock tree configuration" 262 menu "Layerscape clock tree configuration"
263 depends on FSL_LSCH2 || FSL_LSCH3 263 depends on FSL_LSCH2 || FSL_LSCH3
264 264
265 config SYS_FSL_CLK 265 config SYS_FSL_CLK
266 bool "Enable clock tree initialization" 266 bool "Enable clock tree initialization"
267 default y 267 default y
268 268
269 config CLUSTER_CLK_FREQ 269 config CLUSTER_CLK_FREQ
270 int "Reference clock of core cluster" 270 int "Reference clock of core cluster"
271 depends on ARCH_LS1012A 271 depends on ARCH_LS1012A
272 default 100000000 272 default 100000000
273 help 273 help
274 This number is the reference clock frequency of core PLL. 274 This number is the reference clock frequency of core PLL.
275 For most platforms, the core PLL and Platform PLL have the same 275 For most platforms, the core PLL and Platform PLL have the same
276 reference clock, but for some platforms, LS1012A for instance, 276 reference clock, but for some platforms, LS1012A for instance,
277 they are provided sepatately. 277 they are provided sepatately.
278 278
279 config SYS_FSL_PCLK_DIV 279 config SYS_FSL_PCLK_DIV
280 int "Platform clock divider" 280 int "Platform clock divider"
281 default 1 if ARCH_LS1043A 281 default 1 if ARCH_LS1043A
282 default 1 if ARCH_LS1046A 282 default 1 if ARCH_LS1046A
283 default 2 283 default 2
284 help 284 help
285 This is the divider that is used to derive Platform clock from 285 This is the divider that is used to derive Platform clock from
286 Platform PLL, in another word: 286 Platform PLL, in another word:
287 Platform_clk = Platform_PLL_freq / this_divider 287 Platform_clk = Platform_PLL_freq / this_divider
288 288
289 config SYS_FSL_DSPI_CLK_DIV 289 config SYS_FSL_DSPI_CLK_DIV
290 int "DSPI clock divider" 290 int "DSPI clock divider"
291 default 1 if ARCH_LS1043A 291 default 1 if ARCH_LS1043A
292 default 2 292 default 2
293 help 293 help
294 This is the divider that is used to derive DSPI clock from Platform 294 This is the divider that is used to derive DSPI clock from Platform
295 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 295 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
296 296
297 config SYS_FSL_DUART_CLK_DIV 297 config SYS_FSL_DUART_CLK_DIV
298 int "DUART clock divider" 298 int "DUART clock divider"
299 default 1 if ARCH_LS1043A 299 default 1 if ARCH_LS1043A
300 default 2 300 default 2
301 help 301 help
302 This is the divider that is used to derive DUART clock from Platform 302 This is the divider that is used to derive DUART clock from Platform
303 clock, in another word DUART_clk = Platform_clk / this_divider. 303 clock, in another word DUART_clk = Platform_clk / this_divider.
304 304
305 config SYS_FSL_I2C_CLK_DIV 305 config SYS_FSL_I2C_CLK_DIV
306 int "I2C clock divider" 306 int "I2C clock divider"
307 default 1 if ARCH_LS1043A 307 default 1 if ARCH_LS1043A
308 default 2 308 default 2
309 help 309 help
310 This is the divider that is used to derive I2C clock from Platform 310 This is the divider that is used to derive I2C clock from Platform
311 clock, in another word I2C_clk = Platform_clk / this_divider. 311 clock, in another word I2C_clk = Platform_clk / this_divider.
312 312
313 config SYS_FSL_IFC_CLK_DIV 313 config SYS_FSL_IFC_CLK_DIV
314 int "IFC clock divider" 314 int "IFC clock divider"
315 default 1 if ARCH_LS1043A 315 default 1 if ARCH_LS1043A
316 default 2 316 default 2
317 help 317 help
318 This is the divider that is used to derive IFC clock from Platform 318 This is the divider that is used to derive IFC clock from Platform
319 clock, in another word IFC_clk = Platform_clk / this_divider. 319 clock, in another word IFC_clk = Platform_clk / this_divider.
320 320
321 config SYS_FSL_LPUART_CLK_DIV 321 config SYS_FSL_LPUART_CLK_DIV
322 int "LPUART clock divider" 322 int "LPUART clock divider"
323 default 1 if ARCH_LS1043A 323 default 1 if ARCH_LS1043A
324 default 2 324 default 2
325 help 325 help
326 This is the divider that is used to derive LPUART clock from Platform 326 This is the divider that is used to derive LPUART clock from Platform
327 clock, in another word LPUART_clk = Platform_clk / this_divider. 327 clock, in another word LPUART_clk = Platform_clk / this_divider.
328 328
329 config SYS_FSL_SDHC_CLK_DIV 329 config SYS_FSL_SDHC_CLK_DIV
330 int "SDHC clock divider" 330 int "SDHC clock divider"
331 default 1 if ARCH_LS1043A 331 default 1 if ARCH_LS1043A
332 default 1 if ARCH_LS1012A 332 default 1 if ARCH_LS1012A
333 default 2 333 default 2
334 help 334 help
335 This is the divider that is used to derive SDHC clock from Platform 335 This is the divider that is used to derive SDHC clock from Platform
336 clock, in another word SDHC_clk = Platform_clk / this_divider. 336 clock, in another word SDHC_clk = Platform_clk / this_divider.
337 endmenu 337 endmenu
338 338
339 config RESV_RAM 339 config RESV_RAM
340 bool 340 bool
341 help 341 help
342 Reserve memory from the top, tracked by gd->arch.resv_ram. This 342 Reserve memory from the top, tracked by gd->arch.resv_ram. This
343 reserved RAM can be used by special driver that resides in memory 343 reserved RAM can be used by special driver that resides in memory
344 after U-Boot exits. It's up to implementation to allocate and allow 344 after U-Boot exits. It's up to implementation to allocate and allow
345 access to this reserved memory. For example, the reserved RAM can 345 access to this reserved memory. For example, the reserved RAM can
346 be at the high end of physical memory. The reserve RAM may be 346 be at the high end of physical memory. The reserve RAM may be
347 excluded from memory bank(s) passed to OS, or marked as reserved. 347 excluded from memory bank(s) passed to OS, or marked as reserved.
348 348
349 config SYS_FSL_ERRATUM_A008336 349 config SYS_FSL_ERRATUM_A008336
350 bool 350 bool
351 351
352 config SYS_FSL_ERRATUM_A008514 352 config SYS_FSL_ERRATUM_A008514
353 bool 353 bool
354 354
355 config SYS_FSL_ERRATUM_A008585 355 config SYS_FSL_ERRATUM_A008585
356 bool 356 bool
357 357
358 config SYS_FSL_ERRATUM_A008850 358 config SYS_FSL_ERRATUM_A008850
359 bool 359 bool
360 360
361 config SYS_FSL_ERRATUM_A009203 361 config SYS_FSL_ERRATUM_A009203
362 bool 362 bool
363 363
364 config SYS_FSL_ERRATUM_A009635 364 config SYS_FSL_ERRATUM_A009635
365 bool 365 bool
366 366
367 config SYS_FSL_ERRATUM_A009660 367 config SYS_FSL_ERRATUM_A009660
368 bool 368 bool
369 369
370 config SYS_FSL_ERRATUM_A009929 370 config SYS_FSL_ERRATUM_A009929
371 bool 371 bool
372 372
373 config SYS_MC_RSV_MEM_ALIGN 373 config SYS_MC_RSV_MEM_ALIGN
374 hex "Management Complex reserved memory alignment" 374 hex "Management Complex reserved memory alignment"
375 depends on RESV_RAM 375 depends on RESV_RAM
376 default 0x20000000 376 default 0x20000000
377 help 377 help
378 Reserved memory needs to be aligned for MC to use. Default value 378 Reserved memory needs to be aligned for MC to use. Default value
379 is 512MB. 379 is 512MB.
380 380
board/freescale/ls2080aqds/README
Diff comments   View file @ f5bf23d
1 Overview 1 Overview
2 -------- 2 --------
3 The LS2080A Development System (QDS) is a high-performance computing, 3 The LS2080A Development System (QDS) is a high-performance computing,
4 evaluation, and development platform that supports the QorIQ LS2080A 4 evaluation, and development platform that supports the QorIQ LS2080A
5 and LS2088A Layerscape Architecture processor. The LS2080AQDS provides 5 and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
6 validation and SW development platform for the Freescale LS2080A, LS2088A 6 validation and SW development platform for the Freescale LS2080A, LS2088A
7 processor series, with a complete debugging environment. 7 processor series, with a complete debugging environment.
8 8
9 LS2080A, LS2088A SoC Overview 9 LS2080A, LS2088A SoC Overview
10 -------------------- 10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, 11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
12 LS2088A SoC overview. 12 LS2088A SoC overview.
13 13
14 LS2080AQDS board Overview 14 LS2080AQDS board Overview
15 ----------------------- 15 -----------------------
16 - SERDES Connections, 16 lanes supporting: 16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0 17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5 18 - SGMII, SGMII 2.5
19 - QSGMII 19 - QSGMII
20 - SATA 3.0 20 - SATA 3.0
21 - XAUI 21 - XAUI
22 - XFI 22 - XFI
23 - DDR Controller 23 - DDR Controller
24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four 24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
25 chip-selects and two DIMM connectors. Support is up to 2133MT/s. 25 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects 26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
27 and two DIMM connectors. Support is up to 1600MT/s. 27 and two DIMM connectors. Support is up to 1600MT/s.
28 -IFC/Local Bus 28 -IFC/Local Bus
29 - IFC rev. 2.0 implementation supporting Little Endian connection scheme. 29 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
30 - One in-socket 128 MB NOR flash 16-bit data bus 30 - One in-socket 128 MB NOR flash 16-bit data bus
31 - One 512 MB NAND flash with ECC support 31 - One 512 MB NAND flash with ECC support
32 - IFC Test Port 32 - IFC Test Port
33 - PromJet Port 33 - PromJet Port
34 - FPGA connection 34 - FPGA connection
35 - USB 3.0 35 - USB 3.0
36 - Two high speed USB 3.0 ports 36 - Two high speed USB 3.0 ports
37 - First USB 3.0 port configured as Host with Type-A connector 37 - First USB 3.0 port configured as Host with Type-A connector
38 - Second USB 3.0 port configured as OTG with micro-AB connector 38 - Second USB 3.0 port configured as OTG with micro-AB connector
39 - SDHC: PCIe x1 Right Angle connector for supporting following cards 39 - SDHC: PCIe x1 Right Angle connector for supporting following cards
40 - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only 40 - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
41 - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only 41 - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
42 - 4-bit eMMC Card Rev 4.4 (1.8V only) 42 - 4-bit eMMC Card Rev 4.4 (1.8V only)
43 - 8-bit eMMC Card Rev 4.5 (1.8V only) 43 - 8-bit eMMC Card Rev 4.5 (1.8V only)
44 - SD Card Rev 2.0 and Rev 3.0 44 - SD Card Rev 2.0 and Rev 3.0
45 - DSPI: 3 high-speed flash Memory for storage 45 - DSPI: 3 high-speed flash Memory for storage
46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) 46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
47 - 8 MB high-speed flash Memory (up to 104 MHz) 47 - 8 MB high-speed flash Memory (up to 104 MHz)
48 - 512 MB low-speed flash Memory (up to 40 MHz) 48 - 512 MB low-speed flash Memory (up to 40 MHz)
49 - QSPI: via NAND/QSPI Card 49 - QSPI: via NAND/QSPI Card
50 - 4 I2C controllers 50 - 4 I2C controllers
51 - Two SATA onboard connectors 51 - Two SATA onboard connectors
52 - UART 52 - UART
53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s 53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
54 - Two DB9 D-Type connectors supporting one Serial port each 54 - Two DB9 D-Type connectors supporting one Serial port each
55 - ARM JTAG support 55 - ARM JTAG support
56 56
57 Memory map from core's view 57 Memory map from core's view
58 ---------------------------- 58 ----------------------------
59 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom 59 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
60 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR 60 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
61 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM 61 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
62 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 62 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
63 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 63 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
64 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 64 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
65 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 65 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
66 66
67 Other addresses are either reserved, or not used directly by U-Boot. 67 Other addresses are either reserved, or not used directly by U-Boot.
68 This list should be updated when more addresses are used. 68 This list should be updated when more addresses are used.
69 69
70 IFC region map from core's view 70 IFC region map from core's view
71 ------------------------------- 71 -------------------------------
72 During boot i.e. IFC Region #1:- 72 During boot i.e. IFC Region #1:-
73 0x30000000 - 0x37ffffff : 128MB : NOR flash 73 0x30000000 - 0x37ffffff : 128MB : NOR flash
74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
75 0x3C000000 - 0x40000000 : 64MB : FPGA etc 75 0x3C000000 - 0x40000000 : 64MB : FPGA etc
76 76
77 After relocate to DDR i.e. IFC Region #2:- 77 After relocate to DDR i.e. IFC Region #2:-
78 0x5_1000_0000..0x5_1fff_ffff Memory Hole 78 0x5_1000_0000..0x5_1fff_ffff Memory Hole
79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
80 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 80 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
81 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 81 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
82 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 82 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
83 83
84 Booting Options 84 Booting Options
85 --------------- 85 ---------------
86 a) Promjet Boot 86 a) Promjet Boot
87 b) NOR boot 87 b) NOR boot
88 c) NAND boot 88 c) NAND boot
89 d) SD boot 89 d) SD boot
90 e) QSPI boot 90 e) QSPI boot
91 91
92 Memory map for NOR boot
93 -------------------------
94 Image Flash Offset
95 RCW+PBI 0x00000000
96 Boot firmware (U-Boot) 0x00100000
97 Boot firmware Environment 0x00300000
98 PPA firmware 0x00400000
99 DPAA2 MC 0x00A00000
100 DPAA2 DPL 0x00D00000
101 DPAA2 DPC 0x00E00000
102 Kernel.itb 0x01000000
103
92 Environment Variables 104 Environment Variables
93 --------------------- 105 ---------------------
94 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined 106 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
95 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. 107 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
96 108
97 - mcmemsize: MC DRAM block size. If this variable is not defined 109 - mcmemsize: MC DRAM block size. If this variable is not defined
98 the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. 110 the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
99 111
100 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) 112 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
101 ------------------------------------------------------------------- 113 -------------------------------------------------------------------
102 One needs to use appropriate bootargs to boot Linux flavors which do 114 One needs to use appropriate bootargs to boot Linux flavors which do
103 not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown 115 not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
104 below: 116 below:
105 117
106 => setenv bootargs 'console=ttyS1,115200 root=/dev/ram 118 => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
107 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m 119 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
108 hugepages=16 mem=2048M' 120 hugepages=16 mem=2048M'
109 121
110 122
111 X-QSGMII-16PORT riser card 123 X-QSGMII-16PORT riser card
112 ---------------------------- 124 ----------------------------
113 The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes 125 The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
114 interfaces implemented in PCIe form factor board. 126 interfaces implemented in PCIe form factor board.
115 It supports following: 127 It supports following:
116 - Card can operate with up to 4 QSGMII lane simultaneously 128 - Card can operate with up to 4 QSGMII lane simultaneously
117 - Card can operate with up to 8 SGMII lane simultaneously 129 - Card can operate with up to 8 SGMII lane simultaneously
118 130
119 Supported card configuration 131 Supported card configuration
120 - CSEL : ON ON ON ON 132 - CSEL : ON ON ON ON
121 - MSEL1 : ON ON ON ON OFF OFF OFF OFF 133 - MSEL1 : ON ON ON ON OFF OFF OFF OFF
122 - MSEL2 : OFF OFF OFF OFF ON ON ON ON 134 - MSEL2 : OFF OFF OFF OFF ON ON ON ON
123 135
124 To enable this card: modify hwconfig to add "xqsgmii" variable. 136 To enable this card: modify hwconfig to add "xqsgmii" variable.
125 137
126 Supported PHY addresses during SGMII: 138 Supported PHY addresses during SGMII:
127 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 139 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
128 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 140 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
129 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 141 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
130 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 142 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
131 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 143 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
132 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 144 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
133 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 145 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
134 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 146 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
135 147
136 Mapping DPMACx to PHY during SGMII 148 Mapping DPMACx to PHY during SGMII
137 DPMAC1 -> PHY1-P0 149 DPMAC1 -> PHY1-P0
138 DPMAC2 -> PHY2-P0 150 DPMAC2 -> PHY2-P0
139 DPMAC3 -> PHY3-P0 151 DPMAC3 -> PHY3-P0
140 DPMAC4 -> PHY4-P0 152 DPMAC4 -> PHY4-P0
141 DPMAC5 -> PHY3-P2 153 DPMAC5 -> PHY3-P2
142 DPMAC6 -> PHY1-P2 154 DPMAC6 -> PHY1-P2
143 DPMAC7 -> PHY4-P1 155 DPMAC7 -> PHY4-P1
144 DPMAC8 -> PHY2-P2 156 DPMAC8 -> PHY2-P2
145 DPMAC9 -> PHY1-P0 157 DPMAC9 -> PHY1-P0
146 DPMAC10 -> PHY2-P0 158 DPMAC10 -> PHY2-P0
147 DPMAC11 -> PHY3-P0 159 DPMAC11 -> PHY3-P0
148 DPMAC12 -> PHY4-P0 160 DPMAC12 -> PHY4-P0
149 DPMAC13 -> PHY3-P2 161 DPMAC13 -> PHY3-P2
150 DPMAC14 -> PHY1-P2 162 DPMAC14 -> PHY1-P2
151 DPMAC15 -> PHY4-P1 163 DPMAC15 -> PHY4-P1
152 DPMAC16 -> PHY2-P2 164 DPMAC16 -> PHY2-P2
153 165
154 166
155 Supported PHY address during QSGMII 167 Supported PHY address during QSGMII
156 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 168 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
157 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 169 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
158 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 170 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
159 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 171 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
160 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 172 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
161 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 173 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
162 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 174 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
163 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 175 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
164 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 176 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
165 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 177 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
166 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 178 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
167 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 179 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
168 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 180 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
169 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 181 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
170 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 182 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
171 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 183 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
172 184
173 Mapping DPMACx to PHY during QSGMII 185 Mapping DPMACx to PHY during QSGMII
174 DPMAC1 -> PHY1-P3 186 DPMAC1 -> PHY1-P3
175 DPMAC2 -> PHY1-P2 187 DPMAC2 -> PHY1-P2
176 DPMAC3 -> PHY1-P1 188 DPMAC3 -> PHY1-P1
177 DPMAC4 -> PHY1-P0 189 DPMAC4 -> PHY1-P0
178 DPMAC5 -> PHY2-P3 190 DPMAC5 -> PHY2-P3
179 DPMAC6 -> PHY2-P2 191 DPMAC6 -> PHY2-P2
180 DPMAC7 -> PHY2-P1 192 DPMAC7 -> PHY2-P1
181 DPMAC8 -> PHY2-P0 193 DPMAC8 -> PHY2-P0
182 DPMAC9 -> PHY3-P0 194 DPMAC9 -> PHY3-P0
183 DPMAC10 -> PHY3-P1 195 DPMAC10 -> PHY3-P1
184 DPMAC11 -> PHY3-P2 196 DPMAC11 -> PHY3-P2
185 DPMAC12 -> PHY3-P3 197 DPMAC12 -> PHY3-P3
186 DPMAC13 -> PHY4-P0 198 DPMAC13 -> PHY4-P0
187 DPMAC14 -> PHY4-P1 199 DPMAC14 -> PHY4-P1
188 DPMAC15 -> PHY4-P2 200 DPMAC15 -> PHY4-P2
189 DPMAC16 -> PHY4-P3 201 DPMAC16 -> PHY4-P3
190 202
191 203
board/freescale/ls2080ardb/README
Diff comments   View file @ f5bf23d
1 Overview 1 Overview
2 -------- 2 --------
3 The LS2080A Reference Design (RDB) is a high-performance computing, 3 The LS2080A Reference Design (RDB) is a high-performance computing,
4 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A 4 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
5 Layerscape Architecture processor. 5 Layerscape Architecture processor.
6 6
7 The LS2081A Reference Design (RDB) is a high-performance computing, 7 The LS2081A Reference Design (RDB) is a high-performance computing,
8 evaluation, and development platform that supports the QorIQ LS2081A 8 evaluation, and development platform that supports the QorIQ LS2081A
9 Layerscape Architecture processor.More details in below sections 9 Layerscape Architecture processor.More details in below sections
10 10
11 LS2080A, LS2088A, LS2081A SoC Overview 11 LS2080A, LS2088A, LS2081A SoC Overview
12 -------------------------------------- 12 --------------------------------------
13 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, 13 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
14 LS2081A, LS2088A SoC overview. 14 LS2081A, LS2088A SoC overview.
15 15
16 LS2080ARDB board Overview 16 LS2080ARDB board Overview
17 ----------------------- 17 -----------------------
18 - SERDES Connections, 16 lanes supporting: 18 - SERDES Connections, 16 lanes supporting:
19 - PCI Express - 3.0 19 - PCI Express - 3.0
20 - SATA 3.0 20 - SATA 3.0
21 - XFI 21 - XFI
22 - DDR Controller 22 - DDR Controller
23 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four 23 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
24 chip-selects and two DIMM connectors. Support is up to 2133MT/s. 24 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
25 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects 25 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
26 and two DIMM connectors. Support is up to 1600MT/s. 26 and two DIMM connectors. Support is up to 1600MT/s.
27 -IFC/Local Bus 27 -IFC/Local Bus
28 - IFC rev. 2.0 implementation supporting Little Endian connection scheme. 28 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
29 - 128 MB NOR flash 16-bit data bus 29 - 128 MB NOR flash 16-bit data bus
30 - One 2 GB NAND flash with ECC support 30 - One 2 GB NAND flash with ECC support
31 - CPLD connection 31 - CPLD connection
32 - USB 3.0 32 - USB 3.0
33 - Two high speed USB 3.0 ports 33 - Two high speed USB 3.0 ports
34 - First USB 3.0 port configured as Host with Type-A connector 34 - First USB 3.0 port configured as Host with Type-A connector
35 - Second USB 3.0 port configured as OTG with micro-AB connector 35 - Second USB 3.0 port configured as OTG with micro-AB connector
36 - SDHC adapter 36 - SDHC adapter
37 - SD Card Rev 2.0 and Rev 3.0 37 - SD Card Rev 2.0 and Rev 3.0
38 - DSPI 38 - DSPI
39 - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz) 39 - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
40 - 4 I2C controllers 40 - 4 I2C controllers
41 - Two SATA onboard connectors 41 - Two SATA onboard connectors
42 - UART 42 - UART
43 - ARM JTAG support 43 - ARM JTAG support
44 44
45 LS2081ARDB board Overview 45 LS2081ARDB board Overview
46 ------------------------- 46 -------------------------
47 LS2081ARDB board is similar to LS2080ARDB board 47 LS2081ARDB board is similar to LS2080ARDB board
48 with few differences like 48 with few differences like
49 - Hosts LS2081A SoC 49 - Hosts LS2081A SoC
50 - Default boot source is QSPI-boot 50 - Default boot source is QSPI-boot
51 - Does not have IFC interface 51 - Does not have IFC interface
52 - RTC and QSPI flash devices are different 52 - RTC and QSPI flash devices are different
53 - Provides QIXIS access via I2C 53 - Provides QIXIS access via I2C
54 54
55 Memory map from core's view 55 Memory map from core's view
56 ---------------------------- 56 ----------------------------
57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom 57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR 58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM 59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
60 0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1 60 0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
64 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 64 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
65 65
66 Other addresses are either reserved, or not used directly by U-Boot. 66 Other addresses are either reserved, or not used directly by U-Boot.
67 This list should be updated when more addresses are used. 67 This list should be updated when more addresses are used.
68 68
69 IFC region map from core's view 69 IFC region map from core's view
70 ------------------------------- 70 -------------------------------
71 During boot i.e. IFC Region #1:- 71 During boot i.e. IFC Region #1:-
72 0x30000000 - 0x37ffffff : 128MB : NOR flash 72 0x30000000 - 0x37ffffff : 128MB : NOR flash
73 0x3C000000 - 0x40000000 : 64MB : CPLD 73 0x3C000000 - 0x40000000 : 64MB : CPLD
74 74
75 After relocate to DDR i.e. IFC Region #2:- 75 After relocate to DDR i.e. IFC Region #2:-
76 0x5_1000_0000..0x5_1fff_ffff Memory Hole 76 0x5_1000_0000..0x5_1fff_ffff Memory Hole
77 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB) 77 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
78 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 78 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
79 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 79 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
80 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 80 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
81 81
82 Booting Options 82 Booting Options
83 --------------- 83 ---------------
84 a) NOR boot 84 a) NOR boot
85 b) NAND boot 85 b) NAND boot
86 c) QSPI boot 86 c) QSPI boot
87 87
88 Memory map for NOR boot
89 -------------------------
90 Image Flash Offset
91 RCW+PBI 0x00000000
92 Boot firmware (U-Boot) 0x00100000
93 Boot firmware Environment 0x00300000
94 PPA firmware 0x00400000
95 Cortina PHY firmware 0x00980000
96 DPAA2 MC 0x00A00000
97 DPAA2 DPL 0x00D00000
98 DPAA2 DPC 0x00E00000
99 Kernel.itb 0x01000000
100
88 cfg_rcw_src switches needs to be changed for booting from different option. 101 cfg_rcw_src switches needs to be changed for booting from different option.
89 Refer to board documentation for correct switch setting. 102 Refer to board documentation for correct switch setting.
90 103
91 QSPI boot details 104 QSPI boot details
92 =================== 105 ===================
93 Supported only for 106 Supported only for
94 LS2088ARDB RevF board with LS2088A SoC. 107 LS2088ARDB RevF board with LS2088A SoC.
95 108
96 Images needs to be copied to QSPI flash 109 Images needs to be copied to QSPI flash
97 as per memory map given below. 110 as per memory map given below.
98 111
99 Memory map for QSPI flash 112 Memory map for QSPI flash
100 ------------------------- 113 -------------------------
101 Image Flash Offset 114 Image Flash Offset
102 RCW+PBI 0x00000000 115 RCW+PBI 0x00000000
103 Boot firmware (U-Boot) 0x00100000 116 Boot firmware (U-Boot) 0x00100000
104 Boot firmware Environment 0x00300000 117 Boot firmware Environment 0x00300000
105 PPA firmware 0x00400000 118 PPA firmware 0x00400000
106 Cortina PHY firmware 0x00980000 119 Cortina PHY firmware 0x00980000
107 DPAA2 MC 0x00A00000 120 DPAA2 MC 0x00A00000
108 DPAA2 DPL 0x00D00000 121 DPAA2 DPL 0x00D00000
109 DPAA2 DPC 0x00E00000 122 DPAA2 DPC 0x00E00000
110 Kernel.itb 0x01000000 123 Kernel.itb 0x01000000
111 124
112 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) 125 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
113 ------------------------------------------------------------------- 126 -------------------------------------------------------------------
114 One needs to use appropriate bootargs to boot Linux flavors which do 127 One needs to use appropriate bootargs to boot Linux flavors which do
115 not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown 128 not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
116 below: 129 below:
117 130
118 => setenv bootargs 'console=ttyS1,115200 root=/dev/ram 131 => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
119 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m 132 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
120 hugepages=16 mem=2048M' 133 hugepages=16 mem=2048M'
121 134
122 135
include/configs/ls2080a_common.h
Diff comments   View file @ f5bf23d
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * Copyright (C) 2014 Freescale Semiconductor 3 * Copyright (C) 2014 Freescale Semiconductor
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __LS2_COMMON_H 8 #ifndef __LS2_COMMON_H
9 #define __LS2_COMMON_H 9 #define __LS2_COMMON_H
10 10
11 #define CONFIG_REMAKE_ELF 11 #define CONFIG_REMAKE_ELF
12 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LAYERSCAPE
13 #define CONFIG_MP 13 #define CONFIG_MP
14 #define CONFIG_GICV3 14 #define CONFIG_GICV3
15 #define CONFIG_FSL_TZPC_BP147 15 #define CONFIG_FSL_TZPC_BP147
16 16
17 #include <asm/arch/stream_id_lsch3.h> 17 #include <asm/arch/stream_id_lsch3.h>
18 #include <asm/arch/config.h> 18 #include <asm/arch/config.h>
19 19
20 /* Link Definitions */ 20 /* Link Definitions */
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
22 22
23 /* We need architecture specific misc initializations */ 23 /* We need architecture specific misc initializations */
24 24
25 /* Link Definitions */ 25 /* Link Definitions */
26 #ifndef CONFIG_QSPI_BOOT 26 #ifndef CONFIG_QSPI_BOOT
27 #ifdef CONFIG_SPL 27 #ifdef CONFIG_SPL
28 #define CONFIG_SYS_TEXT_BASE 0x80400000 28 #define CONFIG_SYS_TEXT_BASE 0x80400000
29 #else 29 #else
30 #define CONFIG_SYS_TEXT_BASE 0x30100000 30 #define CONFIG_SYS_TEXT_BASE 0x30100000
31 #endif 31 #endif
32 #else 32 #else
33 #define CONFIG_SYS_TEXT_BASE 0x20100000 33 #define CONFIG_SYS_TEXT_BASE 0x20100000
34 #define CONFIG_ENV_IS_IN_SPI_FLASH 34 #define CONFIG_ENV_IS_IN_SPI_FLASH
35 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 35 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
36 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 36 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
37 #define CONFIG_ENV_SECT_SIZE 0x10000 37 #define CONFIG_ENV_SECT_SIZE 0x10000
38 #endif 38 #endif
39 39
40 #define CONFIG_SUPPORT_RAW_INITRD 40 #define CONFIG_SUPPORT_RAW_INITRD
41 41
42 #define CONFIG_SKIP_LOWLEVEL_INIT 42 #define CONFIG_SKIP_LOWLEVEL_INIT
43 43
44 #ifndef CONFIG_SPL 44 #ifndef CONFIG_SPL
45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #endif 46 #endif
47 #ifndef CONFIG_SYS_FSL_DDR4 47 #ifndef CONFIG_SYS_FSL_DDR4
48 #define CONFIG_SYS_DDR_RAW_TIMING 48 #define CONFIG_SYS_DDR_RAW_TIMING
49 #endif 49 #endif
50 50
51 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 51 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
52 52
53 #define CONFIG_VERY_BIG_RAM 53 #define CONFIG_VERY_BIG_RAM
54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
55 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 55 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
57 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 57 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
58 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 58 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
59 59
60 /* 60 /*
61 * SMP Definitinos 61 * SMP Definitinos
62 */ 62 */
63 #define CPU_RELEASE_ADDR secondary_boot_func 63 #define CPU_RELEASE_ADDR secondary_boot_func
64 64
65 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 65 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
66 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 66 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
67 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 67 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
68 /* 68 /*
69 * DDR controller use 0 as the base address for binding. 69 * DDR controller use 0 as the base address for binding.
70 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 70 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
71 */ 71 */
72 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 72 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
73 #define CONFIG_DP_DDR_CTRL 2 73 #define CONFIG_DP_DDR_CTRL 2
74 #define CONFIG_DP_DDR_NUM_CTRLS 1 74 #define CONFIG_DP_DDR_NUM_CTRLS 1
75 #endif 75 #endif
76 76
77 /* Generic Timer Definitions */ 77 /* Generic Timer Definitions */
78 /* 78 /*
79 * This is not an accurate number. It is used in start.S. The frequency 79 * This is not an accurate number. It is used in start.S. The frequency
80 * will be udpated later when get_bus_freq(0) is available. 80 * will be udpated later when get_bus_freq(0) is available.
81 */ 81 */
82 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 82 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
83 83
84 /* Size of malloc() pool */ 84 /* Size of malloc() pool */
85 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 85 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
86 86
87 /* I2C */ 87 /* I2C */
88 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_I2C_MXC 89 #define CONFIG_SYS_I2C_MXC
90 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 90 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
91 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 91 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
92 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 92 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
93 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 93 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
94 94
95 /* Serial Port */ 95 /* Serial Port */
96 #define CONFIG_CONS_INDEX 1 96 #define CONFIG_CONS_INDEX 1
97 #define CONFIG_SYS_NS16550_SERIAL 97 #define CONFIG_SYS_NS16550_SERIAL
98 #define CONFIG_SYS_NS16550_REG_SIZE 1 98 #define CONFIG_SYS_NS16550_REG_SIZE 1
99 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 99 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
100 100
101 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 101 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
102 102
103 /* IFC */ 103 /* IFC */
104 #define CONFIG_FSL_IFC 104 #define CONFIG_FSL_IFC
105 105
106 /* 106 /*
107 * During booting, IFC is mapped at the region of 0x30000000. 107 * During booting, IFC is mapped at the region of 0x30000000.
108 * But this region is limited to 256MB. To accommodate NOR, promjet 108 * But this region is limited to 256MB. To accommodate NOR, promjet
109 * and FPGA. This region is divided as below: 109 * and FPGA. This region is divided as below:
110 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 110 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
111 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 111 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
112 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 112 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
113 * 113 *
114 * To accommodate bigger NOR flash and other devices, we will map IFC 114 * To accommodate bigger NOR flash and other devices, we will map IFC
115 * chip selects to as below: 115 * chip selects to as below:
116 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 116 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
117 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 117 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
118 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 118 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
119 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 119 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
120 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 120 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
121 * 121 *
122 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 122 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
123 * CONFIG_SYS_FLASH_BASE has the final address (core view) 123 * CONFIG_SYS_FLASH_BASE has the final address (core view)
124 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 124 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
125 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 125 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
126 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 126 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
127 */ 127 */
128 128
129 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 129 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
130 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 130 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
131 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 131 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
132 132
133 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 133 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
134 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 134 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
135 135
136 #ifndef __ASSEMBLY__ 136 #ifndef __ASSEMBLY__
137 unsigned long long get_qixis_addr(void); 137 unsigned long long get_qixis_addr(void);
138 #endif 138 #endif
139 #define QIXIS_BASE get_qixis_addr() 139 #define QIXIS_BASE get_qixis_addr()
140 #define QIXIS_BASE_PHYS 0x20000000 140 #define QIXIS_BASE_PHYS 0x20000000
141 #define QIXIS_BASE_PHYS_EARLY 0xC000000 141 #define QIXIS_BASE_PHYS_EARLY 0xC000000
142 #define QIXIS_STAT_PRES1 0xb 142 #define QIXIS_STAT_PRES1 0xb
143 #define QIXIS_SDID_MASK 0x07 143 #define QIXIS_SDID_MASK 0x07
144 #define QIXIS_ESDHC_NO_ADAPTER 0x7 144 #define QIXIS_ESDHC_NO_ADAPTER 0x7
145 145
146 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 146 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
147 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 147 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
148 148
149 /* MC firmware */ 149 /* MC firmware */
150 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 150 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
151 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 151 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
152 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 152 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
153 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 153 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
154 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 154 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
155 /* For LS2085A */ 155 /* For LS2085A */
156 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 156 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
157 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 157 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
158 158
159 /* 159 /*
160 * Carve out a DDR region which will not be used by u-boot/Linux 160 * Carve out a DDR region which will not be used by u-boot/Linux
161 * 161 *
162 * It will be used by MC and Debug Server. The MC region must be 162 * It will be used by MC and Debug Server. The MC region must be
163 * 512MB aligned, so the min size to hide is 512MB. 163 * 512MB aligned, so the min size to hide is 512MB.
164 */ 164 */
165 #ifdef CONFIG_FSL_MC_ENET 165 #ifdef CONFIG_FSL_MC_ENET
166 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 166 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
167 #endif 167 #endif
168 168
169 /* Command line configuration */ 169 /* Command line configuration */
170 #define CONFIG_CMD_ENV 170 #define CONFIG_CMD_ENV
171 171
172 /* Miscellaneous configurable options */ 172 /* Miscellaneous configurable options */
173 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 173 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
174 174
175 /* Physical Memory Map */ 175 /* Physical Memory Map */
176 /* fixme: these need to be checked against the board */ 176 /* fixme: these need to be checked against the board */
177 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 177 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
178 178
179 #define CONFIG_NR_DRAM_BANKS 3 179 #define CONFIG_NR_DRAM_BANKS 3
180 180
181 #define CONFIG_HWCONFIG 181 #define CONFIG_HWCONFIG
182 #define HWCONFIG_BUFFER_SIZE 128 182 #define HWCONFIG_BUFFER_SIZE 128
183 183
184 /* Allow to overwrite serial and ethaddr */ 184 /* Allow to overwrite serial and ethaddr */
185 #define CONFIG_ENV_OVERWRITE 185 #define CONFIG_ENV_OVERWRITE
186 186
187 /* Initial environment variables */ 187 /* Initial environment variables */
188 #define CONFIG_EXTRA_ENV_SETTINGS \ 188 #define CONFIG_EXTRA_ENV_SETTINGS \
189 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 189 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
190 "loadaddr=0x80100000\0" \ 190 "loadaddr=0x80100000\0" \
191 "kernel_addr=0x100000\0" \ 191 "kernel_addr=0x100000\0" \
192 "ramdisk_addr=0x800000\0" \ 192 "ramdisk_addr=0x800000\0" \
193 "ramdisk_size=0x2000000\0" \ 193 "ramdisk_size=0x2000000\0" \
194 "fdt_high=0xa0000000\0" \ 194 "fdt_high=0xa0000000\0" \
195 "initrd_high=0xffffffffffffffff\0" \ 195 "initrd_high=0xffffffffffffffff\0" \
196 "kernel_start=0x581200000\0" \ 196 "kernel_start=0x581000000\0" \
197 "kernel_load=0xa0000000\0" \ 197 "kernel_load=0xa0000000\0" \
198 "kernel_size=0x2800000\0" \ 198 "kernel_size=0x2800000\0" \
199 "console=ttyAMA0,38400n8\0" \ 199 "console=ttyAMA0,38400n8\0" \
200 "mcinitcmd=fsl_mc start mc 0x580300000" \ 200 "mcinitcmd=fsl_mc start mc 0x580a00000" \
201 " 0x580800000 \0" 201 " 0x580e00000 \0"
202 202
203 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 203 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
204 "earlycon=uart8250,mmio,0x21c0500 " \ 204 "earlycon=uart8250,mmio,0x21c0500 " \
205 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 205 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
206 " hugepagesz=2m hugepages=256" 206 " hugepagesz=2m hugepages=256"
207 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ 207 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
208 " cp.b $kernel_start $kernel_load" \ 208 " cp.b $kernel_start $kernel_load" \
209 " $kernel_size && bootm $kernel_load" 209 " $kernel_size && bootm $kernel_load"
210 210
211 /* Monitor Command Prompt */ 211 /* Monitor Command Prompt */
212 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 212 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
214 sizeof(CONFIG_SYS_PROMPT) + 16) 214 sizeof(CONFIG_SYS_PROMPT) + 16)
215 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 215 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
216 #define CONFIG_SYS_LONGHELP 216 #define CONFIG_SYS_LONGHELP
217 #define CONFIG_CMDLINE_EDITING 1 217 #define CONFIG_CMDLINE_EDITING 1
218 #define CONFIG_AUTO_COMPLETE 218 #define CONFIG_AUTO_COMPLETE
219 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 219 #define CONFIG_SYS_MAXARGS 64 /* max command args */
220 220
221 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 221 #define CONFIG_PANIC_HANG /* do not reset board on panic */
222 222
223 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 223 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
224 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 224 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
225 #define CONFIG_SPL_FRAMEWORK 225 #define CONFIG_SPL_FRAMEWORK
226 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 226 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
227 #define CONFIG_SPL_MAX_SIZE 0x16000 227 #define CONFIG_SPL_MAX_SIZE 0x16000
228 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 228 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
229 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 229 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
230 #define CONFIG_SPL_TEXT_BASE 0x1800a000 230 #define CONFIG_SPL_TEXT_BASE 0x1800a000
231 231
232 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 232 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
233 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 233 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
234 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 234 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
235 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 235 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
236 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) 236 #define CONFIG_SYS_MONITOR_LEN (640 * 1024)
237 237
238 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 238 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
239 239
240 /* Hash command with SHA acceleration supported in hardware */ 240 /* Hash command with SHA acceleration supported in hardware */
241 #ifdef CONFIG_FSL_CAAM 241 #ifdef CONFIG_FSL_CAAM
242 #define CONFIG_CMD_HASH 242 #define CONFIG_CMD_HASH
243 #define CONFIG_SHA_HW_ACCEL 243 #define CONFIG_SHA_HW_ACCEL
244 #endif 244 #endif
245 245
246 #endif /* __LS2_COMMON_H */ 246 #endif /* __LS2_COMMON_H */
247 247
include/configs/ls2080aqds.h
Diff comments   View file @ f5bf23d
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * Copyright 2015 Freescale Semiconductor 3 * Copyright 2015 Freescale Semiconductor
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __LS2_QDS_H 8 #ifndef __LS2_QDS_H
9 #define __LS2_QDS_H 9 #define __LS2_QDS_H
10 10
11 #include "ls2080a_common.h" 11 #include "ls2080a_common.h"
12 12
13 #ifndef __ASSEMBLY__ 13 #ifndef __ASSEMBLY__
14 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_sys_clk(void);
15 unsigned long get_board_ddr_clk(void); 15 unsigned long get_board_ddr_clk(void);
16 #endif 16 #endif
17 17
18 #ifdef CONFIG_FSL_QSPI 18 #ifdef CONFIG_FSL_QSPI
19 #undef CONFIG_CMD_IMLS 19 #undef CONFIG_CMD_IMLS
20 #define CONFIG_QIXIS_I2C_ACCESS 20 #define CONFIG_QIXIS_I2C_ACCESS
21 #define CONFIG_SYS_I2C_EARLY_INIT 21 #define CONFIG_SYS_I2C_EARLY_INIT
22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #endif 23 #endif
24 24
25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
29 29
30 #define CONFIG_DDR_SPD 30 #define CONFIG_DDR_SPD
31 #define CONFIG_DDR_ECC 31 #define CONFIG_DDR_ECC
32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS1 0x51 34 #define SPD_EEPROM_ADDRESS1 0x51
35 #define SPD_EEPROM_ADDRESS2 0x52 35 #define SPD_EEPROM_ADDRESS2 0x52
36 #define SPD_EEPROM_ADDRESS3 0x53 36 #define SPD_EEPROM_ADDRESS3 0x53
37 #define SPD_EEPROM_ADDRESS4 0x54 37 #define SPD_EEPROM_ADDRESS4 0x54
38 #define SPD_EEPROM_ADDRESS5 0x55 38 #define SPD_EEPROM_ADDRESS5 0x55
39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
46 #endif 46 #endif
47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
48 48
49 /* SATA */ 49 /* SATA */
50 #define CONFIG_LIBATA 50 #define CONFIG_LIBATA
51 #define CONFIG_SCSI_AHCI 51 #define CONFIG_SCSI_AHCI
52 #define CONFIG_SCSI_AHCI_PLAT 52 #define CONFIG_SCSI_AHCI_PLAT
53 #define CONFIG_SCSI 53 #define CONFIG_SCSI
54 54
55 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 55 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
56 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 56 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
57 57
58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
59 #define CONFIG_SYS_SCSI_MAX_LUN 1 59 #define CONFIG_SYS_SCSI_MAX_LUN 1
60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
61 CONFIG_SYS_SCSI_MAX_LUN) 61 CONFIG_SYS_SCSI_MAX_LUN)
62 62
63 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 63 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
64 64
65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
67 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 67 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
68 68
69 #define CONFIG_SYS_NOR0_CSPR \ 69 #define CONFIG_SYS_NOR0_CSPR \
70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
71 CSPR_PORT_SIZE_16 | \ 71 CSPR_PORT_SIZE_16 | \
72 CSPR_MSEL_NOR | \ 72 CSPR_MSEL_NOR | \
73 CSPR_V) 73 CSPR_V)
74 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 74 #define CONFIG_SYS_NOR0_CSPR_EARLY \
75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
76 CSPR_PORT_SIZE_16 | \ 76 CSPR_PORT_SIZE_16 | \
77 CSPR_MSEL_NOR | \ 77 CSPR_MSEL_NOR | \
78 CSPR_V) 78 CSPR_V)
79 #define CONFIG_SYS_NOR1_CSPR \ 79 #define CONFIG_SYS_NOR1_CSPR \
80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
81 CSPR_PORT_SIZE_16 | \ 81 CSPR_PORT_SIZE_16 | \
82 CSPR_MSEL_NOR | \ 82 CSPR_MSEL_NOR | \
83 CSPR_V) 83 CSPR_V)
84 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 84 #define CONFIG_SYS_NOR1_CSPR_EARLY \
85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
86 CSPR_PORT_SIZE_16 | \ 86 CSPR_PORT_SIZE_16 | \
87 CSPR_MSEL_NOR | \ 87 CSPR_MSEL_NOR | \
88 CSPR_V) 88 CSPR_V)
89 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 89 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
90 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 90 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
91 FTIM0_NOR_TEADC(0x5) | \ 91 FTIM0_NOR_TEADC(0x5) | \
92 FTIM0_NOR_TEAHC(0x5)) 92 FTIM0_NOR_TEAHC(0x5))
93 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 93 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
94 FTIM1_NOR_TRAD_NOR(0x1a) |\ 94 FTIM1_NOR_TRAD_NOR(0x1a) |\
95 FTIM1_NOR_TSEQRAD_NOR(0x13)) 95 FTIM1_NOR_TSEQRAD_NOR(0x13))
96 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 96 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
97 FTIM2_NOR_TCH(0x4) | \ 97 FTIM2_NOR_TCH(0x4) | \
98 FTIM2_NOR_TWPH(0x0E) | \ 98 FTIM2_NOR_TWPH(0x0E) | \
99 FTIM2_NOR_TWP(0x1c)) 99 FTIM2_NOR_TWP(0x1c))
100 #define CONFIG_SYS_NOR_FTIM3 0x04000000 100 #define CONFIG_SYS_NOR_FTIM3 0x04000000
101 #define CONFIG_SYS_IFC_CCR 0x01000000 101 #define CONFIG_SYS_IFC_CCR 0x01000000
102 102
103 #ifdef CONFIG_MTD_NOR_FLASH 103 #ifdef CONFIG_MTD_NOR_FLASH
104 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_FLASH_CFI_DRIVER
105 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
107 #define CONFIG_SYS_FLASH_QUIET_TEST 107 #define CONFIG_SYS_FLASH_QUIET_TEST
108 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 108 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
109 109
110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
114 114
115 #define CONFIG_SYS_FLASH_EMPTY_INFO 115 #define CONFIG_SYS_FLASH_EMPTY_INFO
116 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 116 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
117 CONFIG_SYS_FLASH_BASE + 0x40000000} 117 CONFIG_SYS_FLASH_BASE + 0x40000000}
118 #endif 118 #endif
119 119
120 #define CONFIG_NAND_FSL_IFC 120 #define CONFIG_NAND_FSL_IFC
121 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 121 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
122 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 122 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
123 123
124 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
125 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
126 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
127 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_MSEL_NAND /* MSEL = NAND */ \
128 | CSPR_V) 128 | CSPR_V)
129 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
130 130
131 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
132 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
133 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
134 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
135 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
136 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
137 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
138 138
139 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 #define CONFIG_SYS_NAND_ONFI_DETECTION
140 140
141 /* ONFI NAND Flash mode0 Timing Params */ 141 /* ONFI NAND Flash mode0 Timing Params */
142 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
143 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWP(0x18) | \
144 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWCHT(0x07) | \
145 FTIM0_NAND_TWH(0x0a)) 145 FTIM0_NAND_TWH(0x0a))
146 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
147 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TWBE(0x39) | \
148 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRR(0x0e) | \
149 FTIM1_NAND_TRP(0x18)) 149 FTIM1_NAND_TRP(0x18))
150 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
151 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TREH(0x0a) | \
152 FTIM2_NAND_TWHRE(0x1e)) 152 FTIM2_NAND_TWHRE(0x1e))
153 #define CONFIG_SYS_NAND_FTIM3 0x0 153 #define CONFIG_SYS_NAND_FTIM3 0x0
154 154
155 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
156 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_SYS_MAX_NAND_DEVICE 1
157 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 #define CONFIG_MTD_NAND_VERIFY_WRITE
158 #define CONFIG_CMD_NAND 158 #define CONFIG_CMD_NAND
159 159
160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
161 161
162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
163 #define QIXIS_LBMAP_SWITCH 0x06 163 #define QIXIS_LBMAP_SWITCH 0x06
164 #define QIXIS_LBMAP_MASK 0x0f 164 #define QIXIS_LBMAP_MASK 0x0f
165 #define QIXIS_LBMAP_SHIFT 0 165 #define QIXIS_LBMAP_SHIFT 0
166 #define QIXIS_LBMAP_DFLTBANK 0x00 166 #define QIXIS_LBMAP_DFLTBANK 0x00
167 #define QIXIS_LBMAP_ALTBANK 0x04 167 #define QIXIS_LBMAP_ALTBANK 0x04
168 #define QIXIS_LBMAP_NAND 0x09 168 #define QIXIS_LBMAP_NAND 0x09
169 #define QIXIS_LBMAP_QSPI 0x0f 169 #define QIXIS_LBMAP_QSPI 0x0f
170 #define QIXIS_RST_CTL_RESET 0x31 170 #define QIXIS_RST_CTL_RESET 0x31
171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
174 #define QIXIS_RCW_SRC_NAND 0x107 174 #define QIXIS_RCW_SRC_NAND 0x107
175 #define QIXIS_RCW_SRC_QSPI 0x62 175 #define QIXIS_RCW_SRC_QSPI 0x62
176 #define QIXIS_RST_FORCE_MEM 0x01 176 #define QIXIS_RST_FORCE_MEM 0x01
177 177
178 #define CONFIG_SYS_CSPR3_EXT (0x0) 178 #define CONFIG_SYS_CSPR3_EXT (0x0)
179 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 179 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
180 | CSPR_PORT_SIZE_8 \ 180 | CSPR_PORT_SIZE_8 \
181 | CSPR_MSEL_GPCM \ 181 | CSPR_MSEL_GPCM \
182 | CSPR_V) 182 | CSPR_V)
183 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 183 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
184 | CSPR_PORT_SIZE_8 \ 184 | CSPR_PORT_SIZE_8 \
185 | CSPR_MSEL_GPCM \ 185 | CSPR_MSEL_GPCM \
186 | CSPR_V) 186 | CSPR_V)
187 187
188 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 188 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
189 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 189 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
190 /* QIXIS Timing parameters for IFC CS3 */ 190 /* QIXIS Timing parameters for IFC CS3 */
191 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 191 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
192 FTIM0_GPCM_TEADC(0x0e) | \ 192 FTIM0_GPCM_TEADC(0x0e) | \
193 FTIM0_GPCM_TEAHC(0x0e)) 193 FTIM0_GPCM_TEAHC(0x0e))
194 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 194 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
195 FTIM1_GPCM_TRAD(0x3f)) 195 FTIM1_GPCM_TRAD(0x3f))
196 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 196 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
197 FTIM2_GPCM_TCH(0xf) | \ 197 FTIM2_GPCM_TCH(0xf) | \
198 FTIM2_GPCM_TWP(0x3E)) 198 FTIM2_GPCM_TWP(0x3E))
199 #define CONFIG_SYS_CS3_FTIM3 0x0 199 #define CONFIG_SYS_CS3_FTIM3 0x0
200 200
201 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 201 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
202 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 202 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
203 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 203 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
204 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 204 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
205 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 205 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
206 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 206 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
207 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 207 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
208 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 208 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
209 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 209 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
210 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 210 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
211 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 211 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
212 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 212 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
213 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 213 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
214 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 214 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
215 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 215 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
216 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 216 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
217 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 217 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
218 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 218 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
219 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 219 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
220 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 220 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
221 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 221 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
225 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 225 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
226 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 226 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
227 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 227 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
228 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 228 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
229 229
230 #define CONFIG_ENV_IS_IN_NAND 230 #define CONFIG_ENV_IS_IN_NAND
231 #define CONFIG_ENV_OFFSET (896 * 1024) 231 #define CONFIG_ENV_OFFSET (896 * 1024)
232 #define CONFIG_ENV_SECT_SIZE 0x20000 232 #define CONFIG_ENV_SECT_SIZE 0x20000
233 #define CONFIG_ENV_SIZE 0x2000 233 #define CONFIG_ENV_SIZE 0x2000
234 #define CONFIG_SPL_PAD_TO 0x20000 234 #define CONFIG_SPL_PAD_TO 0x20000
235 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
237 #else 237 #else
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
240 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 240 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
249 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 249 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
251 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 251 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
252 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 252 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
253 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 253 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
254 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 254 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
255 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 255 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
256 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 256 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
257 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 257 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
258 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 258 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
259 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 259 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
260 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 260 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
261 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 261 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
262 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 262 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
265 265
266 #ifndef CONFIG_QSPI_BOOT 266 #ifndef CONFIG_QSPI_BOOT
267 #define CONFIG_ENV_IS_IN_FLASH 267 #define CONFIG_ENV_IS_IN_FLASH
268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
269 #define CONFIG_ENV_SECT_SIZE 0x20000 269 #define CONFIG_ENV_SECT_SIZE 0x20000
270 #define CONFIG_ENV_SIZE 0x2000 270 #define CONFIG_ENV_SIZE 0x2000
271 #endif 271 #endif
272 #endif 272 #endif
273 273
274 /* Debug Server firmware */ 274 /* Debug Server firmware */
275 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 275 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
276 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 276 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
277 277
278 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 278 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
279 279
280 /* 280 /*
281 * I2C 281 * I2C
282 */ 282 */
283 #define I2C_MUX_PCA_ADDR 0x77 283 #define I2C_MUX_PCA_ADDR 0x77
284 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 284 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
285 285
286 /* I2C bus multiplexer */ 286 /* I2C bus multiplexer */
287 #define I2C_MUX_CH_DEFAULT 0x8 287 #define I2C_MUX_CH_DEFAULT 0x8
288 288
289 /* SPI */ 289 /* SPI */
290 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 290 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
291 #define CONFIG_SPI_FLASH 291 #define CONFIG_SPI_FLASH
292 292
293 #ifdef CONFIG_FSL_DSPI 293 #ifdef CONFIG_FSL_DSPI
294 #define CONFIG_SPI_FLASH_STMICRO 294 #define CONFIG_SPI_FLASH_STMICRO
295 #define CONFIG_SPI_FLASH_SST 295 #define CONFIG_SPI_FLASH_SST
296 #define CONFIG_SPI_FLASH_EON 296 #define CONFIG_SPI_FLASH_EON
297 #endif 297 #endif
298 298
299 #ifdef CONFIG_FSL_QSPI 299 #ifdef CONFIG_FSL_QSPI
300 #define CONFIG_SPI_FLASH_SPANSION 300 #define CONFIG_SPI_FLASH_SPANSION
301 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 301 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
302 #define FSL_QSPI_FLASH_NUM 4 302 #define FSL_QSPI_FLASH_NUM 4
303 #endif 303 #endif
304 /* 304 /*
305 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 305 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
306 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 306 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
307 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 307 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
308 */ 308 */
309 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 309 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
310 310
311 #endif 311 #endif
312 312
313 /* 313 /*
314 * MMC 314 * MMC
315 */ 315 */
316 #ifdef CONFIG_MMC 316 #ifdef CONFIG_MMC
317 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 317 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
318 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 318 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
319 #endif 319 #endif
320 320
321 /* 321 /*
322 * RTC configuration 322 * RTC configuration
323 */ 323 */
324 #define RTC 324 #define RTC
325 #define CONFIG_RTC_DS3231 1 325 #define CONFIG_RTC_DS3231 1
326 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 326 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
327 327
328 /* EEPROM */ 328 /* EEPROM */
329 #define CONFIG_ID_EEPROM 329 #define CONFIG_ID_EEPROM
330 #define CONFIG_CMD_EEPROM 330 #define CONFIG_CMD_EEPROM
331 #define CONFIG_SYS_I2C_EEPROM_NXID 331 #define CONFIG_SYS_I2C_EEPROM_NXID
332 #define CONFIG_SYS_EEPROM_BUS_NUM 0 332 #define CONFIG_SYS_EEPROM_BUS_NUM 0
333 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 333 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
337 337
338 #define CONFIG_FSL_MEMAC 338 #define CONFIG_FSL_MEMAC
339 339
340 #ifdef CONFIG_PCI 340 #ifdef CONFIG_PCI
341 #define CONFIG_PCI_SCAN_SHOW 341 #define CONFIG_PCI_SCAN_SHOW
342 #define CONFIG_CMD_PCI 342 #define CONFIG_CMD_PCI
343 #endif 343 #endif
344 344
345 /* MMC */ 345 /* MMC */
346 #ifdef CONFIG_MMC 346 #ifdef CONFIG_MMC
347 #define CONFIG_FSL_ESDHC 347 #define CONFIG_FSL_ESDHC
348 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 348 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
349 #endif 349 #endif
350 350
351 /* Initial environment variables */ 351 /* Initial environment variables */
352 #undef CONFIG_EXTRA_ENV_SETTINGS 352 #undef CONFIG_EXTRA_ENV_SETTINGS
353 #ifdef CONFIG_SECURE_BOOT 353 #ifdef CONFIG_SECURE_BOOT
354 #define CONFIG_EXTRA_ENV_SETTINGS \ 354 #define CONFIG_EXTRA_ENV_SETTINGS \
355 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 355 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
356 "loadaddr=0x80100000\0" \ 356 "loadaddr=0x80100000\0" \
357 "kernel_addr=0x100000\0" \ 357 "kernel_addr=0x100000\0" \
358 "ramdisk_addr=0x800000\0" \ 358 "ramdisk_addr=0x800000\0" \
359 "ramdisk_size=0x2000000\0" \ 359 "ramdisk_size=0x2000000\0" \
360 "fdt_high=0xa0000000\0" \ 360 "fdt_high=0xa0000000\0" \
361 "initrd_high=0xffffffffffffffff\0" \ 361 "initrd_high=0xffffffffffffffff\0" \
362 "kernel_start=0x581100000\0" \ 362 "kernel_start=0x581100000\0" \
363 "kernel_load=0xa0000000\0" \ 363 "kernel_load=0xa0000000\0" \
364 "kernel_size=0x2800000\0" \ 364 "kernel_size=0x2800000\0" \
365 "mcmemsize=0x40000000\0" \ 365 "mcmemsize=0x40000000\0" \
366 "mcinitcmd=esbc_validate 0x580c80000;" \ 366 "mcinitcmd=esbc_validate 0x580c80000;" \
367 "esbc_validate 0x580cc0000;" \ 367 "esbc_validate 0x580cc0000;" \
368 "fsl_mc start mc 0x580300000" \ 368 "fsl_mc start mc 0x580300000" \
369 " 0x580800000 \0" 369 " 0x580800000 \0"
370 #else 370 #else
371 #define CONFIG_EXTRA_ENV_SETTINGS \ 371 #define CONFIG_EXTRA_ENV_SETTINGS \
372 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 372 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
373 "loadaddr=0x80100000\0" \ 373 "loadaddr=0x80100000\0" \
374 "kernel_addr=0x100000\0" \ 374 "kernel_addr=0x100000\0" \
375 "ramdisk_addr=0x800000\0" \ 375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \ 376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \ 377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \ 378 "initrd_high=0xffffffffffffffff\0" \
379 "kernel_start=0x581100000\0" \ 379 "kernel_start=0x581000000\0" \
380 "kernel_load=0xa0000000\0" \ 380 "kernel_load=0xa0000000\0" \
381 "kernel_size=0x2800000\0" \ 381 "kernel_size=0x2800000\0" \
382 "mcmemsize=0x40000000\0" \ 382 "mcmemsize=0x40000000\0" \
383 "mcinitcmd=fsl_mc start mc 0x580300000" \ 383 "mcinitcmd=fsl_mc start mc 0x580a00000" \
384 " 0x580800000 \0" 384 " 0x580e00000 \0"
385 #endif /* CONFIG_SECURE_BOOT */ 385 #endif /* CONFIG_SECURE_BOOT */
386 386
387 387
388 #ifdef CONFIG_FSL_MC_ENET 388 #ifdef CONFIG_FSL_MC_ENET
389 #define CONFIG_FSL_MEMAC 389 #define CONFIG_FSL_MEMAC
390 #define CONFIG_PHYLIB 390 #define CONFIG_PHYLIB
391 #define CONFIG_PHYLIB_10G 391 #define CONFIG_PHYLIB_10G
392 #define CONFIG_PHY_VITESSE 392 #define CONFIG_PHY_VITESSE
393 #define CONFIG_PHY_REALTEK 393 #define CONFIG_PHY_REALTEK
394 #define CONFIG_PHY_TERANETICS 394 #define CONFIG_PHY_TERANETICS
395 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 395 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
396 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 396 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
397 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 397 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
398 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 398 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
399 399
400 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 400 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
401 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 401 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
402 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 402 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
403 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 403 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
404 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 404 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
405 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 405 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
406 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 406 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
407 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 407 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
408 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 408 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
409 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 409 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
410 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 410 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
411 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 411 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
412 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 412 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
413 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 413 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
414 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 414 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
415 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 415 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
416 416
417 #define CONFIG_MII /* MII PHY management */ 417 #define CONFIG_MII /* MII PHY management */
418 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 418 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
419 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 419 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
420 420
421 #endif 421 #endif
422 422
423 /* 423 /*
424 * USB 424 * USB
425 */ 425 */
426 #define CONFIG_HAS_FSL_XHCI_USB 426 #define CONFIG_HAS_FSL_XHCI_USB
427 #define CONFIG_USB_XHCI_FSL 427 #define CONFIG_USB_XHCI_FSL
428 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 428 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
429 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 429 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
430 430
431 #include <asm/fsl_secure_boot.h> 431 #include <asm/fsl_secure_boot.h>
432 432
433 #endif /* __LS2_QDS_H */ 433 #endif /* __LS2_QDS_H */
434 434
include/configs/ls2080ardb.h
Diff comments   View file @ f5bf23d
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * Copyright 2015 Freescale Semiconductor 3 * Copyright 2015 Freescale Semiconductor
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __LS2_RDB_H 8 #ifndef __LS2_RDB_H
9 #define __LS2_RDB_H 9 #define __LS2_RDB_H
10 10
11 #include "ls2080a_common.h" 11 #include "ls2080a_common.h"
12 12
13 #undef CONFIG_CONS_INDEX 13 #undef CONFIG_CONS_INDEX
14 #define CONFIG_CONS_INDEX 2 14 #define CONFIG_CONS_INDEX 2
15 15
16 #ifdef CONFIG_FSL_QSPI 16 #ifdef CONFIG_FSL_QSPI
17 #ifdef CONFIG_TARGET_LS2081ARDB 17 #ifdef CONFIG_TARGET_LS2081ARDB
18 #define CONFIG_QIXIS_I2C_ACCESS 18 #define CONFIG_QIXIS_I2C_ACCESS
19 #endif 19 #endif
20 #define CONFIG_SYS_I2C_EARLY_INIT 20 #define CONFIG_SYS_I2C_EARLY_INIT
21 #define CONFIG_DISPLAY_BOARDINFO_LATE 21 #define CONFIG_DISPLAY_BOARDINFO_LATE
22 #endif 22 #endif
23 23
24 #define I2C_MUX_CH_VOL_MONITOR 0xa 24 #define I2C_MUX_CH_VOL_MONITOR 0xa
25 #define I2C_VOL_MONITOR_ADDR 0x38 25 #define I2C_VOL_MONITOR_ADDR 0x38
26 #define CONFIG_VOL_MONITOR_IR36021_READ 26 #define CONFIG_VOL_MONITOR_IR36021_READ
27 #define CONFIG_VOL_MONITOR_IR36021_SET 27 #define CONFIG_VOL_MONITOR_IR36021_SET
28 28
29 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 29 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
30 #ifndef CONFIG_SPL_BUILD 30 #ifndef CONFIG_SPL_BUILD
31 #define CONFIG_VID 31 #define CONFIG_VID
32 #endif 32 #endif
33 /* step the IR regulator in 5mV increments */ 33 /* step the IR regulator in 5mV increments */
34 #define IR_VDD_STEP_DOWN 5 34 #define IR_VDD_STEP_DOWN 5
35 #define IR_VDD_STEP_UP 5 35 #define IR_VDD_STEP_UP 5
36 /* The lowest and highest voltage allowed for LS2080ARDB */ 36 /* The lowest and highest voltage allowed for LS2080ARDB */
37 #define VDD_MV_MIN 819 37 #define VDD_MV_MIN 819
38 #define VDD_MV_MAX 1212 38 #define VDD_MV_MAX 1212
39 39
40 #ifndef __ASSEMBLY__ 40 #ifndef __ASSEMBLY__
41 unsigned long get_board_sys_clk(void); 41 unsigned long get_board_sys_clk(void);
42 #endif 42 #endif
43 43
44 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 44 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
45 #define CONFIG_DDR_CLK_FREQ 133333333 45 #define CONFIG_DDR_CLK_FREQ 133333333
46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
47 47
48 #define CONFIG_DDR_SPD 48 #define CONFIG_DDR_SPD
49 #define CONFIG_DDR_ECC 49 #define CONFIG_DDR_ECC
50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
52 #define SPD_EEPROM_ADDRESS1 0x51 52 #define SPD_EEPROM_ADDRESS1 0x51
53 #define SPD_EEPROM_ADDRESS2 0x52 53 #define SPD_EEPROM_ADDRESS2 0x52
54 #define SPD_EEPROM_ADDRESS3 0x53 54 #define SPD_EEPROM_ADDRESS3 0x53
55 #define SPD_EEPROM_ADDRESS4 0x54 55 #define SPD_EEPROM_ADDRESS4 0x54
56 #define SPD_EEPROM_ADDRESS5 0x55 56 #define SPD_EEPROM_ADDRESS5 0x55
57 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 57 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
58 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 58 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
59 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 59 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
60 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 60 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
61 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 61 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
62 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 62 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
63 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 63 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
64 #endif 64 #endif
65 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 65 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
66 66
67 /* SATA */ 67 /* SATA */
68 #define CONFIG_LIBATA 68 #define CONFIG_LIBATA
69 #define CONFIG_SCSI_AHCI 69 #define CONFIG_SCSI_AHCI
70 #define CONFIG_SCSI_AHCI_PLAT 70 #define CONFIG_SCSI_AHCI_PLAT
71 #define CONFIG_SCSI 71 #define CONFIG_SCSI
72 72
73 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 73 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
74 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 74 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
75 75
76 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 76 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
77 #define CONFIG_SYS_SCSI_MAX_LUN 1 77 #define CONFIG_SYS_SCSI_MAX_LUN 1
78 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 78 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
79 CONFIG_SYS_SCSI_MAX_LUN) 79 CONFIG_SYS_SCSI_MAX_LUN)
80 80
81 #ifndef CONFIG_FSL_QSPI 81 #ifndef CONFIG_FSL_QSPI
82 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 82 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
83 83
84 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 84 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
85 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 85 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
86 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 86 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
87 87
88 #define CONFIG_SYS_NOR0_CSPR \ 88 #define CONFIG_SYS_NOR0_CSPR \
89 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 89 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
90 CSPR_PORT_SIZE_16 | \ 90 CSPR_PORT_SIZE_16 | \
91 CSPR_MSEL_NOR | \ 91 CSPR_MSEL_NOR | \
92 CSPR_V) 92 CSPR_V)
93 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 93 #define CONFIG_SYS_NOR0_CSPR_EARLY \
94 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 94 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
95 CSPR_PORT_SIZE_16 | \ 95 CSPR_PORT_SIZE_16 | \
96 CSPR_MSEL_NOR | \ 96 CSPR_MSEL_NOR | \
97 CSPR_V) 97 CSPR_V)
98 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 98 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
99 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 99 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
100 FTIM0_NOR_TEADC(0x5) | \ 100 FTIM0_NOR_TEADC(0x5) | \
101 FTIM0_NOR_TEAHC(0x5)) 101 FTIM0_NOR_TEAHC(0x5))
102 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 102 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
103 FTIM1_NOR_TRAD_NOR(0x1a) |\ 103 FTIM1_NOR_TRAD_NOR(0x1a) |\
104 FTIM1_NOR_TSEQRAD_NOR(0x13)) 104 FTIM1_NOR_TSEQRAD_NOR(0x13))
105 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 105 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
106 FTIM2_NOR_TCH(0x4) | \ 106 FTIM2_NOR_TCH(0x4) | \
107 FTIM2_NOR_TWPH(0x0E) | \ 107 FTIM2_NOR_TWPH(0x0E) | \
108 FTIM2_NOR_TWP(0x1c)) 108 FTIM2_NOR_TWP(0x1c))
109 #define CONFIG_SYS_NOR_FTIM3 0x04000000 109 #define CONFIG_SYS_NOR_FTIM3 0x04000000
110 #define CONFIG_SYS_IFC_CCR 0x01000000 110 #define CONFIG_SYS_IFC_CCR 0x01000000
111 111
112 #ifdef CONFIG_MTD_NOR_FLASH 112 #ifdef CONFIG_MTD_NOR_FLASH
113 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_FLASH_CFI_DRIVER
114 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #define CONFIG_SYS_FLASH_QUIET_TEST 116 #define CONFIG_SYS_FLASH_QUIET_TEST
117 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 117 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
118 118
119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
120 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 120 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
121 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
122 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
123 123
124 #define CONFIG_SYS_FLASH_EMPTY_INFO 124 #define CONFIG_SYS_FLASH_EMPTY_INFO
125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
126 CONFIG_SYS_FLASH_BASE + 0x40000000} 126 CONFIG_SYS_FLASH_BASE + 0x40000000}
127 #endif 127 #endif
128 128
129 #define CONFIG_NAND_FSL_IFC 129 #define CONFIG_NAND_FSL_IFC
130 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 130 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
131 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 131 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
132 132
133 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 133 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
134 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 134 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
135 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 135 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
136 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 136 | CSPR_MSEL_NAND /* MSEL = NAND */ \
137 | CSPR_V) 137 | CSPR_V)
138 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 138 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
139 139
140 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 140 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
141 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 141 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
142 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 142 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
143 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 143 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
144 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 144 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
145 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 145 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
146 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 146 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
147 147
148 #define CONFIG_SYS_NAND_ONFI_DETECTION 148 #define CONFIG_SYS_NAND_ONFI_DETECTION
149 149
150 /* ONFI NAND Flash mode0 Timing Params */ 150 /* ONFI NAND Flash mode0 Timing Params */
151 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 151 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
152 FTIM0_NAND_TWP(0x30) | \ 152 FTIM0_NAND_TWP(0x30) | \
153 FTIM0_NAND_TWCHT(0x0e) | \ 153 FTIM0_NAND_TWCHT(0x0e) | \
154 FTIM0_NAND_TWH(0x14)) 154 FTIM0_NAND_TWH(0x14))
155 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 155 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
156 FTIM1_NAND_TWBE(0xab) | \ 156 FTIM1_NAND_TWBE(0xab) | \
157 FTIM1_NAND_TRR(0x1c) | \ 157 FTIM1_NAND_TRR(0x1c) | \
158 FTIM1_NAND_TRP(0x30)) 158 FTIM1_NAND_TRP(0x30))
159 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 159 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
160 FTIM2_NAND_TREH(0x14) | \ 160 FTIM2_NAND_TREH(0x14) | \
161 FTIM2_NAND_TWHRE(0x3c)) 161 FTIM2_NAND_TWHRE(0x3c))
162 #define CONFIG_SYS_NAND_FTIM3 0x0 162 #define CONFIG_SYS_NAND_FTIM3 0x0
163 163
164 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 164 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
165 #define CONFIG_SYS_MAX_NAND_DEVICE 1 165 #define CONFIG_SYS_MAX_NAND_DEVICE 1
166 #define CONFIG_MTD_NAND_VERIFY_WRITE 166 #define CONFIG_MTD_NAND_VERIFY_WRITE
167 #define CONFIG_CMD_NAND 167 #define CONFIG_CMD_NAND
168 168
169 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 169 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
170 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 170 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
171 #define QIXIS_LBMAP_SWITCH 0x06 171 #define QIXIS_LBMAP_SWITCH 0x06
172 #define QIXIS_LBMAP_MASK 0x0f 172 #define QIXIS_LBMAP_MASK 0x0f
173 #define QIXIS_LBMAP_SHIFT 0 173 #define QIXIS_LBMAP_SHIFT 0
174 #define QIXIS_LBMAP_DFLTBANK 0x00 174 #define QIXIS_LBMAP_DFLTBANK 0x00
175 #define QIXIS_LBMAP_ALTBANK 0x04 175 #define QIXIS_LBMAP_ALTBANK 0x04
176 #define QIXIS_LBMAP_NAND 0x09 176 #define QIXIS_LBMAP_NAND 0x09
177 #define QIXIS_RST_CTL_RESET 0x31 177 #define QIXIS_RST_CTL_RESET 0x31
178 #define QIXIS_RST_CTL_RESET_EN 0x30 178 #define QIXIS_RST_CTL_RESET_EN 0x30
179 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 179 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
180 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 180 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
181 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 181 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
182 #define QIXIS_RCW_SRC_NAND 0x119 182 #define QIXIS_RCW_SRC_NAND 0x119
183 #define QIXIS_RST_FORCE_MEM 0x01 183 #define QIXIS_RST_FORCE_MEM 0x01
184 184
185 #define CONFIG_SYS_CSPR3_EXT (0x0) 185 #define CONFIG_SYS_CSPR3_EXT (0x0)
186 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 186 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
187 | CSPR_PORT_SIZE_8 \ 187 | CSPR_PORT_SIZE_8 \
188 | CSPR_MSEL_GPCM \ 188 | CSPR_MSEL_GPCM \
189 | CSPR_V) 189 | CSPR_V)
190 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 190 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
191 | CSPR_PORT_SIZE_8 \ 191 | CSPR_PORT_SIZE_8 \
192 | CSPR_MSEL_GPCM \ 192 | CSPR_MSEL_GPCM \
193 | CSPR_V) 193 | CSPR_V)
194 194
195 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 195 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
196 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 196 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
197 /* QIXIS Timing parameters for IFC CS3 */ 197 /* QIXIS Timing parameters for IFC CS3 */
198 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 198 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
199 FTIM0_GPCM_TEADC(0x0e) | \ 199 FTIM0_GPCM_TEADC(0x0e) | \
200 FTIM0_GPCM_TEAHC(0x0e)) 200 FTIM0_GPCM_TEAHC(0x0e))
201 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 201 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
202 FTIM1_GPCM_TRAD(0x3f)) 202 FTIM1_GPCM_TRAD(0x3f))
203 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 203 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
204 FTIM2_GPCM_TCH(0xf) | \ 204 FTIM2_GPCM_TCH(0xf) | \
205 FTIM2_GPCM_TWP(0x3E)) 205 FTIM2_GPCM_TWP(0x3E))
206 #define CONFIG_SYS_CS3_FTIM3 0x0 206 #define CONFIG_SYS_CS3_FTIM3 0x0
207 207
208 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 208 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
209 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 209 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
210 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 210 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
211 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 211 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
212 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 212 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
213 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 213 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
214 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 214 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
215 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 215 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
216 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 216 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
217 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 217 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
218 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 218 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
226 226
227 #define CONFIG_ENV_IS_IN_NAND 227 #define CONFIG_ENV_IS_IN_NAND
228 #define CONFIG_ENV_OFFSET (2048 * 1024) 228 #define CONFIG_ENV_OFFSET (2048 * 1024)
229 #define CONFIG_ENV_SECT_SIZE 0x20000 229 #define CONFIG_ENV_SECT_SIZE 0x20000
230 #define CONFIG_ENV_SIZE 0x2000 230 #define CONFIG_ENV_SIZE 0x2000
231 #define CONFIG_SPL_PAD_TO 0x80000 231 #define CONFIG_SPL_PAD_TO 0x80000
232 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 232 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
233 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 233 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
234 #else 234 #else
235 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 235 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
236 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 236 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
237 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 237 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
238 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 238 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
239 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 239 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
240 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 240 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
241 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 241 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
242 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 242 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
243 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 243 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 244 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
245 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 245 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 246 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 247 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 248 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
249 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 249 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
250 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 250 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
252 252
253 #define CONFIG_ENV_IS_IN_FLASH 253 #define CONFIG_ENV_IS_IN_FLASH
254 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 254 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
255 #define CONFIG_ENV_SECT_SIZE 0x20000 255 #define CONFIG_ENV_SECT_SIZE 0x20000
256 #define CONFIG_ENV_SIZE 0x2000 256 #define CONFIG_ENV_SIZE 0x2000
257 #endif 257 #endif
258 258
259 /* Debug Server firmware */ 259 /* Debug Server firmware */
260 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 260 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
261 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 261 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
262 #endif 262 #endif
263 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 263 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
264 264
265 #ifdef CONFIG_TARGET_LS2081ARDB 265 #ifdef CONFIG_TARGET_LS2081ARDB
266 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 266 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
267 #define QIXIS_QMAP_MASK 0x07 267 #define QIXIS_QMAP_MASK 0x07
268 #define QIXIS_QMAP_SHIFT 5 268 #define QIXIS_QMAP_SHIFT 5
269 #define QIXIS_LBMAP_DFLTBANK 0x00 269 #define QIXIS_LBMAP_DFLTBANK 0x00
270 #define QIXIS_LBMAP_QSPI 0x00 270 #define QIXIS_LBMAP_QSPI 0x00
271 #define QIXIS_RCW_SRC_QSPI 0x62 271 #define QIXIS_RCW_SRC_QSPI 0x62
272 #define QIXIS_LBMAP_ALTBANK 0x20 272 #define QIXIS_LBMAP_ALTBANK 0x20
273 #define QIXIS_RST_CTL_RESET 0x31 273 #define QIXIS_RST_CTL_RESET 0x31
274 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 274 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
275 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 275 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
276 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 276 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
277 #define QIXIS_LBMAP_MASK 0x0f 277 #define QIXIS_LBMAP_MASK 0x0f
278 #define QIXIS_RST_CTL_RESET_EN 0x30 278 #define QIXIS_RST_CTL_RESET_EN 0x30
279 #endif 279 #endif
280 280
281 /* 281 /*
282 * I2C 282 * I2C
283 */ 283 */
284 #ifdef CONFIG_TARGET_LS2081ARDB 284 #ifdef CONFIG_TARGET_LS2081ARDB
285 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 285 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
286 #endif 286 #endif
287 #define I2C_MUX_PCA_ADDR 0x75 287 #define I2C_MUX_PCA_ADDR 0x75
288 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 288 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
289 289
290 /* I2C bus multiplexer */ 290 /* I2C bus multiplexer */
291 #define I2C_MUX_CH_DEFAULT 0x8 291 #define I2C_MUX_CH_DEFAULT 0x8
292 292
293 /* SPI */ 293 /* SPI */
294 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 294 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
295 #define CONFIG_SPI_FLASH 295 #define CONFIG_SPI_FLASH
296 #ifdef CONFIG_FSL_QSPI 296 #ifdef CONFIG_FSL_QSPI
297 #define CONFIG_SPI_FLASH_STMICRO 297 #define CONFIG_SPI_FLASH_STMICRO
298 #endif 298 #endif
299 #ifdef CONFIG_FSL_QSPI 299 #ifdef CONFIG_FSL_QSPI
300 #ifdef CONFIG_TARGET_LS2081ARDB 300 #ifdef CONFIG_TARGET_LS2081ARDB
301 #define CONFIG_SPI_FLASH_STMICRO 301 #define CONFIG_SPI_FLASH_STMICRO
302 #else 302 #else
303 #define CONFIG_SPI_FLASH_SPANSION 303 #define CONFIG_SPI_FLASH_SPANSION
304 #endif 304 #endif
305 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 305 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
306 #define FSL_QSPI_FLASH_NUM 2 306 #define FSL_QSPI_FLASH_NUM 2
307 #endif 307 #endif
308 #endif 308 #endif
309 309
310 /* 310 /*
311 * RTC configuration 311 * RTC configuration
312 */ 312 */
313 #define RTC 313 #define RTC
314 #ifdef CONFIG_TARGET_LS2081ARDB 314 #ifdef CONFIG_TARGET_LS2081ARDB
315 #define CONFIG_RTC_PCF8563 1 315 #define CONFIG_RTC_PCF8563 1
316 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 316 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
317 #else 317 #else
318 #define CONFIG_RTC_DS3231 1 318 #define CONFIG_RTC_DS3231 1
319 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 319 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
320 #endif 320 #endif
321 321
322 /* EEPROM */ 322 /* EEPROM */
323 #define CONFIG_ID_EEPROM 323 #define CONFIG_ID_EEPROM
324 #define CONFIG_CMD_EEPROM 324 #define CONFIG_CMD_EEPROM
325 #define CONFIG_SYS_I2C_EEPROM_NXID 325 #define CONFIG_SYS_I2C_EEPROM_NXID
326 #define CONFIG_SYS_EEPROM_BUS_NUM 0 326 #define CONFIG_SYS_EEPROM_BUS_NUM 0
327 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 327 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
328 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 328 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
331 331
332 #define CONFIG_FSL_MEMAC 332 #define CONFIG_FSL_MEMAC
333 333
334 #ifdef CONFIG_PCI 334 #ifdef CONFIG_PCI
335 #define CONFIG_PCI_SCAN_SHOW 335 #define CONFIG_PCI_SCAN_SHOW
336 #define CONFIG_CMD_PCI 336 #define CONFIG_CMD_PCI
337 #endif 337 #endif
338 338
339 /* MMC */ 339 /* MMC */
340 #ifdef CONFIG_MMC 340 #ifdef CONFIG_MMC
341 #define CONFIG_FSL_ESDHC 341 #define CONFIG_FSL_ESDHC
342 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 342 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
343 #endif 343 #endif
344 344
345 #define CONFIG_MISC_INIT_R 345 #define CONFIG_MISC_INIT_R
346 346
347 /* 347 /*
348 * USB 348 * USB
349 */ 349 */
350 #define CONFIG_HAS_FSL_XHCI_USB 350 #define CONFIG_HAS_FSL_XHCI_USB
351 #define CONFIG_USB_XHCI_FSL 351 #define CONFIG_USB_XHCI_FSL
352 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 352 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
353 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 353 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
354 354
355 #undef CONFIG_CMDLINE_EDITING 355 #undef CONFIG_CMDLINE_EDITING
356 #include <config_distro_defaults.h> 356 #include <config_distro_defaults.h>
357 357
358 #define BOOT_TARGET_DEVICES(func) \ 358 #define BOOT_TARGET_DEVICES(func) \
359 func(USB, usb, 0) \ 359 func(USB, usb, 0) \
360 func(MMC, mmc, 0) \ 360 func(MMC, mmc, 0) \
361 func(SCSI, scsi, 0) \ 361 func(SCSI, scsi, 0) \
362 func(DHCP, dhcp, na) 362 func(DHCP, dhcp, na)
363 #include <config_distro_bootcmd.h> 363 #include <config_distro_bootcmd.h>
364 364
365 /* Initial environment variables */ 365 /* Initial environment variables */
366 #undef CONFIG_EXTRA_ENV_SETTINGS 366 #undef CONFIG_EXTRA_ENV_SETTINGS
367 #ifdef CONFIG_SECURE_BOOT 367 #ifdef CONFIG_SECURE_BOOT
368 #define CONFIG_EXTRA_ENV_SETTINGS \ 368 #define CONFIG_EXTRA_ENV_SETTINGS \
369 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 369 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
370 "scriptaddr=0x80800000\0" \ 370 "scriptaddr=0x80800000\0" \
371 "kernel_addr_r=0x81000000\0" \ 371 "kernel_addr_r=0x81000000\0" \
372 "pxefile_addr_r=0x81000000\0" \ 372 "pxefile_addr_r=0x81000000\0" \
373 "fdt_addr_r=0x88000000\0" \ 373 "fdt_addr_r=0x88000000\0" \
374 "ramdisk_addr_r=0x89000000\0" \ 374 "ramdisk_addr_r=0x89000000\0" \
375 "loadaddr=0x80100000\0" \ 375 "loadaddr=0x80100000\0" \
376 "kernel_addr=0x100000\0" \ 376 "kernel_addr=0x100000\0" \
377 "ramdisk_addr=0x800000\0" \ 377 "ramdisk_addr=0x800000\0" \
378 "ramdisk_size=0x2000000\0" \ 378 "ramdisk_size=0x2000000\0" \
379 "fdt_high=0xa0000000\0" \ 379 "fdt_high=0xa0000000\0" \
380 "initrd_high=0xffffffffffffffff\0" \ 380 "initrd_high=0xffffffffffffffff\0" \
381 "kernel_start=0x581100000\0" \ 381 "kernel_start=0x581100000\0" \
382 "kernel_load=0xa0000000\0" \ 382 "kernel_load=0xa0000000\0" \
383 "kernel_size=0x2800000\0" \ 383 "kernel_size=0x2800000\0" \
384 "mcmemsize=0x40000000\0" \ 384 "mcmemsize=0x40000000\0" \
385 "fdtfile=fsl-ls2080a-rdb.dtb\0" \ 385 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
386 "mcinitcmd=esbc_validate 0x580c80000;" \ 386 "mcinitcmd=esbc_validate 0x580c80000;" \
387 "esbc_validate 0x580cc0000;" \ 387 "esbc_validate 0x580cc0000;" \
388 "fsl_mc start mc 0x580300000" \ 388 "fsl_mc start mc 0x580300000" \
389 " 0x580800000 \0" \ 389 " 0x580800000 \0" \
390 BOOTENV 390 BOOTENV
391 #else 391 #else
392 #ifdef CONFIG_QSPI_BOOT 392 #ifdef CONFIG_QSPI_BOOT
393 #define CONFIG_EXTRA_ENV_SETTINGS \ 393 #define CONFIG_EXTRA_ENV_SETTINGS \
394 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 394 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
395 "scriptaddr=0x80800000\0" \ 395 "scriptaddr=0x80800000\0" \
396 "kernel_addr_r=0x81000000\0" \ 396 "kernel_addr_r=0x81000000\0" \
397 "pxefile_addr_r=0x81000000\0" \ 397 "pxefile_addr_r=0x81000000\0" \
398 "fdt_addr_r=0x88000000\0" \ 398 "fdt_addr_r=0x88000000\0" \
399 "ramdisk_addr_r=0x89000000\0" \ 399 "ramdisk_addr_r=0x89000000\0" \
400 "loadaddr=0x80100000\0" \ 400 "loadaddr=0x80100000\0" \
401 "kernel_addr=0x100000\0" \ 401 "kernel_addr=0x100000\0" \
402 "ramdisk_size=0x2000000\0" \ 402 "ramdisk_size=0x2000000\0" \
403 "fdt_high=0xa0000000\0" \ 403 "fdt_high=0xa0000000\0" \
404 "initrd_high=0xffffffffffffffff\0" \ 404 "initrd_high=0xffffffffffffffff\0" \
405 "kernel_start=0x21000000\0" \ 405 "kernel_start=0x21000000\0" \
406 "mcmemsize=0x40000000\0" \ 406 "mcmemsize=0x40000000\0" \
407 "mcinitcmd=fsl_mc start mc 0x20a00000" \ 407 "mcinitcmd=fsl_mc start mc 0x20a00000" \
408 " 0x20e00000 \0" \ 408 " 0x20e00000 \0" \
409 BOOTENV 409 BOOTENV
410 #else 410 #else
411 #define CONFIG_EXTRA_ENV_SETTINGS \ 411 #define CONFIG_EXTRA_ENV_SETTINGS \
412 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 412 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
413 "scriptaddr=0x80800000\0" \ 413 "scriptaddr=0x80800000\0" \
414 "kernel_addr_r=0x81000000\0" \ 414 "kernel_addr_r=0x81000000\0" \
415 "pxefile_addr_r=0x81000000\0" \ 415 "pxefile_addr_r=0x81000000\0" \
416 "fdt_addr_r=0x88000000\0" \ 416 "fdt_addr_r=0x88000000\0" \
417 "ramdisk_addr_r=0x89000000\0" \ 417 "ramdisk_addr_r=0x89000000\0" \
418 "loadaddr=0x80100000\0" \ 418 "loadaddr=0x80100000\0" \
419 "kernel_addr=0x100000\0" \ 419 "kernel_addr=0x100000\0" \
420 "ramdisk_addr=0x800000\0" \ 420 "ramdisk_addr=0x800000\0" \
421 "ramdisk_size=0x2000000\0" \ 421 "ramdisk_size=0x2000000\0" \
422 "fdt_high=0xa0000000\0" \ 422 "fdt_high=0xa0000000\0" \
423 "initrd_high=0xffffffffffffffff\0" \ 423 "initrd_high=0xffffffffffffffff\0" \
424 "kernel_start=0x581100000\0" \ 424 "kernel_start=0x581000000\0" \
425 "kernel_load=0xa0000000\0" \ 425 "kernel_load=0xa0000000\0" \
426 "kernel_size=0x2800000\0" \ 426 "kernel_size=0x2800000\0" \
427 "mcmemsize=0x40000000\0" \ 427 "mcmemsize=0x40000000\0" \
428 "fdtfile=fsl-ls2080a-rdb.dtb\0" \ 428 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
429 "mcinitcmd=fsl_mc start mc 0x580300000" \ 429 "mcinitcmd=fsl_mc start mc 0x580a00000" \
430 " 0x580800000 \0" \ 430 " 0x580e00000 \0" \
431 BOOTENV 431 BOOTENV
432 #endif 432 #endif
433 #endif 433 #endif
434 434
435 435
436 #undef CONFIG_BOOTARGS 436 #undef CONFIG_BOOTARGS
437 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ 437 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
438 "earlycon=uart8250,mmio,0x21c0600 " \ 438 "earlycon=uart8250,mmio,0x21c0600 " \
439 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 439 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
440 " hugepagesz=2m hugepages=256" 440 " hugepagesz=2m hugepages=256"
441 441
442 #undef CONFIG_BOOTCOMMAND 442 #undef CONFIG_BOOTCOMMAND
443 #ifdef CONFIG_QSPI_BOOT 443 #ifdef CONFIG_QSPI_BOOT
444 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 444 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
445 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \ 445 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
446 " && bootm $kernel_start" \ 446 " && bootm $kernel_start" \
447 " || run distro_bootcmd" 447 " || run distro_bootcmd"
448 #else 448 #else
449 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 449 /* Try to boot an on-NOR kernel first, then do normal distro boot */
450 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ 450 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
451 " && cp.b $kernel_start $kernel_load $kernel_size" \ 451 " && cp.b $kernel_start $kernel_load $kernel_size" \
452 " && bootm $kernel_load" \ 452 " && bootm $kernel_load" \
453 " || run distro_bootcmd" 453 " || run distro_bootcmd"
454 #endif 454 #endif
455 455
456 /* MAC/PHY configuration */ 456 /* MAC/PHY configuration */
457 #ifdef CONFIG_FSL_MC_ENET 457 #ifdef CONFIG_FSL_MC_ENET
458 #define CONFIG_PHYLIB_10G 458 #define CONFIG_PHYLIB_10G
459 #define CONFIG_PHY_AQUANTIA 459 #define CONFIG_PHY_AQUANTIA
460 #define CONFIG_PHY_CORTINA 460 #define CONFIG_PHY_CORTINA
461 #define CONFIG_PHYLIB 461 #define CONFIG_PHYLIB
462 #define CONFIG_SYS_CORTINA_FW_IN_NOR 462 #define CONFIG_SYS_CORTINA_FW_IN_NOR
463 #ifdef CONFIG_QSPI_BOOT 463 #ifdef CONFIG_QSPI_BOOT
464 #define CONFIG_CORTINA_FW_ADDR 0x20980000 464 #define CONFIG_CORTINA_FW_ADDR 0x20980000
465 #else 465 #else
466 #define CONFIG_CORTINA_FW_ADDR 0x581000000 466 #define CONFIG_CORTINA_FW_ADDR 0x580980000
467 #endif 467 #endif
468 #define CONFIG_CORTINA_FW_LENGTH 0x40000 468 #define CONFIG_CORTINA_FW_LENGTH 0x40000
469 469
470 #define CORTINA_PHY_ADDR1 0x10 470 #define CORTINA_PHY_ADDR1 0x10
471 #define CORTINA_PHY_ADDR2 0x11 471 #define CORTINA_PHY_ADDR2 0x11
472 #define CORTINA_PHY_ADDR3 0x12 472 #define CORTINA_PHY_ADDR3 0x12
473 #define CORTINA_PHY_ADDR4 0x13 473 #define CORTINA_PHY_ADDR4 0x13
474 #define AQ_PHY_ADDR1 0x00 474 #define AQ_PHY_ADDR1 0x00
475 #define AQ_PHY_ADDR2 0x01 475 #define AQ_PHY_ADDR2 0x01
476 #define AQ_PHY_ADDR3 0x02 476 #define AQ_PHY_ADDR3 0x02
477 #define AQ_PHY_ADDR4 0x03 477 #define AQ_PHY_ADDR4 0x03
478 #define AQR405_IRQ_MASK 0x36 478 #define AQR405_IRQ_MASK 0x36
479 479
480 #define CONFIG_MII 480 #define CONFIG_MII
481 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 481 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
482 #define CONFIG_PHY_GIGE 482 #define CONFIG_PHY_GIGE
483 #define CONFIG_PHY_AQUANTIA 483 #define CONFIG_PHY_AQUANTIA
484 #endif 484 #endif
485 485
486 #include <asm/fsl_secure_boot.h> 486 #include <asm/fsl_secure_boot.h>
487 487
488 #endif /* __LS2_RDB_H */ 488 #endif /* __LS2_RDB_H */
489 489