Eric Lee / smarc-uboot

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Commit f7a35a60cf45491871a5c28e9ad24db005487857

Authored by Heiko Schocher
Committed by Wolfgang Denk
1 parent c2537ee859
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mgcoge: add redundant environment sector 

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 1 changed file with 5 additions and 0 deletions Inline Diff

include/configs/mgcoge.h
Diff comments   View file @ f7a35a6
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #ifndef __CONFIG_H 24 #ifndef __CONFIG_H
25 #define __CONFIG_H 25 #define __CONFIG_H
26 26
27 /* 27 /*
28 * High Level Configuration Options 28 * High Level Configuration Options
29 * (easy to change) 29 * (easy to change)
30 */ 30 */
31 31
32 #define CONFIG_MPC8247 1 32 #define CONFIG_MPC8247 1
33 #define CONFIG_MPC8272_FAMILY 1 33 #define CONFIG_MPC8272_FAMILY 1
34 #define CONFIG_MGCOGE 1 34 #define CONFIG_MGCOGE 1
35 35
36 #define CONFIG_CPM2 1 /* Has a CPM2 */ 36 #define CONFIG_CPM2 1 /* Has a CPM2 */
37 37
38 /* Do boardspecific init */ 38 /* Do boardspecific init */
39 #define CONFIG_BOARD_EARLY_INIT_R 1 39 #define CONFIG_BOARD_EARLY_INIT_R 1
40 40
41 /* 41 /*
42 * Select serial console configuration 42 * Select serial console configuration
43 * 43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC). 46 * for SCC).
47 */ 47 */
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */ 48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */ 50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ 51 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
52 52
53 /* 53 /*
54 * Select ethernet configuration 54 * Select ethernet configuration
55 * 55 *
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
58 * SCC, 1-3 for FCC) 58 * SCC, 1-3 for FCC)
59 * 59 *
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
62 * must be unset. 62 * must be unset.
63 */ 63 */
64 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ 64 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
65 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ 65 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
66 #undef CONFIG_ETHER_NONE /* No external Ethernet */ 66 #undef CONFIG_ETHER_NONE /* No external Ethernet */
67 67
68 #define CONFIG_ETHER_INDEX 4 68 #define CONFIG_ETHER_INDEX 4
69 #define CFG_SCC_TOUT_LOOP 10000000 69 #define CFG_SCC_TOUT_LOOP 10000000
70 70
71 # define CFG_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) 71 # define CFG_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
72 72
73 #ifndef CONFIG_8260_CLKIN 73 #ifndef CONFIG_8260_CLKIN
74 #define CONFIG_8260_CLKIN 66000000 /* in Hz */ 74 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
75 #endif 75 #endif
76 76
77 #define CONFIG_BAUDRATE 115200 77 #define CONFIG_BAUDRATE 115200
78 78
79 /* 79 /*
80 * Command line configuration. 80 * Command line configuration.
81 */ 81 */
82 #include <config_cmd_default.h> 82 #include <config_cmd_default.h>
83 83
84 #define CONFIG_CMD_ECHO 84 #define CONFIG_CMD_ECHO
85 #define CONFIG_CMD_IMMAP 85 #define CONFIG_CMD_IMMAP
86 #define CONFIG_CMD_MII 86 #define CONFIG_CMD_MII
87 #define CONFIG_CMD_PING 87 #define CONFIG_CMD_PING
88 88
89 /* 89 /*
90 * Default environment settings 90 * Default environment settings
91 */ 91 */
92 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 #define CONFIG_EXTRA_ENV_SETTINGS \
93 "netdev=eth0\0" \ 93 "netdev=eth0\0" \
94 "u-boot_addr=100000\0" \ 94 "u-boot_addr=100000\0" \
95 "kernel_addr=200000\0" \ 95 "kernel_addr=200000\0" \
96 "fdt_addr=400000\0" \ 96 "fdt_addr=400000\0" \
97 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \ 97 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
98 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \ 98 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
99 "bootfile=/tftpboot/mgcoge/uImage\0" \ 99 "bootfile=/tftpboot/mgcoge/uImage\0" \
100 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \ 100 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
101 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 101 "load=tftp ${u-boot_addr} ${u-boot}\0" \
102 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \ 102 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
103 "cp.b ${u-boot_addr} fe000000 ${filesize};" \ 103 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
104 "prot on fe000000 fe03ffff\0" \ 104 "prot on fe000000 fe03ffff\0" \
105 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 105 "ramargs=setenv bootargs root=/dev/ram rw\0" \
106 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 106 "nfsargs=setenv bootargs root=/dev/nfs rw " \
107 "nfsroot=${serverip}:${rootpath}\0" \ 107 "nfsroot=${serverip}:${rootpath}\0" \
108 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ 108 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
109 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 109 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
110 "addip=setenv bootargs ${bootargs} " \ 110 "addip=setenv bootargs ${bootargs} " \
111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
112 "${netmask}:${hostname}:${netdev}:off panic=1\0" \ 112 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
113 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ 113 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
114 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \ 114 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
115 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 115 "bootm ${kernel_addr} - ${fdt_addr}\0" \
116 "net_self=tftp ${kernel_addr} ${bootfile}; " \ 116 "net_self=tftp ${kernel_addr} ${bootfile}; " \
117 "tftp ${fdt_addr} ${fdt_file}; " \ 117 "tftp ${fdt_addr} ${fdt_file}; " \
118 "tftp ${ramdisk_addr} ${ramdisk_file}; " \ 118 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
119 "run ramargs addip; " \ 119 "run ramargs addip; " \
120 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 120 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
121 "" 121 ""
122 #define CONFIG_BOOTCOMMAND "run net_nfs" 122 #define CONFIG_BOOTCOMMAND "run net_nfs"
123 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 123 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
124 124
125 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 125 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
126 126
127 /* 127 /*
128 * Miscellaneous configurable options 128 * Miscellaneous configurable options
129 */ 129 */
130 #define CFG_HUSH_PARSER 130 #define CFG_HUSH_PARSER
131 #define CFG_PROMPT_HUSH_PS2 "> " 131 #define CFG_PROMPT_HUSH_PS2 "> "
132 #define CFG_LONGHELP /* undef to save memory */ 132 #define CFG_LONGHELP /* undef to save memory */
133 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 133 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
134 #if defined(CONFIG_CMD_KGDB) 134 #if defined(CONFIG_CMD_KGDB)
135 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 135 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
136 #else 136 #else
137 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 137 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
138 #endif 138 #endif
139 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 139 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
140 #define CFG_MAXARGS 16 /* max number of command args */ 140 #define CFG_MAXARGS 16 /* max number of command args */
141 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 141 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
142 142
143 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ 143 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
144 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 144 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
145 145
146 #define CFG_LOAD_ADDR 0x100000 /* default load address */ 146 #define CFG_LOAD_ADDR 0x100000 /* default load address */
147 147
148 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ 148 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
149 149
150 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 150 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
151 151
152 #define CFG_SDRAM_BASE 0x00000000 152 #define CFG_SDRAM_BASE 0x00000000
153 #define CFG_FLASH_BASE 0xFE000000 153 #define CFG_FLASH_BASE 0xFE000000
154 #define CFG_FLASH_SIZE 32 154 #define CFG_FLASH_SIZE 32
155 #define CFG_FLASH_CFI 155 #define CFG_FLASH_CFI
156 #define CONFIG_FLASH_CFI_DRIVER 156 #define CONFIG_FLASH_CFI_DRIVER
157 #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ 157 #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
158 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 158 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
159 159
160 #define CFG_FLASH_BASE_1 0x50000000 160 #define CFG_FLASH_BASE_1 0x50000000
161 #define CFG_FLASH_SIZE_1 64 161 #define CFG_FLASH_SIZE_1 64
162 162
163 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 } 163 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
164 164
165 #define CFG_MONITOR_BASE TEXT_BASE 165 #define CFG_MONITOR_BASE TEXT_BASE
166 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 166 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
167 #define CFG_RAMBOOT 167 #define CFG_RAMBOOT
168 #endif 168 #endif
169 169
170 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ 170 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
171 171
172 #define CONFIG_ENV_IS_IN_FLASH 172 #define CONFIG_ENV_IS_IN_FLASH
173 173
174 #ifdef CONFIG_ENV_IS_IN_FLASH 174 #ifdef CONFIG_ENV_IS_IN_FLASH
175 #define CONFIG_ENV_SECT_SIZE 0x20000 175 #define CONFIG_ENV_SECT_SIZE 0x20000
176 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 176 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
177 #define CONFIG_ENV_OFFSET CFG_MONITOR_LEN
178
179 /* Address and size of Redundant Environment Sector */
180 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
181 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
177 #endif /* CONFIG_ENV_IS_IN_FLASH */ 182 #endif /* CONFIG_ENV_IS_IN_FLASH */
178 183
179 #define CFG_IMMR 0xF0000000 184 #define CFG_IMMR 0xF0000000
180 185
181 #define CFG_INIT_RAM_ADDR CFG_IMMR 186 #define CFG_INIT_RAM_ADDR CFG_IMMR
182 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 187 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
183 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 188 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
184 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 189 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
185 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 190 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
186 191
187 /* Hard reset configuration word */ 192 /* Hard reset configuration word */
188 #define CFG_HRCW_MASTER 0x0604b211 193 #define CFG_HRCW_MASTER 0x0604b211
189 194
190 /* No slaves */ 195 /* No slaves */
191 #define CFG_HRCW_SLAVE1 0 196 #define CFG_HRCW_SLAVE1 0
192 #define CFG_HRCW_SLAVE2 0 197 #define CFG_HRCW_SLAVE2 0
193 #define CFG_HRCW_SLAVE3 0 198 #define CFG_HRCW_SLAVE3 0
194 #define CFG_HRCW_SLAVE4 0 199 #define CFG_HRCW_SLAVE4 0
195 #define CFG_HRCW_SLAVE5 0 200 #define CFG_HRCW_SLAVE5 0
196 #define CFG_HRCW_SLAVE6 0 201 #define CFG_HRCW_SLAVE6 0
197 #define CFG_HRCW_SLAVE7 0 202 #define CFG_HRCW_SLAVE7 0
198 203
199 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 204 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
200 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 205 #define BOOTFLAG_WARM 0x02 /* Software reboot */
201 206
202 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 207 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
203 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 208 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204 209
205 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 210 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
206 #if defined(CONFIG_CMD_KGDB) 211 #if defined(CONFIG_CMD_KGDB)
207 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 212 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
208 #endif 213 #endif
209 214
210 #define CFG_HID0_INIT 0 215 #define CFG_HID0_INIT 0
211 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) 216 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
212 217
213 #define CFG_HID2 0 218 #define CFG_HID2 0
214 219
215 #define CFG_SIUMCR 0x4020c200 220 #define CFG_SIUMCR 0x4020c200
216 #define CFG_SYPCR 0xFFFFFFC3 221 #define CFG_SYPCR 0xFFFFFFC3
217 #define CFG_BCR 0x10000000 222 #define CFG_BCR 0x10000000
218 #define CFG_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) 223 #define CFG_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
219 224
220 /*----------------------------------------------------------------------- 225 /*-----------------------------------------------------------------------
221 * RMR - Reset Mode Register 5-5 226 * RMR - Reset Mode Register 5-5
222 *----------------------------------------------------------------------- 227 *-----------------------------------------------------------------------
223 * turn on Checkstop Reset Enable 228 * turn on Checkstop Reset Enable
224 */ 229 */
225 #define CFG_RMR 0 230 #define CFG_RMR 0
226 231
227 /*----------------------------------------------------------------------- 232 /*-----------------------------------------------------------------------
228 * TMCNTSC - Time Counter Status and Control 4-40 233 * TMCNTSC - Time Counter Status and Control 4-40
229 *----------------------------------------------------------------------- 234 *-----------------------------------------------------------------------
230 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 235 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
231 * and enable Time Counter 236 * and enable Time Counter
232 */ 237 */
233 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 238 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
234 239
235 /*----------------------------------------------------------------------- 240 /*-----------------------------------------------------------------------
236 * PISCR - Periodic Interrupt Status and Control 4-42 241 * PISCR - Periodic Interrupt Status and Control 4-42
237 *----------------------------------------------------------------------- 242 *-----------------------------------------------------------------------
238 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 243 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
239 * Periodic timer 244 * Periodic timer
240 */ 245 */
241 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 246 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
242 247
243 /*----------------------------------------------------------------------- 248 /*-----------------------------------------------------------------------
244 * RCCR - RISC Controller Configuration 13-7 249 * RCCR - RISC Controller Configuration 13-7
245 *----------------------------------------------------------------------- 250 *-----------------------------------------------------------------------
246 */ 251 */
247 #define CFG_RCCR 0 252 #define CFG_RCCR 0
248 253
249 /* 254 /*
250 * Init Memory Controller: 255 * Init Memory Controller:
251 * 256 *
252 * Bank Bus Machine PortSz Device 257 * Bank Bus Machine PortSz Device
253 * ---- --- ------- ------ ------ 258 * ---- --- ------- ------ ------
254 * 0 60x GPCM 8 bit FLASH 259 * 0 60x GPCM 8 bit FLASH
255 * 1 60x SDRAM 32 bit SDRAM 260 * 1 60x SDRAM 32 bit SDRAM
256 * 3 60x GPCM 8 bit GPIO/PIGGY 261 * 3 60x GPCM 8 bit GPIO/PIGGY
257 * 5 60x GPCM 16 bit CFG-Flash 262 * 5 60x GPCM 16 bit CFG-Flash
258 * 263 *
259 */ 264 */
260 /* Bank 0 - FLASH 265 /* Bank 0 - FLASH
261 */ 266 */
262 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ 267 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
263 BRx_PS_8 |\ 268 BRx_PS_8 |\
264 BRx_MS_GPCM_P |\ 269 BRx_MS_GPCM_P |\
265 BRx_V) 270 BRx_V)
266 271
267 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ 272 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
268 ORxG_CSNT |\ 273 ORxG_CSNT |\
269 ORxG_ACS_DIV2 |\ 274 ORxG_ACS_DIV2 |\
270 ORxG_SCY_5_CLK |\ 275 ORxG_SCY_5_CLK |\
271 ORxG_TRLX ) 276 ORxG_TRLX )
272 277
273 278
274 /* Bank 1 - 60x bus SDRAM 279 /* Bank 1 - 60x bus SDRAM
275 */ 280 */
276 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 281 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
277 #define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ 282 #define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
278 283
279 #define CFG_MPTPR 0x1800 284 #define CFG_MPTPR 0x1800
280 285
281 /*----------------------------------------------------------------------------- 286 /*-----------------------------------------------------------------------------
282 * Address for Mode Register Set (MRS) command 287 * Address for Mode Register Set (MRS) command
283 *----------------------------------------------------------------------------- 288 *-----------------------------------------------------------------------------
284 */ 289 */
285 #define CFG_MRS_OFFS 0x00000110 290 #define CFG_MRS_OFFS 0x00000110
286 #define CFG_PSRT 0x0e 291 #define CFG_PSRT 0x0e
287 292
288 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ 293 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
289 BRx_PS_64 |\ 294 BRx_PS_64 |\
290 BRx_MS_SDRAM_P |\ 295 BRx_MS_SDRAM_P |\
291 BRx_V) 296 BRx_V)
292 297
293 #define CFG_OR1_PRELIM CFG_OR1 298 #define CFG_OR1_PRELIM CFG_OR1
294 299
295 /* SDRAM initialization values 300 /* SDRAM initialization values
296 */ 301 */
297 302
298 #define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 303 #define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
299 ORxS_BPD_8 |\ 304 ORxS_BPD_8 |\
300 ORxS_ROWST_PBI0_A7 |\ 305 ORxS_ROWST_PBI0_A7 |\
301 ORxS_NUMR_13) 306 ORxS_NUMR_13)
302 307
303 #define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ 308 #define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
304 PSDMR_BSMA_A14_A16 |\ 309 PSDMR_BSMA_A14_A16 |\
305 PSDMR_SDA10_PBI0_A9 |\ 310 PSDMR_SDA10_PBI0_A9 |\
306 PSDMR_RFRC_5_CLK |\ 311 PSDMR_RFRC_5_CLK |\
307 PSDMR_PRETOACT_2W |\ 312 PSDMR_PRETOACT_2W |\
308 PSDMR_ACTTORW_2W |\ 313 PSDMR_ACTTORW_2W |\
309 PSDMR_LDOTOPRE_1C |\ 314 PSDMR_LDOTOPRE_1C |\
310 PSDMR_WRC_1C |\ 315 PSDMR_WRC_1C |\
311 PSDMR_CL_2) 316 PSDMR_CL_2)
312 317
313 /* GPIO/PIGGY on CS3 initialization values 318 /* GPIO/PIGGY on CS3 initialization values
314 */ 319 */
315 #define CFG_PIGGY_BASE 0x30000000 320 #define CFG_PIGGY_BASE 0x30000000
316 #define CFG_PIGGY_SIZE 128 321 #define CFG_PIGGY_SIZE 128
317 322
318 #define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\ 323 #define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
319 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) 324 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
320 325
321 #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\ 326 #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\
322 ORxG_CSNT | ORxG_ACS_DIV2 |\ 327 ORxG_CSNT | ORxG_ACS_DIV2 |\
323 ORxG_SCY_3_CLK | ORxG_TRLX ) 328 ORxG_SCY_3_CLK | ORxG_TRLX )
324 329
325 /* CFG-Flash on CS5 initialization values 330 /* CFG-Flash on CS5 initialization values
326 */ 331 */
327 #define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\ 332 #define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
328 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) 333 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
329 334
330 #define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\ 335 #define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
331 ORxG_CSNT | ORxG_ACS_DIV2 |\ 336 ORxG_CSNT | ORxG_ACS_DIV2 |\
332 ORxG_SCY_5_CLK | ORxG_TRLX ) 337 ORxG_SCY_5_CLK | ORxG_TRLX )
333 338
334 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 339 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
335 340
336 /* pass open firmware flat tree */ 341 /* pass open firmware flat tree */
337 #define CONFIG_OF_LIBFDT 1 342 #define CONFIG_OF_LIBFDT 1
338 #define CONFIG_OF_BOARD_SETUP 1 343 #define CONFIG_OF_BOARD_SETUP 1
339 344
340 #define OF_CPU "PowerPC,8247@0" 345 #define OF_CPU "PowerPC,8247@0"
341 #define OF_SOC "soc@f0000000" 346 #define OF_SOC "soc@f0000000"
342 #define OF_TBCLK (bd->bi_busfreq / 4) 347 #define OF_TBCLK (bd->bi_busfreq / 4)
343 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" 348 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
344 349
345 #endif /* __CONFIG_H */ 350 #endif /* __CONFIG_H */
346 351