Eric Lee / smarc-uboot | Embedian Git Server

Commit f8296d6975e69196b522b43dd4396138e237a964

Authored by Masahiro Yamada 2015-03-17 11:28:04 +0800

Committed by Tom Rini 2015-03-17 22:59:53 +0800

Exists in v2017.01-smarct4x and in 39 other branches

powerpc: mpc5xxx: remove BC3450 board support

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 10 changed files with 8 additions and 1987 deletions Inline Diff

arch/powerpc/cpu/mpc5xxx/Kconfig
board/bc3450/Kconfig
board/bc3450/MAINTAINERS
board/bc3450/Makefile
board/bc3450/bc3450.c
board/bc3450/cmd_bc3450.c
board/bc3450/mt48lc16m16a2-75.h
configs/BC3450_defconfig
doc/README.scrapyard
include/configs/BC3450.h

arch/powerpc/cpu/mpc5xxx/Kconfig

Diff comments View file @ f8296d6

 menu "mpc5xxx CPU"
 	depends on MPC5xxx
 config SYS_CPU
 	default "mpc5xxx"
 choice
 	prompt "Target select"
 config TARGET_A3M071
 	bool "Support a3m071"
 	select SUPPORT_SPL
 config TARGET_A4M072
 	bool "Support a4m072"
-config TARGET_BC3450
-	bool "Support BC3450"
 config TARGET_CANMB
 	bool "Support canmb"
 config TARGET_CM5200
 	bool "Support cm5200"
 config TARGET_GALAXY5200
 	bool "Support galaxy5200"
 config TARGET_INKA4X0
 	bool "Support inka4x0"
 config TARGET_IPEK01
 	bool "Support ipek01"
 config TARGET_JUPITER
 	bool "Support jupiter"
 config TARGET_MOTIONPRO
 	bool "Support motionpro"
 config TARGET_MUNICES
 	bool "Support munices"
 config TARGET_V38B
 	bool "Support v38b"
 config TARGET_O2D
 	bool "Support O2D"
 config TARGET_O2D300
 	bool "Support O2D300"
 config TARGET_O2DNT2
 	bool "Support O2DNT2"
 config TARGET_O2I
 	bool "Support O2I"
 config TARGET_O2MNT
 	bool "Support O2MNT"
 config TARGET_O3DNT
 	bool "Support O3DNT"
 config TARGET_DIGSY_MTC
 	bool "Support digsy_mtc"
 config TARGET_PCM030
 	bool "Support pcm030"
 config TARGET_AEV
 	bool "Support aev"
 config TARGET_CHARON
 	bool "Support charon"
 config TARGET_TB5200
 	bool "Support TB5200"
 config TARGET_TQM5200
 	bool "Support TQM5200"
 endchoice
 source "board/a3m071/Kconfig"
 source "board/a4m072/Kconfig"
-source "board/bc3450/Kconfig"
 source "board/canmb/Kconfig"
 source "board/cm5200/Kconfig"
 source "board/galaxy5200/Kconfig"
 source "board/ifm/o2dnt2/Kconfig"
 source "board/inka4x0/Kconfig"
 source "board/intercontrol/digsy_mtc/Kconfig"
 source "board/ipek01/Kconfig"
 source "board/jupiter/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
 source "board/phytec/pcm030/Kconfig"
 source "board/tqc/tqm5200/Kconfig"
 source "board/v38b/Kconfig"
 endmenu

board/bc3450/Kconfig

View file @ f8296d6

1	if TARGET_BC3450		File was deleted
2
3	config SYS_BOARD
4	default "bc3450"
5
6	config SYS_CONFIG_NAME
7	default "BC3450"
8
9	endif
10		1	if TARGET_BC3450

board/bc3450/MAINTAINERS

View file @ f8296d6

1	BC3450 BOARD		File was deleted
2	#M: -
3	S: Maintained
4	F: board/bc3450/
5	F: include/configs/BC3450.h
6	F: configs/BC3450_defconfig
7		1	BC3450 BOARD

board/bc3450/Makefile

View file @ f8296d6

1	#		File was deleted
2	# (C) Copyright 2003-2006
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#
5	# SPDX-License-Identifier: GPL-2.0+
6	#
7
8	obj-y := bc3450.o cmd_bc3450.o
9		1	#

board/bc3450/bc3450.c

View file @ f8296d6

1	/*		File was deleted
2	* (C) Copyright 2003-2004
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*
5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*
8	* (C) Copyright 2004-2005
9	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10	*
11	* (C) Copyright 2006
12	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
13	*
14	* SPDX-License-Identifier: GPL-2.0+
15	*/
16
17	#include <common.h>
18	#include <mpc5xxx.h>
19	#include <pci.h>
20	#include <netdev.h>
21
22	#ifdef CONFIG_VIDEO_SM501
23	#include <sm501.h>
24	#endif
25
26	#if defined(CONFIG_MPC5200_DDR)
27	#include "mt46v16m16-75.h"
28	#else
29	#include "mt48lc16m16a2-75.h"
30	#endif
31
32	#ifdef CONFIG_RTC_MPC5200
33	#include <rtc.h>
34	#endif
35
36	#ifdef CONFIG_PS2MULT
37	void ps2mult_early_init(void);
38	#endif
39
40	#ifndef CONFIG_SYS_RAMBOOT
41	static void sdram_start (int hi_addr)
42	{
43	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44
45	/* unlock mode register */
46	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \|
47	hi_addr_bit;
48	__asm__ volatile ("sync");
49
50	/* precharge all banks */
51	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
52	hi_addr_bit;
53	__asm__ volatile ("sync");
54
55	#if SDRAM_DDR
56	/* set mode register: extended mode */
57	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
58	__asm__ volatile ("sync");
59
60	/* set mode register: reset DLL */
61	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
62	__asm__ volatile ("sync");
63	#endif
64
65	/* precharge all banks */
66	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
67	hi_addr_bit;
68	__asm__ volatile ("sync");
69
70	/* auto refresh */
71	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|
72	hi_addr_bit;
73	__asm__ volatile ("sync");
74
75	/* set mode register */
76	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
77	__asm__ volatile ("sync");
78
79	/* normal operation */
80	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
81	__asm__ volatile ("sync");
82	}
83	#endif
84
85	/*
86	* ATTENTION: Although partially referenced initdram does NOT make real use
87	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
88	* is something else than 0x00000000.
89	*/
90
91	phys_size_t initdram (int board_type)
92	{
93	ulong dramsize = 0;
94	ulong dramsize2 = 0;
95	#ifndef CONFIG_SYS_RAMBOOT
96	ulong test1, test2;
97
98	/* setup SDRAM chip selects */
99	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
100	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
101	__asm__ volatile ("sync");
102
103	/* setup config registers */
104	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
105	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
106	__asm__ volatile ("sync");
107
108	#if SDRAM_DDR
109	/* set tap delay */
110	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
111	__asm__ volatile ("sync");
112	#endif
113
114	/* find RAM size using SDRAM CS0 only */
115	sdram_start(0);
116	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
117	sdram_start(1);
118	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
119	if (test1 > test2) {
120	sdram_start(0);
121	dramsize = test1;
122	} else {
123	dramsize = test2;
124	}
125
126	/* memory smaller than 1MB is impossible */
127	if (dramsize < (1 << 20)) {
128	dramsize = 0;
129	}
130
131	/* set SDRAM CS0 size according to the amount of RAM found */
132	if (dramsize > 0) {
133	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +
134	__builtin_ffs(dramsize >> 20) - 1;
135	} else {
136	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
137	}
138
139	/* let SDRAM CS1 start right after CS0 */
140	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
141
142	/* find RAM size using SDRAM CS1 only */
143	sdram_start(0);
144	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
145	sdram_start(1);
146	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
147	if (test1 > test2) {
148	sdram_start(0);
149	dramsize2 = test1;
150	} else {
151	dramsize2 = test2;
152	}
153
154	/* memory smaller than 1MB is impossible */
155	if (dramsize2 < (1 << 20)) {
156	dramsize2 = 0;
157	}
158
159	/* set SDRAM CS1 size according to the amount of RAM found */
160	if (dramsize2 > 0) {
161	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
162	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
163	} else {
164	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
165	}
166
167	#else /* CONFIG_SYS_RAMBOOT */
168
169	/* retrieve size of memory connected to SDRAM CS0 */
170	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
171	if (dramsize >= 0x13) {
172	dramsize = (1 << (dramsize - 0x13)) << 20;
173	} else {
174	dramsize = 0;
175	}
176
177	/* retrieve size of memory connected to SDRAM CS1 */
178	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
179	if (dramsize2 >= 0x13) {
180	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
181	} else {
182	dramsize2 = 0;
183	}
184
185	#endif /* CONFIG_SYS_RAMBOOT */
186
187	return dramsize;
188	}
189
190	int checkboard (void)
191	{
192	#if defined (CONFIG_TQM5200)
193	puts ("Board: TQM5200 (TQ-Components GmbH)\n");
194	#endif
195
196	#if defined (CONFIG_BC3450)
197	puts ("Dev: GERSYS BC3450\n");
198	#endif
199
200	return 0;
201	}
202
203	void flash_preinit(void)
204	{
205	/*
206	* Now, when we are in RAM, enable flash write
207	* access for detection process.
208	* Note that CS_BOOT cannot be cleared when
209	* executing in flash.
210	*/
211	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
212	}
213
214
215	#ifdef CONFIG_PCI
216	static struct pci_controller hose;
217
218	extern void pci_mpc5xxx_init(struct pci_controller *);
219
220	void pci_init_board(void)
221	{
222	pci_mpc5xxx_init(&hose);
223	}
224	#endif
225
226	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
227
228	void init_ide_reset (void)
229	{
230	debug ("init_ide_reset\n");
231
232	/* Configure PSC1_4 as GPIO output for ATA reset */
233	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
234	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
235	}
236
237	void ide_set_reset (int idereset)
238	{
239	debug ("ide_reset(%d)\n", idereset);
240
241	if (idereset) {
242	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
243	} else {
244	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
245	}
246	}
247	#endif
248
249	#ifdef CONFIG_POST
250	/*
251	* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
252	* is left open, no keypress is detected.
253	*/
254	int post_hotkeys_pressed(void)
255	{
256	struct mpc5xxx_gpio *gpio;
257
258	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
259
260	/*
261	* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
262	* CODEC or UART mode. Consumer IrDA should still be possible.
263	*/
264	gpio->port_config &= ~(0x07000000);
265	gpio->port_config \|= 0x03000000;
266
267	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
268	gpio->simple_gpioe \|= 0x20000000;
269
270	/* Configure GPIO_IRDA_1 as input */
271	gpio->simple_ddr &= ~(0x20000000);
272
273	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
274	}
275	#endif
276
277	#ifdef CONFIG_BOARD_EARLY_INIT_R
278	int board_early_init_r (void)
279	{
280	#ifdef CONFIG_RTC_MPC5200
281	struct rtc_time t;
282
283	/* set to Wed Dec 31 19:00:00 1969 */
284	t.tm_sec = t.tm_min = 0;
285	t.tm_hour = 19;
286	t.tm_mday = 31;
287	t.tm_mon = 12;
288	t.tm_year = 1969;
289	t.tm_wday = 3;
290
291	rtc_set(&t);
292	#endif /* CONFIG_RTC_MPC5200 */
293
294	#ifdef CONFIG_PS2MULT
295	ps2mult_early_init();
296	#endif /* CONFIG_PS2MULT */
297	return (0);
298	}
299	#endif /* CONFIG_BOARD_EARLY_INIT_R */
300
301
302	int last_stage_init (void)
303	{
304	/*
305	* auto scan for really existing devices and re-set chip select
306	* configuration.
307	*/
308	u16 save, tmp;
309	int restore;
310
311	/*
312	* Check for SRAM and SRAM size
313	*/
314
315	/* save original SRAM content */
316	save = (volatile u16 )CONFIG_SYS_CS2_START;
317	restore = 1;
318
319	/* write test pattern to SRAM */
320	(volatile u16 )CONFIG_SYS_CS2_START = 0xA5A5;
321	__asm__ volatile ("sync");
322	/*
323	* Put a different pattern on the data lines: otherwise they may float
324	* long enough to read back what we wrote.
325	*/
326	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
327	if (tmp == 0xA5A5)
328	puts ("!! possible error in SRAM detection\n");
329
330	if ((volatile u16 )CONFIG_SYS_CS2_START != 0xA5A5) {
331	/* no SRAM at all, disable cs */
332	(vu_long )MPC5XXX_ADDECR &= ~(1 << 18);
333	(vu_long )MPC5XXX_CS2_START = 0x0000FFFF;
334	(vu_long )MPC5XXX_CS2_STOP = 0x0000FFFF;
335	restore = 0;
336	__asm__ volatile ("sync");
337	} else if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
338	/* make sure that we access a mirrored address */
339	(volatile u16 )CONFIG_SYS_CS2_START = 0x1111;
340	__asm__ volatile ("sync");
341	if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
342	/* SRAM size = 512 kByte */
343	(vu_long )MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
344	0x80000);
345	__asm__ volatile ("sync");
346	puts ("SRAM: 512 kB\n");
347	}
348	else
349	puts ("!! possible error in SRAM detection\n");
350	} else {
351	puts ("SRAM: 1 MB\n");
352	}
353	/* restore origianl SRAM content */
354	if (restore) {
355	(volatile u16 )CONFIG_SYS_CS2_START = save;
356	__asm__ volatile ("sync");
357	}
358
359	/*
360	* Check for Grafic Controller
361	*/
362
363	/* save origianl FB content */
364	save = (volatile u16 )CONFIG_SYS_CS1_START;
365	restore = 1;
366
367	/* write test pattern to FB memory */
368	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;
369	__asm__ volatile ("sync");
370	/*
371	* Put a different pattern on the data lines: otherwise they may float
372	* long enough to read back what we wrote.
373	*/
374	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
375	if (tmp == 0xA5A5)
376	puts ("!! possible error in grafic controller detection\n");
377
378	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {
379	/* no grafic controller at all, disable cs */
380	(vu_long )MPC5XXX_ADDECR &= ~(1 << 17);
381	(vu_long )MPC5XXX_CS1_START = 0x0000FFFF;
382	(vu_long )MPC5XXX_CS1_STOP = 0x0000FFFF;
383	restore = 0;
384	__asm__ volatile ("sync");
385	} else {
386	puts ("VGA: SMI501 (Voyager) with 8 MB\n");
387	}
388	/* restore origianl FB content */
389	if (restore) {
390	(volatile u16 )CONFIG_SYS_CS1_START = save;
391	__asm__ volatile ("sync");
392	}
393
394	return 0;
395	}
396
397	#ifdef CONFIG_VIDEO_SM501
398
399	#define DISPLAY_WIDTH 640
400	#define DISPLAY_HEIGHT 480
401
402	#ifdef CONFIG_VIDEO_SM501_8BPP
403	#error CONFIG_VIDEO_SM501_8BPP not supported.
404	#endif /* CONFIG_VIDEO_SM501_8BPP */
405
406	#ifdef CONFIG_VIDEO_SM501_16BPP
407	#error CONFIG_VIDEO_SM501_16BPP not supported.
408	#endif /* CONFIG_VIDEO_SM501_16BPP */
409
410	#ifdef CONFIG_VIDEO_SM501_32BPP
411	static const SMI_REGS init_regs [] =
412	{
413	#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
414	/* FP only */
415	{0x00004, 0x0},
416	{0x00048, 0x00021807},
417	{0x0004C, 0x091a0a01},
418	{0x00054, 0x1},
419	{0x00040, 0x00021807},
420	{0x00044, 0x091a0a01},
421	{0x00054, 0x0},
422	{0x80000, 0x01013106},
423	{0x80004, 0xc428bb17},
424	{0x80000, 0x03013106},
425	{0x8000C, 0x00000000},
426	{0x80010, 0x0a000a00},
427	{0x80014, 0x02800000},
428	{0x80018, 0x01e00000},
429	{0x8001C, 0x00000000},
430	{0x80020, 0x01e00280},
431	{0x80024, 0x02fa027f},
432	{0x80028, 0x004a028b},
433	{0x8002C, 0x020c01df},
434	{0x80030, 0x000201e9},
435	{0x80200, 0x00010200},
436	{0x80000, 0x0f013106},
437	#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
438	/* CRT only */
439	{0x00004, 0x0},
440	{0x00048, 0x00021807},
441	{0x0004C, 0x10090a01},
442	{0x00054, 0x1},
443	{0x00040, 0x00021807},
444	{0x00044, 0x10090a01},
445	{0x00054, 0x0},
446	{0x80200, 0x00010000},
447	{0x80204, 0x0},
448	{0x80208, 0x0A000A00},
449	{0x8020C, 0x02fa027f},
450	{0x80210, 0x004a028b},
451	{0x80214, 0x020c01df},
452	{0x80218, 0x000201e9},
453	{0x80200, 0x00013306},
454	#else /* panel + CRT */
455	{0x00004, 0x0},
456	{0x00048, 0x00021807},
457	{0x0004C, 0x091a0a01},
458	{0x00054, 0x1},
459	{0x00040, 0x00021807},
460	{0x00044, 0x091a0a01},
461	{0x00054, 0x0},
462	{0x80000, 0x0f013106},
463	{0x80004, 0xc428bb17},
464	{0x8000C, 0x00000000},
465	{0x80010, 0x0a000a00},
466	{0x80014, 0x02800000},
467	{0x80018, 0x01e00000},
468	{0x8001C, 0x00000000},
469	{0x80020, 0x01e00280},
470	{0x80024, 0x02fa027f},
471	{0x80028, 0x004a028b},
472	{0x8002C, 0x020c01df},
473	{0x80030, 0x000201e9},
474	{0x80200, 0x00010000},
475	#endif
476	{0, 0}
477	};
478	#endif /* CONFIG_VIDEO_SM501_32BPP */
479
480	#ifdef CONFIG_CONSOLE_EXTRA_INFO
481	/*
482	* Return text to be printed besides the logo.
483	*/
484	void video_get_info_str (int line_number, char *info)
485	{
486	if (line_number == 1) {
487	#if defined (CONFIG_TQM5200)
488	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
489	#else
490	#error No supported board selected
491	#endif /* CONFIG_TQM5200 */
492
493	#if defined (CONFIG_BC3450)
494	} else if (line_number == 2) {
495	strcpy (info, " Dev: GERSYS BC3450");
496	#endif /* CONFIG_BC3450 */
497	}
498	else {
499	info [0] = '\0';
500	}
501	}
502	#endif
503
504	/*
505	* Returns SM501 register base address. First thing called in the
506	* driver. Checks if SM501 is physically present.
507	*/
508	unsigned int board_video_init (void)
509	{
510	u16 save, tmp;
511	int restore, ret;
512
513	/*
514	* Check for Grafic Controller
515	*/
516
517	/* save origianl FB content */
518	save = (volatile u16 )CONFIG_SYS_CS1_START;
519	restore = 1;
520
521	/* write test pattern to FB memory */
522	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;
523	__asm__ volatile ("sync");
524	/*
525	* Put a different pattern on the data lines: otherwise they may float
526	* long enough to read back what we wrote.
527	*/
528	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
529	if (tmp == 0xA5A5)
530	puts ("!! possible error in grafic controller detection\n");
531
532	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {
533	/* no grafic controller found */
534	restore = 0;
535	ret = 0;
536	} else {
537	ret = SM501_MMIO_BASE;
538	}
539
540	if (restore) {
541	(volatile u16 )CONFIG_SYS_CS1_START = save;
542	__asm__ volatile ("sync");
543	}
544	return ret;
545	}
546
547	/*
548	* Returns SM501 framebuffer address
549	*/
550	unsigned int board_video_get_fb (void)
551	{
552	return SM501_FB_BASE;
553	}
554
555	/*
556	* Called after initializing the SM501 and before clearing the screen.
557	*/
558	void board_validate_screen (unsigned int base)
559	{
560	}
561
562	/*
563	* Return a pointer to the initialization sequence.
564	*/
565	const SMI_REGS *board_get_regs (void)
566	{
567	return init_regs;
568	}
569
570	int board_get_width (void)
571	{
572	return DISPLAY_WIDTH;
573	}
574
575	int board_get_height (void)
576	{
577	return DISPLAY_HEIGHT;
578	}
579
580	#endif /* CONFIG_VIDEO_SM501 */
581
582	int board_eth_init(bd_t *bis)
583	{
584	cpu_eth_init(bis); /* Built in FEC comes first */
585	return pci_eth_init(bis);
586	}
587		1	/*

board/bc3450/cmd_bc3450.c

View file @ f8296d6

1	/*		File was deleted
2	* (C) Copyright 2005
3	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
4	*
5	* (C) Copyright 2005
6	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
7	*
8	* SPDX-License-Identifier: GPL-2.0+
9	*/
10
11	#include <common.h>
12	#include <command.h>
13
14	/*
15	* BC3450 specific commands
16	*/
17	#if defined(CONFIG_CMD_BSP)
18
19	/*
20	* Definitions for DS1620 chip
21	*/
22	#define THERM_START_CONVERT 0xee
23	#define THERM_RESET 0xaf
24	#define THERM_READ_CONFIG 0xac
25	#define THERM_READ_TEMP 0xaa
26	#define THERM_READ_TL 0xa2
27	#define THERM_READ_TH 0xa1
28	#define THERM_WRITE_CONFIG 0x0c
29	#define THERM_WRITE_TL 0x02
30	#define THERM_WRITE_TH 0x01
31
32	#define CONFIG_SYS_1SHOT 1
33	#define CONFIG_SYS_STANDALONE 0
34
35	struct therm {
36	int hi;
37	int lo;
38	};
39
40	/*
41	* SM501 Register
42	*/
43	#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */
44	#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */
45	#define SM501_POWER_MODE0_GATE 0x00000040UL
46	#define SM501_POWER_MODE1_GATE 0x00000048UL
47	#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
48	#define SM501_GPIO_DATA_LOW 0x00010000UL
49	#define SM501_GPIO_DATA_HIGH 0x00010004UL
50	#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
51	#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
52	#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
53	#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL
54
55	/* SM501 CRT Display Control Bits */
56	#define SM501_CDC_SEL (1 << 9)
57	#define SM501_CDC_TE (1 << 8)
58	#define SM501_CDC_E (1 << 2)
59
60	/* SM501 Panel Display Control Bits */
61	#define SM501_PDC_FPEN (1 << 27)
62	#define SM501_PDC_BIAS (1 << 26)
63	#define SM501_PDC_DATA (1 << 25)
64	#define SM501_PDC_VDDEN (1 << 24)
65
66	/* SM501 GPIO Data LOW Bits */
67	#define SM501_GPIO24 0x01000000
68	#define SM501_GPIO25 0x02000000
69	#define SM501_GPIO26 0x04000000
70	#define SM501_GPIO27 0x08000000
71	#define SM501_GPIO28 0x10000000
72	#define SM501_GPIO29 0x20000000
73	#define SM501_GPIO30 0x40000000
74	#define SM501_GPIO31 0x80000000
75
76	/* SM501 GPIO Data HIGH Bits */
77	#define SM501_GPIO46 0x00004000
78	#define SM501_GPIO47 0x00008000
79	#define SM501_GPIO48 0x00010000
80	#define SM501_GPIO49 0x00020000
81	#define SM501_GPIO50 0x00040000
82	#define SM501_GPIO51 0x00080000
83
84	/* BC3450 GPIOs @ SM501 Data LOW */
85	#define DIP (SM501_GPIO24 \| SM501_GPIO25 \| SM501_GPIO26 \| SM501_GPIO27)
86	#define DS1620_DQ SM501_GPIO29 /* I/O */
87	#define DS1620_CLK SM501_GPIO30 /* High active O/P */
88	#define DS1620_RES SM501_GPIO31 /* Low active O/P */
89	/* BC3450 GPIOs @ SM501 Data HIGH */
90	#define BUZZER SM501_GPIO47 /* Low active O/P */
91	#define DS1620_TLOW SM501_GPIO48 /* High active I/P */
92	#define PWR_OFF SM501_GPIO49 /* Low active O/P */
93	#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */
94
95
96	/*
97	* Initialise GPIO on SM501
98	*
99	* This function may be called from several other functions.
100	* Yet, the initialisation sequence is executed only the first
101	* time the function is called.
102	*/
103	int sm501_gpio_init (void)
104	{
105	static int init_done = 0;
106
107	if (init_done) {
108	debug("sm501_gpio_init: nothing to be done.\n");
109	return 1;
110	}
111
112	/* enable SM501 GPIO control (in both power modes) */
113	(vu_long ) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) \|=
114	POWER_MODE_GATE_GPIO_PWM_I2C;
115	(vu_long ) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) \|=
116	POWER_MODE_GATE_GPIO_PWM_I2C;
117
118	/* set up default O/Ps */
119	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
120	~(DS1620_RES \| DS1620_CLK);
121	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) \|= DS1620_DQ;
122	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
123	~(FP_DATA_TRI);
124	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) \|=
125	(BUZZER \| PWR_OFF);
126
127	/* configure directions for SM501 GPIO pins */
128	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
129	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
130	~(0x3F << 14);
131	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
132	~(DIP \| DS1620_DQ);
133	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) \|=
134	(DS1620_RES \| DS1620_CLK);
135	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
136	~DS1620_TLOW;
137	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) \|=
138	(PWR_OFF \| BUZZER \| FP_DATA_TRI);
139
140	init_done = 1;
141	debug("sm501_gpio_init: done.\n");
142
143	return 0;
144	}
145
146
147	/*
148	* dip - read Config Inputs
149	*
150	* read and prints the dip switch
151	* and/or external config inputs (4bits) 0...0x0F
152	*/
153	int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
154	{
155	vu_long rc = 0;
156
157	sm501_gpio_init ();
158
159	/* read dip switch */
160	rc = (vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
161	rc = ~rc;
162	rc &= DIP;
163	rc = (int) (rc >> 24);
164
165	/* plausibility check */
166	if (rc > 0x0F)
167	return -1;
168
169	printf ("0x%lx\n", rc);
170	return 0;
171	}
172
173	U_BOOT_CMD (dip, 1, 1, cmd_dip,
174	"read dip switch and config inputs",
175	"\n"
176	" - prints the state of the dip switch and/or\n"
177	" external configuration inputs as hex value.\n"
178	" - \"Config 1\" is the LSB");
179
180
181	/*
182	* buz - turns Buzzer on/off
183	*/
184	#ifdef CONFIG_BC3450_BUZZER
185	static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
186	{
187	if (argc != 2) {
188	printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
189	return 1;
190	}
191
192	sm501_gpio_init ();
193
194	if (strncmp (argv[1], "on", 2) == 0) {
195	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
196	~(BUZZER);
197	return 0;
198	} else if (strncmp (argv[1], "off", 3) == 0) {
199	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) \|=
200	BUZZER;
201	return 0;
202	}
203	printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
204	return 1;
205	}
206
207	U_BOOT_CMD (buz, 2, 1, cmd_buz,
208	"turns buzzer on/off",
209	"\n" "buz <on/off>\n" " - turns the buzzer on or off");
210	#endif /* CONFIG_BC3450_BUZZER */
211
212
213	/*
214	* fp - front panel commands
215	*/
216	static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
217	{
218	sm501_gpio_init ();
219
220	if (strncmp (argv[1], "on", 2) == 0) {
221	/* turn on VDD first */
222	(vu_long ) (SM501_MMIO_BASE +
223	SM501_PANEL_DISPLAY_CONTROL) \|= SM501_PDC_VDDEN;
224	udelay (1000);
225	/* then put data on */
226	(vu_long ) (SM501_MMIO_BASE +
227	SM501_PANEL_DISPLAY_CONTROL) \|= SM501_PDC_DATA;
228	/* wait some time and enable backlight */
229	udelay (1000);
230	(vu_long ) (SM501_MMIO_BASE +
231	SM501_PANEL_DISPLAY_CONTROL) \|= SM501_PDC_BIAS;
232	udelay (1000);
233	(vu_long ) (SM501_MMIO_BASE +
234	SM501_PANEL_DISPLAY_CONTROL) \|= SM501_PDC_FPEN;
235	return 0;
236	} else if (strncmp (argv[1], "off", 3) == 0) {
237	/* turn off the backlight first */
238	(vu_long ) (SM501_MMIO_BASE +
239	SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
240	udelay (1000);
241	(vu_long ) (SM501_MMIO_BASE +
242	SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
243	udelay (200000);
244	/* wait some time, then remove data */
245	(vu_long ) (SM501_MMIO_BASE +
246	SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
247	udelay (1000);
248	/* and remove VDD last */
249	(vu_long ) (SM501_MMIO_BASE +
250	SM501_PANEL_DISPLAY_CONTROL) &=
251	~SM501_PDC_VDDEN;
252	return 0;
253	} else if (strncmp (argv[1], "bl", 2) == 0) {
254	/* turn on/off backlight only */
255	if (strncmp (argv[2], "on", 2) == 0) {
256	(vu_long ) (SM501_MMIO_BASE +
257	SM501_PANEL_DISPLAY_CONTROL) \|=
258	SM501_PDC_BIAS;
259	udelay (1000);
260	(vu_long ) (SM501_MMIO_BASE +
261	SM501_PANEL_DISPLAY_CONTROL) \|=
262	SM501_PDC_FPEN;
263	return 0;
264	} else if (strncmp (argv[2], "off", 3) == 0) {
265	(vu_long ) (SM501_MMIO_BASE +
266	SM501_PANEL_DISPLAY_CONTROL) &=
267	~SM501_PDC_FPEN;
268	udelay (1000);
269	(vu_long ) (SM501_MMIO_BASE +
270	SM501_PANEL_DISPLAY_CONTROL) &=
271	~SM501_PDC_BIAS;
272	return 0;
273	}
274	}
275	#ifdef CONFIG_BC3450_CRT
276	else if (strncmp (argv[1], "crt", 3) == 0) {
277	/* enables/disables the crt output (debug only) */
278	if (strncmp (argv[2], "on", 2) == 0) {
279	(vu_long ) (SM501_MMIO_BASE +
280	SM501_CRT_DISPLAY_CONTROL) \|=
281	(SM501_CDC_TE \| SM501_CDC_E);
282	(vu_long ) (SM501_MMIO_BASE +
283	SM501_CRT_DISPLAY_CONTROL) &=
284	~SM501_CDC_SEL;
285	return 0;
286	} else if (strncmp (argv[2], "off", 3) == 0) {
287	(vu_long ) (SM501_MMIO_BASE +
288	SM501_CRT_DISPLAY_CONTROL) &=
289	~(SM501_CDC_TE \| SM501_CDC_E);
290	(vu_long ) (SM501_MMIO_BASE +
291	SM501_CRT_DISPLAY_CONTROL) \|=
292	SM501_CDC_SEL;
293	return 0;
294	}
295	}
296	#endif /* CONFIG_BC3450_CRT */
297	printf ("Usage:%s\n", cmdtp->help);
298	return 1;
299	}
300
301	U_BOOT_CMD (fp, 3, 1, cmd_fp,
302	"front panes access functions",
303	"\n"
304	"fp bl <on/off>\n"
305	" - turns the CCFL backlight of the display on/off\n"
306	"fp <on/off>\n" " - turns the whole display on/off"
307	#ifdef CONFIG_BC3450_CRT
308	"\n"
309	"fp crt <on/off>\n"
310	" - enables/disables the crt output (debug only)"
311	#endif /* CONFIG_BC3450_CRT */
312	);
313
314	/*
315	* temp - DS1620 thermometer
316	*/
317	/* GERSYS BC3450 specific functions */
318	static inline void bc_ds1620_set_clk (int clk)
319	{
320	if (clk)
321	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) \|=
322	DS1620_CLK;
323	else
324	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
325	~DS1620_CLK;
326	}
327
328	static inline void bc_ds1620_set_data (int dat)
329	{
330	if (dat)
331	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) \|=
332	DS1620_DQ;
333	else
334	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
335	~DS1620_DQ;
336	}
337
338	static inline int bc_ds1620_get_data (void)
339	{
340	vu_long rc;
341
342	rc = (vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
343	rc &= DS1620_DQ;
344	if (rc != 0)
345	rc = 1;
346	return (int) rc;
347	}
348
349	static inline void bc_ds1620_set_data_dir (int dir)
350	{
351	if (dir) /* in */
352	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
353	else /* out */
354	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) \|= DS1620_DQ;
355	}
356
357	static inline void bc_ds1620_set_reset (int res)
358	{
359	if (res)
360	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) \|= DS1620_RES;
361	else
362	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
363	}
364
365	/* hardware independent functions */
366	static void ds1620_send_bits (int nr, int value)
367	{
368	int i;
369
370	for (i = 0; i < nr; i++) {
371	bc_ds1620_set_data (value & 1);
372	bc_ds1620_set_clk (0);
373	udelay (1);
374	bc_ds1620_set_clk (1);
375	udelay (1);
376
377	value >>= 1;
378	}
379	}
380
381	static unsigned int ds1620_recv_bits (int nr)
382	{
383	unsigned int value = 0, mask = 1;
384	int i;
385
386	bc_ds1620_set_data (0);
387
388	for (i = 0; i < nr; i++) {
389	bc_ds1620_set_clk (0);
390	udelay (1);
391
392	if (bc_ds1620_get_data ())
393	value \|= mask;
394
395	mask <<= 1;
396
397	bc_ds1620_set_clk (1);
398	udelay (1);
399	}
400
401	return value;
402	}
403
404	static void ds1620_out (int cmd, int bits, int value)
405	{
406	bc_ds1620_set_clk (1);
407	bc_ds1620_set_data_dir (0);
408
409	bc_ds1620_set_reset (0);
410	udelay (1);
411	bc_ds1620_set_reset (1);
412
413	udelay (1);
414
415	ds1620_send_bits (8, cmd);
416	if (bits)
417	ds1620_send_bits (bits, value);
418
419	udelay (1);
420
421	/* go stand alone */
422	bc_ds1620_set_data_dir (1);
423	bc_ds1620_set_reset (0);
424	bc_ds1620_set_clk (0);
425
426	udelay (10000);
427	}
428
429	static unsigned int ds1620_in (int cmd, int bits)
430	{
431	unsigned int value;
432
433	bc_ds1620_set_clk (1);
434	bc_ds1620_set_data_dir (0);
435
436	bc_ds1620_set_reset (0);
437	udelay (1);
438	bc_ds1620_set_reset (1);
439
440	udelay (1);
441
442	ds1620_send_bits (8, cmd);
443
444	bc_ds1620_set_data_dir (1);
445	value = ds1620_recv_bits (bits);
446
447	/* go stand alone */
448	bc_ds1620_set_data_dir (1);
449	bc_ds1620_set_reset (0);
450	bc_ds1620_set_clk (0);
451
452	return value;
453	}
454
455	static int cvt_9_to_int (unsigned int val)
456	{
457	if (val & 0x100)
458	val \|= 0xfffffe00;
459
460	return val;
461	}
462
463	/* set thermostate thresholds */
464	static void ds1620_write_state (struct therm *therm)
465	{
466	ds1620_out (THERM_WRITE_TL, 9, therm->lo);
467	ds1620_out (THERM_WRITE_TH, 9, therm->hi);
468	ds1620_out (THERM_START_CONVERT, 0, 0);
469	}
470
471	static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
472	{
473	int i;
474	struct therm therm;
475
476	sm501_gpio_init ();
477
478	/* print temperature */
479	if (argc == 1) {
480	i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
481	printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
482	return 0;
483	}
484
485	/* set to default operation */
486	if (strncmp (argv[1], "set", 3) == 0) {
487	if (strncmp (argv[2], "default", 3) == 0) {
488	therm.hi = +88;
489	therm.lo = -20;
490	therm.hi <<= 1;
491	therm.lo <<= 1;
492	ds1620_write_state (&therm);
493	ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
494	return 0;
495	}
496	}
497
498	printf ("Usage:%s\n", cmdtp->help);
499	return 1;
500	}
501
502	U_BOOT_CMD (temp, 3, 1, cmd_temp,
503	"print current temperature",
504	"\n" "temp\n" " - print current temperature");
505
506	#ifdef CONFIG_BC3450_CAN
507	/*
508	* Initialise CAN interface
509	*
510	* return 1 on CAN initialization failure
511	* return 0 if no failure
512	*/
513	int can_init (void)
514	{
515	static int init_done = 0;
516	int i;
517	struct mpc5xxx_mscan *can1 =
518	(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
519	struct mpc5xxx_mscan *can2 =
520	(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
521
522	/* GPIO configuration of the CAN pins is done in BC3450.h */
523
524	if (!init_done) {
525	/* init CAN 1 */
526	can1->canctl1 \|= 0x80; /* CAN enable */
527	udelay (100);
528
529	i = 0;
530	can1->canctl0 \|= 0x02; /* sleep mode */
531	/* wait until sleep mode reached */
532	while (!(can1->canctl1 & 0x02)) {
533	udelay (10);
534	i++;
535	if (i == 10) {
536	printf ("%s: CAN1 initialize error, "
537	"can not enter sleep mode!\n",
538	__FUNCTION__);
539	return 1;
540	}
541	}
542	i = 0;
543	can1->canctl0 = 0x01; /* enter init mode */
544	/* wait until init mode reached */
545	while (!(can1->canctl1 & 0x01)) {
546	udelay (10);
547	i++;
548	if (i == 10) {
549	printf ("%s: CAN1 initialize error, "
550	"can not enter init mode!\n",
551	__FUNCTION__);
552	return 1;
553	}
554	}
555	can1->canctl1 = 0x80;
556	can1->canctl1 \|= 0x40;
557	can1->canbtr0 = 0x0F;
558	can1->canbtr1 = 0x7F;
559	can1->canidac &= ~(0x30);
560	can1->canidar1 = 0x00;
561	can1->canidar3 = 0x00;
562	can1->canidar5 = 0x00;
563	can1->canidar7 = 0x00;
564	can1->canidmr0 = 0xFF;
565	can1->canidmr1 = 0xFF;
566	can1->canidmr2 = 0xFF;
567	can1->canidmr3 = 0xFF;
568	can1->canidmr4 = 0xFF;
569	can1->canidmr5 = 0xFF;
570	can1->canidmr6 = 0xFF;
571	can1->canidmr7 = 0xFF;
572
573	i = 0;
574	can1->canctl0 &= ~(0x01); /* leave init mode */
575	can1->canctl0 &= ~(0x02);
576	/* wait until init and sleep mode left */
577	while ((can1->canctl1 & 0x01) \|\| (can1->canctl1 & 0x02)) {
578	udelay (10);
579	i++;
580	if (i == 10) {
581	printf ("%s: CAN1 initialize error, "
582	"can not leave init/sleep mode!\n",
583	__FUNCTION__);
584	return 1;
585	}
586	}
587
588	/* init CAN 2 */
589	can2->canctl1 \|= 0x80; /* CAN enable */
590	udelay (100);
591
592	i = 0;
593	can2->canctl0 \|= 0x02; /* sleep mode */
594	/* wait until sleep mode reached */
595	while (!(can2->canctl1 & 0x02)) {
596	udelay (10);
597	i++;
598	if (i == 10) {
599	printf ("%s: CAN2 initialize error, "
600	"can not enter sleep mode!\n",
601	__FUNCTION__);
602	return 1;
603	}
604	}
605	i = 0;
606	can2->canctl0 = 0x01; /* enter init mode */
607	/* wait until init mode reached */
608	while (!(can2->canctl1 & 0x01)) {
609	udelay (10);
610	i++;
611	if (i == 10) {
612	printf ("%s: CAN2 initialize error, "
613	"can not enter init mode!\n",
614	__FUNCTION__);
615	return 1;
616	}
617	}
618	can2->canctl1 = 0x80;
619	can2->canctl1 \|= 0x40;
620	can2->canbtr0 = 0x0F;
621	can2->canbtr1 = 0x7F;
622	can2->canidac &= ~(0x30);
623	can2->canidar1 = 0x00;
624	can2->canidar3 = 0x00;
625	can2->canidar5 = 0x00;
626	can2->canidar7 = 0x00;
627	can2->canidmr0 = 0xFF;
628	can2->canidmr1 = 0xFF;
629	can2->canidmr2 = 0xFF;
630	can2->canidmr3 = 0xFF;
631	can2->canidmr4 = 0xFF;
632	can2->canidmr5 = 0xFF;
633	can2->canidmr6 = 0xFF;
634	can2->canidmr7 = 0xFF;
635	can2->canctl0 &= ~(0x01); /* leave init mode */
636	can2->canctl0 &= ~(0x02);
637
638	i = 0;
639	/* wait until init mode left */
640	while ((can2->canctl1 & 0x01) \|\| (can2->canctl1 & 0x02)) {
641	udelay (10);
642	i++;
643	if (i == 10) {
644	printf ("%s: CAN2 initialize error, "
645	"can not leave init/sleep mode!\n",
646	__FUNCTION__);
647	return 1;
648	}
649	}
650	init_done = 1;
651	}
652	return 0;
653	}
654
655	/*
656	* Do CAN test
657	* by sending message between CAN1 and CAN2
658	*
659	* return 1 on CAN failure
660	* return 0 if no failure
661	*/
662	int do_can (char * const argv[])
663	{
664	int i;
665	struct mpc5xxx_mscan *can1 =
666	(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
667	struct mpc5xxx_mscan *can2 =
668	(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
669
670	/* send a message on CAN1 */
671	can1->cantbsel = 0x01;
672	can1->cantxfg.idr[0] = 0x55;
673	can1->cantxfg.idr[1] = 0x00;
674	can1->cantxfg.idr[1] &= ~0x8;
675	can1->cantxfg.idr[1] &= ~0x10;
676	can1->cantxfg.dsr[0] = 0xCC;
677	can1->cantxfg.dlr = 1;
678	can1->cantxfg.tbpr = 0;
679	can1->cantflg = 0x01;
680
681	i = 0;
682	while ((can1->cantflg & 0x01) == 0) {
683	i++;
684	if (i == 10) {
685	printf ("%s: CAN1 send timeout, "
686	"can not send message!\n", __FUNCTION__);
687	return 1;
688	}
689	udelay (1000);
690	}
691	udelay (1000);
692
693	i = 0;
694	while (!(can2->canrflg & 0x01)) {
695	i++;
696	if (i == 10) {
697	printf ("%s: CAN2 receive timeout, "
698	"no message received!\n", __FUNCTION__);
699	return 1;
700	}
701	udelay (1000);
702	}
703
704	if (can2->canrxfg.dsr[0] != 0xCC) {
705	printf ("%s: CAN2 receive error, "
706	"data mismatch!\n", __FUNCTION__);
707	return 1;
708	}
709
710	/* send a message on CAN2 */
711	can2->cantbsel = 0x01;
712	can2->cantxfg.idr[0] = 0x55;
713	can2->cantxfg.idr[1] = 0x00;
714	can2->cantxfg.idr[1] &= ~0x8;
715	can2->cantxfg.idr[1] &= ~0x10;
716	can2->cantxfg.dsr[0] = 0xCC;
717	can2->cantxfg.dlr = 1;
718	can2->cantxfg.tbpr = 0;
719	can2->cantflg = 0x01;
720
721	i = 0;
722	while ((can2->cantflg & 0x01) == 0) {
723	i++;
724	if (i == 10) {
725	printf ("%s: CAN2 send error, "
726	"can not send message!\n", __FUNCTION__);
727	return 1;
728	}
729	udelay (1000);
730	}
731	udelay (1000);
732
733	i = 0;
734	while (!(can1->canrflg & 0x01)) {
735	i++;
736	if (i == 10) {
737	printf ("%s: CAN1 receive timeout, "
738	"no message received!\n", __FUNCTION__);
739	return 1;
740	}
741	udelay (1000);
742	}
743
744	if (can1->canrxfg.dsr[0] != 0xCC) {
745	printf ("%s: CAN1 receive error 0x%02x\n",
746	__FUNCTION__, (can1->canrxfg.dsr[0]));
747	return 1;
748	}
749
750	return 0;
751	}
752	#endif /* CONFIG_BC3450_CAN */
753
754	/*
755	* test - BC3450 HW test routines
756	*/
757	int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
758	{
759	#ifdef CONFIG_BC3450_CAN
760	int rcode;
761
762	can_init ();
763	#endif /* CONFIG_BC3450_CAN */
764
765	sm501_gpio_init ();
766
767	if (argc != 2) {
768	printf ("Usage:%s\n", cmdtp->help);
769	return 1;
770	}
771
772	if (strncmp (argv[1], "unit-off", 8) == 0) {
773	printf ("waiting 2 seconds...\n");
774	udelay (2000000);
775	(vu_long ) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
776	~PWR_OFF;
777	return 0;
778	}
779	#ifdef CONFIG_BC3450_CAN
780	else if (strncmp (argv[1], "can", 2) == 0) {
781	rcode = do_can (argv);
782	if (simple_strtoul (argv[2], NULL, 10) == 2) {
783	if (rcode == 0)
784	printf ("OK\n");
785	else
786	printf ("Error\n");
787	}
788	return rcode;
789	}
790	#endif /* CONFIG_BC3450_CAN */
791
792	printf ("Usage:%s\n", cmdtp->help);
793	return 1;
794	}
795
796	U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
797	#ifdef CONFIG_BC3450_CAN
798	"test can\n"
799	" - connect CAN1 (X8) with CAN2 (X9) for this test\n"
800	#endif /* CONFIG_BC3450_CAN */
801	"test unit-off\n"
802	" - turns off the BC3450 unit\n"
803	" WARNING: Unsaved environment variables will be lost!"
804	);
805	#endif
806		1	/*

board/bc3450/mt48lc16m16a2-75.h

View file @ f8296d6

1	/*		File was deleted
2	* (C) Copyright 2004
3	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4	*
5	* SPDX-License-Identifier: GPL-2.0+
6	*/
7
8	#define SDRAM_DDR 0 /* is SDR */
9
10	/* Settings for XLB = 132 MHz */
11	#define SDRAM_MODE 0x00CD0000
12	/* #define SDRAM_MODE 0x008D0000 / / CAS latency 2 */
13	#define SDRAM_CONTROL 0x504F0000
14	#define SDRAM_CONFIG1 0xD2322800
15	/* #define SDRAM_CONFIG1 0xD2222800 / / CAS latency 2 */
16	/#define SDRAM_CONFIG1 0xD7322800 / /* SDRAM controller bug workaround */
17	#define SDRAM_CONFIG2 0x8AD70000
18	/#define SDRAM_CONFIG2 0xDDD70000 / /* SDRAM controller bug workaround */
19		1	/*

configs/BC3450_defconfig

View file @ f8296d6

1	CONFIG_PPC=y		File was deleted
2	CONFIG_MPC5xxx=y
3	CONFIG_TARGET_BC3450=y
4		1	CONFIG_PPC=y

doc/README.scrapyard

Diff comments View file @ f8296d6

 Over time, support for more and more boards gets added to U-Boot -
 while other board support code dies a silent death caused by
 negligence in combination with ordinary bitrot.  Sometimes this goes
 by unnoticed, but often build errors will result.  If nobody cares any
 more to resolve such problems, then the code is really dead and will
 be removed from the U-Boot source tree.  The remainders rest in piece
 in the imperishable depths of the git history.  This document tries to
 maintain a list of such former fellows, so archaeologists can check
 easily if there is something they might want to dig for...
 The list should be sorted in reverse chronological order.
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-hawkboard        arm         arm926ejs      -           -           Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+BC3450           powerpc     mpc5xxx        -           -
-tnetv107x        arm         arm1176        -           -           Chan-Taek Park <c-park@ti.com>
+hawkboard        arm         arm926ejs      cb957cda    2015-02-24  Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-a320evb          arm         arm920t        -           -           Po-Yu Chuang <ratbert@faraday-tech.com>
+tnetv107x        arm         arm1176        50b82c4b    2015-02-24  Chan-Taek Park <c-park@ti.com>
-cm4008           arm         arm920t        -           -           Greg Ungerer <greg.ungerer@opengear.com>
+a320evb          arm         arm920t        29fc6f24    2015-02-24  Po-Yu Chuang <ratbert@faraday-tech.com>
-cm41xx           arm         arm920t        -           -
+cm4008           arm         arm920t        a2f39e83    2015-02-24  Greg Ungerer <greg.ungerer@opengear.com>
-dkb              arm         arm926ejs      -           -           Lei Wen <leiwen@marvell.com>
+cm41xx           arm         arm920t        a2f39e83    2015-02-24
-jadecpu          arm         arm926ejs      -           -           Matthias Weisser <weisserm@arcor.de>
+dkb              arm         arm926ejs      346cfba4    2015-02-24  Lei Wen <leiwen@marvell.com>
+jadecpu          arm         arm926ejs      41fbbbbc    2015-02-24  Matthias Weisser <weisserm@arcor.de>
 icecube_5200     powerpc     mpc5xxx        37b608a5    2015-01-23  Wolfgang Denk <wd@denx.de>
 Lite5200         powerpc     mpc5xxx        37b608a5    2015-01-23
 cpci5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 mecp5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 pf5200           powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 PM520            powerpc     mpc5xxx        a258e732    2015-01-23  Josef Wagner <Wagner@Microsys.de>
 Total5200        powerpc     mpc5xxx        ad734f7d    2015-01-23
 CATcenter        powerpc     ppc4xx         5344cc1a    2015-01-23
 PPChameleonEVB   powerpc     ppc4xx         5344cc1a    2015-01-23  Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 P2020DS          powerpc     mpc85xx        168dcc6c    2015-01-23
 P2020COME        powerpc     mpc85xx        89123536    2015-01-23  Ira W. Snyder <iws@ovro.caltech.edu>
 P2020RDB         powerpc     mpc85xx        743d4815    2015-01-23  Poonam Aggrwal <poonam.aggrwal@freescale.com>
 P2010RDB         powerpc     mpc85xx        743d4815    2015-01-23
 P1020RDB         powerpc     mpc85xx        743d4815    2015-01-23
 P1011RDB         powerpc     mpc85xx        743d4815    2015-01-23
 MPC8360EMDS      powerpc     mpc83xx        8d1e3cb1    2015-01-23  Dave Liu <daveliu@freescale.com>
 MPC8360ERDK      powerpc     mpc83xx        8d1e3cb1    2015-01-23  Anton Vorontsov <avorontsov@ru.mvista.com>
 P3G4             powerpc     74xx_7xx       d928664f    2015-01-16  Wolfgang Denk <wd@denx.de>
 ZUMA             powerpc     74xx_7xx       d928664f    2015-01-16  Nye Liu <nyet@zumanetworks.com>
 ppmc7xx          powerpc     74xx_7xx       d928664f    2015-01-16
 ELPPC            powerpc     74xx_7xx       d928664f    2015-01-16
 mpc7448hpc2      powerpc     74xx_7xx       d928664f    2015-01-16  Roy Zang <tie-fei.zang@freescale.com>
 CPCI405          ppc4xx      405gp          5f1459dc    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 CPCI405DT        ppc4xx      405gpr         5f1459dc    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 CPCI405AB        ppc4xx      405gpr         5f1459dc    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 G2000            ppc4xx      405ep          5f8f6294    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 WUH405           ppc4xx      405ep          fc88a5bf    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 VOH405           ppc4xx      405ep          807db88b    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 PMC405           ppc4xx      405gp          d5263304    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 PCI405           ppc4xx      405gp          dbe7bb0d    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 OCRTC            ppc4xx      405gpr         cc6e715f    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 HUB405           ppc4xx      405ep          e434d5d7    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 HH405            ppc4xx      405ep          843125da    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 DU440            ppc4xx      440epx         7ac9d47a    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 DU405            ppc4xx      405gpr         bc114076    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 DP405            ppc4xx      405ep          9a4018e0    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 CPCIISER4        ppc4xx      405gp          37057260    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 CMS700           ppc4xx      405ep          2404124c    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 ASH405           ppc4xx      405ep          b5e7c84f    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 AR405            ppc4xx      405gpr         61b57c4a    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 APC405           ppc4xx      405gpr         2b8a04e5    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 TASREG           m68k        mcf52x2        cbdc662a    2015-01-13  Matthias Fuchs <matthias.fuchs@esd.eu>
 A3000            powerpc     mpc824x        d622ac39    2015-01-05
 CPC45            powerpc     mpc824x        d622ac39    2015-01-05  Josef Wagner <Wagner@Microsys.de>
 CU824            powerpc     mpc824x        d622ac39    2015-01-05  Wolfgang Denk <wd@denx.de>
 eXalion          powerpc     mpc824x        d622ac39    2015-01-05  Torsten Demke <torsten.demke@fci.com>
 MVBLUE           powerpc     mpc824x        d622ac39    2015-01-05
 MUSENKI          powerpc     mpc824x        d622ac39    2015-01-05  Jim Thompson <jim@musenki.com>
 Sandpoint8240    powerpc     mpc824x        d622ac39    2015-01-05  Wolfgang Denk <wd@denx.de>
 Sandpoint8245    powerpc     mpc824x        d622ac39    2015-01-05  Jim Thompson <jim@musenki.com>
 utx8245          powerpc     mpc824x        d622ac39    2015-01-05  Greg Allen <gallen@arlut.utexas.edu>
 atc              powerpc     mpc8260        9067b300    2015-01-05  Wolfgang Denk <wd@denx.de>
 CPU86            powerpc     mpc8260        f7e1af86    2015-01-05  Wolfgang Denk <wd@denx.de>
 CPU87            powerpc     mpc8260        f7e1af86    2015-01-05
 ep82xxm          powerpc     mpc8260        e2b19629    2015-01-05
 gw8260           powerpc     mpc8260        8eecbaf3    2015-01-05  Oliver Brown <obrown@adventnetworks.com>
 IPHASE4539       powerpc     mpc8260        87882f57    2015-01-05  Wolfgang Grandegger <wg@denx.de>
 muas3001         powerpc     mpc8260        d2fd1d66    2015-01-05  Heiko Schocher <hs@denx.de>
 PM825            powerpc     mpc8260        dc0b2fb4    2015-01-05  Wolfgang Denk <wd@denx.de>
 PM826            powerpc     mpc8260        dc0b2fb4    2015-01-05  Wolfgang Denk <wd@denx.de>
 PM828            powerpc     mpc8260        dc0b2fb4    2015-01-05
 MPC8266ADS       powerpc     mpc8260        b3a2bbe1    2015-01-05  Rune Torgersen <runet@innovsys.com>
 VoVPN-GW         powerpc     mpc8260        cc90905f    2015-01-05
 ep8260           powerpc     mpc8260        4ad015ba    2015-01-05  Frank Panno <fpanno@delphintech.com>
 ppmc8260         powerpc     mpc8260        793116d2    2015-01-05  Brad Kemp <Brad.Kemp@seranoa.com>
 sacsng           powerpc     mpc8260        b35c0ad6    2015-01-05  Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 cogent_mpc8260   powerpc     mpc8260        d19f6a60    2015-01-05  Murray Jensen <Murray.Jensen@csiro.au>
 cogent_8xx       powerpc     mpc8xx         d19f6a60    2015-01-05  Murray Jensen <Murray.Jensen@csiro.au>
 ESTEEM192E       powerpc     mpc8xx         af0e3514    2015-01-05  Conn Clark <clark@esteem.com>
 IP860            powerpc     mpc8xx         5ec71100    2015-01-05  Wolfgang Denk <wd@denx.de>
 IVML24           powerpc     mpc8xx         ca620cd1    2015-01-05  Wolfgang Denk <wd@denx.de>
 IVMS8            powerpc     mpc8xx         ca620cd1    2015-01-05  Wolfgang Denk <wd@denx.de>
 lwmon            powerpc     mpc8xx         acc2372d    2015-01-05  Wolfgang Denk <wd@denx.de>
 NETVIA           powerpc     mpc8xx         f017cd7f    2015-01-05  Pantelis Antoniou <panto@intracom.gr>
 R360MPI          powerpc     mpc8xx         79cbecb8    2015-01-05  Wolfgang Denk <wd@denx.de>
 RRvision         powerpc     mpc8xx         8737fc75    2015-01-05  Wolfgang Denk <wd@denx.de>
 SPD823TS         powerpc     mpc8xx         72ba368f    2015-01-05  Wolfgang Denk <wd@denx.de>
 KUP4K            powerpc     mpc8xx         4317d070    2015-01-05  Klaus Heydeck <heydeck@kieback-peter.de>
 KUP4X            powerpc     mpc8xx         4317d070    2015-01-05  Klaus Heydeck <heydeck@kieback-peter.de>
 ELPT860          powerpc     mpc8xx         3c5b20f1    2015-01-05  The LEOX team <team@leox.org>
 hmi1001          powerpc     mpc5xxx        ceaf499b    2015-01-05
 mucmc52          powerpc     mpc5xxx        ceaf499b    2015-01-05  Heiko Schocher <hs@denx.de>
 uc101            powerpc     mpc5xxx        ceaf499b    2015-01-05  Heiko Schocher <hs@denx.de>
 uc100            powerpc     mpc8xx         ceaf499b    2015-01-05  Stefan Roese <sr@denx.de>
 FPS850L          powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 FPS860L          powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 NSCU             powerpc     mpc8xx         5d2a5ef7    2015-01-05
 SM850            powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 TK885D           powerpc     mpc8xx         5d2a5ef7    2015-01-05
 virtlab2         powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 hermes           powerpc     mpc8xx         36da51e     2014-12-08  Wolfgang Denk <wd@denx.de>
 PRS200		 powerpc     mpc5200	    ecfdcee	2014-11-12
 MCC200		 powerpc     mpc5200	    ecfdcee     2014-11-12
 TOP5200		 powerpc     mpc5200	    d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TOP860		 powerpc     mpc860	    d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TOP9000		 arm	     at91sam9xeXXX  d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TQM8272          powerpc     mpc8260        f06f9a1     2014-10-27  Wolfgang Denk <wd@denx.de>
 TQM8260          powerpc     mpc8260        ccc1950     2014-10-27  Wolfgang Denk <wd@denx.de>
 IDS8247          powerpc     mpc8260        6afb357     2014-10-27  Heiko Schocher <hs@denx.de>
 HWW1U1A          powerpc     mpc85xx        4109cb0     2014-10-27  Kyle Moffett <Kyle.D.Moffett@boeing.com>
 hymod            powerpc     mpc8260        5038d7f     2014-10-27  Murray Jensen <Murray.Jensen@csiro.au>
 MHPC             powerpc     mpc8xx         1655f9f     2014-10-27  Frank Gottschling <fgottschling@eltec.de>
 ICU862           powerpc     mpc8xx         4af5f0f     2014-10-27  Wolfgang Denk <wd@denx.de>
 CPCI750		 powerpc     74xx_7xx	    03b0040	2014-10-27  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 DB64360		 powerpc     74xx_7xx	    03b0040	2014-10-27
 DB64460		 powerpc     74xx_7xx	    03b0040	2014-10-27
 p3m750		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
 p3m7448		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
 MVBC_P           powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 MVSMR            powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 MERGERBOX        powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 MVBLM7           powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 bluestone        powerpc     ppc4xx         9ed3246	2014-10-10  Tirumala Marri <tmarri@apm.com>
 CRAYL1           powerpc     ppc4xx         1521cdc	2014-10-10  David Updegraff <dave@cray.com>
 KAREF            powerpc     ppc4xx         dc9617e	2014-10-10  Travis Sawyer <travis.sawyer@sandburst.com>
 METROBOX         powerpc     ppc4xx         dc9617e	2014-10-10  Travis Sawyer <travis.sawyer@sandburst.com>
 PK1C20           nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 PCI5441          nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 flagadm          powerpc     mpc8xx         aec6f8c5    2014-08-22  Kári Davíðsson <kd@flaga.is>
 gen860t          powerpc     mpc8xx         6bde1ec1    2014-08-22  Keith Outwater <Keith_Outwater@mvis.com>
 sixnet           powerpc     mpc8xx         4723ce49    2014-08-22  Dave Ellis <DGE@sixnetio.com>
 svm_sc8xx        powerpc     mpc8xx         d1a4aafd    2014-08-22  John Zhan <zhanz@sinovee.com>
 stxxtc           powerpc     mpc8xx         0ace4d9d    2014-08-22  Dan Malek <dan@embeddedalley.com>
 omap5912osk      arm         arm926ejs      62d636aa    2014-08-22  Rishi Bhattacharya <rishi@ti.com>
 p1023rds         powerpc     mpc85xx        d0bc5140    2014-07-22  Roy Zang <tie-fei.zang@freescale.com>
 spc1920          powerpc     mpc8xx         98ad54be    2014-07-07
 v37              powerpc     mpc8xx         b8c1438a    2014-07-07
 fads             powerpc     mpc8xx         03f9d7d1    2014-07-07
 netphone         powerpc     mpc8xx         c51c1c9a    2014-07-07
 netta2           powerpc     mpc8xx         c51c1c9a    2014-07-07
 netta            powerpc     mpc8xx         c51c1c9a    2014-07-07
 rbc823           powerpc     mpc8xx         c750b9c0    2014-07-07
 quantum          powerpc     mpc8xx         0657e46e    2014-07-07
 RPXlite_dw       powerpc     mpc8xx         0657e46e    2014-07-07
 qs850            powerpc     mpc8xx         dab0f762    2014-07-07
 qs860t           powerpc     mpc8xx         dab0f762    2014-07-07
 simpc8313        powerpc     mpc83xx        7445207f    2014-06-05  Ron Madrid <info@sheldoninst.com>
 hidden_dragon    powerpc     mpc824x        3fe1a854    2014-05-30  Yusdi Santoso <yusdi_santoso@adaptec.com>
 debris           powerpc     mpc824x        7edb1f7b    2014-05-30  Sangmoon Kim <dogoil@etinsys.com>
 kvme080          powerpc     mpc824x        2868f862    2014-05-30  Sangmoon Kim <dogoil@etinsys.com>
 ep8248           powerpc     mpc8260        49ad566d    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 ispan            powerpc     mpc8260        80bae39a    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 rattler          powerpc     mpc8260        d0664db4    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 zpc1900          powerpc     mpc8260        6f80bb48    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 mpc8260ads       powerpc     mpc8260        facb6725    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 adder            powerpc     mpc8xx         373a9788    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 quad100hd        powerpc     ppc405ep       3569571d    2014-05-30  Gary Jennejohn <gljennjohn@googlemail.com>
 incaip           mips        mips32         538cf92c    2014-04-20  Wolfgang Denk <wd@denx.de>
 lubbock          arm         pxa            36bf57b     2014-04-18  Kyle Harris <kharris@nexus-tech.net>
 EVB64260	 powerpc     mpc824x        bb3aef9	2014-04-18
 MOUSSE           powerpc     mpc824x        03f2ecc     2014-04-18
 rsdproto         powerpc     mpc8260        8b043e6     2014-04-18
 RPXsuper         powerpc     mpc8260        0ebf5f5     2014-04-18
 RPXClassic       powerpc     mpc8xx         4fb3925     2014-04-18
 RPXlite          powerpc     mpc8xx         4fb3925     2014-04-18
 FADS		 powerpc     mpc8xx	    aa6e1e4	2014-04-18
 genietv          powerpc     mpc8xx         b8a49bd     2014-04-18
 mbx8xx           powerpc     mpc8xx         d6b11fd     2014-04-18
 nx823            powerpc     mpc8xx         a146e8b     2014-04-18
 idmr             m68k        mcf52x2        ba650e9b    2014-01-28
 M5271EVB         m68k        mcf52x2        ba650e9b    2014-01-28
 dvl_host         arm         ixp            e317de6b    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux4           arm         ixp            6ff7aafa    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux3           arm         ixp            38da33f3    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux2           arm         ixp            13e0ee7f    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux1           arm         ixp            373ee048    2014-01-28  Michael Schwingen <michael@schwingen.org>
 mx1ads           arm         arm920t        e570aca9    2014-01-13
 mini2440         arm         arm920t        af5b9b1f    2014-01-13  Gabriel Huau <contact@huau-gabriel.fr>
 omap730p2        arm         arm926ejs      79c5c08d    2013-11-11
 pn62             powerpc     mpc824x        649acfe1    2013-11-11  Wolfgang Grandegger <wg@grandegger.com>
 pdnb3            arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 scpu             arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 omap1510inn      arm         arm925t        0610a16     2013-09-23  Kshitij Gupta <kshitij@ti.com>
 CANBT            powerpc     405CR          fb8f4fd     2013-08-07  Matthias Fuchs <matthias.fuchs@esd.eu>
 omap2420h4       arm         omap24xx       7f5eef9     2013-06-04  Richard Woodruff <r-woodruff2@ti.com>
 Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
 Yukon8220        powerpc     mpc8220        d6ed322     2013-05-11
 sorcery          powerpc     mpc8220        d6ed322     2013-05-11
 smdk6400         arm         arm1176        52587f1     2013-04-12  Zhong Hongbo <bocui107@gmail.com>
 ns9750dev        arm         arm926ejs      4cfc611     2013-02-28  Markus Pietrek <mpietrek@fsforth.de>
 eNET             x86         x86            7e8c53d     2013-02-14  Graeme Russ <graeme.russ@gmail.com>
 PCIPPC2          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 PCIPPC6          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 c2mon            powerpc     mpc855         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 EP88x            powerpc     mpc885         1b0757e     2012-10-28
 ETX094           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 IAD210           powerpc     mpc860         1b0757e     2012-10-28  -
 LANTEC           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 SCM              powerpc     mpc8260        1b0757e     2012-10-28  Wolfgang Grandegger <wg@denx.de>
 SX1              arm         arm925t        53c4154     2012-10-26
 TQM85xx          powerpc     MPC85xx        d923a5d     2012-10-04  Stefan Roese <sr@denx.de>
 ADCIOP           powerpc     ppc4xx         99bcad1     2012-09-19  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 DASA_SIM         powerpc     ppc4xx         99bcad1     2012-09-19  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 apollon          arm         omap24xx       535c74f     2012-09-18  Kyungmin Park <kyungmin.park@samsung.com>
 tb0229           mips        mips32         3f3110d     2011-12-12
 rmu              powerpc     MPC850         fb82fd7     2011-12-07  Wolfgang Denk <wd@denx.de>
 OXC              powerpc     MPC8240        309a292     2011-12-07
 BAB7xx           powerpc     MPC740/MPC750  c53043b     2011-12-07  Frank Gottschling <fgottschling@eltec.de>
 xm250            arm         pxa            c477d72     2011-11-25
 pleb2            arm         pxa            d299173     2011-11-25
 cradle           arm         pxa            00c4aca     2011-11-25  Kyle Harris <kharris@nexus-tech.net>
 cerf250          arm         pxa            f13eba6     2011-11-25  Prakash Kumar <prakash@embedx.com>
 mpq101           powerpc     mpc85xx        e877fab     2011-10-23  Alex Dubov <oakad@yahoo.com>
 ixdpg425         arm         ixp            0ca8eb7     2011-09-22  Stefan Roese <sr@denx.de>
 ixdp425          arm         ixp            0ca8eb7     2011-09-22  Kyle Harris <kharris@nexus-tech.net>
 zylonite         arm         pxa            b66521a     2011-09-05
 shannon          arm         sa1100         5df092d     2011-09-05  Rolf Offermanns <rof@sysgo.de>
 modnet50         arm         arm720t        9c62815     2011-09-05  Thomas Elste <info@elste.org>
 lpc2292sodimm    arm         arm720t        d1a067a     2011-09-05
 lart             arm         sa1100         3d57573     2011-09-05  Alex Züpke <azu@sysgo.de>
 impa7            arm         arm720t        c1f8750     2011-09-05  Marius Gröger <mag@sysgo.de>
 gcplus           arm         sa1100         2c650e2     2011-09-05  George G. Davis <gdavis@mvista.com>
 evb4510          arm         arm720t        26e670e     2011-09-05  Curt Brune <curt@cucy.com>
 ep7312           arm         arm720t        c8f63b4     2011-09-05  Marius Gröger <mag@sysgo.de>
 dnp1110          arm         sa1100         fc5e5ce     2011-09-05  Alex Züpke <azu@sysgo.de>
 SMN42            arm         arm720t        6aac646     2011-09-05
 at91rm9200dk     arm         arm920t        1c85752     2011-07-17
 m501sk           arm         arm920t        b1a2bd4     2011-07-17
 kb9202           arm         arm920t        5bd3814     2011-07-17
 csb637           arm         arm920t        d14af08     2011-07-17
 cmc_pu2          arm         arm920t        37a9b4d     2011-07-17
 at91cap9adk      arm         arm926ejs      b550834     2011-07-17  Stelian Pop <stelian@popies.net>
 voiceblue        arm         arm925t        1b793a4     2011-07-17
 smdk2400         arm         arm920t        ad218a8     2011-07-17  Gary Jennejohn <garyj@denx.de>
 sbc2410x         arm         arm920t        1f7f0ed     2011-07-17
 netstar          arm         arm925t        6ea2405     2011-07-17
 mx1fs2           arm         arm920t        6962419     2011-07-17
 lpd7a404         arm         lh7a40x        957731e     2011-07-17
 edb9301          arm         arm920t        716f7ad     2011-07-17
 edb9302          arm         arm920t        716f7ad     2011-07-17
 edb9302a         arm         arm920t        716f7ad     2011-07-17
 edb9307          arm         arm920t        716f7ad     2011-07-17
 edb9307a         arm         arm920t        716f7ad     2011-07-17
 edb9312          arm         arm920t        716f7ad     2011-07-17
 edb9315          arm         arm920t        716f7ad     2011-07-17
 edb9315a         arm         arm920t        716f7ad     2011-07-17
 B2               arm         s3c44b0        5dcf536     2011-07-16  Andrea Scian <andrea.scian@dave-tech.it>
 armadillo        arm         arm720t        be28857     2011-07-16  Rowel Atienza <rowel@diwalabs.com>
 assabet          arm         sa1100         c91e90d     2011-07-16  George G. Davis <gdavis@mvista.com>
 trab             arm         S3C2400        566e5cf     2011-05-01  Gary Jennejohn <garyj@denx.de>
 mp2usb           ARM         AT91RM2900     ee986e2     2011-01-25  Eric Bénard <eric@eukrea.com>
 barco            powerpc     MPC8245        afaa27b     2010-11-23  Marc Leeman <marc.leeman@barco.com>
 ERIC             powerpc     405GP          d9ba451     2010-11-21  Swen Anderson <sand@peppercon.de>
 VoVPN-GW_100MHz  powerpc     MPC8260        26fe3d2     2010-10-24  Juergen Selent <j.selent@elmeg.de>
 xsengine         ARM         PXA2xx         4262a7c     2010-10-20
 wepep250         ARM         PXA2xx         7369478     2010-10-20  Peter Figuli <peposh@etc.sk>
 delta            ARM         PXA2xx         75e2035     2010-10-20
 NC650            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
 CP850            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
 logodl           ARM         PXA2xx         059e778     2010-10-18  August Hoeraendl <august.hoerandl@gmx.at>
 CCM              powerpc     MPC860         dff07e1     2010-10-06  Wolfgang Grandegger <wg@denx.de>
 PCU_E            powerpc     MPC860T        544d97e     2010-10-06  Wolfgang Denk <wd@denx.de>
 spieval          powerpc     MPC5200        69434e4     2010-09-19
 smmaco4          powerpc     MPC5200        9ddc3af     2010-09-19
 HMI10            powerpc     MPC823         77efe35     2010-09-19  Wolfgang Denk <wd@denx.de>
 GTH              powerpc     MPC860         0fe247b     2010-07-17  Thomas Lange <thomas@corelatus.se>
 AmigaOneG3SE     powerpc     74xx_7xx       953b7e6     2010-06-23
 suzaku           microblaze  -              4f18060     2009-10-03  Yasushi Shoji <yashi@atmark-techno.com>
 XUPV2P           microblaze  -              8fab49e     2008-12-10  Michal Simek <monstr@monstr.eu>
 MVS1             powerpc     MPC823         306620b     2008-08-26  Andre Schwarz <andre.schwarz@matrix-vision.de>
 adsvix           ARM         PXA27x         7610db1     2008-07-30  Adrian Filipi <adrian.filipi@eurotech.com>
 R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. Landau <zachary.landau@labxtechnologies.com>
 CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>

include/configs/BC3450.h

View file @ f8296d6

1	/*		File was deleted
2	* -- Version 1.1 --
3	*
4	* (C) Copyright 2003-2005
5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6	*
7	* (C) Copyright 2004-2005
8	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
9	*
10	* (C) Copyright 2005
11	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
12	*
13	* History:
14	* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
15	*
16	* SPDX-License-Identifier: GPL-2.0+
17	*/
18
19	#ifndef __CONFIG_H
20	#define __CONFIG_H
21
22	/*
23	* High Level Configuration Options
24	*/
25	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
26	#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
27
28	#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
29	#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
30	#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
31	#define CONFIG_BC3450_USB 1 /* + USB support */
32	# define CONFIG_FAT 1 /* + FAT support */
33	# define CONFIG_EXT2 1 /* + EXT2 support */
34	#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
35	#undef CONFIG_BC3450_CAN /* + CAN transceiver */
36	#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
37	#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
38	#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
39	#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
40	#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
41
42	/*
43	* Valid values for CONFIG_SYS_TEXT_BASE are:
44	* 0xFC000000 boot low (standard configuration with room for
45	* max 64 MByte Flash ROM)
46	* 0x00100000 boot from RAM (for testing only)
47	*/
48	#ifndef CONFIG_SYS_TEXT_BASE
49	#define CONFIG_SYS_TEXT_BASE 0xFC000000
50	#endif
51
52	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
53
54	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
55
56	/*
57	* Serial console configuration
58	*/
59	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
60	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
61	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
62
63	/*
64	* AT-PS/2 Multiplexer
65	*/
66	#ifdef CONFIG_BC3450_PS2
67	# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
68	# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
69	# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
70	# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
71	# define CONFIG_BOARD_EARLY_INIT_R
72	#endif /* CONFIG_BC3450_PS2 */
73
74	/*
75	* PCI Mapping:
76	* 0x40000000 - 0x4fffffff - PCI Memory
77	* 0x50000000 - 0x50ffffff - PCI IO Space
78	*/
79	# define CONFIG_PCI 1
80	# define CONFIG_PCI_PNP 1
81	/* #define CONFIG_PCI_SCAN_SHOW 1 */
82	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
83
84	#define CONFIG_PCI_MEM_BUS 0x40000000
85	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
86	#define CONFIG_PCI_MEM_SIZE 0x10000000
87
88	#define CONFIG_PCI_IO_BUS 0x50000000
89	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
90	#define CONFIG_PCI_IO_SIZE 0x01000000
91
92	/#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled /
93	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
94	#define CONFIG_NS8382X 1
95
96	/*
97	* Video console
98	*/
99	# define CONFIG_VIDEO
100	# define CONFIG_VIDEO_SM501
101	# define CONFIG_VIDEO_SM501_32BPP
102	# define CONFIG_CFB_CONSOLE
103	# define CONFIG_VIDEO_LOGO
104	# define CONFIG_VGA_AS_SINGLE_DEVICE
105	# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
106	# define CONFIG_VIDEO_SW_CURSOR
107	# define CONFIG_SPLASH_SCREEN
108	# define CONFIG_SYS_CONSOLE_IS_IN_ENV
109
110	/*
111	* Partitions
112	*/
113	#define CONFIG_MAC_PARTITION
114	#define CONFIG_DOS_PARTITION
115	#define CONFIG_ISO_PARTITION
116
117	/*
118	* USB
119	*/
120	#ifdef CONFIG_BC3450_USB
121	# define CONFIG_USB_OHCI
122	# define CONFIG_USB_STORAGE
123	#endif /* CONFIG_BC3450_USB */
124
125	/*
126	* POST support
127	*/
128	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
129	CONFIG_SYS_POST_CPU \| \
130	CONFIG_SYS_POST_I2C)
131
132	#ifdef CONFIG_POST
133	/* preserve space for the post_word at end of on-chip SRAM */
134	# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
135	#endif /* CONFIG_POST */
136
137
138	/*
139	* BOOTP options
140	*/
141	#define CONFIG_BOOTP_BOOTFILESIZE
142	#define CONFIG_BOOTP_BOOTPATH
143	#define CONFIG_BOOTP_GATEWAY
144	#define CONFIG_BOOTP_HOSTNAME
145
146
147	/*
148	* Command line configuration.
149	*/
150	#include <config_cmd_default.h>
151
152	#define CONFIG_CMD_ASKENV
153	#define CONFIG_CMD_DATE
154	#define CONFIG_CMD_DHCP
155	#define CONFIG_CMD_ECHO
156	#define CONFIG_CMD_EEPROM
157	#define CONFIG_CMD_I2C
158	#define CONFIG_CMD_JFFS2
159	#define CONFIG_CMD_MII
160	#define CONFIG_CMD_NFS
161	#define CONFIG_CMD_PING
162	#define CONFIG_CMD_REGINFO
163	#define CONFIG_CMD_SNTP
164	#define CONFIG_CMD_BSP
165
166	#ifdef CONFIG_VIDEO
167	#define CONFIG_CMD_BMP
168	#endif
169
170	#ifdef CONFIG_BC3450_IDE
171	#define CONFIG_CMD_IDE
172	#endif
173
174	#if defined(CONFIG_BC3450_IDE) \|\| defined(CONFIG_BC3450_USB)
175	#ifdef CONFIG_FAT
176	#define CONFIG_CMD_FAT
177	#endif
178
179	#ifdef CONFIG_EXT2
180	#define CONFIG_CMD_EXT2
181	#endif
182	#endif
183
184	#ifdef CONFIG_BC3450_USB
185	#define CONFIG_CMD_USB
186	#endif
187
188	#ifdef CONFIG_PCI
189	#define CONFIG_CMD_PCI
190	#endif
191
192	#ifdef CONFIG_POST
193	#define CONFIG_CMD_DIAG
194	#endif
195
196
197	#define CONFIG_TIMESTAMP /* display image timestamps */
198
199	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
200	# define CONFIG_SYS_LOWBOOT 1
201	#endif
202
203	/*
204	* Autobooting
205	*/
206	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
207	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
208
209	#define CONFIG_PREBOOT "echo;" \
210	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
211	"echo;"
212
213	#undef CONFIG_BOOTARGS
214
215	#define CONFIG_EXTRA_ENV_SETTINGS \
216	"netdev=eth0\0" \
217	"ipaddr=192.168.1.10\0" \
218	"serverip=192.168.1.3\0" \
219	"netmask=255.255.255.0\0" \
220	"hostname=bc3450\0" \
221	"rootpath=/opt/eldk/ppc_6xx\0" \
222	"kernel_addr=fc0a0000\0" \
223	"ramdisk_addr=fc1c0000\0" \
224	"ramargs=setenv bootargs root=/dev/ram rw\0" \
225	"nfsargs=setenv bootargs root=/dev/nfs rw " \
226	"nfsroot=$(serverip):$(rootpath)\0" \
227	"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
228	"addip=setenv bootargs $(bootargs) " \
229	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
230	":$(hostname):$(netdev):off panic=1\0" \
231	"addcons=setenv bootargs $(bootargs) " \
232	"console=ttyS0,$(baudrate) console=tty0\0" \
233	"flash_self=run ramargs addip addcons;" \
234	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
235	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
236	"net_nfs=tftp 200000 $(bootfile); " \
237	"run nfsargs addip addcons; bootm\0" \
238	"ide_nfs=run nfsargs addip addcons; " \
239	"disk 200000 0:1; bootm\0" \
240	"ide_ide=run ideargs addip addcons; " \
241	"disk 200000 0:1; bootm\0" \
242	"usb_self=run usbload; run ramargs addip addcons; " \
243	"bootm 200000 400000\0" \
244	"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
245	"usbboot 400000 0:2\0" \
246	"bootfile=uImage\0" \
247	"load=tftp 200000 $(u-boot)\0" \
248	"u-boot=u-boot.bin\0" \
249	"update=protect off FC000000 FC05FFFF;" \
250	"erase FC000000 FC05FFFF;" \
251	"cp.b 200000 FC000000 $(filesize);" \
252	"protect on FC000000 FC05FFFF\0" \
253	""
254
255	#define CONFIG_BOOTCOMMAND "run flash_self"
256
257	/*
258	* IPB Bus clocking configuration.
259	*/
260	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
261
262	/*
263	* PCI Bus clocking configuration
264	*
265	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
266	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
267	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
268	*/
269	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
270	# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
271	#endif
272
273	/*
274	* I2C configuration
275	*/
276	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
277	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
278
279	/*
280	* I2C clock frequency
281	*
282	* Please notice, that the resulting clock frequency could differ from the
283	* configured value. This is because the I2C clock is derived from system
284	* clock over a frequency divider with only a few divider values. U-boot
285	* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
286	* approximation allways lies below the configured value, never above.
287	*/
288	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
289	#define CONFIG_SYS_I2C_SLAVE 0x7F
290
291	/*
292	* EEPROM configuration for I²C EEPROM M24C32
293	* M24C64 should work also. For other EEPROMs config should be verified.
294	*
295	* The TQM5200 module may hold an EEPROM at address 0x50.
296	*/
297	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
298	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
299	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
300	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
301
302	/*
303	* RTC configuration
304	*/
305	#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
306	# define CONFIG_RTC_M41T11 1
307	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
308	#else
309	# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
310	# define CONFIG_BOARD_EARLY_INIT_R
311	#endif
312
313	/*
314	* Flash configuration
315	*/
316	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
317
318	/* use CFI flash driver if no module variant is spezified */
319	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
320	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
321	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
322	#define CONFIG_SYS_FLASH_EMPTY_INFO
323	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
324	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
325	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
326
327	#if !defined(CONFIG_SYS_LOWBOOT)
328	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
329	#else /* CONFIG_SYS_LOWBOOT */
330	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
331	#endif /* CONFIG_SYS_LOWBOOT */
332	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
333	(= chip selects) */
334	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
335	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
336
337	/* Dynamic MTD partition support */
338	#define CONFIG_CMD_MTDPARTS
339	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
340	#define CONFIG_FLASH_CFI_MTD
341	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
342	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
343	"1408k(kernel)," \
344	"2m(initrd)," \
345	"4m(small-fs)," \
346	"16m(big-fs)," \
347	"8m(misc)"
348
349	/*
350	* Environment settings
351	*/
352	#define CONFIG_ENV_IS_IN_FLASH 1
353	#define CONFIG_ENV_SIZE 0x10000
354	#define CONFIG_ENV_SECT_SIZE 0x20000
355	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
356	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
357
358	/*
359	* Memory map
360	*/
361	#define CONFIG_SYS_MBAR 0xF0000000
362	#define CONFIG_SYS_SDRAM_BASE 0x00000000
363	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
364
365	/* Use ON-Chip SRAM until RAM will be available */
366	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
367	#ifdef CONFIG_POST
368	/* preserve space for the post_word at end of on-chip SRAM */
369	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
370	#else
371	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
372	#endif /CONFIG_POST/
373
374	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
375	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
376
377	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
378	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
379	# define CONFIG_SYS_RAMBOOT 1
380	#endif
381
382	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
383	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
384	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
385
386	/*
387	* Ethernet configuration
388	*
389	* Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
390	*/
391	#define CONFIG_MPC5xxx_FEC 1
392	#define CONFIG_MPC5xxx_FEC_MII100
393	#undef CONFIG_MPC5xxx_MII10
394	#define CONFIG_PHY_ADDR 0x00
395
396	/*
397	* GPIO configuration on BC3450
398	*
399	* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
400	* PSC2: UART2 [0x xxxxxx4x]
401	* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
402	* PSC3: USB2 [0x xxxxx1xx]
403	* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
404	* (this has to match
405	* CONFIG_USB_CONFIG which is
406	* used by usb_ohci.c to set
407	* the USB ports)
408	* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
409	* (this is reset to '5'
410	* in FEC driver: fec.c)
411	* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
412	* ATA/CS: ??? [0x x1xxxxxx]
413	* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
414	* CS1: Use Pin gpio_wkup_6 as second
415	* SDRAM chip select (mem_cs1)
416	* Timer: CAN2 / SPI
417	* I2C: CAN1 / I²C2 [0x bxxxxxxx]
418	*/
419	#ifdef CONFIG_BC3450_AC97
420	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
421	#else /* PSC2=UART2 */
422	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
423	#endif
424
425	/*
426	* Miscellaneous configurable options
427	*/
428	#define CONFIG_SYS_LONGHELP /* undef to save memory */
429	#if defined(CONFIG_CMD_KGDB)
430	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
431	#else
432	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
433	#endif
434	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
435	#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
436	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
437
438	#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
439	/* more extensive mem test */
440
441	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
442	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
443
444	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
445
446	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
447	#if defined(CONFIG_CMD_KGDB)
448	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
449	#endif
450
451	/*
452	* Enable loopw command.
453	*/
454	#define CONFIG_LOOPW
455
456	/*
457	* Various low-level settings
458	*/
459	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
460	#define CONFIG_SYS_HID0_FINAL HID0_ICE
461
462	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
463	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
464	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
465	# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
466	#else
467	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
468	#endif
469	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
470	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
471
472	/* automatic configuration of chip selects */
473	#ifdef CONFIG_TQM5200
474	# define CONFIG_LAST_STAGE_INIT
475	#endif /* CONFIG_TQM5200 */
476
477	/*
478	* SRAM - Do not map below 2 GB in address space, because this area is used
479	* for SDRAM autosizing.
480	*/
481	#ifdef CONFIG_TQM5200
482	# define CONFIG_SYS_CS2_START 0xE5000000
483	# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
484	# define CONFIG_SYS_CS2_CFG 0x0004D930
485	#endif /* CONFIG_TQM5200 */
486
487	/*
488	* Grafic controller - Do not map below 2 GB in address space, because this
489	* area is used for SDRAM autosizing.
490	*/
491	#ifdef CONFIG_TQM5200
492	# define SM501_FB_BASE 0xE0000000
493	# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
494	# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
495	# define CONFIG_SYS_CS1_CFG 0x8F48FF70
496	# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
497	#endif /* CONFIG_TQM5200 */
498
499	#define CONFIG_SYS_CS_BURST 0x00000000
500	#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
501	/* flash and SM501 */
502
503	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
504
505	/*
506	* USB stuff
507	*/
508	#define CONFIG_USB_CLOCK 0x0001BBBB
509	#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
510
511	/*
512	* IDE/ATA stuff Supports IDE harddisk
513	*/
514	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
515
516	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
517	#undef CONFIG_IDE_LED /* LED for ide not supported */
518
519	#define CONFIG_IDE_RESET /* reset for ide supported */
520	#define CONFIG_IDE_PREINIT
521
522	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
523	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
524
525	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
526
527	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
528
529	/* Offset for data I/O */
530	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
531
532	/* Offset for normal register accesses */
533	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
534
535	/* Offset for alternate registers */
536	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
537
538	/* Interval between registers */
539	#define CONFIG_SYS_ATA_STRIDE 4
540
541	#endif /* __CONFIG_H */
542		1	/*