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Commit f8c320609366176b31104d9bf5e295232e1c7f1d

Authored by Shinya Kuribayashi
Committed by Wolfgang Denk
1 parent e8da58f2bc
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

[MIPS] board/gth2/lowlevel_init.S: Fix a build warning 

lowlevel_init.S: Assembler messages:
lowlevel_init.S:413: Warning: Pretending global symbol used as branch target is local.

Looking at codes, the `memtest' and `clearmem' are intentional mixed
use of `global symbols' and `label' for debugging purpose. To make it
build, just disable global-symbols-use for now. As a result `memtest'
still remains as unused, but leave it be...

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>

Showing 1 changed file with 4 additions and 0 deletions Inline Diff

board/gth2/lowlevel_init.S
Diff comments   View file @ f8c3206
1 /* Memory sub-system initialization code */ 1 /* Memory sub-system initialization code */
2 2
3 #include <config.h> 3 #include <config.h>
4 #include <version.h> 4 #include <version.h>
5 #include <asm/regdef.h> 5 #include <asm/regdef.h>
6 #include <asm/au1x00.h> 6 #include <asm/au1x00.h>
7 #include <asm/mipsregs.h> 7 #include <asm/mipsregs.h>
8 8
9 #define CP0_Config0 $16 9 #define CP0_Config0 $16
10 #define MEM_1MS ((CFG_MHZ) * 1000) 10 #define MEM_1MS ((CFG_MHZ) * 1000)
11 #define GPIO_RJ1LY (1<<22) 11 #define GPIO_RJ1LY (1<<22)
12 #define GPIO_CFRESET (1<<10) 12 #define GPIO_CFRESET (1<<10)
13 13
14 .text 14 .text
15 .set noreorder 15 .set noreorder
16 .set mips32 16 .set mips32
17 17
18 .globl lowlevel_init 18 .globl lowlevel_init
19 lowlevel_init: 19 lowlevel_init:
20 /* 20 /*
21 * Step 2) Establish Status Register 21 * Step 2) Establish Status Register
22 * (set BEV, clear ERL, clear EXL, clear IE) 22 * (set BEV, clear ERL, clear EXL, clear IE)
23 */ 23 */
24 li t1, 0x00400000 24 li t1, 0x00400000
25 mtc0 t1, CP0_STATUS 25 mtc0 t1, CP0_STATUS
26 26
27 /* 27 /*
28 * Step 3) Establish CP0 Config0 28 * Step 3) Establish CP0 Config0
29 * (set OD, set K0=3) 29 * (set OD, set K0=3)
30 */ 30 */
31 li t1, 0x00080003 31 li t1, 0x00080003
32 mtc0 t1, CP0_CONFIG 32 mtc0 t1, CP0_CONFIG
33 33
34 /* 34 /*
35 * Step 4) Disable Watchpoint facilities 35 * Step 4) Disable Watchpoint facilities
36 */ 36 */
37 li t1, 0x00000000 37 li t1, 0x00000000
38 mtc0 t1, CP0_WATCHLO 38 mtc0 t1, CP0_WATCHLO
39 mtc0 t1, CP0_IWATCHLO 39 mtc0 t1, CP0_IWATCHLO
40 /* 40 /*
41 * Step 5) Disable the performance counters 41 * Step 5) Disable the performance counters
42 */ 42 */
43 mtc0 zero, CP0_PERFORMANCE 43 mtc0 zero, CP0_PERFORMANCE
44 nop 44 nop
45 45
46 /* 46 /*
47 * Step 6) Establish EJTAG Debug register 47 * Step 6) Establish EJTAG Debug register
48 */ 48 */
49 mtc0 zero, CP0_DEBUG 49 mtc0 zero, CP0_DEBUG
50 nop 50 nop
51 51
52 /* 52 /*
53 * Step 7) Establish Cause 53 * Step 7) Establish Cause
54 * (set IV bit) 54 * (set IV bit)
55 */ 55 */
56 li t1, 0x00800000 56 li t1, 0x00800000
57 mtc0 t1, CP0_CAUSE 57 mtc0 t1, CP0_CAUSE
58 58
59 /* Establish Wired (and Random) */ 59 /* Establish Wired (and Random) */
60 mtc0 zero, CP0_WIRED 60 mtc0 zero, CP0_WIRED
61 nop 61 nop
62 62
63 /* No workaround if running from ram */ 63 /* No workaround if running from ram */
64 lui t0, 0xffc0 64 lui t0, 0xffc0
65 lui t3, 0xbfc0 65 lui t3, 0xbfc0
66 and t1, ra, t0 66 and t1, ra, t0
67 bne t1, t3, noCacheJump 67 bne t1, t3, noCacheJump
68 nop 68 nop
69 69
70 /*** From AMD YAMON ***/ 70 /*** From AMD YAMON ***/
71 /* 71 /*
72 * Step 8) Initialize the caches 72 * Step 8) Initialize the caches
73 */ 73 */
74 li t0, (16*1024) 74 li t0, (16*1024)
75 li t1, 32 75 li t1, 32
76 li t2, 0x80000000 76 li t2, 0x80000000
77 addu t3, t0, t2 77 addu t3, t0, t2
78 cacheloop: 78 cacheloop:
79 cache 0, 0(t2) 79 cache 0, 0(t2)
80 cache 1, 0(t2) 80 cache 1, 0(t2)
81 addu t2, t1 81 addu t2, t1
82 bne t2, t3, cacheloop 82 bne t2, t3, cacheloop
83 nop 83 nop
84 84
85 /* Save return address */ 85 /* Save return address */
86 move t3, ra 86 move t3, ra
87 87
88 /* Run from cacheable space now */ 88 /* Run from cacheable space now */
89 bal cachehere 89 bal cachehere
90 nop 90 nop
91 cachehere: 91 cachehere:
92 li t1, ~0x20000000 /* convert to KSEG0 */ 92 li t1, ~0x20000000 /* convert to KSEG0 */
93 and t0, ra, t1 93 and t0, ra, t1
94 addi t0, 5*4 /* 5 insns beyond cachehere */ 94 addi t0, 5*4 /* 5 insns beyond cachehere */
95 jr t0 95 jr t0
96 nop 96 nop
97 97
98 /* Restore return address */ 98 /* Restore return address */
99 move ra, t3 99 move ra, t3
100 100
101 /* 101 /*
102 * Step 9) Initialize the TLB 102 * Step 9) Initialize the TLB
103 */ 103 */
104 li t0, 0 # index value 104 li t0, 0 # index value
105 li t1, 0x00000000 # entryhi value 105 li t1, 0x00000000 # entryhi value
106 li t2, 32 # 32 entries 106 li t2, 32 # 32 entries
107 107
108 tlbloop: 108 tlbloop:
109 /* Probe TLB for matching EntryHi */ 109 /* Probe TLB for matching EntryHi */
110 mtc0 t1, CP0_ENTRYHI 110 mtc0 t1, CP0_ENTRYHI
111 tlbp 111 tlbp
112 nop 112 nop
113 113
114 /* Examine Index[P], 1=no matching entry */ 114 /* Examine Index[P], 1=no matching entry */
115 mfc0 t3, CP0_INDEX 115 mfc0 t3, CP0_INDEX
116 li t4, 0x80000000 116 li t4, 0x80000000
117 and t3, t4, t3 117 and t3, t4, t3
118 addiu t1, t1, 1 # increment t1 (asid) 118 addiu t1, t1, 1 # increment t1 (asid)
119 beq zero, t3, tlbloop 119 beq zero, t3, tlbloop
120 nop 120 nop
121 121
122 /* Initialize the TLB entry */ 122 /* Initialize the TLB entry */
123 mtc0 t0, CP0_INDEX 123 mtc0 t0, CP0_INDEX
124 mtc0 zero, CP0_ENTRYLO0 124 mtc0 zero, CP0_ENTRYLO0
125 mtc0 zero, CP0_ENTRYLO1 125 mtc0 zero, CP0_ENTRYLO1
126 mtc0 zero, CP0_PAGEMASK 126 mtc0 zero, CP0_PAGEMASK
127 tlbwi 127 tlbwi
128 128
129 /* Do it again */ 129 /* Do it again */
130 addiu t0, t0, 1 130 addiu t0, t0, 1
131 bne t0, t2, tlbloop 131 bne t0, t2, tlbloop
132 nop 132 nop
133 133
134 /* First setup pll:s to make serial work ok */ 134 /* First setup pll:s to make serial work ok */
135 /* We have a 12.5 MHz crystal */ 135 /* We have a 12.5 MHz crystal */
136 li t0, SYS_CPUPLL 136 li t0, SYS_CPUPLL
137 li t1, 0x28 /* CPU clock, 500 MHz */ 137 li t1, 0x28 /* CPU clock, 500 MHz */
138 sw t1, 0(t0) 138 sw t1, 0(t0)
139 sync 139 sync
140 nop 140 nop
141 nop 141 nop
142 142
143 /* wait 1mS for clocks to settle */ 143 /* wait 1mS for clocks to settle */
144 li t1, MEM_1MS 144 li t1, MEM_1MS
145 1: add t1, -1 145 1: add t1, -1
146 bne t1, zero, 1b 146 bne t1, zero, 1b
147 nop 147 nop
148 /* Setup AUX PLL */ 148 /* Setup AUX PLL */
149 li t0, SYS_AUXPLL 149 li t0, SYS_AUXPLL
150 li t1, 0 150 li t1, 0
151 sw t1, 0(t0) /* aux pll */ 151 sw t1, 0(t0) /* aux pll */
152 sync 152 sync
153 153
154 /* Static memory controller */ 154 /* Static memory controller */
155 /* RCE0 - can not change while fetching, do so from icache */ 155 /* RCE0 - can not change while fetching, do so from icache */
156 move t2, ra /* Store return address */ 156 move t2, ra /* Store return address */
157 bal getAddr 157 bal getAddr
158 nop 158 nop
159 159
160 getAddr: 160 getAddr:
161 move t1, ra 161 move t1, ra
162 move ra, t2 /* Move return addess back */ 162 move ra, t2 /* Move return addess back */
163 163
164 cache 0x14,0(t1) 164 cache 0x14,0(t1)
165 cache 0x14,32(t1) 165 cache 0x14,32(t1)
166 /*** /From YAMON ***/ 166 /*** /From YAMON ***/
167 167
168 noCacheJump: 168 noCacheJump:
169 169
170 /* Static memory controller */ 170 /* Static memory controller */
171 171
172 /* RCE0 AMD 29LV800 Flash */ 172 /* RCE0 AMD 29LV800 Flash */
173 li t0, MEM_STCFG0 173 li t0, MEM_STCFG0
174 li t1, 0x00000243 174 li t1, 0x00000243
175 sw t1, 0(t0) 175 sw t1, 0(t0)
176 176
177 li t0, MEM_STTIME0 177 li t0, MEM_STTIME0
178 li t1, 0x040181D7 /* FIXME */ 178 li t1, 0x040181D7 /* FIXME */
179 sw t1, 0(t0) 179 sw t1, 0(t0)
180 180
181 li t0, MEM_STADDR0 181 li t0, MEM_STADDR0
182 li t1, 0x11E03F80 182 li t1, 0x11E03F80
183 sw t1, 0(t0) 183 sw t1, 0(t0)
184 184
185 /* RCE1 PCMCIA 250ns */ 185 /* RCE1 PCMCIA 250ns */
186 li t0, MEM_STCFG1 186 li t0, MEM_STCFG1
187 li t1, 0x00000002 187 li t1, 0x00000002
188 sw t1, 0(t0) 188 sw t1, 0(t0)
189 189
190 li t0, MEM_STTIME1 190 li t0, MEM_STTIME1
191 li t1, 0x280E3E07 191 li t1, 0x280E3E07
192 sw t1, 0(t0) 192 sw t1, 0(t0)
193 193
194 li t0, MEM_STADDR1 194 li t0, MEM_STADDR1
195 li t1, 0x10000000 195 li t1, 0x10000000
196 sw t1, 0(t0) 196 sw t1, 0(t0)
197 197
198 /* RCE2 CP Altera */ 198 /* RCE2 CP Altera */
199 li t0, MEM_STCFG2 199 li t0, MEM_STCFG2
200 li t1, 0x00000280 /* BE, EW */ 200 li t1, 0x00000280 /* BE, EW */
201 sw t1, 0(t0) 201 sw t1, 0(t0)
202 202
203 li t0, MEM_STTIME2 203 li t0, MEM_STTIME2
204 li t1, 0x0303000c 204 li t1, 0x0303000c
205 sw t1, 0(t0) 205 sw t1, 0(t0)
206 206
207 li t0, MEM_STADDR2 207 li t0, MEM_STADDR2
208 li t1, 0x10c03f80 /* 1 MB */ 208 li t1, 0x10c03f80 /* 1 MB */
209 sw t1, 0(t0) 209 sw t1, 0(t0)
210 210
211 /* RCE3 DP Altera */ 211 /* RCE3 DP Altera */
212 li t0, MEM_STCFG3 212 li t0, MEM_STCFG3
213 li t1, 0x00000280 /* BE, EW */ 213 li t1, 0x00000280 /* BE, EW */
214 sw t1, 0(t0) 214 sw t1, 0(t0)
215 215
216 li t0, MEM_STTIME3 216 li t0, MEM_STTIME3
217 li t1, 0x0303000c 217 li t1, 0x0303000c
218 sw t1, 0(t0) 218 sw t1, 0(t0)
219 219
220 li t0, MEM_STADDR3 220 li t0, MEM_STADDR3
221 li t1, 0x10e03f80 /* 1 MB */ 221 li t1, 0x10e03f80 /* 1 MB */
222 sw t1, 0(t0) 222 sw t1, 0(t0)
223 223
224 sync 224 sync
225 225
226 /* Set peripherals to a known state */ 226 /* Set peripherals to a known state */
227 li t0, IC0_CFG0CLR 227 li t0, IC0_CFG0CLR
228 li t1, 0xFFFFFFFF 228 li t1, 0xFFFFFFFF
229 sw t1, 0(t0) 229 sw t1, 0(t0)
230 230
231 li t0, IC0_CFG0CLR 231 li t0, IC0_CFG0CLR
232 sw t1, 0(t0) 232 sw t1, 0(t0)
233 233
234 li t0, IC0_CFG1CLR 234 li t0, IC0_CFG1CLR
235 sw t1, 0(t0) 235 sw t1, 0(t0)
236 236
237 li t0, IC0_CFG2CLR 237 li t0, IC0_CFG2CLR
238 sw t1, 0(t0) 238 sw t1, 0(t0)
239 239
240 li t0, IC0_SRCSET 240 li t0, IC0_SRCSET
241 sw t1, 0(t0) 241 sw t1, 0(t0)
242 242
243 li t0, IC0_ASSIGNSET 243 li t0, IC0_ASSIGNSET
244 sw t1, 0(t0) 244 sw t1, 0(t0)
245 245
246 li t0, IC0_WAKECLR 246 li t0, IC0_WAKECLR
247 sw t1, 0(t0) 247 sw t1, 0(t0)
248 248
249 li t0, IC0_RISINGCLR 249 li t0, IC0_RISINGCLR
250 sw t1, 0(t0) 250 sw t1, 0(t0)
251 251
252 li t0, IC0_FALLINGCLR 252 li t0, IC0_FALLINGCLR
253 sw t1, 0(t0) 253 sw t1, 0(t0)
254 254
255 li t0, IC0_TESTBIT 255 li t0, IC0_TESTBIT
256 li t1, 0x00000000 256 li t1, 0x00000000
257 sw t1, 0(t0) 257 sw t1, 0(t0)
258 sync 258 sync
259 259
260 li t0, IC1_CFG0CLR 260 li t0, IC1_CFG0CLR
261 li t1, 0xFFFFFFFF 261 li t1, 0xFFFFFFFF
262 sw t1, 0(t0) 262 sw t1, 0(t0)
263 263
264 li t0, IC1_CFG0CLR 264 li t0, IC1_CFG0CLR
265 sw t1, 0(t0) 265 sw t1, 0(t0)
266 266
267 li t0, IC1_CFG1CLR 267 li t0, IC1_CFG1CLR
268 sw t1, 0(t0) 268 sw t1, 0(t0)
269 269
270 li t0, IC1_CFG2CLR 270 li t0, IC1_CFG2CLR
271 sw t1, 0(t0) 271 sw t1, 0(t0)
272 272
273 li t0, IC1_SRCSET 273 li t0, IC1_SRCSET
274 sw t1, 0(t0) 274 sw t1, 0(t0)
275 275
276 li t0, IC1_ASSIGNSET 276 li t0, IC1_ASSIGNSET
277 sw t1, 0(t0) 277 sw t1, 0(t0)
278 278
279 li t0, IC1_WAKECLR 279 li t0, IC1_WAKECLR
280 sw t1, 0(t0) 280 sw t1, 0(t0)
281 281
282 li t0, IC1_RISINGCLR 282 li t0, IC1_RISINGCLR
283 sw t1, 0(t0) 283 sw t1, 0(t0)
284 284
285 li t0, IC1_FALLINGCLR 285 li t0, IC1_FALLINGCLR
286 sw t1, 0(t0) 286 sw t1, 0(t0)
287 287
288 li t0, IC1_TESTBIT 288 li t0, IC1_TESTBIT
289 li t1, 0x00000000 289 li t1, 0x00000000
290 sw t1, 0(t0) 290 sw t1, 0(t0)
291 sync 291 sync
292 292
293 li t0, SYS_FREQCTRL0 293 li t0, SYS_FREQCTRL0
294 li t1, 0x00000000 294 li t1, 0x00000000
295 sw t1, 0(t0) 295 sw t1, 0(t0)
296 296
297 li t0, SYS_FREQCTRL1 297 li t0, SYS_FREQCTRL1
298 li t1, 0x00000000 298 li t1, 0x00000000
299 sw t1, 0(t0) 299 sw t1, 0(t0)
300 300
301 li t0, SYS_CLKSRC 301 li t0, SYS_CLKSRC
302 li t1, 0x00000000 302 li t1, 0x00000000
303 sw t1, 0(t0) 303 sw t1, 0(t0)
304 304
305 li t0, SYS_PININPUTEN 305 li t0, SYS_PININPUTEN
306 li t1, 0x00000000 306 li t1, 0x00000000
307 sw t1, 0(t0) 307 sw t1, 0(t0)
308 sync 308 sync
309 309
310 li t0, 0xB1100100 310 li t0, 0xB1100100
311 li t1, 0x00000000 311 li t1, 0x00000000
312 sw t1, 0(t0) 312 sw t1, 0(t0)
313 313
314 li t0, 0xB1400100 314 li t0, 0xB1400100
315 li t1, 0x00000000 315 li t1, 0x00000000
316 sw t1, 0(t0) 316 sw t1, 0(t0)
317 317
318 318
319 li t0, SYS_WAKEMSK 319 li t0, SYS_WAKEMSK
320 li t1, 0x00000000 320 li t1, 0x00000000
321 sw t1, 0(t0) 321 sw t1, 0(t0)
322 322
323 li t0, SYS_WAKESRC 323 li t0, SYS_WAKESRC
324 li t1, 0x00000000 324 li t1, 0x00000000
325 sw t1, 0(t0) 325 sw t1, 0(t0)
326 326
327 /* wait 1mS before setup */ 327 /* wait 1mS before setup */
328 li t1, MEM_1MS 328 li t1, MEM_1MS
329 1: add t1, -1 329 1: add t1, -1
330 bne t1, zero, 1b 330 bne t1, zero, 1b
331 nop 331 nop
332 332
333 333
334 /* SDCS 0 SDRAM */ 334 /* SDCS 0 SDRAM */
335 li t0, MEM_SDMODE0 335 li t0, MEM_SDMODE0
336 li t1, 0x592CD1 336 li t1, 0x592CD1
337 sw t1, 0(t0) 337 sw t1, 0(t0)
338 338
339 li t0, MEM_SDMODE1 339 li t0, MEM_SDMODE1
340 li t1, 0x00000000 340 li t1, 0x00000000
341 sw t1, 0(t0) 341 sw t1, 0(t0)
342 342
343 li t0, MEM_SDMODE2 343 li t0, MEM_SDMODE2
344 li t1, 0x00000000 344 li t1, 0x00000000
345 sw t1, 0(t0) 345 sw t1, 0(t0)
346 346
347 /* 64 MB SDRAM at addr 0 */ 347 /* 64 MB SDRAM at addr 0 */
348 li t0, MEM_SDADDR0 348 li t0, MEM_SDADDR0
349 li t1, 0x001003F0 349 li t1, 0x001003F0
350 sw t1, 0(t0) 350 sw t1, 0(t0)
351 351
352 352
353 li t0, MEM_SDADDR1 353 li t0, MEM_SDADDR1
354 li t1, 0x00000000 354 li t1, 0x00000000
355 sw t1, 0(t0) 355 sw t1, 0(t0)
356 356
357 li t0, MEM_SDADDR2 357 li t0, MEM_SDADDR2
358 li t1, 0x00000000 358 li t1, 0x00000000
359 sw t1, 0(t0) 359 sw t1, 0(t0)
360 360
361 sync 361 sync
362 362
363 li t0, MEM_SDREFCFG 363 li t0, MEM_SDREFCFG
364 li t1, 0x880007A1 /* Disable */ 364 li t1, 0x880007A1 /* Disable */
365 sw t1, 0(t0) 365 sw t1, 0(t0)
366 sync 366 sync
367 367
368 li t0, MEM_SDPRECMD 368 li t0, MEM_SDPRECMD
369 sw zero, 0(t0) 369 sw zero, 0(t0)
370 sync 370 sync
371 371
372 li t0, MEM_SDAUTOREF 372 li t0, MEM_SDAUTOREF
373 sw zero, 0(t0) 373 sw zero, 0(t0)
374 sync 374 sync
375 sw zero, 0(t0) 375 sw zero, 0(t0)
376 sync 376 sync
377 377
378 li t0, MEM_SDREFCFG 378 li t0, MEM_SDREFCFG
379 li t1, 0x8A0007A1 /* Enable */ 379 li t1, 0x8A0007A1 /* Enable */
380 sw t1, 0(t0) 380 sw t1, 0(t0)
381 sync 381 sync
382 382
383 li t0, MEM_SDWRMD0 383 li t0, MEM_SDWRMD0
384 li t1, 0x00000023 384 li t1, 0x00000023
385 sw t1, 0(t0) 385 sw t1, 0(t0)
386 sync 386 sync
387 387
388 /* wait 1mS after setup */ 388 /* wait 1mS after setup */
389 li t1, MEM_1MS 389 li t1, MEM_1MS
390 1: add t1, -1 390 1: add t1, -1
391 bne t1, zero, 1b 391 bne t1, zero, 1b
392 nop 392 nop
393 393
394 /* Setup GPIO pins */ 394 /* Setup GPIO pins */
395 395
396 li t0, SYS_PINFUNC 396 li t0, SYS_PINFUNC
397 li t1, 0x00007025 /* 0x8080 */ 397 li t1, 0x00007025 /* 0x8080 */
398 sw t1, 0(t0) 398 sw t1, 0(t0)
399 399
400 li t0, SYS_TRIOUTCLR 400 li t0, SYS_TRIOUTCLR
401 li t1, 0xFFFFFFFF /* 0x1FFF */ 401 li t1, 0xFFFFFFFF /* 0x1FFF */
402 sw t1, 0(t0) 402 sw t1, 0(t0)
403 403
404 /* Turn yellow front led on */ 404 /* Turn yellow front led on */
405 /* Release reset on CF */ 405 /* Release reset on CF */
406 li t0, SYS_OUTPUTCLR 406 li t0, SYS_OUTPUTCLR
407 li t1, GPIO_RJ1LG 407 li t1, GPIO_RJ1LG
408 sw t1, 0(t0) 408 sw t1, 0(t0)
409 li t0, SYS_OUTPUTSET 409 li t0, SYS_OUTPUTSET
410 li t1, GPIO_RJ1LY|GPIO_CFRESET 410 li t1, GPIO_RJ1LY|GPIO_CFRESET
411 sw t1, 0(t0) 411 sw t1, 0(t0)
412 sync 412 sync
413 j clearmem 413 j clearmem
414 nop 414 nop
415 415
416 #if 0
416 .globl memtest 417 .globl memtest
418 #endif
417 memtest: 419 memtest:
418 /* Fill memory with address */ 420 /* Fill memory with address */
419 li t0, 0x80000000 421 li t0, 0x80000000
420 li t1, 0xFFF000 /* 64 MB */ 422 li t1, 0xFFF000 /* 64 MB */
421 mt0: sw t0, 0(t0) 423 mt0: sw t0, 0(t0)
422 add t1, -1 424 add t1, -1
423 add t0, 4 425 add t0, 4
424 bne t1, zero, mt0 426 bne t1, zero, mt0
425 nop 427 nop
426 nop 428 nop
427 /* Verify addr */ 429 /* Verify addr */
428 li t0, 0x80000000 430 li t0, 0x80000000
429 li t1, 0xFFF000 /* 64 MB */ 431 li t1, 0xFFF000 /* 64 MB */
430 mt1: lw t2, 0(t0) 432 mt1: lw t2, 0(t0)
431 bne t0, t2, memhang 433 bne t0, t2, memhang
432 add t1, -1 434 add t1, -1
433 add t0, 4 435 add t0, 4
434 bne t1, zero, mt1 436 bne t1, zero, mt1
435 nop 437 nop
436 nop 438 nop
439 #if 0
437 .globl clearmem 440 .globl clearmem
441 #endif
438 clearmem: 442 clearmem:
439 /* Clear memory */ 443 /* Clear memory */
440 li t0, 0x80000000 444 li t0, 0x80000000
441 li t1, 0xFFF000 /* 64 MB */ 445 li t1, 0xFFF000 /* 64 MB */
442 mtc: sw zero, 0(t0) 446 mtc: sw zero, 0(t0)
443 add t1, -1 447 add t1, -1
444 add t0, 4 448 add t0, 4
445 bne t1, zero, mtc 449 bne t1, zero, mtc
446 nop 450 nop
447 nop 451 nop
448 memtestend: 452 memtestend:
449 j ra 453 j ra
450 nop 454 nop
451 455
452 memhang: 456 memhang:
453 b memhang 457 b memhang
454 nop 458 nop
455 459