Commit fa752d64f94649b0b078957316b2e4a68cbe5733
Committed by
Marek Vasut
Marek Vasut
1 parent
99d672fa54
Exists in
v2017.01-smarct4x
and in
37 other branches
pxa: colibri_pxa270: fix wrong comment about voipac ethernet chip
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Showing 1 changed file with 0 additions and 1 deletions Inline Diff
include/configs/colibri_pxa270.h
| 1 | /* | 1 | /* |
| 2 | * Toradex Colibri PXA270 configuration file | 2 | * Toradex Colibri PXA270 configuration file |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> | 5 | * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> |
| 6 | * | 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #ifndef __CONFIG_H | 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H | 11 | #define __CONFIG_H |
| 12 | 12 | ||
| 13 | /* | 13 | /* |
| 14 | * High Level Board Configuration Options | 14 | * High Level Board Configuration Options |
| 15 | */ | 15 | */ |
| 16 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ | 16 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
| 17 | #define CONFIG_SYS_GENERIC_BOARD | 17 | #define CONFIG_SYS_GENERIC_BOARD |
| 18 | #define CONFIG_SYS_TEXT_BASE 0x0 | 18 | #define CONFIG_SYS_TEXT_BASE 0x0 |
| 19 | /* Avoid overwriting factory configuration block */ | 19 | /* Avoid overwriting factory configuration block */ |
| 20 | #define CONFIG_BOARD_SIZE_LIMIT 0x40000 | 20 | #define CONFIG_BOARD_SIZE_LIMIT 0x40000 |
| 21 | 21 | ||
| 22 | /* | 22 | /* |
| 23 | * Environment settings | 23 | * Environment settings |
| 24 | */ | 24 | */ |
| 25 | #define CONFIG_ENV_OVERWRITE | 25 | #define CONFIG_ENV_OVERWRITE |
| 26 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) | 26 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
| 27 | #define CONFIG_ARCH_CPU_INIT | 27 | #define CONFIG_ARCH_CPU_INIT |
| 28 | #define CONFIG_BOOTCOMMAND \ | 28 | #define CONFIG_BOOTCOMMAND \ |
| 29 | "if fatload mmc 0 0xa0000000 uImage; then " \ | 29 | "if fatload mmc 0 0xa0000000 uImage; then " \ |
| 30 | "bootm 0xa0000000; " \ | 30 | "bootm 0xa0000000; " \ |
| 31 | "fi; " \ | 31 | "fi; " \ |
| 32 | "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ | 32 | "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ |
| 33 | "bootm 0xa0000000; " \ | 33 | "bootm 0xa0000000; " \ |
| 34 | "fi; " \ | 34 | "fi; " \ |
| 35 | "bootm 0xc0000;" | 35 | "bootm 0xc0000;" |
| 36 | #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" | 36 | #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" |
| 37 | #define CONFIG_TIMESTAMP | 37 | #define CONFIG_TIMESTAMP |
| 38 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ | 38 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
| 39 | #define CONFIG_CMDLINE_TAG | 39 | #define CONFIG_CMDLINE_TAG |
| 40 | #define CONFIG_SETUP_MEMORY_TAGS | 40 | #define CONFIG_SETUP_MEMORY_TAGS |
| 41 | #define CONFIG_LZMA /* LZMA compression support */ | 41 | #define CONFIG_LZMA /* LZMA compression support */ |
| 42 | #define CONFIG_OF_LIBFDT | 42 | #define CONFIG_OF_LIBFDT |
| 43 | 43 | ||
| 44 | /* | 44 | /* |
| 45 | * Serial Console Configuration | 45 | * Serial Console Configuration |
| 46 | */ | 46 | */ |
| 47 | #define CONFIG_PXA_SERIAL | 47 | #define CONFIG_PXA_SERIAL |
| 48 | #define CONFIG_FFUART 1 | 48 | #define CONFIG_FFUART 1 |
| 49 | #define CONFIG_CONS_INDEX 3 | 49 | #define CONFIG_CONS_INDEX 3 |
| 50 | #define CONFIG_BAUDRATE 115200 | 50 | #define CONFIG_BAUDRATE 115200 |
| 51 | 51 | ||
| 52 | /* | 52 | /* |
| 53 | * Bootloader Components Configuration | 53 | * Bootloader Components Configuration |
| 54 | */ | 54 | */ |
| 55 | #include <config_cmd_default.h> | 55 | #include <config_cmd_default.h> |
| 56 | 56 | ||
| 57 | #undef CONFIG_CMD_LOADB /* Both together */ | 57 | #undef CONFIG_CMD_LOADB /* Both together */ |
| 58 | #undef CONFIG_CMD_LOADS /* saves 10 KB */ | 58 | #undef CONFIG_CMD_LOADS /* saves 10 KB */ |
| 59 | #define CONFIG_CMD_NET | 59 | #define CONFIG_CMD_NET |
| 60 | #define CONFIG_CMD_ENV | 60 | #define CONFIG_CMD_ENV |
| 61 | #undef CONFIG_CMD_IMLS | 61 | #undef CONFIG_CMD_IMLS |
| 62 | #define CONFIG_CMD_MMC | 62 | #define CONFIG_CMD_MMC |
| 63 | #define CONFIG_CMD_USB | 63 | #define CONFIG_CMD_USB |
| 64 | #define CONFIG_CMD_FLASH | 64 | #define CONFIG_CMD_FLASH |
| 65 | 65 | ||
| 66 | /* | 66 | /* |
| 67 | * Networking Configuration | 67 | * Networking Configuration |
| 68 | * chip on the Voipac PXA270 board | ||
| 69 | */ | 68 | */ |
| 70 | #ifdef CONFIG_CMD_NET | 69 | #ifdef CONFIG_CMD_NET |
| 71 | #define CONFIG_CMD_PING | 70 | #define CONFIG_CMD_PING |
| 72 | #define CONFIG_CMD_DHCP | 71 | #define CONFIG_CMD_DHCP |
| 73 | 72 | ||
| 74 | #define CONFIG_DRIVER_DM9000 1 | 73 | #define CONFIG_DRIVER_DM9000 1 |
| 75 | #define CONFIG_DM9000_BASE 0x08000000 | 74 | #define CONFIG_DM9000_BASE 0x08000000 |
| 76 | #define DM9000_IO (CONFIG_DM9000_BASE) | 75 | #define DM9000_IO (CONFIG_DM9000_BASE) |
| 77 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | 76 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
| 78 | #define CONFIG_NET_RETRY_COUNT 10 | 77 | #define CONFIG_NET_RETRY_COUNT 10 |
| 79 | 78 | ||
| 80 | #define CONFIG_BOOTP_BOOTFILESIZE | 79 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 81 | #define CONFIG_BOOTP_BOOTPATH | 80 | #define CONFIG_BOOTP_BOOTPATH |
| 82 | #define CONFIG_BOOTP_GATEWAY | 81 | #define CONFIG_BOOTP_GATEWAY |
| 83 | #define CONFIG_BOOTP_HOSTNAME | 82 | #define CONFIG_BOOTP_HOSTNAME |
| 84 | #endif | 83 | #endif |
| 85 | 84 | ||
| 86 | /* | 85 | /* |
| 87 | * HUSH Shell Configuration | 86 | * HUSH Shell Configuration |
| 88 | */ | 87 | */ |
| 89 | #define CONFIG_SYS_HUSH_PARSER 1 | 88 | #define CONFIG_SYS_HUSH_PARSER 1 |
| 90 | 89 | ||
| 91 | #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ | 90 | #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ |
| 92 | #ifdef CONFIG_SYS_HUSH_PARSER | 91 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 93 | #define CONFIG_SYS_PROMPT "$ " | 92 | #define CONFIG_SYS_PROMPT "$ " |
| 94 | #else | 93 | #else |
| 95 | #endif | 94 | #endif |
| 96 | #define CONFIG_SYS_CBSIZE 256 | 95 | #define CONFIG_SYS_CBSIZE 256 |
| 97 | #define CONFIG_SYS_PBSIZE \ | 96 | #define CONFIG_SYS_PBSIZE \ |
| 98 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | 97 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 99 | #define CONFIG_SYS_MAXARGS 16 | 98 | #define CONFIG_SYS_MAXARGS 16 |
| 100 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | 99 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 101 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | 100 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
| 102 | #define CONFIG_CMDLINE_EDITING 1 | 101 | #define CONFIG_CMDLINE_EDITING 1 |
| 103 | #define CONFIG_AUTO_COMPLETE 1 | 102 | #define CONFIG_AUTO_COMPLETE 1 |
| 104 | 103 | ||
| 105 | /* | 104 | /* |
| 106 | * Clock Configuration | 105 | * Clock Configuration |
| 107 | */ | 106 | */ |
| 108 | #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ | 107 | #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ |
| 109 | 108 | ||
| 110 | /* | 109 | /* |
| 111 | * DRAM Map | 110 | * DRAM Map |
| 112 | */ | 111 | */ |
| 113 | #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ | 112 | #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ |
| 114 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | 113 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
| 115 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | 114 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
| 116 | 115 | ||
| 117 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | 116 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
| 118 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ | 117 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ |
| 119 | 118 | ||
| 120 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | 119 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
| 121 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | 120 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
| 122 | 121 | ||
| 123 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 | 122 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 |
| 124 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | 123 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 125 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 | 124 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
| 126 | 125 | ||
| 127 | /* | 126 | /* |
| 128 | * NOR FLASH | 127 | * NOR FLASH |
| 129 | */ | 128 | */ |
| 130 | #ifdef CONFIG_CMD_FLASH | 129 | #ifdef CONFIG_CMD_FLASH |
| 131 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | 130 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 132 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | 131 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 133 | 132 | ||
| 134 | #define CONFIG_SYS_FLASH_CFI | 133 | #define CONFIG_SYS_FLASH_CFI |
| 135 | #define CONFIG_FLASH_CFI_DRIVER 1 | 134 | #define CONFIG_FLASH_CFI_DRIVER 1 |
| 136 | 135 | ||
| 137 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) | 136 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) |
| 138 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | 137 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 139 | 138 | ||
| 140 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) | 139 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) |
| 141 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) | 140 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) |
| 142 | 141 | ||
| 143 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | 142 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
| 144 | #define CONFIG_SYS_FLASH_PROTECTION 1 | 143 | #define CONFIG_SYS_FLASH_PROTECTION 1 |
| 145 | 144 | ||
| 146 | #define CONFIG_ENV_IS_IN_FLASH 1 | 145 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 147 | 146 | ||
| 148 | #else /* No flash */ | 147 | #else /* No flash */ |
| 149 | #define CONFIG_SYS_NO_FLASH | 148 | #define CONFIG_SYS_NO_FLASH |
| 150 | #define CONFIG_ENV_IS_NOWHERE | 149 | #define CONFIG_ENV_IS_NOWHERE |
| 151 | #endif | 150 | #endif |
| 152 | 151 | ||
| 153 | #define CONFIG_SYS_MONITOR_BASE 0x0 | 152 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
| 154 | #define CONFIG_SYS_MONITOR_LEN 0x40000 | 153 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
| 155 | 154 | ||
| 156 | /* Skip factory configuration block */ | 155 | /* Skip factory configuration block */ |
| 157 | #define CONFIG_ENV_ADDR \ | 156 | #define CONFIG_ENV_ADDR \ |
| 158 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) | 157 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) |
| 159 | #define CONFIG_ENV_SIZE 0x40000 | 158 | #define CONFIG_ENV_SIZE 0x40000 |
| 160 | #define CONFIG_ENV_SECT_SIZE 0x40000 | 159 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
| 161 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | 160 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 162 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | 161 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 163 | 162 | ||
| 164 | /* | 163 | /* |
| 165 | * GPIO settings | 164 | * GPIO settings |
| 166 | */ | 165 | */ |
| 167 | #define CONFIG_SYS_GPSR0_VAL 0x00000000 | 166 | #define CONFIG_SYS_GPSR0_VAL 0x00000000 |
| 168 | #define CONFIG_SYS_GPSR1_VAL 0x00020000 | 167 | #define CONFIG_SYS_GPSR1_VAL 0x00020000 |
| 169 | #define CONFIG_SYS_GPSR2_VAL 0x0002C000 | 168 | #define CONFIG_SYS_GPSR2_VAL 0x0002C000 |
| 170 | #define CONFIG_SYS_GPSR3_VAL 0x00000000 | 169 | #define CONFIG_SYS_GPSR3_VAL 0x00000000 |
| 171 | 170 | ||
| 172 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | 171 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 |
| 173 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | 172 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 |
| 174 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | 173 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 |
| 175 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 | 174 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 |
| 176 | 175 | ||
| 177 | #define CONFIG_SYS_GPDR0_VAL 0x08000000 | 176 | #define CONFIG_SYS_GPDR0_VAL 0x08000000 |
| 178 | #define CONFIG_SYS_GPDR1_VAL 0x0002A981 | 177 | #define CONFIG_SYS_GPDR1_VAL 0x0002A981 |
| 179 | #define CONFIG_SYS_GPDR2_VAL 0x0202FC00 | 178 | #define CONFIG_SYS_GPDR2_VAL 0x0202FC00 |
| 180 | #define CONFIG_SYS_GPDR3_VAL 0x00000000 | 179 | #define CONFIG_SYS_GPDR3_VAL 0x00000000 |
| 181 | 180 | ||
| 182 | #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 | 181 | #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 |
| 183 | #define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 | 182 | #define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 |
| 184 | #define CONFIG_SYS_GAFR1_L_VAL 0x999A901A | 183 | #define CONFIG_SYS_GAFR1_L_VAL 0x999A901A |
| 185 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 | 184 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 |
| 186 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA | 185 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA |
| 187 | #define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 | 186 | #define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 |
| 188 | #define CONFIG_SYS_GAFR3_L_VAL 0x54000300 | 187 | #define CONFIG_SYS_GAFR3_L_VAL 0x54000300 |
| 189 | #define CONFIG_SYS_GAFR3_U_VAL 0x00024001 | 188 | #define CONFIG_SYS_GAFR3_U_VAL 0x00024001 |
| 190 | 189 | ||
| 191 | #define CONFIG_SYS_PSSR_VAL 0x30 | 190 | #define CONFIG_SYS_PSSR_VAL 0x30 |
| 192 | 191 | ||
| 193 | /* | 192 | /* |
| 194 | * Clock settings | 193 | * Clock settings |
| 195 | */ | 194 | */ |
| 196 | #define CONFIG_SYS_CKEN 0x00500240 | 195 | #define CONFIG_SYS_CKEN 0x00500240 |
| 197 | #define CONFIG_SYS_CCCR 0x02000290 | 196 | #define CONFIG_SYS_CCCR 0x02000290 |
| 198 | 197 | ||
| 199 | /* | 198 | /* |
| 200 | * Memory settings | 199 | * Memory settings |
| 201 | */ | 200 | */ |
| 202 | #define CONFIG_SYS_MSC0_VAL 0x000095f2 | 201 | #define CONFIG_SYS_MSC0_VAL 0x000095f2 |
| 203 | #define CONFIG_SYS_MSC1_VAL 0x00007ff4 | 202 | #define CONFIG_SYS_MSC1_VAL 0x00007ff4 |
| 204 | #define CONFIG_SYS_MSC2_VAL 0x00000000 | 203 | #define CONFIG_SYS_MSC2_VAL 0x00000000 |
| 205 | #define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 | 204 | #define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 |
| 206 | #define CONFIG_SYS_MDREFR_VAL 0x2013e01e | 205 | #define CONFIG_SYS_MDREFR_VAL 0x2013e01e |
| 207 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 | 206 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 |
| 208 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | 207 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
| 209 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | 208 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
| 210 | 209 | ||
| 211 | /* | 210 | /* |
| 212 | * PCMCIA and CF Interfaces | 211 | * PCMCIA and CF Interfaces |
| 213 | */ | 212 | */ |
| 214 | #define CONFIG_SYS_MECR_VAL 0x00000001 | 213 | #define CONFIG_SYS_MECR_VAL 0x00000001 |
| 215 | #define CONFIG_SYS_MCMEM0_VAL 0x00014307 | 214 | #define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
| 216 | #define CONFIG_SYS_MCMEM1_VAL 0x00014307 | 215 | #define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
| 217 | #define CONFIG_SYS_MCATT0_VAL 0x0001c787 | 216 | #define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
| 218 | #define CONFIG_SYS_MCATT1_VAL 0x0001c787 | 217 | #define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
| 219 | #define CONFIG_SYS_MCIO0_VAL 0x0001430f | 218 | #define CONFIG_SYS_MCIO0_VAL 0x0001430f |
| 220 | #define CONFIG_SYS_MCIO1_VAL 0x0001430f | 219 | #define CONFIG_SYS_MCIO1_VAL 0x0001430f |
| 221 | 220 | ||
| 222 | #include "pxa-common.h" | 221 | #include "pxa-common.h" |
| 223 | 222 | ||
| 224 | #endif /* __CONFIG_H */ | 223 | #endif /* __CONFIG_H */ |
| 225 | 224 |