Eric Lee / smarc-uboot | Embedian Git Server

Commit fb4000e87178bf20aeb0d6c6a71b0e25ff8dcda3

Authored by Michal Simek 2017-02-07 21:32:26 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

arm64: zynqmp: Check pmufw version

If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 4 changed files with 46 additions and 0 deletions Inline Diff

arch/arm/cpu/armv8/zynqmp/cpu.c
arch/arm/include/asm/arch-zynqmp/sys_proto.h
board/xilinx/zynqmp/zynqmp.c
include/configs/xilinx_zynqmp.h

arch/arm/cpu/armv8/zynqmp/cpu.c

Diff comments View file @ fb4000e

 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 #define ZYNQ_SILICON_VER_MASK	0xF000
 #define ZYNQ_SILICON_VER_SHIFT	12
 DECLARE_GLOBAL_DATA_PTR;
 static struct mm_region zynqmp_mem_map[] = {
 	{
 		.virt = 0x0UL,
 		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
 		.size = 0x70000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		.virt = 0xf8000000UL,
 		.phys = 0xf8000000UL,
 		.size = 0x07e00000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
 		.size = 0x200000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		.virt = 0x600000000UL,
 		.phys = 0x600000000UL,
 		.size = 0x800000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
 		.virt = 0xe00000000UL,
 		.phys = 0xe00000000UL,
 		.size = 0xf200000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		/* List terminator */
 		0,
 	}
 };
 struct mm_region *mem_map = zynqmp_mem_map;
 u64 get_page_table_size(void)
 {
 	return 0x14000;
 }
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
 	ver = readl(&csu_base->version);
 	ver &= ZYNQMP_SILICON_VER_MASK;
 	ver >>= ZYNQMP_SILICON_VER_SHIFT;
 	return ver;
 }
 unsigned int zynqmp_get_silicon_version(void)
 {
 	if (current_el() == 3)
 		return zynqmp_get_silicon_version_secure();
 	gd->cpu_clk = get_tbclk();
 	switch (gd->cpu_clk) {
 	case 0 ... 1000000:
 		return ZYNQMP_CSU_VERSION_VELOCE;
 	case 50000000:
 		return ZYNQMP_CSU_VERSION_QEMU;
 	case 4000000:
 		return ZYNQMP_CSU_VERSION_EP108;
 	}
 	return ZYNQMP_CSU_VERSION_SILICON;
 }
 #define ZYNQMP_MMIO_READ	0xC2000014
 #define ZYNQMP_MMIO_WRITE	0xC2000013
 #ifndef CONFIG_SPL_BUILD
 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
 	       u32 *ret_payload)
 {
 	/*
 	 * Added SIP service call Function Identifier
 	 * Make sure to stay in x0 register
 	 */
 	struct pt_regs regs;
 	regs.regs[0] = pm_api_id;
 	regs.regs[1] = ((u64)arg1 << 32) | arg0;
 	regs.regs[2] = ((u64)arg3 << 32) | arg2;
 	smc_call(&regs);
 	if (ret_payload != NULL) {
 		ret_payload[0] = (u32)regs.regs[0];
 		ret_payload[1] = upper_32_bits(regs.regs[0]);
 		ret_payload[2] = (u32)regs.regs[1];
 		ret_payload[3] = upper_32_bits(regs.regs[1]);
 		ret_payload[4] = (u32)regs.regs[2];
 	}
 	return regs.regs[0];
 }
+#define ZYNQMP_SIP_SVC_GET_API_VERSION		0xC2000001
+#define ZYNQMP_PM_VERSION_MAJOR		0
+#define ZYNQMP_PM_VERSION_MINOR		3
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
+#define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
+#define ZYNQMP_PM_VERSION	\
+	((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
+				 ZYNQMP_PM_VERSION_MINOR)
+#if defined(CONFIG_CLK_ZYNQMP)
+void zynqmp_pmufw_version(void)
+{
+	int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 pm_api_version;
+	ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
+			 ret_payload);
+	pm_api_version = ret_payload[1];
+	if (ret)
+		panic("PMUFW is not found - Please load it!\n");
+	printf("PMUFW:\tv%d.%d\n",
+	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
+	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
+	if (pm_api_version != ZYNQMP_PM_VERSION)
+		panic("PMUFW version error. Expected: v%d.%d\n",
+		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
+}
+#endif
 int zynqmp_mmio_write(const u32 address,
 		      const u32 mask,
 		      const u32 value)
 {
 	return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
 }
 int zynqmp_mmio_read(const u32 address, u32 *value)
 {
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	u32 ret;
 	if (!value)
 		return -EINVAL;
 	ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
 	*value = ret_payload[1];
 	return ret;
 }
 #else
 int zynqmp_mmio_write(const u32 address,
 		      const u32 mask,
 		      const u32 value)
 {
 	u32 data;
 	u32 value_local = value;
 	zynqmp_mmio_read(address, &data);
 	data &= ~mask;
 	value_local &= mask;
 	value_local |= data;
 	writel(value_local, (ulong)address);
 	return 0;
 }
 int zynqmp_mmio_read(const u32 address, u32 *value)
 {
 	*value = readl((ulong)address);
 	return 0;
 }
 #endif

arch/arm/include/asm/arch-zynqmp/sys_proto.h

Diff comments View file @ fb4000e

 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 #define PAYLOAD_ARG_CNT		5
 int zynq_slcr_get_mio_pin_status(const char *periph);
 unsigned int zynqmp_get_silicon_version(void);
 void psu_init(void);
 void handoff_setup(void);
+void zynqmp_pmufw_version(void);
 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
 int zynqmp_mmio_read(const u32 address, u32 *value);
 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
 	       u32 *ret_payload);
 #endif /* _ASM_ARCH_SYS_PROTO_H */

board/xilinx/zynqmp/zynqmp.c

Diff comments View file @ fb4000e

 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
 #include <malloc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
 #include <zynqmppl.h>
 #include <i2c.h>
 #include <g_dnl.h>
 DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
     !defined(CONFIG_SPL_BUILD)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 static const struct {
 	uint32_t id;
 	char *name;
 } zynqmp_devices[] = {
 	{
 		.id = 0x10,
 		.name = "3eg",
 	},
 	{
 		.id = 0x11,
 		.name = "2eg",
 	},
 	{
 		.id = 0x20,
 		.name = "5ev",
 	},
 	{
 		.id = 0x21,
 		.name = "4ev",
 	},
 	{
 		.id = 0x30,
 		.name = "7ev",
 	},
 	{
 		.id = 0x38,
 		.name = "9eg",
 	},
 	{
 		.id = 0x39,
 		.name = "6eg",
 	},
 	{
 		.id = 0x40,
 		.name = "11eg",
 	},
 	{
 		.id = 0x50,
 		.name = "15eg",
 	},
 	{
 		.id = 0x58,
 		.name = "19eg",
 	},
 	{
 		.id = 0x59,
 		.name = "17eg",
 	},
 };
 static int chip_id(void)
 {
 	struct pt_regs regs;
 	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 	regs.regs[1] = 0;
 	regs.regs[2] = 0;
 	regs.regs[3] = 0;
 	smc_call(&regs);
 	/*
 	 * SMC returns:
 	 * regs[0][31:0]  = status of the operation
 	 * regs[0][63:32] = CSU.IDCODE register
 	 * regs[1][31:0]  = CSU.version register
 	 */
 	regs.regs[0] = upper_32_bits(regs.regs[0]);
 	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 			ZYNQMP_CSU_IDCODE_SVD_MASK;
 	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 	return regs.regs[0];
 }
 static char *zynqmp_get_silicon_idcode_name(void)
 {
 	uint32_t i, id;
 	id = chip_id();
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 		if (zynqmp_devices[i].id == id)
 			return zynqmp_devices[i].name;
 	}
 	return "unknown";
 }
 #endif
+int board_early_init_f(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
+	zynqmp_pmufw_version();
+#endif
+	return 0;
+}
 #define ZYNQMP_VERSION_SIZE	9
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
     defined(CONFIG_SPL_BUILD))
 	if (current_el() != 3) {
 		static char version[ZYNQMP_VERSION_SIZE];
 		strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 		zynqmppl.name = strncat(version,
 					zynqmp_get_silicon_idcode_name(),
 					ZYNQMP_VERSION_SIZE);
 		printf("Chip ID:\t%s\n", zynqmppl.name);
 		fpga_init();
 		fpga_add(fpga_xilinx, &zynqmppl);
 	}
 #endif
 	return 0;
 }
 int board_early_init_r(void)
 {
 	u32 val;
 	if (current_el() == 3) {
 		val = readl(&crlapb_base->timestamp_ref_ctrl);
 		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 		writel(val, &crlapb_base->timestamp_ref_ctrl);
 		/* Program freq register in System counter */
 		writel(zynqmp_get_system_timer_freq(),
 		       &iou_scntr_secure->base_frequency_id_register);
 		/* And enable system counter */
 		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 		       &iou_scntr_secure->counter_control_register);
 	}
 	/* Program freq register in System counter and enable system counter */
 	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
 	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
 	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 	       &iou_scntr->counter_control_register);
 	return 0;
 }
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
     defined(CONFIG_ZYNQ_EEPROM_BUS)
 	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 			ethaddr, 6))
 		printf("I2C EEPROM MAC address read failed\n");
 #endif
 	return 0;
 }
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
 	fdtdec_setup_memory_banksize();
 	return 0;
 }
 int dram_init(void)
 {
 	if (fdtdec_setup_memory_size() != 0)
 		return -EINVAL;
 	return 0;
 }
 #else
 int dram_init(void)
 {
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
 #endif
 void reset_cpu(ulong addr)
 {
 }
 int board_late_init(void)
 {
 	u32 reg = 0;
 	u8 bootmode;
 	const char *mode;
 	char *new_targets;
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 		debug("Saved variables - Skipping\n");
 		return 0;
 	}
 	reg = readl(&crlapb_base->boot_mode);
 	if (reg >> BOOT_MODE_ALT_SHIFT)
 		reg >>= BOOT_MODE_ALT_SHIFT;
 	bootmode = reg & BOOT_MODES_MASK;
 	puts("Bootmode: ");
 	switch (bootmode) {
 	case USB_MODE:
 		puts("USB_MODE\n");
 		mode = "usb";
 		break;
 	case JTAG_MODE:
 		puts("JTAG_MODE\n");
 		mode = "pxe dhcp";
 		break;
 	case QSPI_MODE_24BIT:
 	case QSPI_MODE_32BIT:
 		mode = "qspi0";
 		puts("QSPI_MODE\n");
 		break;
 	case EMMC_MODE:
 		puts("EMMC_MODE\n");
 		mode = "mmc0";
 		break;
 	case SD_MODE:
 		puts("SD_MODE\n");
 		mode = "mmc0";
 		break;
 	case SD1_LSHFT_MODE:
 		puts("LVL_SHFT_");
 		/* fall through */
 	case SD_MODE1:
 		puts("SD_MODE1\n");
 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 		mode = "mmc1";
 #else
 		mode = "mmc0";
 #endif
 		break;
 	case NAND_MODE:
 		puts("NAND_MODE\n");
 		mode = "nand0";
 		break;
 	default:
 		mode = "";
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
 	}
 	/*
 	 * One terminating char + one byte for space between mode
 	 * and default boot_targets
 	 */
 	new_targets = calloc(1, strlen(mode) +
 				strlen(getenv("boot_targets")) + 2);
 	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 	setenv("boot_targets", new_targets);
 	return 0;
 }
 int checkboard(void)
 {
 	puts("Board: Xilinx ZynqMP\n");
 	return 0;
 }
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data0 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = ZYNQMP_USB0_XHCI_BASEADDR,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
 static struct dwc3_device dwc3_device_data1 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = ZYNQMP_USB1_XHCI_BASEADDR,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 1,
 };
 int usb_gadget_handle_interrupts(int index)
 {
 	dwc3_uboot_handle_interrupt(index);
 	return 0;
 }
 int board_usb_init(int index, enum usb_init_type init)
 {
 	debug("%s: index %x\n", __func__, index);
 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 #endif
 	switch (index) {
 	case 0:
 		return dwc3_uboot_init(&dwc3_device_data0);
 	case 1:
 		return dwc3_uboot_init(&dwc3_device_data1);
 	};
 	return -1;
 }
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
 	dwc3_uboot_exit(index);
 	return 0;
 }
 #endif

include/configs/xilinx_zynqmp.h

Diff comments View file @ fb4000e

 /*
  * Configuration for Xilinx ZynqMP
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
  * Based on Configuration for Versatile Express
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __XILINX_ZYNQMP_H
 #define __XILINX_ZYNQMP_H
 #define CONFIG_REMAKE_ELF
 /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
 /* Generic Interrupt Controller Definitions */
 #define CONFIG_GICV2
 #define GICD_BASE	0xF9010000
 #define GICC_BASE	0xF9020000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_SCRATCH	0xfffc0000
 #ifndef CONFIG_NR_DRAM_BANKS
 # define CONFIG_NR_DRAM_BANKS		2
 #endif
 #define CONFIG_SYS_MEMTEST_START	0
 #define CONFIG_SYS_MEMTEST_END		1000
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
 # define COUNTER_FREQUENCY		100000000
 #endif
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x2000000)
 /* Serial setup */
 #define CONFIG_ARM_DCC
 #define CONFIG_CPU_ARMV8
 #define CONFIG_ZYNQ_SERIAL
 #define CONFIG_CONS_INDEX		0
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 /* Command line configuration */
 #define CONFIG_MP
 /* BOOTP options */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
 /* Diff from config_distro_defaults.h */
 #define CONFIG_SUPPORT_RAW_INITRD
 #if !defined(CONFIG_SPL_BUILD)
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #endif
 #define CONFIG_AUTO_COMPLETE
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define CONFIG_SUPPORT_EMMC_BOOT
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
 # endif
 # define CONFIG_ENV_IS_IN_FAT
 # define FAT_ENV_DEVICE_AND_PART	"0:auto"
 # define FAT_ENV_FILE			"uboot.env"
 # define FAT_ENV_INTERFACE		"mmc"
 #endif
 #ifdef CONFIG_NAND_ARASAN
 # define CONFIG_CMD_NAND_LOCK_UNLOCK
 # define CONFIG_SYS_MAX_NAND_DEVICE	1
 # define CONFIG_SYS_NAND_SELF_INIT
 # define CONFIG_SYS_NAND_ONFI_DETECTION
 # define CONFIG_MTD_DEVICE
 #endif
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 #if defined(CONFIG_ZYNQMP_USB)
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define CONFIG_USB_CABLE_CHECK
 #define CONFIG_CMD_THOR_DOWNLOAD
 #define CONFIG_USB_FUNCTION_THOR
 #define CONFIG_THOR_RESET_OFF
 #define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
 	"setenv dfu_alt_info " \
 	"Image ram $kernel_addr $kernel_size\\\\;" \
 	"system.dtb ram $fdt_addr $fdt_size\0" \
 	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
 	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
 #define DFU_ALT_INFO  \
 		DFU_ALT_INFO_RAM
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_USB_FUNCTION_FASTBOOT
 # define CONFIG_CMD_FASTBOOT
 # define CONFIG_ANDROID_BOOT_IMAGE
 # define CONFIG_FASTBOOT_BUF_ADDR 0x100000
 # define CONFIG_FASTBOOT_BUF_SIZE 0x6000000
 # define CONFIG_FASTBOOT_FLASH
 # ifdef CONFIG_MMC_SDHCI_ZYNQ
 #  define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
 # endif
 # define CONFIG_RANDOM_UUID
 # define PARTS_DEFAULT \
 	"partitions=uuid_disk=${uuid_gpt_disk};" \
 	"name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \
 	"name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0"
 #endif
 #endif
 #if !defined(DFU_ALT_INFO)
 # define DFU_ALT_INFO
 #endif
 #if !defined(PARTS_DEFAULT)
 # define PARTS_DEFAULT
 #endif
 /* Do not preserve environment */
 #if !defined(CONFIG_ENV_IS_IN_FAT)
 #define CONFIG_ENV_IS_NOWHERE		1
 #endif
 #define CONFIG_ENV_SIZE			0x8000
 /* Monitor Command Prompt */
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_MAXARGS		64
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
 # define CONFIG_NET_MULTI
 # define CONFIG_MII
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 # define CONFIG_PHY_MARVELL
 # define CONFIG_PHY_NATSEMI
 # define CONFIG_PHY_TI
 # define CONFIG_PHY_GIGE
 # define CONFIG_PHY_VITESSE
 # define CONFIG_PHY_REALTEK
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
 # define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 # define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
 #endif
 /* EEPROM */
 #ifdef CONFIG_ZYNQMP_EEPROM
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 # define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 # define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
 #endif
 #ifdef CONFIG_SATA_CEVA
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_SCSI
 #endif
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_high=10000000\0" \
 	"initrd_high=10000000\0" \
 	"fdt_addr_r=0x40000000\0" \
 	"pxefile_addr_r=0x10000000\0" \
 	"kernel_addr_r=0x18000000\0" \
 	"scriptaddr=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
 #else
 # define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 #if defined(CONFIG_SATA_CEVA)
 # define BOOT_TARGET_DEVICES_SCSI(func)	func(SCSI, scsi, 0)
 #else
 # define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 #if defined(CONFIG_ZYNQMP_USB)
 # define BOOT_TARGET_DEVICES_USB(func)	func(USB, usb, 0) func(USB, usb, 1)
 #else
 # define BOOT_TARGET_DEVICES_USB(func)
 #endif
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_USB(func) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 /* Initial environment variables */
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV \
 	DFU_ALT_INFO
 #endif
 /* SPL can't handle all huge variables - define just DFU */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 # define CONFIG_EXTRA_ENV_SETTINGS \
 	"dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \
 			  "atf-uboot.ub ram 0x10000000 0x1000000;" \
 			  "Image ram 0x80000 0x3f80000;" \
 			  "system.dtb ram 0x4000000 0x100000\0" \
 	"dfu_bufsiz=0x1000\0"
 #endif
 #define CONFIG_SPL_TEXT_BASE		0xfffc0000
 #define CONFIG_SPL_STACK		0xfffffffc
 #define CONFIG_SPL_MAX_SIZE		0x40000
 /* Just random location in OCM */
 #define CONFIG_SPL_BSS_START_ADDR	0x0
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 #define CONFIG_SPL_FRAMEWORK
 /* u-boot is like dtb */
 #define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
 /* ATF is my kernel image */
 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf-uboot.ub"
 /* FIT load address for RAM boot */
 #define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
 /* MMC support */
 #ifdef CONFIG_MMC_SDHCI_ZYNQ
 # define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
 # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #endif
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
 # undef CONFIG_CMD_BOOTD
 # define CONFIG_SPL_ENV_SUPPORT
 # define CONFIG_SPL_HASH_SUPPORT
 # define CONFIG_ENV_MAX_ENTRIES	10
 # define CONFIG_SYS_SPL_MALLOC_START	0x20000000
 # define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
 #endif
 #endif
+#define CONFIG_BOARD_EARLY_INIT_F
 #endif /* __XILINX_ZYNQMP_H */