Eric Lee / smarc-uboot | Embedian Git Server

Commit fc843a02acad62e231a3e779cebd1712688146fc

Authored by Simon Glass 2017-05-17 17:25:30 +0800

Committed by Tom Rini 2017-05-23 00:45:27 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

Kconfig: Add a CONFIG_IDE option

At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.

Update existing users and move the ide driver into drivers/block since
it should not be in common/.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 38 changed files with 1291 additions and 1284 deletions Inline Diff

README
api/api_storage.c
arch/arm/mach-kirkwood/include/mach/config.h
arch/powerpc/cpu/mpc5xxx/ide.c
arch/powerpc/lib/Makefile
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m54455evb/m54455evb.c
board/intercontrol/digsy_mtc/digsy_mtc.c
board/jupiter/jupiter.c
board/phytec/pcm030/pcm030.c
board/tqc/tqm5200/tqm5200.c
board/v38b/v38b.c
cmd/Kconfig
cmd/pcmcia.c
common/Makefile
common/board_r.c
common/ide.c
drivers/block/Kconfig
drivers/block/Makefile
drivers/block/ide.c
drivers/block/sil680.c
drivers/pcmcia/marubun_pcmcia.c
drivers/pcmcia/mpc8xx_pcmcia.c
drivers/pcmcia/tqm8xx_pcmcia.c
fs/fat/fat.c
include/config_distro_bootcmd.h
include/config_fallbacks.h
include/configs/M5253DEMO.h
include/configs/edminiv2.h
include/configs/ib62x0.h
include/configs/lsxl.h
include/configs/mpc5121ads.h
include/configs/nsa310s.h
include/configs/qemu-x86.h
include/configs/r7780mp.h
include/configs/sheevaplug.h
include/pcmcia.h

README

Diff comments View file @ fc843a0

api/api_storage.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2007-2008 Semihalf	2	* (C) Copyright 2007-2008 Semihalf
3	*	3	*
4	* Written by: Rafal Jaworowski <raj@semihalf.com>	4	* Written by: Rafal Jaworowski <raj@semihalf.com>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	#include <config.h>	9	#include <config.h>
10	#include <common.h>	10	#include <common.h>
11	#include <api_public.h>	11	#include <api_public.h>
12		12
13	#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)	13	#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
14	#include <usb.h>	14	#include <usb.h>
15	#endif	15	#endif
16		16
17	#define DEBUG	17	#define DEBUG
18	#undef DEBUG	18	#undef DEBUG
19		19
20	#ifdef DEBUG	20	#ifdef DEBUG
21	#define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)	21	#define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)
22	#else	22	#else
23	#define debugf(fmt, args...)	23	#define debugf(fmt, args...)
24	#endif	24	#endif
25		25
26	#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)	26	#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
27		27
28		28
29	#define ENUM_IDE 0	29	#define ENUM_IDE 0
30	#define ENUM_USB 1	30	#define ENUM_USB 1
31	#define ENUM_SCSI 2	31	#define ENUM_SCSI 2
32	#define ENUM_MMC 3	32	#define ENUM_MMC 3
33	#define ENUM_SATA 4	33	#define ENUM_SATA 4
34	#define ENUM_MAX 5	34	#define ENUM_MAX 5
35		35
36	struct stor_spec {	36	struct stor_spec {
37	int max_dev;	37	int max_dev;
38	int enum_started;	38	int enum_started;
39	int enum_ended;	39	int enum_ended;
40	int type; /* "external" type: DT_STOR_{IDE,USB,etc} */	40	int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
41	char *name;	41	char *name;
42	};	42	};
43		43
44	static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };	44	static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
45		45
46		46
47	void dev_stor_init(void)	47	void dev_stor_init(void)
48	{	48	{
49	#if defined(CONFIG_CMD_IDE)	49	#if defined(CONFIG_IDE)
50	specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;	50	specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
51	specs[ENUM_IDE].enum_started = 0;	51	specs[ENUM_IDE].enum_started = 0;
52	specs[ENUM_IDE].enum_ended = 0;	52	specs[ENUM_IDE].enum_ended = 0;
53	specs[ENUM_IDE].type = DEV_TYP_STOR \| DT_STOR_IDE;	53	specs[ENUM_IDE].type = DEV_TYP_STOR \| DT_STOR_IDE;
54	specs[ENUM_IDE].name = "ide";	54	specs[ENUM_IDE].name = "ide";
55	#endif	55	#endif
56	#if defined(CONFIG_CMD_MMC)	56	#if defined(CONFIG_CMD_MMC)
57	specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;	57	specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
58	specs[ENUM_MMC].enum_started = 0;	58	specs[ENUM_MMC].enum_started = 0;
59	specs[ENUM_MMC].enum_ended = 0;	59	specs[ENUM_MMC].enum_ended = 0;
60	specs[ENUM_MMC].type = DEV_TYP_STOR \| DT_STOR_MMC;	60	specs[ENUM_MMC].type = DEV_TYP_STOR \| DT_STOR_MMC;
61	specs[ENUM_MMC].name = "mmc";	61	specs[ENUM_MMC].name = "mmc";
62	#endif	62	#endif
63	#if defined(CONFIG_CMD_SATA)	63	#if defined(CONFIG_CMD_SATA)
64	specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;	64	specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
65	specs[ENUM_SATA].enum_started = 0;	65	specs[ENUM_SATA].enum_started = 0;
66	specs[ENUM_SATA].enum_ended = 0;	66	specs[ENUM_SATA].enum_ended = 0;
67	specs[ENUM_SATA].type = DEV_TYP_STOR \| DT_STOR_SATA;	67	specs[ENUM_SATA].type = DEV_TYP_STOR \| DT_STOR_SATA;
68	specs[ENUM_SATA].name = "sata";	68	specs[ENUM_SATA].name = "sata";
69	#endif	69	#endif
70	#if defined(CONFIG_SCSI)	70	#if defined(CONFIG_SCSI)
71	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;	71	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
72	specs[ENUM_SCSI].enum_started = 0;	72	specs[ENUM_SCSI].enum_started = 0;
73	specs[ENUM_SCSI].enum_ended = 0;	73	specs[ENUM_SCSI].enum_ended = 0;
74	specs[ENUM_SCSI].type = DEV_TYP_STOR \| DT_STOR_SCSI;	74	specs[ENUM_SCSI].type = DEV_TYP_STOR \| DT_STOR_SCSI;
75	specs[ENUM_SCSI].name = "scsi";	75	specs[ENUM_SCSI].name = "scsi";
76	#endif	76	#endif
77	#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)	77	#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
78	specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;	78	specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
79	specs[ENUM_USB].enum_started = 0;	79	specs[ENUM_USB].enum_started = 0;
80	specs[ENUM_USB].enum_ended = 0;	80	specs[ENUM_USB].enum_ended = 0;
81	specs[ENUM_USB].type = DEV_TYP_STOR \| DT_STOR_USB;	81	specs[ENUM_USB].type = DEV_TYP_STOR \| DT_STOR_USB;
82	specs[ENUM_USB].name = "usb";	82	specs[ENUM_USB].name = "usb";
83	#endif	83	#endif
84	}	84	}
85		85
86	/*	86	/*
87	* Finds next available device in the storage group	87	* Finds next available device in the storage group
88	*	88	*
89	* type: storage group type - ENUM_IDE, ENUM_SCSI etc.	89	* type: storage group type - ENUM_IDE, ENUM_SCSI etc.
90	*	90	*
91	* more: returns 0/1 depending if there are more devices in this group	91	* more: returns 0/1 depending if there are more devices in this group
92	* available (for future iterations)	92	* available (for future iterations)
93	*	93	*
94	* returns: 0/1 depending if device found in this iteration	94	* returns: 0/1 depending if device found in this iteration
95	*/	95	*/
96	static int dev_stor_get(int type, int more, struct device_info di)	96	static int dev_stor_get(int type, int more, struct device_info di)
97	{	97	{
98	struct blk_desc *dd;	98	struct blk_desc *dd;
99	int found = 0;	99	int found = 0;
100	int i = 0;	100	int i = 0;
101		101
102	/* Wasn't configured for this type, return 0 directly */	102	/* Wasn't configured for this type, return 0 directly */
103	if (specs[type].name == NULL)	103	if (specs[type].name == NULL)
104	return 0;	104	return 0;
105		105
106	if (di->cookie != NULL) {	106	if (di->cookie != NULL) {
107	/* Find the last device we've returned */	107	/* Find the last device we've returned */
108	for (i = 0; i < specs[type].max_dev; i++) {	108	for (i = 0; i < specs[type].max_dev; i++) {
109	if (di->cookie ==	109	if (di->cookie ==
110	(void *)blk_get_dev(specs[type].name, i)) {	110	(void *)blk_get_dev(specs[type].name, i)) {
111	i += 1;	111	i += 1;
112	break;	112	break;
113	}	113	}
114	}	114	}
115	}	115	}
116		116
117	for (; i < specs[type].max_dev; i++) {	117	for (; i < specs[type].max_dev; i++) {
118	di->cookie = (void *)blk_get_dev(specs[type].name, i);	118	di->cookie = (void *)blk_get_dev(specs[type].name, i);
119		119
120	if (di->cookie != NULL) {	120	if (di->cookie != NULL) {
121	found = 1;	121	found = 1;
122	break;	122	break;
123	}	123	}
124	}	124	}
125		125
126	if (i == specs[type].max_dev)	126	if (i == specs[type].max_dev)
127	*more = 0;	127	*more = 0;
128	else	128	else
129	*more = 1;	129	*more = 1;
130		130
131	if (found) {	131	if (found) {
132	di->type = specs[type].type;	132	di->type = specs[type].type;
133		133
134	dd = (struct blk_desc *)di->cookie;	134	dd = (struct blk_desc *)di->cookie;
135	if (dd->type == DEV_TYPE_UNKNOWN) {	135	if (dd->type == DEV_TYPE_UNKNOWN) {
136	debugf("device instance exists, but is not active..");	136	debugf("device instance exists, but is not active..");
137	found = 0;	137	found = 0;
138	} else {	138	} else {
139	di->di_stor.block_count = dd->lba;	139	di->di_stor.block_count = dd->lba;
140	di->di_stor.block_size = dd->blksz;	140	di->di_stor.block_size = dd->blksz;
141	}	141	}
142	} else {	142	} else {
143	di->cookie = NULL;	143	di->cookie = NULL;
144	}	144	}
145		145
146	return found;	146	return found;
147	}	147	}
148		148
149		149
150	/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */	150	/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
151		151
152	static int dev_stor_type(struct blk_desc *dd)	152	static int dev_stor_type(struct blk_desc *dd)
153	{	153	{
154	int i, j;	154	int i, j;
155		155
156	for (i = ENUM_IDE; i < ENUM_MAX; i++)	156	for (i = ENUM_IDE; i < ENUM_MAX; i++)
157	for (j = 0; j < specs[i].max_dev; j++)	157	for (j = 0; j < specs[i].max_dev; j++)
158	if (dd == blk_get_dev(specs[i].name, j))	158	if (dd == blk_get_dev(specs[i].name, j))
159	return i;	159	return i;
160		160
161	return ENUM_MAX;	161	return ENUM_MAX;
162	}	162	}
163		163
164		164
165	/* returns: 0/1 whether cookie points to some device in this group */	165	/* returns: 0/1 whether cookie points to some device in this group */
166		166
167	static int dev_is_stor(int type, struct device_info *di)	167	static int dev_is_stor(int type, struct device_info *di)
168	{	168	{
169	return (dev_stor_type(di->cookie) == type) ? 1 : 0;	169	return (dev_stor_type(di->cookie) == type) ? 1 : 0;
170	}	170	}
171		171
172		172
173	static int dev_enum_stor(int type, struct device_info *di)	173	static int dev_enum_stor(int type, struct device_info *di)
174	{	174	{
175	int found = 0, more = 0;	175	int found = 0, more = 0;
176		176
177	debugf("called, type %d\n", type);	177	debugf("called, type %d\n", type);
178		178
179	/*	179	/*
180	* Formulae for enumerating storage devices:	180	* Formulae for enumerating storage devices:
181	* 1. if cookie (hint from previous enum call) is NULL we start again	181	* 1. if cookie (hint from previous enum call) is NULL we start again
182	* with enumeration, so return the first available device, done.	182	* with enumeration, so return the first available device, done.
183	*	183	*
184	* 2. if cookie is not NULL, check if it identifies some device in	184	* 2. if cookie is not NULL, check if it identifies some device in
185	* this group:	185	* this group:
186	*	186	*
187	* 2a. if cookie is a storage device from our group (IDE, USB etc.),	187	* 2a. if cookie is a storage device from our group (IDE, USB etc.),
188	* return next available (if exists) in this group	188	* return next available (if exists) in this group
189	*	189	*
190	* 2b. if it isn't device from our group, check if such devices were	190	* 2b. if it isn't device from our group, check if such devices were
191	* ever enumerated before:	191	* ever enumerated before:
192	* - if not, return the first available device from this group	192	* - if not, return the first available device from this group
193	* - else return 0	193	* - else return 0
194	*/	194	*/
195		195
196	if (di->cookie == NULL) {	196	if (di->cookie == NULL) {
197	debugf("group%d - enum restart\n", type);	197	debugf("group%d - enum restart\n", type);
198		198
199	/*	199	/*
200	* 1. Enumeration (re-)started: take the first available	200	* 1. Enumeration (re-)started: take the first available
201	* device, if exists	201	* device, if exists
202	*/	202	*/
203	found = dev_stor_get(type, &more, di);	203	found = dev_stor_get(type, &more, di);
204	specs[type].enum_started = 1;	204	specs[type].enum_started = 1;
205		205
206	} else if (dev_is_stor(type, di)) {	206	} else if (dev_is_stor(type, di)) {
207	debugf("group%d - enum continued for the next device\n", type);	207	debugf("group%d - enum continued for the next device\n", type);
208		208
209	if (specs[type].enum_ended) {	209	if (specs[type].enum_ended) {
210	debugf("group%d - nothing more to enum!\n", type);	210	debugf("group%d - nothing more to enum!\n", type);
211	return 0;	211	return 0;
212	}	212	}
213		213
214	/* 2a. Attempt to take a next available device in the group */	214	/* 2a. Attempt to take a next available device in the group */
215	found = dev_stor_get(type, &more, di);	215	found = dev_stor_get(type, &more, di);
216		216
217	} else {	217	} else {
218	if (specs[type].enum_ended) {	218	if (specs[type].enum_ended) {
219	debugf("group %d - already enumerated, skipping\n", type);	219	debugf("group %d - already enumerated, skipping\n", type);
220	return 0;	220	return 0;
221	}	221	}
222		222
223	debugf("group%d - first time enum\n", type);	223	debugf("group%d - first time enum\n", type);
224		224
225	if (specs[type].enum_started == 0) {	225	if (specs[type].enum_started == 0) {
226	/*	226	/*
227	* 2b. If enumerating devices in this group did not	227	* 2b. If enumerating devices in this group did not
228	* happen before, it means the cookie pointed to a	228	* happen before, it means the cookie pointed to a
229	* device from some other group (another storage	229	* device from some other group (another storage
230	* group, or network); in this case try to take the	230	* group, or network); in this case try to take the
231	* first available device from our group	231	* first available device from our group
232	*/	232	*/
233	specs[type].enum_started = 1;	233	specs[type].enum_started = 1;
234		234
235	/*	235	/*
236	* Attempt to take the first device in this group:	236	* Attempt to take the first device in this group:
237	*'first element' flag is set	237	*'first element' flag is set
238	*/	238	*/
239	found = dev_stor_get(type, &more, di);	239	found = dev_stor_get(type, &more, di);
240		240
241	} else {	241	} else {
242	errf("group%d - out of order iteration\n", type);	242	errf("group%d - out of order iteration\n", type);
243	found = 0;	243	found = 0;
244	more = 0;	244	more = 0;
245	}	245	}
246	}	246	}
247		247
248	/*	248	/*
249	* If there are no more devices in this group, consider its	249	* If there are no more devices in this group, consider its
250	* enumeration finished	250	* enumeration finished
251	*/	251	*/
252	specs[type].enum_ended = (!more) ? 1 : 0;	252	specs[type].enum_ended = (!more) ? 1 : 0;
253		253
254	if (found)	254	if (found)
255	debugf("device found, returning cookie 0x%08x\n",	255	debugf("device found, returning cookie 0x%08x\n",
256	(u_int32_t)di->cookie);	256	(u_int32_t)di->cookie);
257	else	257	else
258	debugf("no device found\n");	258	debugf("no device found\n");
259		259
260	return found;	260	return found;
261	}	261	}
262		262
263	void dev_enum_reset(void)	263	void dev_enum_reset(void)
264	{	264	{
265	int i;	265	int i;
266		266
267	for (i = 0; i < ENUM_MAX; i ++) {	267	for (i = 0; i < ENUM_MAX; i ++) {
268	specs[i].enum_started = 0;	268	specs[i].enum_started = 0;
269	specs[i].enum_ended = 0;	269	specs[i].enum_ended = 0;
270	}	270	}
271	}	271	}
272		272
273	int dev_enum_storage(struct device_info *di)	273	int dev_enum_storage(struct device_info *di)
274	{	274	{
275	int i;	275	int i;
276		276
277	/* check: ide, usb, scsi, mmc */	277	/* check: ide, usb, scsi, mmc */
278	for (i = ENUM_IDE; i < ENUM_MAX; i ++) {	278	for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
279	if (dev_enum_stor(i, di))	279	if (dev_enum_stor(i, di))
280	return 1;	280	return 1;
281	}	281	}
282		282
283	return 0;	283	return 0;
284	}	284	}
285		285
286	static int dev_stor_is_valid(int type, struct blk_desc *dd)	286	static int dev_stor_is_valid(int type, struct blk_desc *dd)
287	{	287	{
288	int i;	288	int i;
289		289
290	for (i = 0; i < specs[type].max_dev; i++)	290	for (i = 0; i < specs[type].max_dev; i++)
291	if (dd == blk_get_dev(specs[type].name, i))	291	if (dd == blk_get_dev(specs[type].name, i))
292	if (dd->type != DEV_TYPE_UNKNOWN)	292	if (dd->type != DEV_TYPE_UNKNOWN)
293	return 1;	293	return 1;
294		294
295	return 0;	295	return 0;
296	}	296	}
297		297
298		298
299	int dev_open_stor(void *cookie)	299	int dev_open_stor(void *cookie)
300	{	300	{
301	int type = dev_stor_type(cookie);	301	int type = dev_stor_type(cookie);
302		302
303	if (type == ENUM_MAX)	303	if (type == ENUM_MAX)
304	return API_ENODEV;	304	return API_ENODEV;
305		305
306	if (dev_stor_is_valid(type, (struct blk_desc *)cookie))	306	if (dev_stor_is_valid(type, (struct blk_desc *)cookie))
307	return 0;	307	return 0;
308		308
309	return API_ENODEV;	309	return API_ENODEV;
310	}	310	}
311		311
312		312
313	int dev_close_stor(void *cookie)	313	int dev_close_stor(void *cookie)
314	{	314	{
315	/*	315	/*
316	* Not much to do as we actually do not alter storage devices upon	316	* Not much to do as we actually do not alter storage devices upon
317	* close	317	* close
318	*/	318	*/
319	return 0;	319	return 0;
320	}	320	}
321		321
322		322
323	lbasize_t dev_read_stor(void cookie, void buf, lbasize_t len, lbastart_t start)	323	lbasize_t dev_read_stor(void cookie, void buf, lbasize_t len, lbastart_t start)
324	{	324	{
325	int type;	325	int type;
326	struct blk_desc dd = (struct blk_desc )cookie;	326	struct blk_desc dd = (struct blk_desc )cookie;
327		327
328	if ((type = dev_stor_type(dd)) == ENUM_MAX)	328	if ((type = dev_stor_type(dd)) == ENUM_MAX)
329	return 0;	329	return 0;
330		330
331	if (!dev_stor_is_valid(type, dd))	331	if (!dev_stor_is_valid(type, dd))
332	return 0;	332	return 0;
333		333
334	#ifdef CONFIG_BLK	334	#ifdef CONFIG_BLK
335	return blk_dread(dd, start, len, buf);	335	return blk_dread(dd, start, len, buf);
336	#else	336	#else
337	if ((dd->block_read) == NULL) {	337	if ((dd->block_read) == NULL) {
338	debugf("no block_read() for device 0x%08x\n", cookie);	338	debugf("no block_read() for device 0x%08x\n", cookie);
339	return 0;	339	return 0;
340	}	340	}
341		341
342	return dd->block_read(dd, start, len, buf);	342	return dd->block_read(dd, start, len, buf);
343	#endif /* defined(CONFIG_BLK) */	343	#endif /* defined(CONFIG_BLK) */
344	}	344	}
345		345

arch/arm/mach-kirkwood/include/mach/config.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2011	2	* (C) Copyright 2011
3	* Marvell Semiconductor <www.marvell.com>	3	* Marvell Semiconductor <www.marvell.com>
4	* Written-by: Lei Wen <leiwen@marvell.com>	4	* Written-by: Lei Wen <leiwen@marvell.com>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	/*	9	/*
10	* This file should be included in board config header file.	10	* This file should be included in board config header file.
11	*	11	*
12	* It supports common definitions for Kirkwood platform	12	* It supports common definitions for Kirkwood platform
13	*/	13	*/
14		14
15	#ifndef _KW_CONFIG_H	15	#ifndef _KW_CONFIG_H
16	#define _KW_CONFIG_H	16	#define _KW_CONFIG_H
17		17
18	#if defined (CONFIG_KW88F6281)	18	#if defined (CONFIG_KW88F6281)
19	#include <asm/arch/kw88f6281.h>	19	#include <asm/arch/kw88f6281.h>
20	#elif defined (CONFIG_KW88F6192)	20	#elif defined (CONFIG_KW88F6192)
21	#include <asm/arch/kw88f6192.h>	21	#include <asm/arch/kw88f6192.h>
22	#else	22	#else
23	#error "SOC Name not defined"	23	#error "SOC Name not defined"
24	#endif /* CONFIG_KW88F6281 */	24	#endif /* CONFIG_KW88F6281 */
25		25
26	#include <asm/arch/soc.h>	26	#include <asm/arch/soc.h>
27	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */	27	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
28	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */	28	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
29	#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */	29	#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
30		30
31	/*	31	/*
32	* By default kwbimage.cfg from board specific folder is used	32	* By default kwbimage.cfg from board specific folder is used
33	* If for some board, different configuration file need to be used,	33	* If for some board, different configuration file need to be used,
34	* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file	34	* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
35	*/	35	*/
36	#ifndef CONFIG_SYS_KWD_CONFIG	36	#ifndef CONFIG_SYS_KWD_CONFIG
37	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg	37	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
38	#endif /* CONFIG_SYS_KWD_CONFIG */	38	#endif /* CONFIG_SYS_KWD_CONFIG */
39		39
40	/* Kirkwood has 2k of Security SRAM, use it for SP */	40	/* Kirkwood has 2k of Security SRAM, use it for SP */
41	#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000	41	#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
42	#define CONFIG_NR_DRAM_BANKS_MAX 2	42	#define CONFIG_NR_DRAM_BANKS_MAX 2
43		43
44	#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE	44	#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
45	#define MV_UART_CONSOLE_BASE KW_UART0_BASE	45	#define MV_UART_CONSOLE_BASE KW_UART0_BASE
46	#define MV_SATA_BASE KW_SATA_BASE	46	#define MV_SATA_BASE KW_SATA_BASE
47	#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET	47	#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
48	#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET	48	#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
49		49
50	/*	50	/*
51	* NAND configuration	51	* NAND configuration
52	*/	52	*/
53	#ifdef CONFIG_CMD_NAND	53	#ifdef CONFIG_CMD_NAND
54	#define CONFIG_NAND_KIRKWOOD	54	#define CONFIG_NAND_KIRKWOOD
55	#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */	55	#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
56	#define NAND_ALLOW_ERASE_ALL 1	56	#define NAND_ALLOW_ERASE_ALL 1
57	#endif	57	#endif
58		58
59	/*	59	/*
60	* SPI Flash configuration	60	* SPI Flash configuration
61	*/	61	*/
62	#ifdef CONFIG_CMD_SF	62	#ifdef CONFIG_CMD_SF
63	#define CONFIG_HARD_SPI 1	63	#define CONFIG_HARD_SPI 1
64	#define CONFIG_KIRKWOOD_SPI 1	64	#define CONFIG_KIRKWOOD_SPI 1
65	#ifndef CONFIG_ENV_SPI_BUS	65	#ifndef CONFIG_ENV_SPI_BUS
66	# define CONFIG_ENV_SPI_BUS 0	66	# define CONFIG_ENV_SPI_BUS 0
67	#endif	67	#endif
68	#ifndef CONFIG_ENV_SPI_CS	68	#ifndef CONFIG_ENV_SPI_CS
69	# define CONFIG_ENV_SPI_CS 0	69	# define CONFIG_ENV_SPI_CS 0
70	#endif	70	#endif
71	#ifndef CONFIG_ENV_SPI_MAX_HZ	71	#ifndef CONFIG_ENV_SPI_MAX_HZ
72	# define CONFIG_ENV_SPI_MAX_HZ 50000000	72	# define CONFIG_ENV_SPI_MAX_HZ 50000000
73	#endif	73	#endif
74	#endif	74	#endif
75		75
76	/*	76	/*
77	* Ethernet Driver configuration	77	* Ethernet Driver configuration
78	*/	78	*/
79	#ifdef CONFIG_CMD_NET	79	#ifdef CONFIG_CMD_NET
80	#define CONFIG_NETCONSOLE /* include NetConsole support */	80	#define CONFIG_NETCONSOLE /* include NetConsole support */
81	#define CONFIG_MII /* expose smi ove miiphy interface */	81	#define CONFIG_MII /* expose smi ove miiphy interface */
82	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */	82	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
83	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */	83	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
84	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */	84	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
85	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */	85	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
86	#endif /* CONFIG_CMD_NET */	86	#endif /* CONFIG_CMD_NET */
87		87
88	/*	88	/*
89	* USB/EHCI	89	* USB/EHCI
90	*/	90	*/
91	#ifdef CONFIG_CMD_USB	91	#ifdef CONFIG_CMD_USB
92	#define CONFIG_EHCI_IS_TDI	92	#define CONFIG_EHCI_IS_TDI
93	#endif /* CONFIG_CMD_USB */	93	#endif /* CONFIG_CMD_USB */
94		94
95	/*	95	/*
96	* IDE Support on SATA ports	96	* IDE Support on SATA ports
97	*/	97	*/
98	#ifdef CONFIG_CMD_IDE	98	#ifdef CONFIG_IDE
99	#define __io	99	#define __io
100	#define CONFIG_MVSATA_IDE	100	#define CONFIG_MVSATA_IDE
101	#define CONFIG_IDE_PREINIT	101	#define CONFIG_IDE_PREINIT
102	#define CONFIG_MVSATA_IDE_USE_PORT1	102	#define CONFIG_MVSATA_IDE_USE_PORT1
103	/* Needs byte-swapping for ATA data register */	103	/* Needs byte-swapping for ATA data register */
104	#define CONFIG_IDE_SWAP_IO	104	#define CONFIG_IDE_SWAP_IO
105	/* Data, registers and alternate blocks are at the same offset */	105	/* Data, registers and alternate blocks are at the same offset */
106	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)	106	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
107	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)	107	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
108	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)	108	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
109	/* Each 8-bit ATA register is aligned to a 4-bytes address */	109	/* Each 8-bit ATA register is aligned to a 4-bytes address */
110	#define CONFIG_SYS_ATA_STRIDE 4	110	#define CONFIG_SYS_ATA_STRIDE 4
111	/* Controller supports 48-bits LBA addressing */	111	/* Controller supports 48-bits LBA addressing */
112	#define CONFIG_LBA48	112	#define CONFIG_LBA48
113	/* CONFIG_CMD_IDE requires some #defines for ATA registers */	113	/* CONFIG_IDE requires some #defines for ATA registers */
114	#define CONFIG_SYS_IDE_MAXBUS 2	114	#define CONFIG_SYS_IDE_MAXBUS 2
115	#define CONFIG_SYS_IDE_MAXDEVICE 2	115	#define CONFIG_SYS_IDE_MAXDEVICE 2
116	/* ATA registers base is at SATA controller base */	116	/* ATA registers base is at SATA controller base */
117	#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE	117	#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
118	#endif /* CONFIG_CMD_IDE */	118	#endif /* CONFIG_IDE */
119		119
120	/*	120	/*
121	* I2C related stuff	121	* I2C related stuff
122	*/	122	*/
123	#ifdef CONFIG_CMD_I2C	123	#ifdef CONFIG_CMD_I2C
124	#ifndef CONFIG_SYS_I2C_SOFT	124	#ifndef CONFIG_SYS_I2C_SOFT
125	#define CONFIG_SYS_I2C	125	#define CONFIG_SYS_I2C
126	#define CONFIG_SYS_I2C_MVTWSI	126	#define CONFIG_SYS_I2C_MVTWSI
127	#endif	127	#endif
128	#define CONFIG_SYS_I2C_SLAVE 0x0	128	#define CONFIG_SYS_I2C_SLAVE 0x0
129	#define CONFIG_SYS_I2C_SPEED 100000	129	#define CONFIG_SYS_I2C_SPEED 100000
130	#endif	130	#endif
131		131
132	/* Use common timer */	132	/* Use common timer */
133	#define CONFIG_SYS_TIMER_COUNTS_DOWN	133	#define CONFIG_SYS_TIMER_COUNTS_DOWN
134	#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)	134	#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
135	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK	135	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
136		136
137	#endif /* _KW_CONFIG_H */	137	#endif /* _KW_CONFIG_H */
138		138

arch/powerpc/cpu/mpc5xxx/ide.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2004	2	* (C) Copyright 2004
3	* Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>	3	* Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*	6	*
7	* Init is derived from Linux code.	7	* Init is derived from Linux code.
8	*/	8	*/
9	#include <common.h>	9	#include <common.h>
10		10
11	#if defined(CONFIG_CMD_IDE)	11	#if defined(CONFIG_IDE)
12	#include <mpc5xxx.h>	12	#include <mpc5xxx.h>
13		13
14	DECLARE_GLOBAL_DATA_PTR;	14	DECLARE_GLOBAL_DATA_PTR;
15		15
16	#define CALC_TIMING(t) (t + period - 1) / period	16	#define CALC_TIMING(t) (t + period - 1) / period
17		17
18	#ifdef CONFIG_IDE_RESET	18	#ifdef CONFIG_IDE_RESET
19	extern void init_ide_reset (void);	19	extern void init_ide_reset (void);
20	#endif	20	#endif
21		21
22	int ide_preinit (void)	22	int ide_preinit (void)
23	{	23	{
24	long period, t0, t1, t2_8, t2_16, t4, ta;	24	long period, t0, t1, t2_8, t2_16, t4, ta;
25	vu_long reg;	25	vu_long reg;
26	struct mpc5xxx_sdma psdma = (struct mpc5xxx_sdma ) MPC5XXX_SDMA;	26	struct mpc5xxx_sdma psdma = (struct mpc5xxx_sdma ) MPC5XXX_SDMA;
27		27
28	reg = (vu_long ) MPC5XXX_GPS_PORT_CONFIG;	28	reg = (vu_long ) MPC5XXX_GPS_PORT_CONFIG;
29	#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)	29	#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
30	/* ATA cs0/1 on i2c2 clk/io */	30	/* ATA cs0/1 on i2c2 clk/io */
31	reg = (reg & ~0x03000000ul) \| 0x02000000ul;	31	reg = (reg & ~0x03000000ul) \| 0x02000000ul;
32	#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)	32	#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
33	/* ATA cs0/1 on Timer 0/1 */	33	/* ATA cs0/1 on Timer 0/1 */
34	reg = (reg & ~0x03000000ul) \| 0x03000000ul;	34	reg = (reg & ~0x03000000ul) \| 0x03000000ul;
35	#else	35	#else
36	/* ATA cs0/1 on Local Plus cs4/5 */	36	/* ATA cs0/1 on Local Plus cs4/5 */
37	reg = (reg & ~0x03000000ul) \| 0x01000000ul;	37	reg = (reg & ~0x03000000ul) \| 0x01000000ul;
38	#endif /* CONFIG_TOTAL5200 */	38	#endif /* CONFIG_TOTAL5200 */
39	(vu_long ) MPC5XXX_GPS_PORT_CONFIG = reg;	39	(vu_long ) MPC5XXX_GPS_PORT_CONFIG = reg;
40		40
41	/* All sample codes do that... */	41	/* All sample codes do that... */
42	(vu_long ) MPC5XXX_ATA_SHARE_COUNT = 0;	42	(vu_long ) MPC5XXX_ATA_SHARE_COUNT = 0;
43		43
44	/* Configure and reset host */	44	/* Configure and reset host */
45	(vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY \|	45	(vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY \|
46	MPC5xxx_ATA_HOSTCONF_SMR \| MPC5xxx_ATA_HOSTCONF_FR;	46	MPC5xxx_ATA_HOSTCONF_SMR \| MPC5xxx_ATA_HOSTCONF_FR;
47	udelay (10);	47	udelay (10);
48	(vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;	48	(vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
49		49
50	/* Disable prefetch on Commbus */	50	/* Disable prefetch on Commbus */
51	psdma->PtdCntrl \|= 1;	51	psdma->PtdCntrl \|= 1;
52		52
53	/* Init timings : we use PIO mode 0 timings */	53	/* Init timings : we use PIO mode 0 timings */
54	period = 1000000000 / gd->arch.ipb_clk; /* period in ns */	54	period = 1000000000 / gd->arch.ipb_clk; /* period in ns */
55		55
56	t0 = CALC_TIMING (600);	56	t0 = CALC_TIMING (600);
57	t2_8 = CALC_TIMING (290);	57	t2_8 = CALC_TIMING (290);
58	t2_16 = CALC_TIMING (165);	58	t2_16 = CALC_TIMING (165);
59	reg = (t0 << 24) \| (t2_8 << 16) \| (t2_16 << 8);	59	reg = (t0 << 24) \| (t2_8 << 16) \| (t2_16 << 8);
60	(vu_long ) MPC5XXX_ATA_PIO1 = reg;	60	(vu_long ) MPC5XXX_ATA_PIO1 = reg;
61		61
62	t4 = CALC_TIMING (30);	62	t4 = CALC_TIMING (30);
63	t1 = CALC_TIMING (70);	63	t1 = CALC_TIMING (70);
64	ta = CALC_TIMING (35);	64	ta = CALC_TIMING (35);
65	reg = (t4 << 24) \| (t1 << 16) \| (ta << 8);	65	reg = (t4 << 24) \| (t1 << 16) \| (ta << 8);
66		66
67	(vu_long ) MPC5XXX_ATA_PIO2 = reg;	67	(vu_long ) MPC5XXX_ATA_PIO2 = reg;
68		68
69	#ifdef CONFIG_IDE_RESET	69	#ifdef CONFIG_IDE_RESET
70	init_ide_reset ();	70	init_ide_reset ();
71	#endif /* CONFIG_IDE_RESET */	71	#endif /* CONFIG_IDE_RESET */
72		72
73	return (0);	73	return (0);
74	}	74	}
75	#endif	75	#endif
76		76

arch/powerpc/lib/Makefile

Diff comments View file @ fc843a0

1	#	1	#
2	# (C) Copyright 2000-2006	2	# (C) Copyright 2000-2006
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#	4	#
5	# SPDX-License-Identifier: GPL-2.0+	5	# SPDX-License-Identifier: GPL-2.0+
6	#	6	#
7		7
8	## Build a couple of necessary functions into a private libgcc	8	## Build a couple of necessary functions into a private libgcc
9	## if the user asked for it	9	## if the user asked for it
10	lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o	10	lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o
11		11
12	MINIMAL=	12	MINIMAL=
13		13
14	ifdef CONFIG_SPL_BUILD	14	ifdef CONFIG_SPL_BUILD
15	ifdef CONFIG_SPL_INIT_MINIMAL	15	ifdef CONFIG_SPL_INIT_MINIMAL
16	MINIMAL=y	16	MINIMAL=y
17	endif	17	endif
18	endif	18	endif
19		19
20	obj-$(CONFIG_SYS_EXTBDINFO) += setup.o	20	obj-$(CONFIG_SYS_EXTBDINFO) += setup.o
21	ifdef MINIMAL	21	ifdef MINIMAL
22	obj-y += cache.o time.o	22	obj-y += cache.o time.o
23	obj-y += ticks.o	23	obj-y += ticks.o
24	else	24	else
25		25
26	obj-y += ppcstring.o	26	obj-y += ppcstring.o
27		27
28	obj-y += ppccache.o	28	obj-y += ppccache.o
29	obj-y += ticks.o	29	obj-y += ticks.o
30	obj-y += reloc.o	30	obj-y += reloc.o
31		31
32	obj-$(CONFIG_BAT_RW) += bat_rw.o	32	obj-$(CONFIG_BAT_RW) += bat_rw.o
33	obj-$(CONFIG_CMD_BOOTM) += bootm.o	33	obj-$(CONFIG_CMD_BOOTM) += bootm.o
34	obj-y += cache.o	34	obj-y += cache.o
35	obj-y += extable.o	35	obj-y += extable.o
36	obj-y += interrupts.o	36	obj-y += interrupts.o
37	obj-$(CONFIG_CMD_KGDB) += kgdb.o	37	obj-$(CONFIG_CMD_KGDB) += kgdb.o
38	obj-$(CONFIG_CMD_IDE) += ide.o	38	obj-$(CONFIG_IDE) += ide.o
39	obj-y += stack.o	39	obj-y += stack.o
40	obj-y += time.o	40	obj-y += time.o
41		41
42	# Don't include the MPC5xxx special memcpy into the	42	# Don't include the MPC5xxx special memcpy into the
43	# SPL U-Boot image. memcpy is used in the SPL NOR	43	# SPL U-Boot image. memcpy is used in the SPL NOR
44	# flash driver. And we need the real, fast memcpy	44	# flash driver. And we need the real, fast memcpy
45	# here. We have no problems with unaligned access.	45	# here. We have no problems with unaligned access.
46	ifndef CONFIG_SPL_BUILD	46	ifndef CONFIG_SPL_BUILD
47	# Workaround for local bus unaligned access problems	47	# Workaround for local bus unaligned access problems
48	# on MPC512x and MPC5200	48	# on MPC512x and MPC5200
49	ifdef CONFIG_MPC512X	49	ifdef CONFIG_MPC512X
50	AFLAGS_ppcstring.o += -Dmemcpy=__memcpy	50	AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
51	obj-y += memcpy_mpc5200.o	51	obj-y += memcpy_mpc5200.o
52	endif	52	endif
53	ifdef CONFIG_MPC5200	53	ifdef CONFIG_MPC5200
54	AFLAGS_ppcstring.o += -Dmemcpy=__memcpy	54	AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
55	obj-y += memcpy_mpc5200.o	55	obj-y += memcpy_mpc5200.o
56	endif	56	endif
57	endif	57	endif
58		58
59	endif # not minimal	59	endif # not minimal
60		60
61	ifdef CONFIG_SPL_BUILD	61	ifdef CONFIG_SPL_BUILD
62	obj-$(CONFIG_SPL_FRAMEWORK) += spl.o	62	obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
63	endif	63	endif
64		64

board/freescale/m5253demo/m5253demo.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2000-2003	2	* (C) Copyright 2000-2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.	5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6	* Hayden Fraser (Hayden.Fraser@freescale.com)	6	* Hayden Fraser (Hayden.Fraser@freescale.com)
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <asm/immap.h>	12	#include <asm/immap.h>
13	#include <netdev.h>	13	#include <netdev.h>
14	#include <asm/io.h>	14	#include <asm/io.h>
15		15
16	DECLARE_GLOBAL_DATA_PTR;	16	DECLARE_GLOBAL_DATA_PTR;
17		17
18	int checkboard(void)	18	int checkboard(void)
19	{	19	{
20	puts("Board: ");	20	puts("Board: ");
21	puts("Freescale MCF5253 DEMO\n");	21	puts("Freescale MCF5253 DEMO\n");
22	return 0;	22	return 0;
23	};	23	};
24		24
25	int dram_init(void)	25	int dram_init(void)
26	{	26	{
27	u32 dramsize = 0;	27	u32 dramsize = 0;
28		28
29	/*	29	/*
30	* Check to see if the SDRAM has already been initialized	30	* Check to see if the SDRAM has already been initialized
31	* by a run control tool	31	* by a run control tool
32	*/	32	*/
33	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {	33	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
34	u32 RC, temp;	34	u32 RC, temp;
35		35
36	RC = (CONFIG_SYS_CLK / 1000000) >> 1;	36	RC = (CONFIG_SYS_CLK / 1000000) >> 1;
37	RC = (RC * 15) >> 4;	37	RC = (RC * 15) >> 4;
38		38
39	/* Initialize DRAM Control Register: DCR */	39	/* Initialize DRAM Control Register: DCR */
40	mbar_writeShort(MCFSIM_DCR, (0x8400 \| RC));	40	mbar_writeShort(MCFSIM_DCR, (0x8400 \| RC));
41	__asm__("nop");	41	__asm__("nop");
42		42
43	mbar_writeLong(MCFSIM_DACR0, 0x00003224);	43	mbar_writeLong(MCFSIM_DACR0, 0x00003224);
44	__asm__("nop");	44	__asm__("nop");
45		45
46	/* Initialize DMR0 */	46	/* Initialize DMR0 */
47	dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);	47	dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
48	temp = (dramsize - 1) & 0xFFFC0000;	48	temp = (dramsize - 1) & 0xFFFC0000;
49	mbar_writeLong(MCFSIM_DMR0, temp \| 1);	49	mbar_writeLong(MCFSIM_DMR0, temp \| 1);
50	__asm__("nop");	50	__asm__("nop");
51		51
52	mbar_writeLong(MCFSIM_DACR0, 0x0000322c);	52	mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
53	mb();	53	mb();
54	__asm__("nop");	54	__asm__("nop");
55		55
56	/* Write to this block to initiate precharge */	56	/* Write to this block to initiate precharge */
57	(u32 ) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;	57	(u32 ) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
58	mb();	58	mb();
59	__asm__("nop");	59	__asm__("nop");
60		60
61	/* Set RE bit in DACR */	61	/* Set RE bit in DACR */
62	mbar_writeLong(MCFSIM_DACR0,	62	mbar_writeLong(MCFSIM_DACR0,
63	mbar_readLong(MCFSIM_DACR0) \| 0x8000);	63	mbar_readLong(MCFSIM_DACR0) \| 0x8000);
64	__asm__("nop");	64	__asm__("nop");
65		65
66	/* Wait for at least 8 auto refresh cycles to occur */	66	/* Wait for at least 8 auto refresh cycles to occur */
67	udelay(500);	67	udelay(500);
68		68
69	/* Finish the configuration by issuing the MRS */	69	/* Finish the configuration by issuing the MRS */
70	mbar_writeLong(MCFSIM_DACR0,	70	mbar_writeLong(MCFSIM_DACR0,
71	mbar_readLong(MCFSIM_DACR0) \| 0x0040);	71	mbar_readLong(MCFSIM_DACR0) \| 0x0040);
72	__asm__("nop");	72	__asm__("nop");
73		73
74	(u32 ) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;	74	(u32 ) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
75	mb();	75	mb();
76	}	76	}
77		77
78	gd->ram_size = dramsize;	78	gd->ram_size = dramsize;
79		79
80	return 0;	80	return 0;
81	}	81	}
82		82
83	int testdram(void)	83	int testdram(void)
84	{	84	{
85	/* TODO: XXX XXX XXX */	85	/* TODO: XXX XXX XXX */
86	printf("DRAM test not implemented!\n");	86	printf("DRAM test not implemented!\n");
87		87
88	return (0);	88	return (0);
89	}	89	}
90		90
91	#ifdef CONFIG_CMD_IDE	91	#ifdef CONFIG_IDE
92	#include <ata.h>	92	#include <ata.h>
93	int ide_preinit(void)	93	int ide_preinit(void)
94	{	94	{
95	return (0);	95	return (0);
96	}	96	}
97		97
98	void ide_set_reset(int idereset)	98	void ide_set_reset(int idereset)
99	{	99	{
100	atac_t ata = (atac_t ) CONFIG_SYS_ATA_BASE_ADDR;	100	atac_t ata = (atac_t ) CONFIG_SYS_ATA_BASE_ADDR;
101	long period;	101	long period;
102	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */	102	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
103	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */	103	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
104	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */	104	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
105	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */	105	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
106	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */	106	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
107	{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */	107	{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
108	};	108	};
109		109
110	if (idereset) {	110	if (idereset) {
111	/* control reset */	111	/* control reset */
112	out_8(&ata->cr, 0);	112	out_8(&ata->cr, 0);
113	udelay(100);	113	udelay(100);
114	} else {	114	} else {
115	mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);	115	mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
116		116
117	#define CALC_TIMING(t) (t + period - 1) / period	117	#define CALC_TIMING(t) (t + period - 1) / period
118	period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */	118	period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
119		119
120	/ata->ton = CALC_TIMING (180); /	120	/ata->ton = CALC_TIMING (180); /
121	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));	121	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
122	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));	122	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
123	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));	123	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
124	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));	124	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
125	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));	125	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
126	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));	126	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
127	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));	127	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
128		128
129	/* IORDY enable */	129	/* IORDY enable */
130	out_8(&ata->cr, 0x40);	130	out_8(&ata->cr, 0x40);
131	udelay(2000);	131	udelay(2000);
132	/* IORDY enable */	132	/* IORDY enable */
133	setbits_8(&ata->cr, 0x01);	133	setbits_8(&ata->cr, 0x01);
134	}	134	}
135	}	135	}
136	#endif /* CONFIG_CMD_IDE */	136	#endif /* CONFIG_IDE */
137		137
138		138
139	#ifdef CONFIG_DRIVER_DM9000	139	#ifdef CONFIG_DRIVER_DM9000
140	int board_eth_init(bd_t *bis)	140	int board_eth_init(bd_t *bis)
141	{	141	{
142	return dm9000_initialize(bis);	142	return dm9000_initialize(bis);
143	}	143	}
144	#endif	144	#endif
145		145

board/freescale/m5253evbe/m5253evbe.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2000-2003	2	* (C) Copyright 2000-2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.	5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6	* Hayden Fraser (Hayden.Fraser@freescale.com)	6	* Hayden Fraser (Hayden.Fraser@freescale.com)
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <asm/immap.h>	12	#include <asm/immap.h>
13	#include <asm/io.h>	13	#include <asm/io.h>
14		14
15	DECLARE_GLOBAL_DATA_PTR;	15	DECLARE_GLOBAL_DATA_PTR;
16		16
17	int checkboard(void)	17	int checkboard(void)
18	{	18	{
19	puts("Board: ");	19	puts("Board: ");
20	puts("Freescale MCF5253 EVBE\n");	20	puts("Freescale MCF5253 EVBE\n");
21	return 0;	21	return 0;
22	};	22	};
23		23
24	int dram_init(void)	24	int dram_init(void)
25	{	25	{
26	/*	26	/*
27	* Check to see if the SDRAM has already been initialized	27	* Check to see if the SDRAM has already been initialized
28	* by a run control tool	28	* by a run control tool
29	*/	29	*/
30	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {	30	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
31	u32 RC, dramsize;	31	u32 RC, dramsize;
32		32
33	RC = (CONFIG_SYS_CLK / 1000000) >> 1;	33	RC = (CONFIG_SYS_CLK / 1000000) >> 1;
34	RC = (RC * 15) >> 4;	34	RC = (RC * 15) >> 4;
35		35
36	/* Initialize DRAM Control Register: DCR */	36	/* Initialize DRAM Control Register: DCR */
37	mbar_writeShort(MCFSIM_DCR, (0x8400 \| RC));	37	mbar_writeShort(MCFSIM_DCR, (0x8400 \| RC));
38	asm("nop");	38	asm("nop");
39		39
40	mbar_writeLong(MCFSIM_DACR0, 0x00002320);	40	mbar_writeLong(MCFSIM_DACR0, 0x00002320);
41	asm("nop");	41	asm("nop");
42		42
43	/* Initialize DMR0 */	43	/* Initialize DMR0 */
44	dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;	44	dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
45	mbar_writeLong(MCFSIM_DMR0, dramsize \| 1);	45	mbar_writeLong(MCFSIM_DMR0, dramsize \| 1);
46	asm("nop");	46	asm("nop");
47		47
48	mbar_writeLong(MCFSIM_DACR0, 0x00002328);	48	mbar_writeLong(MCFSIM_DACR0, 0x00002328);
49	asm("nop");	49	asm("nop");
50		50
51	/* Write to this block to initiate precharge */	51	/* Write to this block to initiate precharge */
52	(u32 ) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;	52	(u32 ) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
53	asm("nop");	53	asm("nop");
54		54
55	/* Set RE bit in DACR */	55	/* Set RE bit in DACR */
56	mbar_writeLong(MCFSIM_DACR0,	56	mbar_writeLong(MCFSIM_DACR0,
57	mbar_readLong(MCFSIM_DACR0) \| 0x8000);	57	mbar_readLong(MCFSIM_DACR0) \| 0x8000);
58	asm("nop");	58	asm("nop");
59		59
60	/* Wait for at least 8 auto refresh cycles to occur */	60	/* Wait for at least 8 auto refresh cycles to occur */
61	udelay(500);	61	udelay(500);
62		62
63	/* Finish the configuration by issuing the MRS */	63	/* Finish the configuration by issuing the MRS */
64	mbar_writeLong(MCFSIM_DACR0,	64	mbar_writeLong(MCFSIM_DACR0,
65	mbar_readLong(MCFSIM_DACR0) \| 0x0040);	65	mbar_readLong(MCFSIM_DACR0) \| 0x0040);
66	asm("nop");	66	asm("nop");
67		67
68	(u32 ) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;	68	(u32 ) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
69	}	69	}
70		70
71	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;	71	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
72		72
73	return 0;	73	return 0;
74	}	74	}
75		75
76	int testdram(void)	76	int testdram(void)
77	{	77	{
78	/* TODO: XXX XXX XXX */	78	/* TODO: XXX XXX XXX */
79	printf("DRAM test not implemented!\n");	79	printf("DRAM test not implemented!\n");
80		80
81	return (0);	81	return (0);
82	}	82	}
83		83
84	#ifdef CONFIG_CMD_IDE	84	#ifdef CONFIG_IDE
85	#include <ata.h>	85	#include <ata.h>
86	int ide_preinit(void)	86	int ide_preinit(void)
87	{	87	{
88	return (0);	88	return (0);
89	}	89	}
90		90
91	void ide_set_reset(int idereset)	91	void ide_set_reset(int idereset)
92	{	92	{
93	atac_t ata = (atac_t ) CONFIG_SYS_ATA_BASE_ADDR;	93	atac_t ata = (atac_t ) CONFIG_SYS_ATA_BASE_ADDR;
94	long period;	94	long period;
95	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */	95	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
96	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */	96	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
97	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */	97	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
98	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */	98	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
99	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */	99	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
100	{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */	100	{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
101	};	101	};
102		102
103	if (idereset) {	103	if (idereset) {
104	/* control reset */	104	/* control reset */
105	out_8(&ata->cr, 0);	105	out_8(&ata->cr, 0);
106	udelay(100);	106	udelay(100);
107	} else {	107	} else {
108	mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);	108	mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
109		109
110	#define CALC_TIMING(t) (t + period - 1) / period	110	#define CALC_TIMING(t) (t + period - 1) / period
111	period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */	111	period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
112		112
113	/ata->ton = CALC_TIMING (180); /	113	/ata->ton = CALC_TIMING (180); /
114	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));	114	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
115	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));	115	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
116	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));	116	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
117	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));	117	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
118	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));	118	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
119	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));	119	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
120	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));	120	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
121		121
122	/* IORDY enable */	122	/* IORDY enable */
123	out_8(&ata->cr, 0x40);	123	out_8(&ata->cr, 0x40);
124	udelay(2000);	124	udelay(2000);
125	/* IORDY enable */	125	/* IORDY enable */
126	setbits_8(&ata->cr, 0x01);	126	setbits_8(&ata->cr, 0x01);
127	}	127	}
128	}	128	}
129	#endif /* CONFIG_CMD_IDE */	129	#endif /* CONFIG_IDE */
130		130

board/freescale/m54455evb/m54455evb.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2000-2003	2	* (C) Copyright 2000-2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.	5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <pci.h>	12	#include <pci.h>
13	#include <asm/immap.h>	13	#include <asm/immap.h>
14	#include <asm/io.h>	14	#include <asm/io.h>
15		15
16	DECLARE_GLOBAL_DATA_PTR;	16	DECLARE_GLOBAL_DATA_PTR;
17		17
18	int checkboard(void)	18	int checkboard(void)
19	{	19	{
20	puts("Board: ");	20	puts("Board: ");
21	puts("Freescale M54455 EVB\n");	21	puts("Freescale M54455 EVB\n");
22	return 0;	22	return 0;
23	};	23	};
24		24
25	int dram_init(void)	25	int dram_init(void)
26	{	26	{
27	u32 dramsize;	27	u32 dramsize;
28	#ifdef CONFIG_CF_SBF	28	#ifdef CONFIG_CF_SBF
29	/*	29	/*
30	* Serial Boot: The dram is already initialized in start.S	30	* Serial Boot: The dram is already initialized in start.S
31	* only require to return DRAM size	31	* only require to return DRAM size
32	*/	32	*/
33	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;	33	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
34	#else	34	#else
35	sdramc_t sdram = (sdramc_t )(MMAP_SDRAM);	35	sdramc_t sdram = (sdramc_t )(MMAP_SDRAM);
36	gpio_t gpio = (gpio_t )(MMAP_GPIO);	36	gpio_t gpio = (gpio_t )(MMAP_GPIO);
37	u32 i;	37	u32 i;
38		38
39	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;	39	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
40		40
41	for (i = 0x13; i < 0x20; i++) {	41	for (i = 0x13; i < 0x20; i++) {
42	if (dramsize == (1 << i))	42	if (dramsize == (1 << i))
43	break;	43	break;
44	}	44	}
45	i--;	45	i--;
46		46
47	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);	47	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
48		48
49	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE \| i);	49	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE \| i);
50	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 \| i);	50	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 \| i);
51		51
52	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);	52	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
53	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);	53	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
54		54
55	/* Issue PALL */	55	/* Issue PALL */
56	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 2);	56	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 2);
57		57
58	/* Issue LEMR */	58	/* Issue LEMR */
59	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD \| 0x408);	59	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD \| 0x408);
60	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE \| 0x300);	60	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE \| 0x300);
61		61
62	udelay(500);	62	udelay(500);
63		63
64	/* Issue PALL */	64	/* Issue PALL */
65	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 2);	65	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 2);
66		66
67	/* Perform two refresh cycles */	67	/* Perform two refresh cycles */
68	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 4);	68	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 4);
69	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 4);	69	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL \| 4);
70		70
71	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE \| 0x200);	71	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE \| 0x200);
72		72
73	out_be32(&sdram->sdcr,	73	out_be32(&sdram->sdcr,
74	(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000c00);	74	(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000c00);
75		75
76	udelay(100);	76	udelay(100);
77	#endif	77	#endif
78	gd->ram_size = dramsize << 1;	78	gd->ram_size = dramsize << 1;
79		79
80	return 0;	80	return 0;
81	};	81	};
82		82
83	int testdram(void)	83	int testdram(void)
84	{	84	{
85	/* TODO: XXX XXX XXX */	85	/* TODO: XXX XXX XXX */
86	printf("DRAM test not implemented!\n");	86	printf("DRAM test not implemented!\n");
87		87
88	return (0);	88	return (0);
89	}	89	}
90		90
91	#if defined(CONFIG_CMD_IDE)	91	#if defined(CONFIG_IDE)
92	#include <ata.h>	92	#include <ata.h>
93		93
94	int ide_preinit(void)	94	int ide_preinit(void)
95	{	95	{
96	gpio_t gpio = (gpio_t ) MMAP_GPIO;	96	gpio_t gpio = (gpio_t ) MMAP_GPIO;
97	u32 tmp;	97	u32 tmp;
98		98
99	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) \| 0x10;	99	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) \| 0x10;
100	setbits_8(&gpio->par_fec, tmp);	100	setbits_8(&gpio->par_fec, tmp);
101	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) \|	101	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) \|
102	(GPIO_PAR_FECI2C_MDC1_ATA_DIOR \| GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));	102	(GPIO_PAR_FECI2C_MDC1_ATA_DIOR \| GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
103	setbits_be16(&gpio->par_feci2c, tmp);	103	setbits_be16(&gpio->par_feci2c, tmp);
104		104
105	setbits_be16(&gpio->par_ata,	105	setbits_be16(&gpio->par_ata,
106	GPIO_PAR_ATA_BUFEN \| GPIO_PAR_ATA_CS1 \| GPIO_PAR_ATA_CS0 \|	106	GPIO_PAR_ATA_BUFEN \| GPIO_PAR_ATA_CS1 \| GPIO_PAR_ATA_CS0 \|
107	GPIO_PAR_ATA_DA2 \| GPIO_PAR_ATA_DA1 \| GPIO_PAR_ATA_DA0 \|	107	GPIO_PAR_ATA_DA2 \| GPIO_PAR_ATA_DA1 \| GPIO_PAR_ATA_DA0 \|
108	GPIO_PAR_ATA_RESET_RESET \| GPIO_PAR_ATA_DMARQ_DMARQ \|	108	GPIO_PAR_ATA_RESET_RESET \| GPIO_PAR_ATA_DMARQ_DMARQ \|
109	GPIO_PAR_ATA_IORDY_IORDY);	109	GPIO_PAR_ATA_IORDY_IORDY);
110	setbits_be16(&gpio->par_pci,	110	setbits_be16(&gpio->par_pci,
111	GPIO_PAR_PCI_GNT3_ATA_DMACK \| GPIO_PAR_PCI_REQ3_ATA_INTRQ);	111	GPIO_PAR_PCI_GNT3_ATA_DMACK \| GPIO_PAR_PCI_REQ3_ATA_INTRQ);
112		112
113	return (0);	113	return (0);
114	}	114	}
115		115
116	void ide_set_reset(int idereset)	116	void ide_set_reset(int idereset)
117	{	117	{
118	atac_t ata = (atac_t ) MMAP_ATA;	118	atac_t ata = (atac_t ) MMAP_ATA;
119	long period;	119	long period;
120	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */	120	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
121	int piotms[5][9] = {	121	int piotms[5][9] = {
122	{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */	122	{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
123	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */	123	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
124	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */	124	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
125	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */	125	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
126	{25, 70, 20, 10, 20, 5, 10, 0, 35}	126	{25, 70, 20, 10, 20, 5, 10, 0, 35}
127	}; /* PIO 4 */	127	}; /* PIO 4 */
128		128
129	if (idereset) {	129	if (idereset) {
130	/* control reset */	130	/* control reset */
131	out_8(&ata->cr, 0);	131	out_8(&ata->cr, 0);
132	udelay(10000);	132	udelay(10000);
133	} else {	133	} else {
134	#define CALC_TIMING(t) (t + period - 1) / period	134	#define CALC_TIMING(t) (t + period - 1) / period
135	period = 1000000000 / gd->bus_clk; /* period in ns */	135	period = 1000000000 / gd->bus_clk; /* period in ns */
136		136
137	/ata->ton = CALC_TIMING (180); /	137	/ata->ton = CALC_TIMING (180); /
138	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));	138	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
139	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));	139	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
140	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));	140	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
141	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));	141	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
142	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));	142	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
143	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));	143	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
144	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));	144	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
145		145
146	/* IORDY enable */	146	/* IORDY enable */
147	out_8(&ata->cr, 0x40);	147	out_8(&ata->cr, 0x40);
148	udelay(200000);	148	udelay(200000);
149	/* IORDY enable */	149	/* IORDY enable */
150	setbits_8(&ata->cr, 0x01);	150	setbits_8(&ata->cr, 0x01);
151	}	151	}
152	}	152	}
153	#endif	153	#endif
154		154
155	#if defined(CONFIG_PCI)	155	#if defined(CONFIG_PCI)
156	/*	156	/*
157	* Initialize PCI devices, report devices found.	157	* Initialize PCI devices, report devices found.
158	*/	158	*/
159	static struct pci_controller hose;	159	static struct pci_controller hose;
160	extern void pci_mcf5445x_init(struct pci_controller *hose);	160	extern void pci_mcf5445x_init(struct pci_controller *hose);
161		161
162	void pci_init_board(void)	162	void pci_init_board(void)
163	{	163	{
164	pci_mcf5445x_init(&hose);	164	pci_mcf5445x_init(&hose);
165	}	165	}
166	#endif /* CONFIG_PCI */	166	#endif /* CONFIG_PCI */
167		167
168	#if defined(CONFIG_FLASH_CFI_LEGACY)	168	#if defined(CONFIG_FLASH_CFI_LEGACY)
169	#include <flash.h>	169	#include <flash.h>
170	ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)	170	ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
171	{	171	{
172	int sect[] = CONFIG_SYS_ATMEL_SECT;	172	int sect[] = CONFIG_SYS_ATMEL_SECT;
173	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;	173	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
174	int i, j, k;	174	int i, j, k;
175		175
176	if (base != CONFIG_SYS_ATMEL_BASE)	176	if (base != CONFIG_SYS_ATMEL_BASE)
177	return 0;	177	return 0;
178		178
179	info->flash_id = 0x01000000;	179	info->flash_id = 0x01000000;
180	info->portwidth = 1;	180	info->portwidth = 1;
181	info->chipwidth = 1;	181	info->chipwidth = 1;
182	info->buffer_size = 1;	182	info->buffer_size = 1;
183	info->erase_blk_tout = 16384;	183	info->erase_blk_tout = 16384;
184	info->write_tout = 2;	184	info->write_tout = 2;
185	info->buffer_write_tout = 5;	185	info->buffer_write_tout = 5;
186	info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */	186	info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
187	info->cmd_reset = 0x00F0;	187	info->cmd_reset = 0x00F0;
188	info->interface = FLASH_CFI_X8;	188	info->interface = FLASH_CFI_X8;
189	info->legacy_unlock = 0;	189	info->legacy_unlock = 0;
190	info->manufacturer_id = (u16) ATM_MANUFACT;	190	info->manufacturer_id = (u16) ATM_MANUFACT;
191	info->device_id = ATM_ID_LV040;	191	info->device_id = ATM_ID_LV040;
192	info->device_id2 = 0;	192	info->device_id2 = 0;
193		193
194	info->ext_addr = 0;	194	info->ext_addr = 0;
195	info->cfi_version = 0x3133;	195	info->cfi_version = 0x3133;
196	info->cfi_offset = 0x0000;	196	info->cfi_offset = 0x0000;
197	info->addr_unlock1 = 0x00000555;	197	info->addr_unlock1 = 0x00000555;
198	info->addr_unlock2 = 0x000002AA;	198	info->addr_unlock2 = 0x000002AA;
199	info->name = "CFI conformant";	199	info->name = "CFI conformant";
200		200
201	info->size = 0;	201	info->size = 0;
202	info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;	202	info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
203	info->start[0] = base;	203	info->start[0] = base;
204	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {	204	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
205	info->size += sect[i] * sectsz[i];	205	info->size += sect[i] * sectsz[i];
206		206
207	for (j = 0; j < sect[i]; j++, k++) {	207	for (j = 0; j < sect[i]; j++, k++) {
208	info->start[k + 1] = info->start[k] + sectsz[i];	208	info->start[k + 1] = info->start[k] + sectsz[i];
209	info->protect[k] = 0;	209	info->protect[k] = 0;
210	}	210	}
211	}	211	}
212		212
213	return 1;	213	return 1;
214	}	214	}
215	#endif /* CONFIG_SYS_FLASH_CFI */	215	#endif /* CONFIG_SYS_FLASH_CFI */
216		216

board/intercontrol/digsy_mtc/digsy_mtc.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2003	2	* (C) Copyright 2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2004	5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*	7	*
8	* (C) Copyright 2005-2009	8	* (C) Copyright 2005-2009
9	* Modified for InterControl digsyMTC MPC5200 board by	9	* Modified for InterControl digsyMTC MPC5200 board by
10	* Frank Bodammer, GCD Hard- & Software GmbH,	10	* Frank Bodammer, GCD Hard- & Software GmbH,
11	* frank.bodammer@gcd-solutions.de	11	* frank.bodammer@gcd-solutions.de
12	*	12	*
13	* (C) Copyright 2009	13	* (C) Copyright 2009
14	* Grzegorz Bernacki, Semihalf, gjb@semihalf.com	14	* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
15	*	15	*
16	* SPDX-License-Identifier: GPL-2.0+	16	* SPDX-License-Identifier: GPL-2.0+
17	*/	17	*/
18		18
19	#include <common.h>	19	#include <common.h>
20	#include <mpc5xxx.h>	20	#include <mpc5xxx.h>
21	#include <net.h>	21	#include <net.h>
22	#include <pci.h>	22	#include <pci.h>
23	#include <asm/processor.h>	23	#include <asm/processor.h>
24	#include <asm/io.h>	24	#include <asm/io.h>
25	#include "eeprom.h"	25	#include "eeprom.h"
26	#if defined(CONFIG_DIGSY_REV5)	26	#if defined(CONFIG_DIGSY_REV5)
27	#include "is45s16800a2.h"	27	#include "is45s16800a2.h"
28	#include <mtd/cfi_flash.h>	28	#include <mtd/cfi_flash.h>
29	#include <flash.h>	29	#include <flash.h>
30	#else	30	#else
31	#include "is42s16800a-7t.h"	31	#include "is42s16800a-7t.h"
32	#endif	32	#endif
33	#include <libfdt.h>	33	#include <libfdt.h>
34	#include <fdt_support.h>	34	#include <fdt_support.h>
35	#include <i2c.h>	35	#include <i2c.h>
36	#include <mb862xx.h>	36	#include <mb862xx.h>
37		37
38	DECLARE_GLOBAL_DATA_PTR;	38	DECLARE_GLOBAL_DATA_PTR;
39		39
40	extern int usb_cpu_init(void);	40	extern int usb_cpu_init(void);
41		41
42	#if defined(CONFIG_DIGSY_REV5)	42	#if defined(CONFIG_DIGSY_REV5)
43	/*	43	/*
44	* The M29W128GH needs a special reset command function,	44	* The M29W128GH needs a special reset command function,
45	* details see the doc/README.cfi file	45	* details see the doc/README.cfi file
46	*/	46	*/
47	void flash_cmd_reset(flash_info_t *info)	47	void flash_cmd_reset(flash_info_t *info)
48	{	48	{
49	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);	49	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
50	}	50	}
51	#endif	51	#endif
52		52
53	#ifndef CONFIG_SYS_RAMBOOT	53	#ifndef CONFIG_SYS_RAMBOOT
54	static void sdram_start(int hi_addr)	54	static void sdram_start(int hi_addr)
55	{	55	{
56	long hi_addr_bit = hi_addr ? 0x01000000 : 0;	56	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
57	long control = SDRAM_CONTROL \| hi_addr_bit;	57	long control = SDRAM_CONTROL \| hi_addr_bit;
58		58
59	/* unlock mode register */	59	/* unlock mode register */
60	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000000);	60	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000000);
61		61
62	/* precharge all banks */	62	/* precharge all banks */
63	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);	63	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);
64		64
65	/* auto refresh */	65	/* auto refresh */
66	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000004);	66	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000004);
67		67
68	/* set mode register */	68	/* set mode register */
69	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);	69	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
70		70
71	/* normal operation */	71	/* normal operation */
72	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);	72	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
73	}	73	}
74	#endif	74	#endif
75		75
76	/*	76	/*
77	* ATTENTION: Although partially referenced dram_init does NOT make real use	77	* ATTENTION: Although partially referenced dram_init does NOT make real use
78	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if	78	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
79	* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.	79	* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
80	*/	80	*/
81		81
82	int dram_init(void)	82	int dram_init(void)
83	{	83	{
84	ulong dramsize = 0;	84	ulong dramsize = 0;
85	ulong dramsize2 = 0;	85	ulong dramsize2 = 0;
86	uint svr, pvr;	86	uint svr, pvr;
87	#ifndef CONFIG_SYS_RAMBOOT	87	#ifndef CONFIG_SYS_RAMBOOT
88	ulong test1, test2;	88	ulong test1, test2;
89		89
90	/* setup SDRAM chip selects */	90	/* setup SDRAM chip selects */
91	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0x0000001C); / 512MB at 0x0 */	91	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0x0000001C); / 512MB at 0x0 */
92	out_be32((void )MPC5XXX_SDRAM_CS1CFG, 0x80000000); / disabled */	92	out_be32((void )MPC5XXX_SDRAM_CS1CFG, 0x80000000); / disabled */
93		93
94	/* setup config registers */	94	/* setup config registers */
95	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);	95	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
96	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);	96	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
97		97
98	/* find RAM size using SDRAM CS0 only */	98	/* find RAM size using SDRAM CS0 only */
99	sdram_start(0);	99	sdram_start(0);
100	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);	100	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
101	sdram_start(1);	101	sdram_start(1);
102	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);	102	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
103	if (test1 > test2) {	103	if (test1 > test2) {
104	sdram_start(0);	104	sdram_start(0);
105	dramsize = test1;	105	dramsize = test1;
106	} else {	106	} else {
107	dramsize = test2;	107	dramsize = test2;
108	}	108	}
109		109
110	/* memory smaller than 1MB is impossible */	110	/* memory smaller than 1MB is impossible */
111	if (dramsize < (1 << 20))	111	if (dramsize < (1 << 20))
112	dramsize = 0;	112	dramsize = 0;
113		113
114	/* set SDRAM CS0 size according to the amount of RAM found */	114	/* set SDRAM CS0 size according to the amount of RAM found */
115	if (dramsize > 0) {	115	if (dramsize > 0) {
116	out_be32((void *)MPC5XXX_SDRAM_CS0CFG,	116	out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
117	(0x13 + __builtin_ffs(dramsize >> 20) - 1));	117	(0x13 + __builtin_ffs(dramsize >> 20) - 1));
118	} else {	118	} else {
119	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0); / disabled */	119	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0); / disabled */
120	}	120	}
121		121
122	/* let SDRAM CS1 start right after CS0 */	122	/* let SDRAM CS1 start right after CS0 */
123	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);	123	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
124		124
125	/* find RAM size using SDRAM CS1 only */	125	/* find RAM size using SDRAM CS1 only */
126	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),	126	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
127	0x08000000);	127	0x08000000);
128	dramsize2 = test1;	128	dramsize2 = test1;
129		129
130	/* memory smaller than 1MB is impossible */	130	/* memory smaller than 1MB is impossible */
131	if (dramsize2 < (1 << 20))	131	if (dramsize2 < (1 << 20))
132	dramsize2 = 0;	132	dramsize2 = 0;
133		133
134	/* set SDRAM CS1 size according to the amount of RAM found */	134	/* set SDRAM CS1 size according to the amount of RAM found */
135	if (dramsize2 > 0) {	135	if (dramsize2 > 0) {
136	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize \|	136	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize \|
137	(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));	137	(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
138	} else {	138	} else {
139	out_be32((void )MPC5XXX_SDRAM_CS1CFG, dramsize); / disabled */	139	out_be32((void )MPC5XXX_SDRAM_CS1CFG, dramsize); / disabled */
140	}	140	}
141		141
142	#else /* CONFIG_SYS_RAMBOOT */	142	#else /* CONFIG_SYS_RAMBOOT */
143		143
144	/* retrieve size of memory connected to SDRAM CS0 */	144	/* retrieve size of memory connected to SDRAM CS0 */
145	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;	145	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
146	if (dramsize >= 0x13)	146	if (dramsize >= 0x13)
147	dramsize = (1 << (dramsize - 0x13)) << 20;	147	dramsize = (1 << (dramsize - 0x13)) << 20;
148	else	148	else
149	dramsize = 0;	149	dramsize = 0;
150		150
151	/* retrieve size of memory connected to SDRAM CS1 */	151	/* retrieve size of memory connected to SDRAM CS1 */
152	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;	152	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
153	if (dramsize2 >= 0x13)	153	if (dramsize2 >= 0x13)
154	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;	154	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
155	else	155	else
156	dramsize2 = 0;	156	dramsize2 = 0;
157		157
158	#endif /* CONFIG_SYS_RAMBOOT */	158	#endif /* CONFIG_SYS_RAMBOOT */
159		159
160	/*	160	/*
161	* On MPC5200B we need to set the special configuration delay in the	161	* On MPC5200B we need to set the special configuration delay in the
162	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM	162	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
163	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:	163	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
164	*	164	*
165	* "The SDelay should be written to a value of 0x00000004. It is	165	* "The SDelay should be written to a value of 0x00000004. It is
166	* required to account for changes caused by normal wafer processing	166	* required to account for changes caused by normal wafer processing
167	* parameters."	167	* parameters."
168	*/	168	*/
169	svr = get_svr();	169	svr = get_svr();
170	pvr = get_pvr();	170	pvr = get_pvr();
171	if ((SVR_MJREV(svr) >= 2) &&	171	if ((SVR_MJREV(svr) >= 2) &&
172	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))	172	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
173	out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);	173	out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
174		174
175	gd->ram_size = dramsize + dramsize2;	175	gd->ram_size = dramsize + dramsize2;
176		176
177	return 0;	177	return 0;
178	}	178	}
179		179
180	int checkboard(void)	180	int checkboard(void)
181	{	181	{
182	char buf[64];	182	char buf[64];
183	int i = getenv_f("serial#", buf, sizeof(buf));	183	int i = getenv_f("serial#", buf, sizeof(buf));
184		184
185	puts ("Board: InterControl digsyMTC");	185	puts ("Board: InterControl digsyMTC");
186	#if defined(CONFIG_DIGSY_REV5)	186	#if defined(CONFIG_DIGSY_REV5)
187	puts (" rev5");	187	puts (" rev5");
188	#endif	188	#endif
189	if (i > 0) {	189	if (i > 0) {
190	puts(", ");	190	puts(", ");
191	puts(buf);	191	puts(buf);
192	}	192	}
193	putc('\n');	193	putc('\n');
194		194
195	return 0;	195	return 0;
196	}	196	}
197		197
198	#if defined(CONFIG_VIDEO)	198	#if defined(CONFIG_VIDEO)
199		199
200	#define GPIO_USB1_0 0x00010000 /* Power-On pin */	200	#define GPIO_USB1_0 0x00010000 /* Power-On pin */
201	#define GPIO_USB1_9 0x08 /* PX_~EN pin */	201	#define GPIO_USB1_9 0x08 /* PX_~EN pin */
202		202
203	#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */	203	#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
204	#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */	204	#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
205	#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */	205	#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
206	#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */	206	#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
207		207
208	#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */	208	#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
209		209
210	static void exbo_hw_init(void)	210	static void exbo_hw_init(void)
211	{	211	{
212	struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )MPC5XXX_GPT;	212	struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )MPC5XXX_GPT;
213	struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;	213	struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
214	struct mpc5xxx_wu_gpio *wu_gpio =	214	struct mpc5xxx_wu_gpio *wu_gpio =
215	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;	215	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
216		216
217	/* configure IrDA pins (PSC6 port) as gpios */	217	/* configure IrDA pins (PSC6 port) as gpios */
218	gpio->port_config &= 0xFF8FFFFF;	218	gpio->port_config &= 0xFF8FFFFF;
219		219
220	/* Init for USB1_0, EE_CLK and EE_DI - Low */	220	/* Init for USB1_0, EE_CLK and EE_DI - Low */
221	setbits_be32(&gpio->simple_ddr,	221	setbits_be32(&gpio->simple_ddr,
222	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);	222	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
223	clrbits_be32(&gpio->simple_ode,	223	clrbits_be32(&gpio->simple_ode,
224	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);	224	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
225	clrbits_be32(&gpio->simple_dvo,	225	clrbits_be32(&gpio->simple_dvo,
226	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);	226	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
227	setbits_be32(&gpio->simple_gpioe,	227	setbits_be32(&gpio->simple_gpioe,
228	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);	228	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
229		229
230	/* Init for EE_DO, EE_CTS - Input */	230	/* Init for EE_DO, EE_CTS - Input */
231	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO \| GPIO_EE_CTS);	231	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO \| GPIO_EE_CTS);
232	setbits_8(&wu_gpio->enable, GPIO_EE_DO \| GPIO_EE_CTS);	232	setbits_8(&wu_gpio->enable, GPIO_EE_DO \| GPIO_EE_CTS);
233		233
234	/* Init for PX_~EN (USB1_9) - High */	234	/* Init for PX_~EN (USB1_9) - High */
235	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);	235	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
236	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);	236	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
237	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);	237	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
238	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);	238	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
239	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);	239	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
240		240
241	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */	241	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
242	out_be32(&gpt[0].emsr, GPT_GPIO_ON);	242	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
243	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */	243	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
244	out_be32(&gpt[1].emsr, GPT_GPIO_ON);	244	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
245		245
246	/* Power-On camera supply */	246	/* Power-On camera supply */
247	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);	247	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
248	}	248	}
249	#else	249	#else
250	static inline void exbo_hw_init(void) {}	250	static inline void exbo_hw_init(void) {}
251	#endif /* CONFIG_VIDEO */	251	#endif /* CONFIG_VIDEO */
252		252
253	int board_early_init_r(void)	253	int board_early_init_r(void)
254	{	254	{
255	/*	255	/*
256	* Now, when we are in RAM, enable flash write access for detection	256	* Now, when we are in RAM, enable flash write access for detection
257	* process. Note that CS_BOOT cannot be cleared when executing in	257	* process. Note that CS_BOOT cannot be cleared when executing in
258	* flash.	258	* flash.
259	*/	259	*/
260	/* disable CS_BOOT */	260	/* disable CS_BOOT */
261	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));	261	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
262	/* enable CS1 */	262	/* enable CS1 */
263	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));	263	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
264	/* enable CS0 */	264	/* enable CS0 */
265	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));	265	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
266		266
267	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)	267	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
268	/* Low level USB init, required for proper kernel operation */	268	/* Low level USB init, required for proper kernel operation */
269	usb_cpu_init();	269	usb_cpu_init();
270	#endif	270	#endif
271		271
272	return (0);	272	return (0);
273	}	273	}
274		274
275	void board_get_enetaddr (uchar * enet)	275	void board_get_enetaddr (uchar * enet)
276	{	276	{
277	ushort read = 0;	277	ushort read = 0;
278	ushort addr_of_eth_addr = 0;	278	ushort addr_of_eth_addr = 0;
279	ushort len_sys = 0;	279	ushort len_sys = 0;
280	ushort len_sys_cfg = 0;	280	ushort len_sys_cfg = 0;
281		281
282	/* check identification word */	282	/* check identification word */
283	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);	283	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
284	if (read != EEPROM_IDENT)	284	if (read != EEPROM_IDENT)
285	return;	285	return;
286		286
287	/* calculate offset of config area */	287	/* calculate offset of config area */
288	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);	288	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
289	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,	289	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
290	(uchar *)&len_sys_cfg, 2);	290	(uchar *)&len_sys_cfg, 2);
291	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;	291	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
292	if (addr_of_eth_addr >= EEPROM_LEN)	292	if (addr_of_eth_addr >= EEPROM_LEN)
293	return;	293	return;
294		294
295	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);	295	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
296	}	296	}
297		297
298	int misc_init_r(void)	298	int misc_init_r(void)
299	{	299	{
300	pci_dev_t devbusfn;	300	pci_dev_t devbusfn;
301	uchar enetaddr[6];	301	uchar enetaddr[6];
302		302
303	/* check if graphic extension board is present */	303	/* check if graphic extension board is present */
304	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,	304	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
305	PCI_DEVICE_ID_CORAL_PA, 0);	305	PCI_DEVICE_ID_CORAL_PA, 0);
306	if (devbusfn != -1)	306	if (devbusfn != -1)
307	exbo_hw_init();	307	exbo_hw_init();
308		308
309	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {	309	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
310	board_get_enetaddr(enetaddr);	310	board_get_enetaddr(enetaddr);
311	eth_setenv_enetaddr("ethaddr", enetaddr);	311	eth_setenv_enetaddr("ethaddr", enetaddr);
312	}	312	}
313		313
314	return 0;	314	return 0;
315	}	315	}
316		316
317	#ifdef CONFIG_PCI	317	#ifdef CONFIG_PCI
318	static struct pci_controller hose;	318	static struct pci_controller hose;
319		319
320	extern void pci_mpc5xxx_init(struct pci_controller *);	320	extern void pci_mpc5xxx_init(struct pci_controller *);
321		321
322	void pci_init_board(void)	322	void pci_init_board(void)
323	{	323	{
324	pci_mpc5xxx_init(&hose);	324	pci_mpc5xxx_init(&hose);
325	}	325	}
326	#endif	326	#endif
327		327
328	#ifdef CONFIG_CMD_IDE	328	#ifdef CONFIG_IDE
329		329
330	#ifdef CONFIG_IDE_RESET	330	#ifdef CONFIG_IDE_RESET
331		331
332	void init_ide_reset(void)	332	void init_ide_reset(void)
333	{	333	{
334	debug ("init_ide_reset\n");	334	debug ("init_ide_reset\n");
335		335
336	/* set gpio output value to 1 */	336	/* set gpio output value to 1 */
337	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));	337	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
338	/* open drain output */	338	/* open drain output */
339	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));	339	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
340	/* direction output */	340	/* direction output */
341	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));	341	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
342	/* enable gpio */	342	/* enable gpio */
343	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));	343	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
344		344
345	}	345	}
346		346
347	void ide_set_reset(int idereset)	347	void ide_set_reset(int idereset)
348	{	348	{
349	debug ("ide_reset(%d)\n", idereset);	349	debug ("ide_reset(%d)\n", idereset);
350		350
351	/* set gpio output value to 0 */	351	/* set gpio output value to 0 */
352	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));	352	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
353	/* open drain output */	353	/* open drain output */
354	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));	354	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
355	/* direction output */	355	/* direction output */
356	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));	356	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
357	/* enable gpio */	357	/* enable gpio */
358	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));	358	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
359		359
360	udelay(10000);	360	udelay(10000);
361		361
362	/* set gpio output value to 1 */	362	/* set gpio output value to 1 */
363	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));	363	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
364	/* open drain output */	364	/* open drain output */
365	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));	365	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
366	/* direction output */	366	/* direction output */
367	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));	367	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
368	/* enable gpio */	368	/* enable gpio */
369	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));	369	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
370	}	370	}
371	#endif /* CONFIG_IDE_RESET */	371	#endif /* CONFIG_IDE_RESET */
372	#endif /* CONFIG_CMD_IDE */	372	#endif /* CONFIG_IDE */
373		373
374	#ifdef CONFIG_OF_BOARD_SETUP	374	#ifdef CONFIG_OF_BOARD_SETUP
375	static void ft_delete_node(void fdt, const char compat)	375	static void ft_delete_node(void fdt, const char compat)
376	{	376	{
377	int off = -1;	377	int off = -1;
378	int ret;	378	int ret;
379		379
380	off = fdt_node_offset_by_compatible(fdt, -1, compat);	380	off = fdt_node_offset_by_compatible(fdt, -1, compat);
381	if (off < 0) {	381	if (off < 0) {
382	printf("Could not find %s node.\n", compat);	382	printf("Could not find %s node.\n", compat);
383	return;	383	return;
384	}	384	}
385		385
386	ret = fdt_del_node(fdt, off);	386	ret = fdt_del_node(fdt, off);
387	if (ret < 0)	387	if (ret < 0)
388	printf("Could not delete %s node.\n", compat);	388	printf("Could not delete %s node.\n", compat);
389	}	389	}
390	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)	390	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
391	static void ft_adapt_flash_base(void *blob)	391	static void ft_adapt_flash_base(void *blob)
392	{	392	{
393	flash_info_t *dev = &flash_info[0];	393	flash_info_t *dev = &flash_info[0];
394	int off;	394	int off;
395	struct fdt_property *prop;	395	struct fdt_property *prop;
396	int len;	396	int len;
397	u32 reg, reg2;	397	u32 reg, reg2;
398		398
399	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");	399	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
400	if (off < 0) {	400	if (off < 0) {
401	printf("Could not find fsl,mpc5200b-lpb node.\n");	401	printf("Could not find fsl,mpc5200b-lpb node.\n");
402	return;	402	return;
403	}	403	}
404		404
405	/* found compatible property */	405	/* found compatible property */
406	prop = fdt_get_property_w(blob, off, "ranges", &len);	406	prop = fdt_get_property_w(blob, off, "ranges", &len);
407	if (prop) {	407	if (prop) {
408	reg = reg2 = (u32 *)&prop->data[0];	408	reg = reg2 = (u32 *)&prop->data[0];
409		409
410	reg[2] = dev->start[0];	410	reg[2] = dev->start[0];
411	reg[3] = dev->size;	411	reg[3] = dev->size;
412	fdt_setprop(blob, off, "ranges", reg2, len);	412	fdt_setprop(blob, off, "ranges", reg2, len);
413	} else	413	} else
414	printf("Could not find ranges\n");	414	printf("Could not find ranges\n");
415	}	415	}
416		416
417	extern ulong flash_get_size (phys_addr_t base, int banknum);	417	extern ulong flash_get_size (phys_addr_t base, int banknum);
418		418
419	/* Update the Flash Baseaddr settings */	419	/* Update the Flash Baseaddr settings */
420	int update_flash_size (int flash_size)	420	int update_flash_size (int flash_size)
421	{	421	{
422	volatile struct mpc5xxx_mmap_ctl *mm =	422	volatile struct mpc5xxx_mmap_ctl *mm =
423	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;	423	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
424	flash_info_t *dev;	424	flash_info_t *dev;
425	int i;	425	int i;
426	int size = 0;	426	int size = 0;
427	unsigned long base = 0x0;	427	unsigned long base = 0x0;
428	u32 cs_reg = (u32 )&mm->cs0_start;	428	u32 cs_reg = (u32 )&mm->cs0_start;
429		429
430	for (i = 0; i < 2; i++) {	430	for (i = 0; i < 2; i++) {
431	dev = &flash_info[i];	431	dev = &flash_info[i];
432		432
433	if (dev->size) {	433	if (dev->size) {
434	/* calculate new base addr for this chipselect */	434	/* calculate new base addr for this chipselect */
435	base -= dev->size;	435	base -= dev->size;
436	out_be32(cs_reg, START_REG(base));	436	out_be32(cs_reg, START_REG(base));
437	cs_reg++;	437	cs_reg++;
438	out_be32(cs_reg, STOP_REG(base, dev->size));	438	out_be32(cs_reg, STOP_REG(base, dev->size));
439	cs_reg++;	439	cs_reg++;
440	/* recalculate the sectoraddr in the cfi driver */	440	/* recalculate the sectoraddr in the cfi driver */
441	size += flash_get_size(base, i);	441	size += flash_get_size(base, i);
442	}	442	}
443	}	443	}
444	flash_protect_default();	444	flash_protect_default();
445	gd->bd->bi_flashstart = base;	445	gd->bd->bi_flashstart = base;
446	return 0;	446	return 0;
447	}	447	}
448	#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */	448	#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
449		449
450	int ft_board_setup(void blob, bd_t bd)	450	int ft_board_setup(void blob, bd_t bd)
451	{	451	{
452	int phy_addr = CONFIG_PHY_ADDR;	452	int phy_addr = CONFIG_PHY_ADDR;
453	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";	453	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
454		454
455	ft_cpu_setup(blob, bd);	455	ft_cpu_setup(blob, bd);
456	/*	456	/*
457	* There are 2 RTC nodes in the DTS, so remove	457	* There are 2 RTC nodes in the DTS, so remove
458	* the unneeded node here.	458	* the unneeded node here.
459	*/	459	*/
460	#if defined(CONFIG_DIGSY_REV5)	460	#if defined(CONFIG_DIGSY_REV5)
461	ft_delete_node(blob, "dallas,ds1339");	461	ft_delete_node(blob, "dallas,ds1339");
462	#else	462	#else
463	ft_delete_node(blob, "mc,rv3029c2");	463	ft_delete_node(blob, "mc,rv3029c2");
464	#endif	464	#endif
465	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)	465	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
466	#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE	466	#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
467	/* Update reg property in all nor flash nodes too */	467	/* Update reg property in all nor flash nodes too */
468	fdt_fixup_nor_flash_size(blob);	468	fdt_fixup_nor_flash_size(blob);
469	#endif	469	#endif
470	ft_adapt_flash_base(blob);	470	ft_adapt_flash_base(blob);
471	#endif	471	#endif
472	/* fix up the phy address */	472	/* fix up the phy address */
473	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);	473	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
474		474
475	return 0;	475	return 0;
476	}	476	}
477	#endif /* CONFIG_OF_BOARD_SETUP */	477	#endif /* CONFIG_OF_BOARD_SETUP */
478		478

board/jupiter/jupiter.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2007	2	* (C) Copyright 2007
3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
4	*	4	*
5	* (C) Copyright 2004	5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <mpc5xxx.h>	12	#include <mpc5xxx.h>
13	#include <pci.h>	13	#include <pci.h>
14	#include <asm/processor.h>	14	#include <asm/processor.h>
15	#include <libfdt.h>	15	#include <libfdt.h>
16		16
17	#define SDRAM_DDR 0	17	#define SDRAM_DDR 0
18	#if 1	18	#if 1
19	/* Settings Icecube */	19	/* Settings Icecube */
20	#define SDRAM_MODE 0x00CD0000	20	#define SDRAM_MODE 0x00CD0000
21	#define SDRAM_CONTROL 0x504F0000	21	#define SDRAM_CONTROL 0x504F0000
22	#define SDRAM_CONFIG1 0xD2322800	22	#define SDRAM_CONFIG1 0xD2322800
23	#define SDRAM_CONFIG2 0x8AD70000	23	#define SDRAM_CONFIG2 0x8AD70000
24	#else	24	#else
25	/Settings Jupiter UB 1.0.0 /	25	/Settings Jupiter UB 1.0.0 /
26	#define SDRAM_MODE 0x008D0000	26	#define SDRAM_MODE 0x008D0000
27	#define SDRAM_CONTROL 0xD04F0000	27	#define SDRAM_CONTROL 0xD04F0000
28	#define SDRAM_CONFIG1 0xf7277f00	28	#define SDRAM_CONFIG1 0xf7277f00
29	#define SDRAM_CONFIG2 0x88b70004	29	#define SDRAM_CONFIG2 0x88b70004
30	#endif	30	#endif
31		31
32	DECLARE_GLOBAL_DATA_PTR;	32	DECLARE_GLOBAL_DATA_PTR;
33		33
34	#ifndef CONFIG_SYS_RAMBOOT	34	#ifndef CONFIG_SYS_RAMBOOT
35	static void sdram_start (int hi_addr)	35	static void sdram_start (int hi_addr)
36	{	36	{
37	long hi_addr_bit = hi_addr ? 0x01000000 : 0;	37	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
38		38
39	/* unlock mode register */	39	/* unlock mode register */
40	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;	40	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
41	__asm__ volatile ("sync");	41	__asm__ volatile ("sync");
42		42
43	/* precharge all banks */	43	/* precharge all banks */
44	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;	44	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
45	__asm__ volatile ("sync");	45	__asm__ volatile ("sync");
46		46
47	#if SDRAM_DDR	47	#if SDRAM_DDR
48	/* set mode register: extended mode */	48	/* set mode register: extended mode */
49	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;	49	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
50	__asm__ volatile ("sync");	50	__asm__ volatile ("sync");
51		51
52	/* set mode register: reset DLL */	52	/* set mode register: reset DLL */
53	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;	53	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
54	__asm__ volatile ("sync");	54	__asm__ volatile ("sync");
55	#endif	55	#endif
56		56
57	/* precharge all banks */	57	/* precharge all banks */
58	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;	58	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
59	__asm__ volatile ("sync");	59	__asm__ volatile ("sync");
60		60
61	/* auto refresh */	61	/* auto refresh */
62	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;	62	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
63	__asm__ volatile ("sync");	63	__asm__ volatile ("sync");
64		64
65	/* set mode register */	65	/* set mode register */
66	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;	66	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
67	__asm__ volatile ("sync");	67	__asm__ volatile ("sync");
68		68
69	/* normal operation */	69	/* normal operation */
70	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;	70	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
71	__asm__ volatile ("sync");	71	__asm__ volatile ("sync");
72	}	72	}
73	#endif	73	#endif
74		74
75	/*	75	/*
76	* ATTENTION: Although partially referenced dram_init does NOT make real use	76	* ATTENTION: Although partially referenced dram_init does NOT make real use
77	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE	77	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
78	* is something else than 0x00000000.	78	* is something else than 0x00000000.
79	*/	79	*/
80		80
81	int dram_init(void)	81	int dram_init(void)
82	{	82	{
83	ulong dramsize = 0;	83	ulong dramsize = 0;
84	ulong dramsize2 = 0;	84	ulong dramsize2 = 0;
85	uint svr, pvr;	85	uint svr, pvr;
86		86
87	#ifndef CONFIG_SYS_RAMBOOT	87	#ifndef CONFIG_SYS_RAMBOOT
88	ulong test1, test2;	88	ulong test1, test2;
89		89
90	/* setup SDRAM chip selects */	90	/* setup SDRAM chip selects */
91	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */	91	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
92	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */	92	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
93	__asm__ volatile ("sync");	93	__asm__ volatile ("sync");
94		94
95	/* setup config registers */	95	/* setup config registers */
96	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;	96	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
97	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;	97	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
98	__asm__ volatile ("sync");	98	__asm__ volatile ("sync");
99		99
100	#if SDRAM_DDR	100	#if SDRAM_DDR
101	/* set tap delay */	101	/* set tap delay */
102	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;	102	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
103	__asm__ volatile ("sync");	103	__asm__ volatile ("sync");
104	#endif	104	#endif
105		105
106	/* find RAM size using SDRAM CS0 only */	106	/* find RAM size using SDRAM CS0 only */
107	sdram_start(0);	107	sdram_start(0);
108	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);	108	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
109	sdram_start(1);	109	sdram_start(1);
110	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);	110	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
111	if (test1 > test2) {	111	if (test1 > test2) {
112	sdram_start(0);	112	sdram_start(0);
113	dramsize = test1;	113	dramsize = test1;
114	} else {	114	} else {
115	dramsize = test2;	115	dramsize = test2;
116	}	116	}
117		117
118	/* memory smaller than 1MB is impossible */	118	/* memory smaller than 1MB is impossible */
119	if (dramsize < (1 << 20)) {	119	if (dramsize < (1 << 20)) {
120	dramsize = 0;	120	dramsize = 0;
121	}	121	}
122		122
123	/* set SDRAM CS0 size according to the amount of RAM found */	123	/* set SDRAM CS0 size according to the amount of RAM found */
124	if (dramsize > 0) {	124	if (dramsize > 0) {
125	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;	125	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
126	} else {	126	} else {
127	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */	127	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
128	}	128	}
129		129
130	/* let SDRAM CS1 start right after CS0 */	130	/* let SDRAM CS1 start right after CS0 */
131	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */	131	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
132		132
133	/* find RAM size using SDRAM CS1 only */	133	/* find RAM size using SDRAM CS1 only */
134	if (!dramsize)	134	if (!dramsize)
135	sdram_start(0);	135	sdram_start(0);
136	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);	136	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
137	if (!dramsize) {	137	if (!dramsize) {
138	sdram_start(1);	138	sdram_start(1);
139	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);	139	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
140	}	140	}
141	if (test1 > test2) {	141	if (test1 > test2) {
142	sdram_start(0);	142	sdram_start(0);
143	dramsize2 = test1;	143	dramsize2 = test1;
144	} else {	144	} else {
145	dramsize2 = test2;	145	dramsize2 = test2;
146	}	146	}
147		147
148	/* memory smaller than 1MB is impossible */	148	/* memory smaller than 1MB is impossible */
149	if (dramsize2 < (1 << 20)) {	149	if (dramsize2 < (1 << 20)) {
150	dramsize2 = 0;	150	dramsize2 = 0;
151	}	151	}
152		152
153	/* set SDRAM CS1 size according to the amount of RAM found */	153	/* set SDRAM CS1 size according to the amount of RAM found */
154	if (dramsize2 > 0) {	154	if (dramsize2 > 0) {
155	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize	155	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
156	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);	156	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
157	} else {	157	} else {
158	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */	158	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
159	}	159	}
160		160
161	#else /* CONFIG_SYS_RAMBOOT */	161	#else /* CONFIG_SYS_RAMBOOT */
162		162
163	/* retrieve size of memory connected to SDRAM CS0 */	163	/* retrieve size of memory connected to SDRAM CS0 */
164	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;	164	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
165	if (dramsize >= 0x13) {	165	if (dramsize >= 0x13) {
166	dramsize = (1 << (dramsize - 0x13)) << 20;	166	dramsize = (1 << (dramsize - 0x13)) << 20;
167	} else {	167	} else {
168	dramsize = 0;	168	dramsize = 0;
169	}	169	}
170		170
171	/* retrieve size of memory connected to SDRAM CS1 */	171	/* retrieve size of memory connected to SDRAM CS1 */
172	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;	172	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
173	if (dramsize2 >= 0x13) {	173	if (dramsize2 >= 0x13) {
174	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;	174	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
175	} else {	175	} else {
176	dramsize2 = 0;	176	dramsize2 = 0;
177	}	177	}
178		178
179	#endif /* CONFIG_SYS_RAMBOOT */	179	#endif /* CONFIG_SYS_RAMBOOT */
180		180
181	/*	181	/*
182	* On MPC5200B we need to set the special configuration delay in the	182	* On MPC5200B we need to set the special configuration delay in the
183	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM	183	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
184	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:	184	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
185	*	185	*
186	* "The SDelay should be written to a value of 0x00000004. It is	186	* "The SDelay should be written to a value of 0x00000004. It is
187	* required to account for changes caused by normal wafer processing	187	* required to account for changes caused by normal wafer processing
188	* parameters."	188	* parameters."
189	*/	189	*/
190	svr = get_svr();	190	svr = get_svr();
191	pvr = get_pvr();	191	pvr = get_pvr();
192	if ((SVR_MJREV(svr) >= 2) &&	192	if ((SVR_MJREV(svr) >= 2) &&
193	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {	193	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
194		194
195	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;	195	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
196	__asm__ volatile ("sync");	196	__asm__ volatile ("sync");
197	}	197	}
198		198
199	gd->ram_size = dramsize + dramsize2;	199	gd->ram_size = dramsize + dramsize2;
200		200
201	return 0;	201	return 0;
202	}	202	}
203		203
204	int checkboard (void)	204	int checkboard (void)
205	{	205	{
206	puts ("Board: Sauter (Jupiter)\n");	206	puts ("Board: Sauter (Jupiter)\n");
207	return 0;	207	return 0;
208	}	208	}
209		209
210	void flash_preinit(void)	210	void flash_preinit(void)
211	{	211	{
212	/*	212	/*
213	* Now, when we are in RAM, enable flash write	213	* Now, when we are in RAM, enable flash write
214	* access for detection process.	214	* access for detection process.
215	* Note that CS_BOOT cannot be cleared when	215	* Note that CS_BOOT cannot be cleared when
216	* executing in flash.	216	* executing in flash.
217	*/	217	*/
218	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */	218	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
219	}	219	}
220		220
221	int board_early_init_r (void)	221	int board_early_init_r (void)
222	{	222	{
223	flash_preinit ();	223	flash_preinit ();
224	return 0;	224	return 0;
225	}	225	}
226		226
227	void flash_afterinit(ulong size)	227	void flash_afterinit(ulong size)
228	{	228	{
229	if (size == 0x1000000) { /* adjust mapping */	229	if (size == 0x1000000) { /* adjust mapping */
230	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =	230	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
231	START_REG(CONFIG_SYS_BOOTCS_START \| size);	231	START_REG(CONFIG_SYS_BOOTCS_START \| size);
232	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =	232	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
233	STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size);	233	STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size);
234	}	234	}
235	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */	235	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
236	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */	236	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */
237	}	237	}
238		238
239	int update_flash_size (int flash_size)	239	int update_flash_size (int flash_size)
240	{	240	{
241	flash_afterinit (flash_size);	241	flash_afterinit (flash_size);
242	return 0;	242	return 0;
243	}	243	}
244		244
245	int board_early_init_f (void)	245	int board_early_init_f (void)
246	{	246	{
247	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */	247	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
248	return 0;	248	return 0;
249	}	249	}
250		250
251	#ifdef CONFIG_PCI	251	#ifdef CONFIG_PCI
252	static struct pci_controller hose;	252	static struct pci_controller hose;
253		253
254	extern void pci_mpc5xxx_init(struct pci_controller *);	254	extern void pci_mpc5xxx_init(struct pci_controller *);
255		255
256	void pci_init_board(void)	256	void pci_init_board(void)
257	{	257	{
258	pci_mpc5xxx_init(&hose);	258	pci_mpc5xxx_init(&hose);
259	}	259	}
260	#endif	260	#endif
261		261
262	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)	262	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
263		263
264	void init_ide_reset (void)	264	void init_ide_reset (void)
265	{	265	{
266	debug ("init_ide_reset\n");	266	debug ("init_ide_reset\n");
267		267
268	/* Configure PSC1_4 as GPIO output for ATA reset */	268	/* Configure PSC1_4 as GPIO output for ATA reset */
269	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;	269	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
270	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;	270	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
271	/* Deassert reset */	271	/* Deassert reset */
272	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	272	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
273	}	273	}
274		274
275	void ide_set_reset (int idereset)	275	void ide_set_reset (int idereset)
276	{	276	{
277	debug ("ide_reset(%d)\n", idereset);	277	debug ("ide_reset(%d)\n", idereset);
278		278
279	if (idereset) {	279	if (idereset) {
280	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;	280	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
281	/* Make a delay. MPC5200 spec says 25 usec min */	281	/* Make a delay. MPC5200 spec says 25 usec min */
282	udelay(500000);	282	udelay(500000);
283	} else {	283	} else {
284	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	284	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
285	}	285	}
286	}	286	}
287	#endif	287	#endif
288		288
289	#ifdef CONFIG_OF_BOARD_SETUP	289	#ifdef CONFIG_OF_BOARD_SETUP
290	int ft_board_setup(void blob, bd_t bd)	290	int ft_board_setup(void blob, bd_t bd)
291	{	291	{
292	ft_cpu_setup(blob, bd);	292	ft_cpu_setup(blob, bd);
293		293
294	return 0;	294	return 0;
295	}	295	}
296	#endif /* CONFIG_OF_BOARD_SETUP */	296	#endif /* CONFIG_OF_BOARD_SETUP */
297		297

board/phytec/pcm030/pcm030.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2003	2	* (C) Copyright 2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2004	5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*	7	*
8	* (C) Copyright 2006	8	* (C) Copyright 2006
9	* Eric Schumann, Phytec Messtechnik GmbH	9	* Eric Schumann, Phytec Messtechnik GmbH
10	*	10	*
11	* SPDX-License-Identifier: GPL-2.0+	11	* SPDX-License-Identifier: GPL-2.0+
12	*/	12	*/
13		13
14	#include <common.h>	14	#include <common.h>
15	#include <mpc5xxx.h>	15	#include <mpc5xxx.h>
16	#include <pci.h>	16	#include <pci.h>
17	#include <asm/io.h>	17	#include <asm/io.h>
18		18
19	#include "mt46v32m16-75.h"	19	#include "mt46v32m16-75.h"
20		20
21	DECLARE_GLOBAL_DATA_PTR;	21	DECLARE_GLOBAL_DATA_PTR;
22		22
23	#ifndef CONFIG_SYS_RAMBOOT	23	#ifndef CONFIG_SYS_RAMBOOT
24	static void sdram_start(int hi_addr)	24	static void sdram_start(int hi_addr)
25	{	25	{
26	volatile struct mpc5xxx_cdm *cdm =	26	volatile struct mpc5xxx_cdm *cdm =
27	(struct mpc5xxx_cdm *)MPC5XXX_CDM;	27	(struct mpc5xxx_cdm *)MPC5XXX_CDM;
28	volatile struct mpc5xxx_sdram *sdram =	28	volatile struct mpc5xxx_sdram *sdram =
29	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;	29	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
30		30
31	long hi_addr_bit = hi_addr ? 0x01000000 : 0;	31	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
32		32
33	/* unlock mode register */	33	/* unlock mode register */
34	out_be32 (&sdram->ctrl,	34	out_be32 (&sdram->ctrl,
35	(SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit));	35	(SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit));
36		36
37	/* precharge all banks */	37	/* precharge all banks */
38	out_be32 (&sdram->ctrl,	38	out_be32 (&sdram->ctrl,
39	(SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));	39	(SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));
40		40
41	#ifdef SDRAM_DDR	41	#ifdef SDRAM_DDR
42	/* set mode register: extended mode */	42	/* set mode register: extended mode */
43	out_be32 (&sdram->mode, (SDRAM_EMODE));	43	out_be32 (&sdram->mode, (SDRAM_EMODE));
44		44
45	/* set mode register: reset DLL */	45	/* set mode register: reset DLL */
46	out_be32 (&sdram->mode,	46	out_be32 (&sdram->mode,
47	(SDRAM_MODE \| 0x04000000));	47	(SDRAM_MODE \| 0x04000000));
48	#endif	48	#endif
49		49
50	/* precharge all banks */	50	/* precharge all banks */
51	out_be32 (&sdram->ctrl,	51	out_be32 (&sdram->ctrl,
52	(SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));	52	(SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));
53		53
54	/* auto refresh */	54	/* auto refresh */
55	out_be32 (&sdram->ctrl,	55	out_be32 (&sdram->ctrl,
56	(SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit));	56	(SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit));
57		57
58	/* set mode register */	58	/* set mode register */
59	out_be32 (&sdram->mode, (SDRAM_MODE));	59	out_be32 (&sdram->mode, (SDRAM_MODE));
60		60
61	/* normal operation */	61	/* normal operation */
62	out_be32 (&sdram->ctrl,	62	out_be32 (&sdram->ctrl,
63	(SDRAM_CONTROL \| hi_addr_bit));	63	(SDRAM_CONTROL \| hi_addr_bit));
64		64
65	/* set CDM clock enable register, set MPC5200B SDRAM bus */	65	/* set CDM clock enable register, set MPC5200B SDRAM bus */
66	/* to reduced driver strength */	66	/* to reduced driver strength */
67	out_be32 (&cdm->clock_enable, (0x00CFFFFF));	67	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
68	}	68	}
69	#endif	69	#endif
70		70
71	/*	71	/*
72	* ATTENTION: Although partially referenced dram_init does NOT make	72	* ATTENTION: Although partially referenced dram_init does NOT make
73	* real use of CONFIG_SYS_SDRAM_BASE. The code does not	73	* real use of CONFIG_SYS_SDRAM_BASE. The code does not
74	* work if CONFIG_SYS_SDRAM_BASE	74	* work if CONFIG_SYS_SDRAM_BASE
75	* is something else than 0x00000000.	75	* is something else than 0x00000000.
76	*/	76	*/
77		77
78	int dram_init(void)	78	int dram_init(void)
79	{	79	{
80	volatile struct mpc5xxx_mmap_ctl *mm =	80	volatile struct mpc5xxx_mmap_ctl *mm =
81	(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;	81	(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
82	volatile struct mpc5xxx_cdm *cdm =	82	volatile struct mpc5xxx_cdm *cdm =
83	(struct mpc5xxx_cdm *)MPC5XXX_CDM;	83	(struct mpc5xxx_cdm *)MPC5XXX_CDM;
84	volatile struct mpc5xxx_sdram *sdram =	84	volatile struct mpc5xxx_sdram *sdram =
85	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;	85	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
86	ulong dramsize = 0;	86	ulong dramsize = 0;
87	ulong dramsize2 = 0;	87	ulong dramsize2 = 0;
88	#ifndef CONFIG_SYS_RAMBOOT	88	#ifndef CONFIG_SYS_RAMBOOT
89	ulong test1, test2;	89	ulong test1, test2;
90		90
91	/* setup SDRAM chip selects */	91	/* setup SDRAM chip selects */
92	/* 256MB at 0x0 */	92	/* 256MB at 0x0 */
93	out_be32 (&mm->sdram0, 0x0000001b);	93	out_be32 (&mm->sdram0, 0x0000001b);
94	/* disabled */	94	/* disabled */
95	out_be32 (&mm->sdram1, 0x10000000);	95	out_be32 (&mm->sdram1, 0x10000000);
96		96
97	/* setup config registers */	97	/* setup config registers */
98	out_be32 (&sdram->config1, SDRAM_CONFIG1);	98	out_be32 (&sdram->config1, SDRAM_CONFIG1);
99	out_be32 (&sdram->config2, SDRAM_CONFIG2);	99	out_be32 (&sdram->config2, SDRAM_CONFIG2);
100		100
101	#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)	101	#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
102	/* set tap delay */	102	/* set tap delay */
103	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);	103	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
104	#endif	104	#endif
105		105
106	/* find RAM size using SDRAM CS0 only */	106	/* find RAM size using SDRAM CS0 only */
107	sdram_start(0);	107	sdram_start(0);
108	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);	108	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
109	sdram_start(1);	109	sdram_start(1);
110	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);	110	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
111	if (test1 > test2) {	111	if (test1 > test2) {
112	sdram_start(0);	112	sdram_start(0);
113	dramsize = test1;	113	dramsize = test1;
114	} else	114	} else
115	dramsize = test2;	115	dramsize = test2;
116		116
117	/* memory smaller than 1MB is impossible */	117	/* memory smaller than 1MB is impossible */
118	if (dramsize < (1 << 20))	118	if (dramsize < (1 << 20))
119	dramsize = 0;	119	dramsize = 0;
120		120
121	/* set SDRAM CS0 size according to the amount of RAM found */	121	/* set SDRAM CS0 size according to the amount of RAM found */
122	if (dramsize > 0) {	122	if (dramsize > 0) {
123	out_be32 (&mm->sdram0,	123	out_be32 (&mm->sdram0,
124	(0x13 + __builtin_ffs(dramsize >> 20) - 1));	124	(0x13 + __builtin_ffs(dramsize >> 20) - 1));
125	} else {	125	} else {
126	/* disabled */	126	/* disabled */
127	out_be32 (&mm->sdram0, 0);	127	out_be32 (&mm->sdram0, 0);
128	}	128	}
129		129
130	#else /* CONFIG_SYS_RAMBOOT */	130	#else /* CONFIG_SYS_RAMBOOT */
131		131
132	/* retrieve size of memory connected to SDRAM CS0 */	132	/* retrieve size of memory connected to SDRAM CS0 */
133	dramsize = in_be32(&mm->sdram0) & 0xFF;	133	dramsize = in_be32(&mm->sdram0) & 0xFF;
134	if (dramsize >= 0x13)	134	if (dramsize >= 0x13)
135	dramsize = (1 << (dramsize - 0x13)) << 20;	135	dramsize = (1 << (dramsize - 0x13)) << 20;
136	else	136	else
137	dramsize = 0;	137	dramsize = 0;
138		138
139	/* retrieve size of memory connected to SDRAM CS1 */	139	/* retrieve size of memory connected to SDRAM CS1 */
140	dramsize2 = in_be32(&mm->sdram1) & 0xFF;	140	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
141	if (dramsize2 >= 0x13)	141	if (dramsize2 >= 0x13)
142	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;	142	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
143	else	143	else
144	dramsize2 = 0;	144	dramsize2 = 0;
145		145
146	#endif /* CONFIG_SYS_RAMBOOT */	146	#endif /* CONFIG_SYS_RAMBOOT */
147		147
148	gd->ram_size = dramsize + dramsize2;	148	gd->ram_size = dramsize + dramsize2;
149		149
150	return 0;	150	return 0;
151	}	151	}
152		152
153	int checkboard(void)	153	int checkboard(void)
154	{	154	{
155	puts("Board: phyCORE-MPC5200B-tiny\n");	155	puts("Board: phyCORE-MPC5200B-tiny\n");
156	return 0;	156	return 0;
157	}	157	}
158		158
159	#ifdef CONFIG_PCI	159	#ifdef CONFIG_PCI
160	static struct pci_controller hose;	160	static struct pci_controller hose;
161		161
162	extern void pci_mpc5xxx_init(struct pci_controller *);	162	extern void pci_mpc5xxx_init(struct pci_controller *);
163		163
164	void pci_init_board(void)	164	void pci_init_board(void)
165	{	165	{
166	pci_mpc5xxx_init(&hose);	166	pci_mpc5xxx_init(&hose);
167	}	167	}
168	#endif	168	#endif
169		169
170	#ifdef CONFIG_OF_BOARD_SETUP	170	#ifdef CONFIG_OF_BOARD_SETUP
171	int ft_board_setup(void blob, bd_t bd)	171	int ft_board_setup(void blob, bd_t bd)
172	{	172	{
173	ft_cpu_setup(blob, bd);	173	ft_cpu_setup(blob, bd);
174		174
175	return 0;	175	return 0;
176	}	176	}
177	#endif /* CONFIG_OF_BOARD_SETUP */	177	#endif /* CONFIG_OF_BOARD_SETUP */
178		178
179	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)	179	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
180		180
181	#define GPIO_PSC2_4 0x02000000UL	181	#define GPIO_PSC2_4 0x02000000UL
182		182
183	void init_ide_reset(void)	183	void init_ide_reset(void)
184	{	184	{
185	volatile struct mpc5xxx_wu_gpio *wu_gpio =	185	volatile struct mpc5xxx_wu_gpio *wu_gpio =
186	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;	186	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
187	debug("init_ide_reset\n");	187	debug("init_ide_reset\n");
188		188
189	/* Configure PSC2_4 as GPIO output for ATA reset */	189	/* Configure PSC2_4 as GPIO output for ATA reset */
190	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);	190	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
191	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);	191	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
192	/* Deassert reset */	192	/* Deassert reset */
193	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);	193	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
194	}	194	}
195		195
196	void ide_set_reset(int idereset)	196	void ide_set_reset(int idereset)
197	{	197	{
198	volatile struct mpc5xxx_wu_gpio *wu_gpio =	198	volatile struct mpc5xxx_wu_gpio *wu_gpio =
199	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;	199	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
200	debug("ide_reset(%d)\n", idereset);	200	debug("ide_reset(%d)\n", idereset);
201		201
202	if (idereset) {	202	if (idereset) {
203	clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);	203	clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
204	/* Make a delay. MPC5200 spec says 25 usec min */	204	/* Make a delay. MPC5200 spec says 25 usec min */
205	udelay(500000);	205	udelay(500000);
206	} else	206	} else
207	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);	207	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
208	}	208	}
209	#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */	209	#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */
210		210

board/tqc/tqm5200/tqm5200.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2003-2006	2	* (C) Copyright 2003-2006
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2004	5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*	7	*
8	* (C) Copyright 2004-2006	8	* (C) Copyright 2004-2006
9	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de	9	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10	*	10	*
11	* SPDX-License-Identifier: GPL-2.0+	11	* SPDX-License-Identifier: GPL-2.0+
12	*/	12	*/
13		13
14	#include <common.h>	14	#include <common.h>
15	#include <console.h>	15	#include <console.h>
16	#include <mpc5xxx.h>	16	#include <mpc5xxx.h>
17	#include <pci.h>	17	#include <pci.h>
18	#include <asm/processor.h>	18	#include <asm/processor.h>
19	#include <libfdt.h>	19	#include <libfdt.h>
20	#include <netdev.h>	20	#include <netdev.h>
21	#include <video.h>	21	#include <video.h>
22		22
23	#ifdef CONFIG_VIDEO_SM501	23	#ifdef CONFIG_VIDEO_SM501
24	#include <sm501.h>	24	#include <sm501.h>
25	#endif	25	#endif
26		26
27	#if defined(CONFIG_MPC5200_DDR)	27	#if defined(CONFIG_MPC5200_DDR)
28	#include "mt46v16m16-75.h"	28	#include "mt46v16m16-75.h"
29	#else	29	#else
30	#include "mt48lc16m16a2-75.h"	30	#include "mt48lc16m16a2-75.h"
31	#endif	31	#endif
32		32
33	#ifdef CONFIG_OF_LIBFDT	33	#ifdef CONFIG_OF_LIBFDT
34	#include <fdt_support.h>	34	#include <fdt_support.h>
35	#endif /* CONFIG_OF_LIBFDT */	35	#endif /* CONFIG_OF_LIBFDT */
36		36
37	DECLARE_GLOBAL_DATA_PTR;	37	DECLARE_GLOBAL_DATA_PTR;
38		38
39	#ifdef CONFIG_PS2MULT	39	#ifdef CONFIG_PS2MULT
40	void ps2mult_early_init(void);	40	void ps2mult_early_init(void);
41	#endif	41	#endif
42		42
43	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \	43	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
44	defined(CONFIG_VIDEO)	44	defined(CONFIG_VIDEO)
45	/*	45	/*
46	* EDID block has been generated using Phoenix EDID Designer 1.3.	46	* EDID block has been generated using Phoenix EDID Designer 1.3.
47	* This tool creates a text file containing:	47	* This tool creates a text file containing:
48	*	48	*
49	* EDID BYTES:	49	* EDID BYTES:
50	*	50	*
51	* 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F	51	* 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
52	* ------------------------------------------------	52	* ------------------------------------------------
53	* 00 \| 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00	53	* 00 \| 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
54	* 10 \| 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00	54	* 10 \| 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
55	* 20 \| 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01	55	* 20 \| 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
56	* 30 \| 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00	56	* 30 \| 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
57	* 40 \| 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00	57	* 40 \| 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
58	* 50 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00	58	* 50 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
59	* 60 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10	59	* 60 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
60	* 70 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17	60	* 70 \| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
61	*	61	*
62	* Then this data has been manually converted to the char	62	* Then this data has been manually converted to the char
63	* array below.	63	* array below.
64	*/	64	*/
65	static unsigned char edid_buf[128] = {	65	static unsigned char edid_buf[128] = {
66	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,	66	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
67	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	67	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,	68	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
69	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	69	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
70	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,	70	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
71	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,	71	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
72	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,	72	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
73	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	73	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	74	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,	75	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
76	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	76	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,	77	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
78	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	78	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,	79	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
80	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	80	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,	81	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
82	};	82	};
83	#endif	83	#endif
84		84
85	#ifndef CONFIG_SYS_RAMBOOT	85	#ifndef CONFIG_SYS_RAMBOOT
86	static void sdram_start (int hi_addr)	86	static void sdram_start (int hi_addr)
87	{	87	{
88	long hi_addr_bit = hi_addr ? 0x01000000 : 0;	88	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
89		89
90	/* unlock mode register */	90	/* unlock mode register */
91	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \|	91	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \|
92	hi_addr_bit;	92	hi_addr_bit;
93	__asm__ volatile ("sync");	93	__asm__ volatile ("sync");
94		94
95	/* precharge all banks */	95	/* precharge all banks */
96	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|	96	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
97	hi_addr_bit;	97	hi_addr_bit;
98	__asm__ volatile ("sync");	98	__asm__ volatile ("sync");
99		99
100	#if SDRAM_DDR	100	#if SDRAM_DDR
101	/* set mode register: extended mode */	101	/* set mode register: extended mode */
102	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;	102	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
103	__asm__ volatile ("sync");	103	__asm__ volatile ("sync");
104		104
105	/* set mode register: reset DLL */	105	/* set mode register: reset DLL */
106	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;	106	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
107	__asm__ volatile ("sync");	107	__asm__ volatile ("sync");
108	#endif	108	#endif
109		109
110	/* precharge all banks */	110	/* precharge all banks */
111	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|	111	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
112	hi_addr_bit;	112	hi_addr_bit;
113	__asm__ volatile ("sync");	113	__asm__ volatile ("sync");
114		114
115	/* auto refresh */	115	/* auto refresh */
116	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|	116	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|
117	hi_addr_bit;	117	hi_addr_bit;
118	__asm__ volatile ("sync");	118	__asm__ volatile ("sync");
119		119
120	/* set mode register */	120	/* set mode register */
121	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;	121	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
122	__asm__ volatile ("sync");	122	__asm__ volatile ("sync");
123		123
124	/* normal operation */	124	/* normal operation */
125	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;	125	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
126	__asm__ volatile ("sync");	126	__asm__ volatile ("sync");
127	}	127	}
128	#endif	128	#endif
129		129
130	/*	130	/*
131	* ATTENTION: Although partially referenced dram_init does NOT make real use	131	* ATTENTION: Although partially referenced dram_init does NOT make real use
132	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE	132	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
133	* is something else than 0x00000000.	133	* is something else than 0x00000000.
134	*/	134	*/
135		135
136	int dram_init(void)	136	int dram_init(void)
137	{	137	{
138	ulong dramsize = 0;	138	ulong dramsize = 0;
139	ulong dramsize2 = 0;	139	ulong dramsize2 = 0;
140	uint svr, pvr;	140	uint svr, pvr;
141		141
142	#ifndef CONFIG_SYS_RAMBOOT	142	#ifndef CONFIG_SYS_RAMBOOT
143	ulong test1, test2;	143	ulong test1, test2;
144		144
145	/* setup SDRAM chip selects */	145	/* setup SDRAM chip selects */
146	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */	146	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
147	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */	147	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
148	__asm__ volatile ("sync");	148	__asm__ volatile ("sync");
149		149
150	/* setup config registers */	150	/* setup config registers */
151	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;	151	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
152	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;	152	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
153	__asm__ volatile ("sync");	153	__asm__ volatile ("sync");
154		154
155	#if SDRAM_DDR	155	#if SDRAM_DDR
156	/* set tap delay */	156	/* set tap delay */
157	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;	157	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
158	__asm__ volatile ("sync");	158	__asm__ volatile ("sync");
159	#endif	159	#endif
160		160
161	/* find RAM size using SDRAM CS0 only */	161	/* find RAM size using SDRAM CS0 only */
162	sdram_start(0);	162	sdram_start(0);
163	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);	163	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
164	sdram_start(1);	164	sdram_start(1);
165	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);	165	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
166	if (test1 > test2) {	166	if (test1 > test2) {
167	sdram_start(0);	167	sdram_start(0);
168	dramsize = test1;	168	dramsize = test1;
169	} else {	169	} else {
170	dramsize = test2;	170	dramsize = test2;
171	}	171	}
172		172
173	/* memory smaller than 1MB is impossible */	173	/* memory smaller than 1MB is impossible */
174	if (dramsize < (1 << 20)) {	174	if (dramsize < (1 << 20)) {
175	dramsize = 0;	175	dramsize = 0;
176	}	176	}
177		177
178	/* set SDRAM CS0 size according to the amount of RAM found */	178	/* set SDRAM CS0 size according to the amount of RAM found */
179	if (dramsize > 0) {	179	if (dramsize > 0) {
180	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +	180	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +
181	__builtin_ffs(dramsize >> 20) - 1;	181	__builtin_ffs(dramsize >> 20) - 1;
182	} else {	182	} else {
183	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */	183	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
184	}	184	}
185		185
186	/* let SDRAM CS1 start right after CS0 */	186	/* let SDRAM CS1 start right after CS0 */
187	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */	187	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
188		188
189	/* find RAM size using SDRAM CS1 only */	189	/* find RAM size using SDRAM CS1 only */
190	if (!dramsize)	190	if (!dramsize)
191	sdram_start(0);	191	sdram_start(0);
192	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);	192	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
193	if (!dramsize) {	193	if (!dramsize) {
194	sdram_start(1);	194	sdram_start(1);
195	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);	195	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
196	}	196	}
197	if (test1 > test2) {	197	if (test1 > test2) {
198	sdram_start(0);	198	sdram_start(0);
199	dramsize2 = test1;	199	dramsize2 = test1;
200	} else {	200	} else {
201	dramsize2 = test2;	201	dramsize2 = test2;
202	}	202	}
203		203
204	/* memory smaller than 1MB is impossible */	204	/* memory smaller than 1MB is impossible */
205	if (dramsize2 < (1 << 20)) {	205	if (dramsize2 < (1 << 20)) {
206	dramsize2 = 0;	206	dramsize2 = 0;
207	}	207	}
208		208
209	/* set SDRAM CS1 size according to the amount of RAM found */	209	/* set SDRAM CS1 size according to the amount of RAM found */
210	if (dramsize2 > 0) {	210	if (dramsize2 > 0) {
211	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize	211	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
212	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);	212	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
213	} else {	213	} else {
214	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */	214	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
215	}	215	}
216		216
217	#else /* CONFIG_SYS_RAMBOOT */	217	#else /* CONFIG_SYS_RAMBOOT */
218		218
219	/* retrieve size of memory connected to SDRAM CS0 */	219	/* retrieve size of memory connected to SDRAM CS0 */
220	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;	220	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
221	if (dramsize >= 0x13) {	221	if (dramsize >= 0x13) {
222	dramsize = (1 << (dramsize - 0x13)) << 20;	222	dramsize = (1 << (dramsize - 0x13)) << 20;
223	} else {	223	} else {
224	dramsize = 0;	224	dramsize = 0;
225	}	225	}
226		226
227	/* retrieve size of memory connected to SDRAM CS1 */	227	/* retrieve size of memory connected to SDRAM CS1 */
228	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;	228	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
229	if (dramsize2 >= 0x13) {	229	if (dramsize2 >= 0x13) {
230	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;	230	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
231	} else {	231	} else {
232	dramsize2 = 0;	232	dramsize2 = 0;
233	}	233	}
234	#endif /* CONFIG_SYS_RAMBOOT */	234	#endif /* CONFIG_SYS_RAMBOOT */
235		235
236	/*	236	/*
237	* On MPC5200B we need to set the special configuration delay in the	237	* On MPC5200B we need to set the special configuration delay in the
238	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM	238	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
239	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:	239	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
240	*	240	*
241	* "The SDelay should be written to a value of 0x00000004. It is	241	* "The SDelay should be written to a value of 0x00000004. It is
242	* required to account for changes caused by normal wafer processing	242	* required to account for changes caused by normal wafer processing
243	* parameters."	243	* parameters."
244	*/	244	*/
245	svr = get_svr();	245	svr = get_svr();
246	pvr = get_pvr();	246	pvr = get_pvr();
247	if ((SVR_MJREV(svr) >= 2) &&	247	if ((SVR_MJREV(svr) >= 2) &&
248	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {	248	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
249		249
250	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;	250	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
251	__asm__ volatile ("sync");	251	__asm__ volatile ("sync");
252	}	252	}
253		253
254	#if defined(CONFIG_TQM5200_B)	254	#if defined(CONFIG_TQM5200_B)
255	gd->ram_size = dramsize + dramsize2;	255	gd->ram_size = dramsize + dramsize2;
256	#else	256	#else
257	gd->ram_size = dramsize;	257	gd->ram_size = dramsize;
258	#endif /* CONFIG_TQM5200_B */	258	#endif /* CONFIG_TQM5200_B */
259		259
260	return 0;	260	return 0;
261	}	261	}
262		262
263	int checkboard (void)	263	int checkboard (void)
264	{	264	{
265	#if defined(CONFIG_TQM5200S)	265	#if defined(CONFIG_TQM5200S)
266	# define MODULE_NAME "TQM5200S"	266	# define MODULE_NAME "TQM5200S"
267	#else	267	#else
268	# define MODULE_NAME "TQM5200"	268	# define MODULE_NAME "TQM5200"
269	#endif	269	#endif
270		270
271	#if defined(CONFIG_STK52XX)	271	#if defined(CONFIG_STK52XX)
272	# define CARRIER_NAME "STK52xx"	272	# define CARRIER_NAME "STK52xx"
273	#elif defined(CONFIG_CAM5200)	273	#elif defined(CONFIG_CAM5200)
274	# define CARRIER_NAME "CAM5200"	274	# define CARRIER_NAME "CAM5200"
275	#elif defined(CONFIG_FO300)	275	#elif defined(CONFIG_FO300)
276	# define CARRIER_NAME "FO300"	276	# define CARRIER_NAME "FO300"
277	#elif defined(CONFIG_CHARON)	277	#elif defined(CONFIG_CHARON)
278	# define CARRIER_NAME "CHARON"	278	# define CARRIER_NAME "CHARON"
279	#else	279	#else
280	# error "UNKNOWN"	280	# error "UNKNOWN"
281	#endif	281	#endif
282		282
283	puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"	283	puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
284	" on a " CARRIER_NAME " carrier board\n");	284	" on a " CARRIER_NAME " carrier board\n");
285		285
286	return 0;	286	return 0;
287	}	287	}
288		288
289	#undef MODULE_NAME	289	#undef MODULE_NAME
290	#undef CARRIER_NAME	290	#undef CARRIER_NAME
291		291
292	void flash_preinit(void)	292	void flash_preinit(void)
293	{	293	{
294	/*	294	/*
295	* Now, when we are in RAM, enable flash write	295	* Now, when we are in RAM, enable flash write
296	* access for detection process.	296	* access for detection process.
297	* Note that CS_BOOT cannot be cleared when	297	* Note that CS_BOOT cannot be cleared when
298	* executing in flash.	298	* executing in flash.
299	*/	299	*/
300	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */	300	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
301	}	301	}
302		302
303		303
304	#ifdef CONFIG_PCI	304	#ifdef CONFIG_PCI
305	static struct pci_controller hose;	305	static struct pci_controller hose;
306		306
307	extern void pci_mpc5xxx_init(struct pci_controller *);	307	extern void pci_mpc5xxx_init(struct pci_controller *);
308		308
309	void pci_init_board(void)	309	void pci_init_board(void)
310	{	310	{
311	pci_mpc5xxx_init(&hose);	311	pci_mpc5xxx_init(&hose);
312	}	312	}
313	#endif	313	#endif
314		314
315	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)	315	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
316		316
317	#if defined (CONFIG_MINIFAP)	317	#if defined (CONFIG_MINIFAP)
318	#define SM501_POWER_MODE0_GATE 0x00000040UL	318	#define SM501_POWER_MODE0_GATE 0x00000040UL
319	#define SM501_POWER_MODE1_GATE 0x00000048UL	319	#define SM501_POWER_MODE1_GATE 0x00000048UL
320	#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL	320	#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
321	#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL	321	#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
322	#define SM501_GPIO_DATA_HIGH 0x00010004UL	322	#define SM501_GPIO_DATA_HIGH 0x00010004UL
323	#define SM501_GPIO_51 0x00080000UL	323	#define SM501_GPIO_51 0x00080000UL
324	#endif /* CONFIG MINIFAP */	324	#endif /* CONFIG MINIFAP */
325		325
326	void init_ide_reset (void)	326	void init_ide_reset (void)
327	{	327	{
328	debug ("init_ide_reset\n");	328	debug ("init_ide_reset\n");
329		329
330	#if defined (CONFIG_MINIFAP)	330	#if defined (CONFIG_MINIFAP)
331	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */	331	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
332		332
333	/* enable GPIO control (in both power modes) */	333	/* enable GPIO control (in both power modes) */
334	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) \|=	334	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) \|=
335	POWER_MODE_GATE_GPIO_PWM_I2C;	335	POWER_MODE_GATE_GPIO_PWM_I2C;
336	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) \|=	336	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) \|=
337	POWER_MODE_GATE_GPIO_PWM_I2C;	337	POWER_MODE_GATE_GPIO_PWM_I2C;
338	/* configure GPIO51 as output */	338	/* configure GPIO51 as output */
339	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) \|=	339	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) \|=
340	SM501_GPIO_51;	340	SM501_GPIO_51;
341	#else	341	#else
342	/* Configure PSC1_4 as GPIO output for ATA reset */	342	/* Configure PSC1_4 as GPIO output for ATA reset */
343	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;	343	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
344	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;	344	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
345		345
346	/* by default the ATA reset is de-asserted */	346	/* by default the ATA reset is de-asserted */
347	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	347	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
348	#endif	348	#endif
349	}	349	}
350		350
351	void ide_set_reset (int idereset)	351	void ide_set_reset (int idereset)
352	{	352	{
353	debug ("ide_reset(%d)\n", idereset);	353	debug ("ide_reset(%d)\n", idereset);
354		354
355	#if defined (CONFIG_MINIFAP)	355	#if defined (CONFIG_MINIFAP)
356	if (idereset) {	356	if (idereset) {
357	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=	357	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
358	~SM501_GPIO_51;	358	~SM501_GPIO_51;
359	} else {	359	} else {
360	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) \|=	360	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) \|=
361	SM501_GPIO_51;	361	SM501_GPIO_51;
362	}	362	}
363	#else	363	#else
364	if (idereset) {	364	if (idereset) {
365	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;	365	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
366	} else {	366	} else {
367	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	367	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
368	}	368	}
369	#endif	369	#endif
370	}	370	}
371	#endif	371	#endif
372		372
373	#ifdef CONFIG_POST	373	#ifdef CONFIG_POST
374	/*	374	/*
375	* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3	375	* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
376	* is left open, no keypress is detected.	376	* is left open, no keypress is detected.
377	*/	377	*/
378	int post_hotkeys_pressed(void)	378	int post_hotkeys_pressed(void)
379	{	379	{
380	#ifdef CONFIG_STK52XX	380	#ifdef CONFIG_STK52XX
381	struct mpc5xxx_gpio *gpio;	381	struct mpc5xxx_gpio *gpio;
382		382
383	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;	383	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
384		384
385	/*	385	/*
386	* Configure PSC6_0 through PSC6_3 as GPIO.	386	* Configure PSC6_0 through PSC6_3 as GPIO.
387	*/	387	*/
388	gpio->port_config &= ~(0x00700000);	388	gpio->port_config &= ~(0x00700000);
389		389
390	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */	390	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
391	gpio->simple_gpioe \|= 0x20000000;	391	gpio->simple_gpioe \|= 0x20000000;
392		392
393	/* Configure GPIO_IRDA_1 as input */	393	/* Configure GPIO_IRDA_1 as input */
394	gpio->simple_ddr &= ~(0x20000000);	394	gpio->simple_ddr &= ~(0x20000000);
395		395
396	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);	396	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
397	#else	397	#else
398	return 0;	398	return 0;
399	#endif	399	#endif
400	}	400	}
401	#endif	401	#endif
402		402
403	#ifdef CONFIG_BOARD_EARLY_INIT_R	403	#ifdef CONFIG_BOARD_EARLY_INIT_R
404	int board_early_init_r (void)	404	int board_early_init_r (void)
405	{	405	{
406		406
407	extern int usb_cpu_init(void);	407	extern int usb_cpu_init(void);
408		408
409	#ifdef CONFIG_PS2MULT	409	#ifdef CONFIG_PS2MULT
410	ps2mult_early_init();	410	ps2mult_early_init();
411	#endif /* CONFIG_PS2MULT */	411	#endif /* CONFIG_PS2MULT */
412		412
413	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)	413	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
414	/* Low level USB init, required for proper kernel operation */	414	/* Low level USB init, required for proper kernel operation */
415	usb_cpu_init();	415	usb_cpu_init();
416	#endif	416	#endif
417		417
418	return (0);	418	return (0);
419	}	419	}
420	#endif	420	#endif
421		421
422	#ifdef CONFIG_FO300	422	#ifdef CONFIG_FO300
423	int silent_boot (void)	423	int silent_boot (void)
424	{	424	{
425	vu_long timer3_status;	425	vu_long timer3_status;
426		426
427	/* Configure GPT3 as GPIO input */	427	/* Configure GPT3 as GPIO input */
428	(vu_long )MPC5XXX_GPT3_ENABLE = 0x00000004;	428	(vu_long )MPC5XXX_GPT3_ENABLE = 0x00000004;
429		429
430	/* Read in TIMER_3 pin status */	430	/* Read in TIMER_3 pin status */
431	timer3_status = (vu_long )MPC5XXX_GPT3_STATUS;	431	timer3_status = (vu_long )MPC5XXX_GPT3_STATUS;
432		432
433	#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	433	#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
434	/* Force silent console mode if S1 switch	434	/* Force silent console mode if S1 switch
435	* is in closed position (TIMER_3 pin status is LOW). */	435	* is in closed position (TIMER_3 pin status is LOW). */
436	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)	436	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
437	return 1;	437	return 1;
438	#else	438	#else
439	/* Force silent console mode if S1 switch	439	/* Force silent console mode if S1 switch
440	* is in open position (TIMER_3 pin status is HIGH). */	440	* is in open position (TIMER_3 pin status is HIGH). */
441	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)	441	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
442	return 1;	442	return 1;
443	#endif	443	#endif
444		444
445	return 0;	445	return 0;
446	}	446	}
447		447
448	int board_early_init_f (void)	448	int board_early_init_f (void)
449	{	449	{
450	if (silent_boot())	450	if (silent_boot())
451	gd->flags \|= GD_FLG_SILENT;	451	gd->flags \|= GD_FLG_SILENT;
452		452
453	return 0;	453	return 0;
454	}	454	}
455	#endif /* CONFIG_FO300 */	455	#endif /* CONFIG_FO300 */
456		456
457	#if defined(CONFIG_CHARON)	457	#if defined(CONFIG_CHARON)
458	#include <i2c.h>	458	#include <i2c.h>
459	#include <asm/io.h>	459	#include <asm/io.h>
460		460
461	/* The TFP410 registers */	461	/* The TFP410 registers */
462	#define TFP410_REG_VEN_ID_L 0x00	462	#define TFP410_REG_VEN_ID_L 0x00
463	#define TFP410_REG_VEN_ID_H 0x01	463	#define TFP410_REG_VEN_ID_H 0x01
464	#define TFP410_REG_DEV_ID_L 0x02	464	#define TFP410_REG_DEV_ID_L 0x02
465	#define TFP410_REG_DEV_ID_H 0x03	465	#define TFP410_REG_DEV_ID_H 0x03
466	#define TFP410_REG_REV_ID 0x04	466	#define TFP410_REG_REV_ID 0x04
467		467
468	#define TFP410_REG_CTL_1_MODE 0x08	468	#define TFP410_REG_CTL_1_MODE 0x08
469	#define TFP410_REG_CTL_2_MODE 0x09	469	#define TFP410_REG_CTL_2_MODE 0x09
470	#define TFP410_REG_CTL_3_MODE 0x0A	470	#define TFP410_REG_CTL_3_MODE 0x0A
471		471
472	#define TFP410_REG_CFG 0x0B	472	#define TFP410_REG_CFG 0x0B
473		473
474	#define TFP410_REG_DE_DLY 0x32	474	#define TFP410_REG_DE_DLY 0x32
475	#define TFP410_REG_DE_CTL 0x33	475	#define TFP410_REG_DE_CTL 0x33
476	#define TFP410_REG_DE_TOP 0x34	476	#define TFP410_REG_DE_TOP 0x34
477	#define TFP410_REG_DE_CNT_L 0x36	477	#define TFP410_REG_DE_CNT_L 0x36
478	#define TFP410_REG_DE_CNT_H 0x37	478	#define TFP410_REG_DE_CNT_H 0x37
479	#define TFP410_REG_DE_LIN_L 0x38	479	#define TFP410_REG_DE_LIN_L 0x38
480	#define TFP410_REG_DE_LIN_H 0x39	480	#define TFP410_REG_DE_LIN_H 0x39
481		481
482	#define TFP410_REG_H_RES_L 0x3A	482	#define TFP410_REG_H_RES_L 0x3A
483	#define TFP410_REG_H_RES_H 0x3B	483	#define TFP410_REG_H_RES_H 0x3B
484	#define TFP410_REG_V_RES_L 0x3C	484	#define TFP410_REG_V_RES_L 0x3C
485	#define TFP410_REG_V_RES_H 0x3D	485	#define TFP410_REG_V_RES_H 0x3D
486		486
487	static int tfp410_read_reg(int reg, uchar *buf)	487	static int tfp410_read_reg(int reg, uchar *buf)
488	{	488	{
489	puts("Error reading the chip.\n");	489	puts("Error reading the chip.\n");
490	return -ENOSYS;	490	return -ENOSYS;
491	}	491	}
492		492
493	static int tfp410_write_reg(int reg, uchar buf)	493	static int tfp410_write_reg(int reg, uchar buf)
494	{	494	{
495	puts("Error writing the chip.\n");	495	puts("Error writing the chip.\n");
496	return -ENOSYS;	496	return -ENOSYS;
497	}	497	}
498		498
499	typedef struct _tfp410_config {	499	typedef struct _tfp410_config {
500	int reg;	500	int reg;
501	uchar val;	501	uchar val;
502	}TFP410_CONFIG;	502	}TFP410_CONFIG;
503		503
504	static TFP410_CONFIG tfp410_configtbl[] = {	504	static TFP410_CONFIG tfp410_configtbl[] = {
505	{TFP410_REG_CTL_1_MODE, 0x37},	505	{TFP410_REG_CTL_1_MODE, 0x37},
506	{TFP410_REG_CTL_2_MODE, 0x20},	506	{TFP410_REG_CTL_2_MODE, 0x20},
507	{TFP410_REG_CTL_3_MODE, 0x80},	507	{TFP410_REG_CTL_3_MODE, 0x80},
508	{TFP410_REG_DE_DLY, 0x90},	508	{TFP410_REG_DE_DLY, 0x90},
509	{TFP410_REG_DE_CTL, 0x00},	509	{TFP410_REG_DE_CTL, 0x00},
510	{TFP410_REG_DE_TOP, 0x23},	510	{TFP410_REG_DE_TOP, 0x23},
511	{TFP410_REG_DE_CNT_H, 0x02},	511	{TFP410_REG_DE_CNT_H, 0x02},
512	{TFP410_REG_DE_CNT_L, 0x80},	512	{TFP410_REG_DE_CNT_L, 0x80},
513	{TFP410_REG_DE_LIN_H, 0x01},	513	{TFP410_REG_DE_LIN_H, 0x01},
514	{TFP410_REG_DE_LIN_L, 0xe0},	514	{TFP410_REG_DE_LIN_L, 0xe0},
515	{-1, 0},	515	{-1, 0},
516	};	516	};
517		517
518	static int charon_last_stage_init(void)	518	static int charon_last_stage_init(void)
519	{	519	{
520	volatile struct mpc5xxx_lpb *lpb =	520	volatile struct mpc5xxx_lpb *lpb =
521	(struct mpc5xxx_lpb *) MPC5XXX_LPB;	521	(struct mpc5xxx_lpb *) MPC5XXX_LPB;
522	uchar buf;	522	uchar buf;
523	int i = 0;	523	int i = 0;
524		524
525	/* check version */	525	/* check version */
526	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)	526	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
527	return -1;	527	return -1;
528	if (!(buf & 0x04))	528	if (!(buf & 0x04))
529	return -1;	529	return -1;
530	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)	530	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
531	return -1;	531	return -1;
532	if (!(buf & 0x10))	532	if (!(buf & 0x10))
533	return -1;	533	return -1;
534	/* OK, now init the chip */	534	/* OK, now init the chip */
535	while (tfp410_configtbl[i].reg != -1) {	535	while (tfp410_configtbl[i].reg != -1) {
536	int ret;	536	int ret;
537		537
538	ret = tfp410_write_reg(tfp410_configtbl[i].reg,	538	ret = tfp410_write_reg(tfp410_configtbl[i].reg,
539	tfp410_configtbl[i].val);	539	tfp410_configtbl[i].val);
540	if (ret != 0)	540	if (ret != 0)
541	return -1;	541	return -1;
542	i++;	542	i++;
543	}	543	}
544	printf("TFP410 initialized.\n");	544	printf("TFP410 initialized.\n");
545		545
546	/* set deadcycle for cs3 to 0 */	546	/* set deadcycle for cs3 to 0 */
547	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);	547	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
548	return 0;	548	return 0;
549	}	549	}
550	#endif	550	#endif
551		551
552	int last_stage_init (void)	552	int last_stage_init (void)
553	{	553	{
554	/*	554	/*
555	* auto scan for really existing devices and re-set chip select	555	* auto scan for really existing devices and re-set chip select
556	* configuration.	556	* configuration.
557	*/	557	*/
558	u16 save, tmp;	558	u16 save, tmp;
559	int restore;	559	int restore;
560		560
561	/*	561	/*
562	* Check for SRAM and SRAM size	562	* Check for SRAM and SRAM size
563	*/	563	*/
564		564
565	/* save original SRAM content */	565	/* save original SRAM content */
566	save = (volatile u16 )CONFIG_SYS_CS2_START;	566	save = (volatile u16 )CONFIG_SYS_CS2_START;
567	restore = 1;	567	restore = 1;
568		568
569	/* write test pattern to SRAM */	569	/* write test pattern to SRAM */
570	(volatile u16 )CONFIG_SYS_CS2_START = 0xA5A5;	570	(volatile u16 )CONFIG_SYS_CS2_START = 0xA5A5;
571	__asm__ volatile ("sync");	571	__asm__ volatile ("sync");
572	/*	572	/*
573	* Put a different pattern on the data lines: otherwise they may float	573	* Put a different pattern on the data lines: otherwise they may float
574	* long enough to read back what we wrote.	574	* long enough to read back what we wrote.
575	*/	575	*/
576	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;	576	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
577	if (tmp == 0xA5A5)	577	if (tmp == 0xA5A5)
578	puts ("!! possible error in SRAM detection\n");	578	puts ("!! possible error in SRAM detection\n");
579		579
580	if ((volatile u16 )CONFIG_SYS_CS2_START != 0xA5A5) {	580	if ((volatile u16 )CONFIG_SYS_CS2_START != 0xA5A5) {
581	/* no SRAM at all, disable cs */	581	/* no SRAM at all, disable cs */
582	(vu_long )MPC5XXX_ADDECR &= ~(1 << 18);	582	(vu_long )MPC5XXX_ADDECR &= ~(1 << 18);
583	(vu_long )MPC5XXX_CS2_START = 0x0000FFFF;	583	(vu_long )MPC5XXX_CS2_START = 0x0000FFFF;
584	(vu_long )MPC5XXX_CS2_STOP = 0x0000FFFF;	584	(vu_long )MPC5XXX_CS2_STOP = 0x0000FFFF;
585	restore = 0;	585	restore = 0;
586	__asm__ volatile ("sync");	586	__asm__ volatile ("sync");
587	} else if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {	587	} else if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
588	/* make sure that we access a mirrored address */	588	/* make sure that we access a mirrored address */
589	(volatile u16 )CONFIG_SYS_CS2_START = 0x1111;	589	(volatile u16 )CONFIG_SYS_CS2_START = 0x1111;
590	__asm__ volatile ("sync");	590	__asm__ volatile ("sync");
591	if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {	591	if ((volatile u16 )(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
592	/* SRAM size = 512 kByte */	592	/* SRAM size = 512 kByte */
593	(vu_long )MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,	593	(vu_long )MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
594	0x80000);	594	0x80000);
595	__asm__ volatile ("sync");	595	__asm__ volatile ("sync");
596	puts ("SRAM: 512 kB\n");	596	puts ("SRAM: 512 kB\n");
597	}	597	}
598	else	598	else
599	puts ("!! possible error in SRAM detection\n");	599	puts ("!! possible error in SRAM detection\n");
600	} else {	600	} else {
601	puts ("SRAM: 1 MB\n");	601	puts ("SRAM: 1 MB\n");
602	}	602	}
603	/* restore origianl SRAM content */	603	/* restore origianl SRAM content */
604	if (restore) {	604	if (restore) {
605	(volatile u16 )CONFIG_SYS_CS2_START = save;	605	(volatile u16 )CONFIG_SYS_CS2_START = save;
606	__asm__ volatile ("sync");	606	__asm__ volatile ("sync");
607	}	607	}
608		608
609	#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */	609	#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
610	/*	610	/*
611	* Check for Grafic Controller	611	* Check for Grafic Controller
612	*/	612	*/
613		613
614	/* save origianl FB content */	614	/* save origianl FB content */
615	save = (volatile u16 )CONFIG_SYS_CS1_START;	615	save = (volatile u16 )CONFIG_SYS_CS1_START;
616	restore = 1;	616	restore = 1;
617		617
618	/* write test pattern to FB memory */	618	/* write test pattern to FB memory */
619	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;	619	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;
620	__asm__ volatile ("sync");	620	__asm__ volatile ("sync");
621	/*	621	/*
622	* Put a different pattern on the data lines: otherwise they may float	622	* Put a different pattern on the data lines: otherwise they may float
623	* long enough to read back what we wrote.	623	* long enough to read back what we wrote.
624	*/	624	*/
625	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;	625	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
626	if (tmp == 0xA5A5)	626	if (tmp == 0xA5A5)
627	puts ("!! possible error in grafic controller detection\n");	627	puts ("!! possible error in grafic controller detection\n");
628		628
629	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {	629	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {
630	/* no grafic controller at all, disable cs */	630	/* no grafic controller at all, disable cs */
631	(vu_long )MPC5XXX_ADDECR &= ~(1 << 17);	631	(vu_long )MPC5XXX_ADDECR &= ~(1 << 17);
632	(vu_long )MPC5XXX_CS1_START = 0x0000FFFF;	632	(vu_long )MPC5XXX_CS1_START = 0x0000FFFF;
633	(vu_long )MPC5XXX_CS1_STOP = 0x0000FFFF;	633	(vu_long )MPC5XXX_CS1_STOP = 0x0000FFFF;
634	restore = 0;	634	restore = 0;
635	__asm__ volatile ("sync");	635	__asm__ volatile ("sync");
636	} else {	636	} else {
637	puts ("VGA: SMI501 (Voyager) with 8 MB\n");	637	puts ("VGA: SMI501 (Voyager) with 8 MB\n");
638	}	638	}
639	/* restore origianl FB content */	639	/* restore origianl FB content */
640	if (restore) {	640	if (restore) {
641	(volatile u16 )CONFIG_SYS_CS1_START = save;	641	(volatile u16 )CONFIG_SYS_CS1_START = save;
642	__asm__ volatile ("sync");	642	__asm__ volatile ("sync");
643	}	643	}
644		644
645	#ifdef CONFIG_FO300	645	#ifdef CONFIG_FO300
646	if (silent_boot()) {	646	if (silent_boot()) {
647	setenv("bootdelay", "0");	647	setenv("bootdelay", "0");
648	disable_ctrlc(1);	648	disable_ctrlc(1);
649	}	649	}
650	#endif	650	#endif
651	#endif /* !CONFIG_TQM5200S */	651	#endif /* !CONFIG_TQM5200S */
652		652
653	#if defined(CONFIG_CHARON)	653	#if defined(CONFIG_CHARON)
654	charon_last_stage_init();	654	charon_last_stage_init();
655	#endif	655	#endif
656	return 0;	656	return 0;
657	}	657	}
658		658
659	#ifdef CONFIG_VIDEO_SM501	659	#ifdef CONFIG_VIDEO_SM501
660		660
661	#ifdef CONFIG_FO300	661	#ifdef CONFIG_FO300
662	#define DISPLAY_WIDTH 800	662	#define DISPLAY_WIDTH 800
663	#else	663	#else
664	#define DISPLAY_WIDTH 640	664	#define DISPLAY_WIDTH 640
665	#endif	665	#endif
666	#define DISPLAY_HEIGHT 480	666	#define DISPLAY_HEIGHT 480
667		667
668	#ifdef CONFIG_VIDEO_SM501_8BPP	668	#ifdef CONFIG_VIDEO_SM501_8BPP
669	#error CONFIG_VIDEO_SM501_8BPP not supported.	669	#error CONFIG_VIDEO_SM501_8BPP not supported.
670	#endif /* CONFIG_VIDEO_SM501_8BPP */	670	#endif /* CONFIG_VIDEO_SM501_8BPP */
671		671
672	#ifdef CONFIG_VIDEO_SM501_16BPP	672	#ifdef CONFIG_VIDEO_SM501_16BPP
673	#error CONFIG_VIDEO_SM501_16BPP not supported.	673	#error CONFIG_VIDEO_SM501_16BPP not supported.
674	#endif /* CONFIG_VIDEO_SM501_16BPP */	674	#endif /* CONFIG_VIDEO_SM501_16BPP */
675	#ifdef CONFIG_VIDEO_SM501_32BPP	675	#ifdef CONFIG_VIDEO_SM501_32BPP
676	static const SMI_REGS init_regs [] =	676	static const SMI_REGS init_regs [] =
677	{	677	{
678	#if 0 /* CRT only */	678	#if 0 /* CRT only */
679	{0x00004, 0x0},	679	{0x00004, 0x0},
680	{0x00048, 0x00021807},	680	{0x00048, 0x00021807},
681	{0x0004C, 0x10090a01},	681	{0x0004C, 0x10090a01},
682	{0x00054, 0x1},	682	{0x00054, 0x1},
683	{0x00040, 0x00021807},	683	{0x00040, 0x00021807},
684	{0x00044, 0x10090a01},	684	{0x00044, 0x10090a01},
685	{0x00054, 0x0},	685	{0x00054, 0x0},
686	{0x80200, 0x00010000},	686	{0x80200, 0x00010000},
687	{0x80204, 0x0},	687	{0x80204, 0x0},
688	{0x80208, 0x0A000A00},	688	{0x80208, 0x0A000A00},
689	{0x8020C, 0x02fa027f},	689	{0x8020C, 0x02fa027f},
690	{0x80210, 0x004a028b},	690	{0x80210, 0x004a028b},
691	{0x80214, 0x020c01df},	691	{0x80214, 0x020c01df},
692	{0x80218, 0x000201e9},	692	{0x80218, 0x000201e9},
693	{0x80200, 0x00013306},	693	{0x80200, 0x00013306},
694	#else /* panel + CRT */	694	#else /* panel + CRT */
695	#ifdef CONFIG_FO300	695	#ifdef CONFIG_FO300
696	{0x00004, 0x0},	696	{0x00004, 0x0},
697	{0x00048, 0x00021807},	697	{0x00048, 0x00021807},
698	{0x0004C, 0x301a0a01},	698	{0x0004C, 0x301a0a01},
699	{0x00054, 0x1},	699	{0x00054, 0x1},
700	{0x00040, 0x00021807},	700	{0x00040, 0x00021807},
701	{0x00044, 0x091a0a01},	701	{0x00044, 0x091a0a01},
702	{0x00054, 0x0},	702	{0x00054, 0x0},
703	{0x80000, 0x0f013106},	703	{0x80000, 0x0f013106},
704	{0x80004, 0xc428bb17},	704	{0x80004, 0xc428bb17},
705	{0x8000C, 0x00000000},	705	{0x8000C, 0x00000000},
706	{0x80010, 0x0C800C80},	706	{0x80010, 0x0C800C80},
707	{0x80014, 0x03200000},	707	{0x80014, 0x03200000},
708	{0x80018, 0x01e00000},	708	{0x80018, 0x01e00000},
709	{0x8001C, 0x00000000},	709	{0x8001C, 0x00000000},
710	{0x80020, 0x01e00320},	710	{0x80020, 0x01e00320},
711	{0x80024, 0x042a031f},	711	{0x80024, 0x042a031f},
712	{0x80028, 0x0086034a},	712	{0x80028, 0x0086034a},
713	{0x8002C, 0x020c01df},	713	{0x8002C, 0x020c01df},
714	{0x80030, 0x000201ea},	714	{0x80030, 0x000201ea},
715	{0x80200, 0x00010000},	715	{0x80200, 0x00010000},
716	#else	716	#else
717	{0x00004, 0x0},	717	{0x00004, 0x0},
718	{0x00048, 0x00021807},	718	{0x00048, 0x00021807},
719	{0x0004C, 0x091a0a01},	719	{0x0004C, 0x091a0a01},
720	{0x00054, 0x1},	720	{0x00054, 0x1},
721	{0x00040, 0x00021807},	721	{0x00040, 0x00021807},
722	{0x00044, 0x091a0a01},	722	{0x00044, 0x091a0a01},
723	{0x00054, 0x0},	723	{0x00054, 0x0},
724	{0x80000, 0x0f013106},	724	{0x80000, 0x0f013106},
725	{0x80004, 0xc428bb17},	725	{0x80004, 0xc428bb17},
726	{0x8000C, 0x00000000},	726	{0x8000C, 0x00000000},
727	{0x80010, 0x0a000a00},	727	{0x80010, 0x0a000a00},
728	{0x80014, 0x02800000},	728	{0x80014, 0x02800000},
729	{0x80018, 0x01e00000},	729	{0x80018, 0x01e00000},
730	{0x8001C, 0x00000000},	730	{0x8001C, 0x00000000},
731	{0x80020, 0x01e00280},	731	{0x80020, 0x01e00280},
732	{0x80024, 0x02fa027f},	732	{0x80024, 0x02fa027f},
733	{0x80028, 0x004a028b},	733	{0x80028, 0x004a028b},
734	{0x8002C, 0x020c01df},	734	{0x8002C, 0x020c01df},
735	{0x80030, 0x000201e9},	735	{0x80030, 0x000201e9},
736	{0x80200, 0x00010000},	736	{0x80200, 0x00010000},
737	#endif /* #ifdef CONFIG_FO300 */	737	#endif /* #ifdef CONFIG_FO300 */
738	#endif	738	#endif
739	{0, 0}	739	{0, 0}
740	};	740	};
741	#endif /* CONFIG_VIDEO_SM501_32BPP */	741	#endif /* CONFIG_VIDEO_SM501_32BPP */
742		742
743	#ifdef CONFIG_CONSOLE_EXTRA_INFO	743	#ifdef CONFIG_CONSOLE_EXTRA_INFO
744	/*	744	/*
745	* Return text to be printed besides the logo.	745	* Return text to be printed besides the logo.
746	*/	746	*/
747	void video_get_info_str (int line_number, char *info)	747	void video_get_info_str (int line_number, char *info)
748	{	748	{
749	if (line_number == 1) {	749	if (line_number == 1) {
750	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");	750	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
751	#if defined (CONFIG_CHARON) \|\| defined (CONFIG_FO300) \|\| \	751	#if defined (CONFIG_CHARON) \|\| defined (CONFIG_FO300) \|\| \
752	defined(CONFIG_STK52XX)	752	defined(CONFIG_STK52XX)
753	} else if (line_number == 2) {	753	} else if (line_number == 2) {
754	#if defined (CONFIG_CHARON)	754	#if defined (CONFIG_CHARON)
755	strcpy (info, " on a CHARON carrier board");	755	strcpy (info, " on a CHARON carrier board");
756	#endif	756	#endif
757	#if defined (CONFIG_STK52XX)	757	#if defined (CONFIG_STK52XX)
758	strcpy (info, " on a STK52xx carrier board");	758	strcpy (info, " on a STK52xx carrier board");
759	#endif	759	#endif
760	#if defined (CONFIG_FO300)	760	#if defined (CONFIG_FO300)
761	strcpy (info, " on a FO300 carrier board");	761	strcpy (info, " on a FO300 carrier board");
762	#endif	762	#endif
763	#endif	763	#endif
764	}	764	}
765	else {	765	else {
766	info [0] = '\0';	766	info [0] = '\0';
767	}	767	}
768	}	768	}
769	#endif	769	#endif
770		770
771	/*	771	/*
772	* Returns SM501 register base address. First thing called in the	772	* Returns SM501 register base address. First thing called in the
773	* driver. Checks if SM501 is physically present.	773	* driver. Checks if SM501 is physically present.
774	*/	774	*/
775	unsigned int board_video_init (void)	775	unsigned int board_video_init (void)
776	{	776	{
777	u16 save, tmp;	777	u16 save, tmp;
778	int restore, ret;	778	int restore, ret;
779		779
780	/*	780	/*
781	* Check for Grafic Controller	781	* Check for Grafic Controller
782	*/	782	*/
783		783
784	/* save origianl FB content */	784	/* save origianl FB content */
785	save = (volatile u16 )CONFIG_SYS_CS1_START;	785	save = (volatile u16 )CONFIG_SYS_CS1_START;
786	restore = 1;	786	restore = 1;
787		787
788	/* write test pattern to FB memory */	788	/* write test pattern to FB memory */
789	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;	789	(volatile u16 )CONFIG_SYS_CS1_START = 0xA5A5;
790	__asm__ volatile ("sync");	790	__asm__ volatile ("sync");
791	/*	791	/*
792	* Put a different pattern on the data lines: otherwise they may float	792	* Put a different pattern on the data lines: otherwise they may float
793	* long enough to read back what we wrote.	793	* long enough to read back what we wrote.
794	*/	794	*/
795	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;	795	tmp = (volatile u16 )CONFIG_SYS_FLASH_BASE;
796	if (tmp == 0xA5A5)	796	if (tmp == 0xA5A5)
797	puts ("!! possible error in grafic controller detection\n");	797	puts ("!! possible error in grafic controller detection\n");
798		798
799	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {	799	if ((volatile u16 )CONFIG_SYS_CS1_START != 0xA5A5) {
800	/* no grafic controller found */	800	/* no grafic controller found */
801	restore = 0;	801	restore = 0;
802	ret = 0;	802	ret = 0;
803	} else {	803	} else {
804	ret = SM501_MMIO_BASE;	804	ret = SM501_MMIO_BASE;
805	}	805	}
806		806
807	if (restore) {	807	if (restore) {
808	(volatile u16 )CONFIG_SYS_CS1_START = save;	808	(volatile u16 )CONFIG_SYS_CS1_START = save;
809	__asm__ volatile ("sync");	809	__asm__ volatile ("sync");
810	}	810	}
811	return ret;	811	return ret;
812	}	812	}
813		813
814	/*	814	/*
815	* Returns SM501 framebuffer address	815	* Returns SM501 framebuffer address
816	*/	816	*/
817	unsigned int board_video_get_fb (void)	817	unsigned int board_video_get_fb (void)
818	{	818	{
819	return SM501_FB_BASE;	819	return SM501_FB_BASE;
820	}	820	}
821		821
822	/*	822	/*
823	* Called after initializing the SM501 and before clearing the screen.	823	* Called after initializing the SM501 and before clearing the screen.
824	*/	824	*/
825	void board_validate_screen (unsigned int base)	825	void board_validate_screen (unsigned int base)
826	{	826	{
827	}	827	}
828		828
829	/*	829	/*
830	* Return a pointer to the initialization sequence.	830	* Return a pointer to the initialization sequence.
831	*/	831	*/
832	const SMI_REGS *board_get_regs (void)	832	const SMI_REGS *board_get_regs (void)
833	{	833	{
834	return init_regs;	834	return init_regs;
835	}	835	}
836		836
837	int board_get_width (void)	837	int board_get_width (void)
838	{	838	{
839	return DISPLAY_WIDTH;	839	return DISPLAY_WIDTH;
840	}	840	}
841		841
842	int board_get_height (void)	842	int board_get_height (void)
843	{	843	{
844	return DISPLAY_HEIGHT;	844	return DISPLAY_HEIGHT;
845	}	845	}
846		846
847	#endif /* CONFIG_VIDEO_SM501 */	847	#endif /* CONFIG_VIDEO_SM501 */
848		848
849	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)	849	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
850	int ft_board_setup(void blob, bd_t bd)	850	int ft_board_setup(void blob, bd_t bd)
851	{	851	{
852	ft_cpu_setup(blob, bd);	852	ft_cpu_setup(blob, bd);
853	#if defined(CONFIG_VIDEO)	853	#if defined(CONFIG_VIDEO)
854	fdt_add_edid(blob, "smi,sm501", edid_buf);	854	fdt_add_edid(blob, "smi,sm501", edid_buf);
855	#endif	855	#endif
856		856
857	return 0;	857	return 0;
858	}	858	}
859	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */	859	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
860		860
861	#if defined(CONFIG_RESET_PHY_R)	861	#if defined(CONFIG_RESET_PHY_R)
862	#include <miiphy.h>	862	#include <miiphy.h>
863		863
864	void reset_phy(void)	864	void reset_phy(void)
865	{	865	{
866	/* init Micrel KSZ8993 PHY */	866	/* init Micrel KSZ8993 PHY */
867	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);	867	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
868	}	868	}
869	#endif	869	#endif
870		870
871	int board_eth_init(bd_t *bis)	871	int board_eth_init(bd_t *bis)
872	{	872	{
873	cpu_eth_init(bis); /* Built in FEC comes first */	873	cpu_eth_init(bis); /* Built in FEC comes first */
874	return pci_eth_init(bis);	874	return pci_eth_init(bis);
875	}	875	}
876		876

board/v38b/v38b.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2003-2006	2	* (C) Copyright 2003-2006
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2004	5	* (C) Copyright 2004
6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <mpc5xxx.h>	12	#include <mpc5xxx.h>
13	#include <net.h>	13	#include <net.h>
14	#include <asm/processor.h>	14	#include <asm/processor.h>
15		15
16	DECLARE_GLOBAL_DATA_PTR;	16	DECLARE_GLOBAL_DATA_PTR;
17		17
18	#ifndef CONFIG_SYS_RAMBOOT	18	#ifndef CONFIG_SYS_RAMBOOT
19	static void sdram_start(int hi_addr)	19	static void sdram_start(int hi_addr)
20	{	20	{
21	long hi_addr_bit = hi_addr ? 0x01000000 : 0;	21	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
22		22
23	/* unlock mode register */	23	/* unlock mode register */
24	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;	24	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
25	__asm__ volatile ("sync");	25	__asm__ volatile ("sync");
26		26
27	/* precharge all banks */	27	/* precharge all banks */
28	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;	28	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
29	__asm__ volatile ("sync");	29	__asm__ volatile ("sync");
30		30
31	#if SDRAM_DDR	31	#if SDRAM_DDR
32	/* set mode register: extended mode */	32	/* set mode register: extended mode */
33	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;	33	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
34	__asm__ volatile ("sync");	34	__asm__ volatile ("sync");
35		35
36	/* set mode register: reset DLL */	36	/* set mode register: reset DLL */
37	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;	37	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
38	__asm__ volatile ("sync");	38	__asm__ volatile ("sync");
39	#endif /* SDRAM_DDR */	39	#endif /* SDRAM_DDR */
40		40
41	/* precharge all banks */	41	/* precharge all banks */
42	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;	42	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
43	__asm__ volatile ("sync");	43	__asm__ volatile ("sync");
44		44
45	/* auto refresh */	45	/* auto refresh */
46	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;	46	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
47	__asm__ volatile ("sync");	47	__asm__ volatile ("sync");
48		48
49	/* set mode register */	49	/* set mode register */
50	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;	50	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
51	__asm__ volatile ("sync");	51	__asm__ volatile ("sync");
52		52
53	/* normal operation */	53	/* normal operation */
54	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;	54	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
55	__asm__ volatile ("sync");	55	__asm__ volatile ("sync");
56	}	56	}
57	#endif /* !CONFIG_SYS_RAMBOOT */	57	#endif /* !CONFIG_SYS_RAMBOOT */
58		58
59		59
60	int dram_init(void)	60	int dram_init(void)
61	{	61	{
62	ulong dramsize = 0;	62	ulong dramsize = 0;
63	ulong dramsize2 = 0;	63	ulong dramsize2 = 0;
64	uint svr, pvr;	64	uint svr, pvr;
65		65
66	#ifndef CONFIG_SYS_RAMBOOT	66	#ifndef CONFIG_SYS_RAMBOOT
67	ulong test1, test2;	67	ulong test1, test2;
68		68
69	/* setup SDRAM chip selects */	69	/* setup SDRAM chip selects */
70	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */	70	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
71	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */	71	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
72	__asm__ volatile ("sync");	72	__asm__ volatile ("sync");
73		73
74	/* setup config registers */	74	/* setup config registers */
75	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;	75	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
76	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;	76	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
77	__asm__ volatile ("sync");	77	__asm__ volatile ("sync");
78		78
79	#if SDRAM_DDR	79	#if SDRAM_DDR
80	/* set tap delay */	80	/* set tap delay */
81	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;	81	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
82	__asm__ volatile ("sync");	82	__asm__ volatile ("sync");
83	#endif /* SDRAM_DDR */	83	#endif /* SDRAM_DDR */
84		84
85	/* find RAM size using SDRAM CS0 only */	85	/* find RAM size using SDRAM CS0 only */
86	sdram_start(0);	86	sdram_start(0);
87	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);	87	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
88	sdram_start(1);	88	sdram_start(1);
89	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);	89	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
90	if (test1 > test2) {	90	if (test1 > test2) {
91	sdram_start(0);	91	sdram_start(0);
92	dramsize = test1;	92	dramsize = test1;
93	} else	93	} else
94	dramsize = test2;	94	dramsize = test2;
95		95
96	/* memory smaller than 1MB is impossible */	96	/* memory smaller than 1MB is impossible */
97	if (dramsize < (1 << 20))	97	if (dramsize < (1 << 20))
98	dramsize = 0;	98	dramsize = 0;
99		99
100	/* set SDRAM CS0 size according to the amount of RAM found */	100	/* set SDRAM CS0 size according to the amount of RAM found */
101	if (dramsize > 0)	101	if (dramsize > 0)
102	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;	102	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
103	else	103	else
104	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */	104	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
105		105
106	/* let SDRAM CS1 start right after CS0 */	106	/* let SDRAM CS1 start right after CS0 */
107	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */	107	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
108		108
109	/* find RAM size using SDRAM CS1 only */	109	/* find RAM size using SDRAM CS1 only */
110	if (!dramsize)	110	if (!dramsize)
111	sdram_start(0);	111	sdram_start(0);
112	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);	112	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
113	if (!dramsize) {	113	if (!dramsize) {
114	sdram_start(1);	114	sdram_start(1);
115	test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);	115	test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
116	}	116	}
117	if (test1 > test2) {	117	if (test1 > test2) {
118	sdram_start(0);	118	sdram_start(0);
119	dramsize2 = test1;	119	dramsize2 = test1;
120	} else	120	} else
121	dramsize2 = test2;	121	dramsize2 = test2;
122		122
123	/* memory smaller than 1MB is impossible */	123	/* memory smaller than 1MB is impossible */
124	if (dramsize2 < (1 << 20))	124	if (dramsize2 < (1 << 20))
125	dramsize2 = 0;	125	dramsize2 = 0;
126		126
127	/* set SDRAM CS1 size according to the amount of RAM found */	127	/* set SDRAM CS1 size according to the amount of RAM found */
128	if (dramsize2 > 0)	128	if (dramsize2 > 0)
129	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize	129	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize
130	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);	130	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
131	else	131	else
132	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */	132	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
133		133
134	#else /* CONFIG_SYS_RAMBOOT */	134	#else /* CONFIG_SYS_RAMBOOT */
135		135
136	/* retrieve size of memory connected to SDRAM CS0 */	136	/* retrieve size of memory connected to SDRAM CS0 */
137	dramsize = (vu_long ) MPC5XXX_SDRAM_CS0CFG & 0xFF;	137	dramsize = (vu_long ) MPC5XXX_SDRAM_CS0CFG & 0xFF;
138	if (dramsize >= 0x13)	138	if (dramsize >= 0x13)
139	dramsize = (1 << (dramsize - 0x13)) << 20;	139	dramsize = (1 << (dramsize - 0x13)) << 20;
140	else	140	else
141	dramsize = 0;	141	dramsize = 0;
142		142
143	/* retrieve size of memory connected to SDRAM CS1 */	143	/* retrieve size of memory connected to SDRAM CS1 */
144	dramsize2 = (vu_long ) MPC5XXX_SDRAM_CS1CFG & 0xFF;	144	dramsize2 = (vu_long ) MPC5XXX_SDRAM_CS1CFG & 0xFF;
145	if (dramsize2 >= 0x13)	145	if (dramsize2 >= 0x13)
146	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;	146	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
147	else	147	else
148	dramsize2 = 0;	148	dramsize2 = 0;
149		149
150	#endif /* CONFIG_SYS_RAMBOOT */	150	#endif /* CONFIG_SYS_RAMBOOT */
151		151
152	/*	152	/*
153	* On MPC5200B we need to set the special configuration delay in the	153	* On MPC5200B we need to set the special configuration delay in the
154	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM	154	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
155	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:	155	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
156	*	156	*
157	* "The SDelay should be written to a value of 0x00000004. It is	157	* "The SDelay should be written to a value of 0x00000004. It is
158	* required to account for changes caused by normal wafer processing	158	* required to account for changes caused by normal wafer processing
159	* parameters."	159	* parameters."
160	*/	160	*/
161	svr = get_svr();	161	svr = get_svr();
162	pvr = get_pvr();	162	pvr = get_pvr();
163	if ((SVR_MJREV(svr) >= 2) &&	163	if ((SVR_MJREV(svr) >= 2) &&
164	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {	164	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
165		165
166	(vu_long ) MPC5XXX_SDRAM_SDELAY = 0x04;	166	(vu_long ) MPC5XXX_SDRAM_SDELAY = 0x04;
167	__asm__ volatile ("sync");	167	__asm__ volatile ("sync");
168	}	168	}
169		169
170	gd->ram_size = dramsize + dramsize2;	170	gd->ram_size = dramsize + dramsize2;
171		171
172	return 0;	172	return 0;
173	}	173	}
174		174
175		175
176	int checkboard (void)	176	int checkboard (void)
177	{	177	{
178	puts("Board: MarelV38B\n");	178	puts("Board: MarelV38B\n");
179	return 0;	179	return 0;
180	}	180	}
181		181
182	int board_early_init_f(void)	182	int board_early_init_f(void)
183	{	183	{
184	#ifdef CONFIG_HW_WATCHDOG	184	#ifdef CONFIG_HW_WATCHDOG
185	/*	185	/*
186	* Enable and configure the direction (output) of PSC3_9 - watchdog	186	* Enable and configure the direction (output) of PSC3_9 - watchdog
187	* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's	187	* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
188	* Manual.	188	* Manual.
189	*/	189	*/
190	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC3_9;	190	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC3_9;
191	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC3_9;	191	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC3_9;
192	#endif /* CONFIG_HW_WATCHDOG */	192	#endif /* CONFIG_HW_WATCHDOG */
193	return 0;	193	return 0;
194	}	194	}
195		195
196	int board_early_init_r(void)	196	int board_early_init_r(void)
197	{	197	{
198	/*	198	/*
199	* Now, when we are in RAM, enable flash write access for the	199	* Now, when we are in RAM, enable flash write access for the
200	* detection process. Note that CS_BOOT cannot be cleared when	200	* detection process. Note that CS_BOOT cannot be cleared when
201	* executing in flash.	201	* executing in flash.
202	*/	202	*/
203	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */	203	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
204		204
205	/*	205	/*
206	* Enable GPIO_WKUP_7 to "read the status of the actual power	206	* Enable GPIO_WKUP_7 to "read the status of the actual power
207	* situation". Default direction is input, so no need to set it	207	* situation". Default direction is input, so no need to set it
208	* explicitly.	208	* explicitly.
209	*/	209	*/
210	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WKUP_7;	210	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WKUP_7;
211	return 0;	211	return 0;
212	}	212	}
213		213
214	extern void board_get_enetaddr(uchar *enetaddr);	214	extern void board_get_enetaddr(uchar *enetaddr);
215	int misc_init_r(void)	215	int misc_init_r(void)
216	{	216	{
217	uchar enetaddr[6];	217	uchar enetaddr[6];
218		218
219	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {	219	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
220	board_get_enetaddr(enetaddr);	220	board_get_enetaddr(enetaddr);
221	eth_setenv_enetaddr("ethaddr", enetaddr);	221	eth_setenv_enetaddr("ethaddr", enetaddr);
222	}	222	}
223		223
224	return 0;	224	return 0;
225	}	225	}
226		226
227	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)	227	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
228	void init_ide_reset(void)	228	void init_ide_reset(void)
229	{	229	{
230	debug("init_ide_reset\n");	230	debug("init_ide_reset\n");
231		231
232	/* Configure PSC1_4 as GPIO output for ATA reset */	232	/* Configure PSC1_4 as GPIO output for ATA reset */
233	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;	233	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
234	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;	234	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
235	/* Deassert reset */	235	/* Deassert reset */
236	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	236	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
237	}	237	}
238		238
239		239
240	void ide_set_reset(int idereset)	240	void ide_set_reset(int idereset)
241	{	241	{
242	debug("ide_reset(%d)\n", idereset);	242	debug("ide_reset(%d)\n", idereset);
243		243
244	if (idereset) {	244	if (idereset) {
245	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;	245	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
246	/* Make a delay. MPC5200 spec says 25 usec min */	246	/* Make a delay. MPC5200 spec says 25 usec min */
247	udelay(500000);	247	udelay(500000);
248	} else	248	} else
249	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;	249	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
250	}	250	}
251	#endif	251	#endif
252		252
253		253
254	#ifdef CONFIG_HW_WATCHDOG	254	#ifdef CONFIG_HW_WATCHDOG
255	void hw_watchdog_reset(void)	255	void hw_watchdog_reset(void)
256	{	256	{
257	/*	257	/*
258	* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog	258	* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
259	* we need a positive or negative transition on WDI i.e., our PSC3_9.	259	* we need a positive or negative transition on WDI i.e., our PSC3_9.
260	*/	260	*/
261	(vu_long ) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;	261	(vu_long ) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
262	}	262	}
263	#endif /* CONFIG_HW_WATCHDOG */	263	#endif /* CONFIG_HW_WATCHDOG */
264		264

cmd/Kconfig

Diff comments View file @ fc843a0

 menu "Command line interface"
 config CMDLINE
 	bool "Support U-Boot commands"
 	default y
 	help
 	  Enable U-Boot's command-line functions. This provides a means
 	  to enter commands into U-Boot for a wide variety of purposes. It
 	  also allows scripts (containing commands) to be executed.
 	  Various commands and command categorys can be indivdually enabled.
 	  Depending on the number of commands enabled, this can add
 	  substantially to the size of U-Boot.
 config HUSH_PARSER
 	bool "Use hush shell"
 	depends on CMDLINE
 	help
 	  This option enables the "hush" shell (from Busybox) as command line
 	  interpreter, thus enabling powerful command line syntax like
 	  if...then...else...fi conditionals or `&&' and '||'
 	  constructs ("shell scripts").
 	  If disabled, you get the old, much simpler behaviour with a somewhat
 	  smaller memory footprint.
 config SYS_PROMPT
 	string "Shell prompt"
 	default "=> "
 	help
 	  This string is displayed in the command line to the left of the
 	  cursor.
 menu "Autoboot options"
 config AUTOBOOT
 	bool "Autoboot"
 	default y
 	help
 	  This enables the autoboot.  See doc/README.autoboot for detail.
 config AUTOBOOT_KEYED
 	bool "Stop autobooting via specific input key / string"
 	default n
 	help
 	  This option enables stopping (aborting) of the automatic
 	  boot feature only by issuing a specific input key or
 	  string. If not enabled, any input key will abort the
 	  U-Boot automatic booting process and bring the device
 	  to the U-Boot prompt for user input.
 config AUTOBOOT_PROMPT
 	string "Autoboot stop prompt"
 	depends on AUTOBOOT_KEYED
 	default "Autoboot in %d seconds\\n"
 	help
 	  This string is displayed before the boot delay selected by
 	  CONFIG_BOOTDELAY starts. If it is not defined	there is no
 	  output indicating that autoboot is in progress.
 	  Note that this define is used as the (only) argument to a
 	  printf() call, so it may contain '%' format specifications,
 	  provided that it also includes, sepearated by commas exactly
 	  like in a printf statement, the required arguments. It is
 	  the responsibility of the user to select only such arguments
 	  that are valid in the given context.
 config AUTOBOOT_ENCRYPTION
 	bool "Enable encryption in autoboot stopping"
 	depends on AUTOBOOT_KEYED
 	default n
 config AUTOBOOT_DELAY_STR
 	string "Delay autobooting via specific input key / string"
 	depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
 	help
 	  This option delays the automatic boot feature by issuing
 	  a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR
 	  or the environment variable "bootdelaykey" is specified
 	  and this string is received from console input before
 	  autoboot starts booting, U-Boot gives a command prompt. The
 	  U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is
 	  used, otherwise it never times out.
 config AUTOBOOT_STOP_STR
 	string "Stop autobooting via specific input key / string"
 	depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
 	help
 	  This option enables stopping (aborting) of the automatic
 	  boot feature only by issuing a specific input key or
 	  string. If CONFIG_AUTOBOOT_STOP_STR or the environment
 	  variable "bootstopkey" is specified and this string is
 	  received from console input before autoboot starts booting,
 	  U-Boot gives a command prompt. The U-Boot prompt never
 	  times out, even if CONFIG_BOOT_RETRY_TIME is used.
 config AUTOBOOT_KEYED_CTRLC
 	bool "Enable Ctrl-C autoboot interruption"
 	depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
 	default n
 	help
 	  This option allows for the boot sequence to be interrupted
 	  by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
 	  Setting this variable	provides an escape sequence from the
 	  limited "password" strings.
 config AUTOBOOT_STOP_STR_SHA256
 	string "Stop autobooting via SHA256 encrypted password"
 	depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
 	help
 	  This option adds the feature to only stop the autobooting,
 	  and therefore boot into the U-Boot prompt, when the input
 	  string / password matches a values that is encypted via
 	  a SHA256 hash and saved in the environment.
 endmenu
 source "cmd/fastboot/Kconfig"
 comment "Commands"
 menu "Info commands"
 config CMD_BDI
 	bool "bdinfo"
 	default y
 	help
 	  Print board info
 config CMD_CONFIG
 	bool "config"
 	select BUILD_BIN2C
 	default SANDBOX
 	help
 	  Print ".config" contents.
 	  If this option is enabled, the ".config" file contents are embedded
 	  in the U-Boot image and can be printed on the console by the "config"
 	  command.  This provides information of which options are enabled on
 	  the running U-Boot.
 config CMD_CONSOLE
 	bool "coninfo"
 	default y
 	help
 	  Print console devices and information.
 config CMD_CPU
 	bool "cpu"
 	help
 	  Print information about available CPUs. This normally shows the
 	  number of CPUs, type (e.g. manufacturer, architecture, product or
 	  internal name) and clock frequency. Other information may be
 	  available depending on the CPU driver.
 config CMD_LICENSE
 	bool "license"
 	select BUILD_BIN2C
 	help
 	  Print GPL license text
 endmenu
 menu "Boot commands"
 config CMD_BOOTD
 	bool "bootd"
 	default y
 	help
 	  Run the command stored in the environment "bootcmd", i.e.
 	  "bootd" does the same thing as "run bootcmd".
 config CMD_BOOTM
 	bool "bootm"
 	default y
 	help
 	  Boot an application image from the memory.
 config CMD_BOOTZ
 	bool "bootz"
 	help
 	  Boot the Linux zImage
 config CMD_BOOTI
 	bool "booti"
 	depends on ARM64
 	default y
 	help
 	  Boot an AArch64 Linux Kernel image from memory.
 config CMD_BOOTEFI
 	bool "bootefi"
 	depends on EFI_LOADER
 	default y
 	help
 	  Boot an EFI image from memory.
 config CMD_BOOTEFI_HELLO_COMPILE
 	bool "Compile a standard EFI hello world binary for testing"
 	depends on CMD_BOOTEFI && (ARM || X86)
 	default y
 	help
 	  This compiles a standard EFI hello world application with U-Boot so
 	  that it can be used with the test/py testing framework. This is useful
 	  for testing that EFI is working at a basic level, and for bringing
 	  up EFI support on a new architecture.
 	  No additional space will be required in the resulting U-Boot binary
 	  when this option is enabled.
 config CMD_BOOTEFI_HELLO
 	bool "Allow booting a standard EFI hello world for testing"
 	depends on CMD_BOOTEFI_HELLO_COMPILE
 	help
 	  This adds a standard EFI hello world application to U-Boot so that
 	  it can be used with the 'bootefi hello' command. This is useful
 	  for testing that EFI is working at a basic level, and for bringing
 	  up EFI support on a new architecture.
 config CMD_BOOTMENU
 	bool "bootmenu"
 	select MENU
 	help
 	  Add an ANSI terminal boot menu command.
 config CMD_ELF
 	bool "bootelf, bootvx"
 	default y
 	help
 	  Boot an ELF/vxWorks image from the memory.
 config CMD_FDT
 	bool "Flattened Device Tree utility commands"
 	default y
 	depends on OF_LIBFDT
 	help
 	  Do FDT related setup before booting into the Operating System.
 config CMD_GO
 	bool "go"
 	default y
 	help
 	  Start an application at a given address.
 config CMD_RUN
 	bool "run"
 	default y
 	help
 	  Run the command in the given environment variable.
 config CMD_IMI
 	bool "iminfo"
 	default y
 	help
 	  Print header information for application image.
 config CMD_IMLS
 	bool "imls"
 	default y
 	help
 	  List all images found in flash
 config CMD_XIMG
 	bool "imxtract"
 	default y
 	help
 	  Extract a part of a multi-image.
 config CMD_POWEROFF
 	bool
 endmenu
 menu "Environment commands"
 config CMD_ASKENV
 	bool "ask for env variable"
 	help
 	  Ask for environment variable
 config CMD_EXPORTENV
 	bool "env export"
 	default y
 	help
 	  Export environments.
 config CMD_IMPORTENV
 	bool "env import"
 	default y
 	help
 	  Import environments.
 config CMD_EDITENV
 	bool "editenv"
 	default y
 	help
 	  Edit environment variable.
 config CMD_GREPENV
 	bool "search env"
 	help
 	  Allow for searching environment variables
 config CMD_SAVEENV
 	bool "saveenv"
 	default y
 	help
 	  Save all environment variables into the compiled-in persistent
 	  storage.
 config CMD_ENV_EXISTS
 	bool "env exists"
 	default y
 	help
 	  Check if a variable is defined in the environment for use in
 	  shell scripting.
 config CMD_ENV_CALLBACK
 	bool "env callbacks - print callbacks and their associated variables"
 	help
 	  Some environment variable have callbacks defined by
 	  U_BOOT_ENV_CALLBACK. These are called when the variable changes.
 	  For example changing "baudrate" adjust the serial baud rate. This
 	  command lists the currently defined callbacks.
 config CMD_ENV_FLAGS
 	bool "env flags -print variables that have non-default flags"
 	help
 	  Some environment variables have special flags that control their
 	  behaviour. For example, serial# can only be written once and cannot
 	  be deleted. This command shows the variables that have special
 	  flags.
 endmenu
 menu "Memory commands"
 config CMD_MEMORY
 	bool "md, mm, nm, mw, cp, cmp, base, loop"
 	default y
 	help
 	  Memory commands.
 	    md - memory display
 	    mm - memory modify (auto-incrementing address)
 	    nm - memory modify (constant address)
 	    mw - memory write (fill)
 	    cp - memory copy
 	    cmp - memory compare
 	    base - print or set address offset
 	    loop - initialize loop on address range
 config CMD_CRC32
 	bool "crc32"
 	select HASH
 	default y
 	help
 	  Compute CRC32.
 config CMD_EEPROM
 	bool "eeprom - EEPROM subsystem"
 	help
 	  (deprecated, needs conversion to driver model)
 	  Provides commands to read and write EEPROM (Electrically Erasable
 	  Programmable Read Only Memory) chips that are connected over an
 	  I2C bus.
 config CMD_EEPROM_LAYOUT
 	bool "Enable layout-aware eeprom commands"
 	depends on CMD_EEPROM
 	help
 	  (deprecated, needs conversion to driver model)
 	  When enabled, additional eeprom sub-commands become available.
 	  eeprom print - prints the contents of the eeprom in a human-readable
 	  way (eeprom layout fields, and data formatted to be fit for human
 	  consumption).
 	  eeprom update - allows user to update eeprom fields by specifying
 	  the field name, and providing the new data in a human readable format
 	  (same format as displayed by the eeprom print command).
 	  Both commands can either auto detect the layout, or be told which
 	  layout to use.
 	  Feature API:
 	  __weak int parse_layout_version(char *str)
 		- override to provide your own layout name parsing
 	  __weak void __eeprom_layout_assign(struct eeprom_layout *layout,
 			int layout_version);
 		- override to setup the layout metadata based on the version
 	  __weak int eeprom_layout_detect(unsigned char *data)
 		- override to provide your own algorithm for detecting layout
 			version
 	  eeprom_field.c
 		- contains various printing and updating functions for common
 			types of eeprom fields. Can be used for defining
 			custom layouts.
 config EEPROM_LAYOUT_HELP_STRING
 	  string "Tells user what layout names are supported"
 	  depends on CMD_EEPROM_LAYOUT
 	  default "<not defined>"
 	  help
 	    Help printed with the LAYOUT VERSIONS part of the 'eeprom'
 	    command's help.
 config CMD_MD5SUM
 	bool "md5sum"
 	default n
 	select MD5
 	help
 	  Compute MD5 checksum.
 config MD5SUM_VERFIY
 	bool "md5sum -v"
 	default n
 	depends on CMD_MD5SUM
 	help
 	  Add -v option to verify data against an MD5 checksum.
 config LOOPW
 	bool "loopw"
 	help
 	  Infinite write loop on address range
 config CMD_MEMTEST
 	bool "memtest"
 	help
 	  Simple RAM read/write test.
 config CMD_MX_CYCLIC
 	bool "mdc, mwc"
 	help
 	  mdc - memory display cyclic
 	  mwc - memory write cyclic
 config CMD_MEMINFO
 	bool "meminfo"
 	help
 	  Display memory information.
 config CMD_UNZIP
 	bool "unzip"
 	help
 	  Uncompress a zip-compressed memory region.
 config CMD_ZIP
 	bool "zip"
 	help
 	  Compress a memory region with zlib deflate method.
 endmenu
 menu "Device access commands"
 config CMD_CLK
 	bool "clk - Show clock frequencies"
 	help
 	  (deprecated)
 	  Shows clock frequences by calling a sock_clk_dump() hook function.
 	  This is depreated in favour of using the CLK uclass and accessing
 	  clock values from associated drivers. However currently no command
 	  exists for this.
 config CMD_DM
 	bool "dm - Access to driver model information"
 	depends on DM
 	default y
 	help
 	  Provides access to driver model data structures and information,
 	  such as a list of devices, list of uclasses and the state of each
 	  device (e.g. activated). This is not required for operation, but
 	  can be useful to see the state of driver model for debugging or
 	  interest.
 config CMD_DEMO
 	bool "demo - Demonstration commands for driver model"
 	depends on DM
 	help
 	  Provides a 'demo' command which can be used to play around with
 	  driver model. To use this properly you will need to enable one or
 	  both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE).
 	  Otherwise you will always get an empty list of devices. The demo
 	  devices are defined in the sandbox device tree, so the easiest
 	  option is to use sandbox and pass the -d point to sandbox's
 	  u-boot.dtb file.
 config CMD_IDE
 	bool "ide - Support for IDE drivers"
+	select IDE
 	help
 	  Provides an 'ide' command which allows accessing the IDE drive,
 	  reseting the IDE interface, printing the partition table and
 	  geting device info. It also enables the 'diskboot' command which
 	  permits booting from an IDE drive.
 config CMD_LOADB
 	bool "loadb"
 	default y
 	help
 	  Load a binary file over serial line.
 config CMD_LOADS
 	bool "loads"
 	default y
 	help
 	  Load an S-Record file over serial line
 config CMD_FLASH
 	bool "flinfo, erase, protect"
 	default y
 	help
 	  NOR flash support.
 	    flinfo - print FLASH memory information
 	    erase - FLASH memory
 	    protect - enable or disable FLASH write protection
 config CMD_GPT
 	bool "GPT (GUID Partition Table) command"
 	select PARTITION_UUIDS
 	select EFI_PARTITION
 	help
 	  Enable the 'gpt' command to ready and write GPT style partition
 	  tables.
 config CMD_ARMFLASH
 	#depends on FLASH_CFI_DRIVER
 	bool "armflash"
 	help
 	  ARM Ltd reference designs flash partition access
 config CMD_MMC
 	bool "mmc"
 	help
 	  MMC memory mapped support.
 config CMD_NAND
 	bool "nand"
 	default y if NAND_SUNXI
 	help
 	  NAND support.
 if CMD_NAND
 config CMD_NAND_TRIMFFS
 	bool "nand write.trimffs"
 	default y if ARCH_SUNXI
 	help
 	  Allows one to skip empty pages when flashing something on a NAND.
 config CMD_NAND_LOCK_UNLOCK
 	bool "nand lock/unlock"
 	help
 	  NAND locking support.
 config CMD_NAND_TORTURE
 	bool "nand torture"
 	help
 	  NAND torture support.
 endif # CMD_NAND
 config CMD_PART
 	bool "part"
 	select PARTITION_UUIDS
 	help
 	  Read and display information about the partition table on
 	  various media.
 config CMD_SF
 	bool "sf"
 	help
 	  SPI Flash support
 config CMD_SPI
 	bool "sspi"
 	help
 	  SPI utility command.
 config CMD_I2C
 	bool "i2c"
 	help
 	  I2C support.
 config CMD_USB
 	bool "usb"
 	help
 	  USB support.
 config CMD_DFU
 	bool "dfu"
 	select USB_FUNCTION_DFU
 	help
 	  Enables the command "dfu" which is used to have U-Boot create a DFU
 	  class device via USB.
 config CMD_USB_MASS_STORAGE
 	bool "UMS usb mass storage"
 	help
 	  USB mass storage support
 config CMD_FPGA
 	bool "fpga"
 	default y
 	help
 	  FPGA support.
 config CMD_FPGA_LOADBP
 	bool "fpga loadbp - load partial bitstream (Xilinx only)"
 	depends on CMD_FPGA
 	help
 	  Supports loading an FPGA device from a bitstream buffer containing
 	  a partial bitstream.
 config CMD_FPGA_LOADFS
 	bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)"
 	depends on CMD_FPGA
 	help
 	  Supports loading an FPGA device from a FAT filesystem.
 config CMD_FPGA_LOADMK
 	bool "fpga loadmk - load bitstream from image"
 	depends on CMD_FPGA
 	help
 	  Supports loading an FPGA device from a image generated by mkimage.
 config CMD_FPGA_LOADP
 	bool "fpga loadp - load partial bitstream"
 	depends on CMD_FPGA
 	help
 	  Supports loading an FPGA device from a bitstream buffer containing
 	  a partial bitstream.
 config CMD_FPGAD
 	bool "fpgad - dump FPGA registers"
 	help
 	  (legacy, needs conversion to driver model)
 	  Provides a way to dump FPGA registers by calling the board-specific
 	  fpga_get_reg() function. This functions similarly to the 'md'
 	  command.
 config CMD_FUSE
 	bool "fuse - support for the fuse subssystem"
 	help
 	  (deprecated - needs conversion to driver model)
 	  This allows reading, sensing, programming or overriding fuses
 	  which control the behaviour of the device. The command uses the
 	  fuse_...() API.
 config CMD_REMOTEPROC
 	bool "remoteproc"
 	depends on REMOTEPROC
 	help
 	  Support for Remote Processor control
 config CMD_GPIO
 	bool "gpio"
 	help
 	  GPIO support.
 config CMD_FDC
 	bool "fdcboot - Boot from floppy device"
 	help
 	  The 'fdtboot' command allows booting an image from a floppy disk.
 endmenu
 menu "Shell scripting commands"
 config CMD_ECHO
 	bool "echo"
 	default y
 	help
 	  Echo args to console
 config CMD_ITEST
 	bool "itest"
 	default y
 	help
 	  Return true/false on integer compare.
 config CMD_SOURCE
 	bool "source"
 	default y
 	help
 	  Run script from memory
 config CMD_SETEXPR
 	bool "setexpr"
 	default y
 	help
 	  Evaluate boolean and math expressions and store the result in an env
 	    variable.
 	  Also supports loading the value at a memory location into a variable.
 	  If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
 endmenu
 menu "Network commands"
 config CMD_NET
 	bool "bootp, tftpboot"
         select NET
 	default y
 	help
 	  Network commands.
 	  bootp - boot image via network using BOOTP/TFTP protocol
 	  tftpboot - boot image via network using TFTP protocol
 config CMD_TFTPPUT
 	bool "tftp put"
 	help
 	  TFTP put command, for uploading files to a server
 config CMD_TFTPSRV
 	bool "tftpsrv"
 	help
 	  Act as a TFTP server and boot the first received file
 config CMD_RARP
 	bool "rarpboot"
 	help
 	  Boot image via network using RARP/TFTP protocol
 config CMD_DHCP
 	bool "dhcp"
 	help
 	  Boot image via network using DHCP/TFTP protocol
 config CMD_PXE
 	bool "pxe"
 	select MENU
 	help
 	  Boot image via network using PXE protocol
 config CMD_NFS
 	bool "nfs"
 	default y
 	help
 	  Boot image via network using NFS protocol.
 config CMD_MII
 	bool "mii"
 	help
 	  Enable MII utility commands.
 config CMD_PING
 	bool "ping"
 	help
 	  Send ICMP ECHO_REQUEST to network host
 config CMD_CDP
 	bool "cdp"
 	help
 	  Perform CDP network configuration
 config CMD_SNTP
 	bool "sntp"
 	help
 	  Synchronize RTC via network
 config CMD_DNS
 	bool "dns"
 	help
 	  Lookup the IP of a hostname
 config CMD_LINK_LOCAL
 	bool "linklocal"
 	help
 	  Acquire a network IP address using the link-local protocol
 config CMD_ETHSW
 	bool "ethsw"
 	help
 	  Allow control of L2 Ethernet switch commands. These are supported
 	  by the vsc9953 Ethernet driver at present. Sub-commands allow
 	  operations such as enabling / disabling a port and
 	  viewing/maintaining the filtering database (FDB)
 endmenu
 menu "Misc commands"
 config CMD_BMP
 	bool "Enable 'bmp' command"
 	depends on LCD || DM_VIDEO || VIDEO
 	help
 	  This provides a way to obtain information about a BMP-format iamge
 	  and to display it. BMP (which presumably stands for BitMaP) is a
 	  file format defined by Microsoft which supports images of various
 	  depths, formats and compression methods. Headers on the file
 	  determine the formats used. This command can be used by first loading
 	  the image into RAM, then using this command to look at it or display
 	  it.
 config CMD_BSP
 	bool "Enable board-specific commands"
 	help
 	  (deprecated: instead, please define a Kconfig option for each command)
 	  Some boards have board-specific commands which are only enabled
 	  during developemnt and need to be turned off for production. This
 	  option provides a way to control this. The commands that are enabled
 	  vary depending on the board.
 config CMD_BKOPS_ENABLE
 	bool "mmc bkops enable"
 	depends on CMD_MMC
 	default n
 	help
 	  Enable command for setting manual background operations handshake
 	  on a eMMC device. The feature is optionally available on eMMC devices
 	  conforming to standard >= 4.41.
 config CMD_BLOCK_CACHE
 	bool "blkcache - control and stats for block cache"
 	depends on BLOCK_CACHE
 	default y if BLOCK_CACHE
 	help
 	  Enable the blkcache command, which can be used to control the
 	  operation of the cache functions.
 	  This is most useful when fine-tuning the operation of the cache
 	  during development, but also allows the cache to be disabled when
 	  it might hurt performance (e.g. when using the ums command).
 config CMD_CACHE
 	bool "icache or dcache"
 	help
 	  Enable the "icache" and "dcache" commands
 config CMD_DISPLAY
 	bool "Enable the 'display' command, for character displays"
 	help
 	  (this needs porting to driver model)
 	  This enables the 'display' command which allows a string to be
 	  displayed on a simple board-specific display. Implement
 	  display_putc() to use it.
 config CMD_LED
 	bool "led"
 	default y if LED
 	help
 	  Enable the 'led' command which allows for control of LEDs supported
 	  by the board. The LEDs can be listed with 'led list' and controlled
 	  with led on/off/togle/blink. Any LED drivers can be controlled with
 	  this command, e.g. led_gpio.
 config CMD_DATE
 	bool "date"
 	default y if DM_RTC
 	help
 	  Enable the 'date' command for getting/setting the time/date in RTC
 	  devices.
 config CMD_TIME
 	bool "time"
 	help
 	  Run commands and summarize execution time.
 config CMD_GETTIME
 	bool "gettime - read elapsed time"
 	help
 	  Enable the 'gettime' command which reads the elapsed time since
 	  U-Boot started running. This shows the time in seconds and
 	  milliseconds. See also the 'bootstage' command which provides more
 	  flexibility for boot timing.
 # TODO: rename to CMD_SLEEP
 config CMD_MISC
 	bool "sleep"
 	default y
 	help
 	  Delay execution for some time
 config CMD_TIMER
 	bool "timer"
 	help
 	  Access the system timer.
 config CMD_SETGETDCR
 	bool "getdcr, setdcr, getidcr, setidcr"
 	depends on 4xx
 	default y
 	help
 	  getdcr - Get an AMCC PPC 4xx DCR's value
 	  setdcr - Set an AMCC PPC 4xx DCR's value
 	  getidcr - Get a register value via indirect DCR addressing
 	  setidcr - Set a register value via indirect DCR addressing
 config CMD_SOUND
 	bool "sound"
 	depends on SOUND
 	help
 	  This provides basic access to the U-Boot's sound support. The main
 	  feature is to play a beep.
 	     sound init   - set up sound system
 	     sound play   - play a sound
 config CMD_QFW
 	bool "qfw"
 	select QFW
 	help
 	  This provides access to the QEMU firmware interface.  The main
 	  feature is to allow easy loading of files passed to qemu-system
 	  via -kernel / -initrd
 source "cmd/mvebu/Kconfig"
 endmenu
 config CMD_BOOTSTAGE
 	bool "Enable the 'bootstage' command"
 	depends on BOOTSTAGE
 	help
 	  Add a 'bootstage' command which supports printing a report
 	  and un/stashing of bootstage data.
 menu "Power commands"
 config CMD_PMIC
 	bool "Enable Driver Model PMIC command"
 	depends on DM_PMIC
 	help
 	  This is the pmic command, based on a driver model pmic's API.
 	  Command features are unchanged:
 	  - list               - list pmic devices
 	  - pmic dev <id>      - show or [set] operating pmic device (NEW)
 	  - pmic dump          - dump registers
 	  - pmic read address  - read byte of register at address
 	  - pmic write address - write byte to register at address
 	  The only one change for this command is 'dev' subcommand.
 config CMD_REGULATOR
 	bool "Enable Driver Model REGULATOR command"
 	depends on DM_REGULATOR
 	help
 	  This command is based on driver model regulator's API.
 	  User interface features:
 	  - list               - list regulator devices
 	  - regulator dev <id> - show or [set] operating regulator device
 	  - regulator info     - print constraints info
 	  - regulator status   - print operating status
 	  - regulator value <val] <-f> - print/[set] voltage value [uV]
 	  - regulator current <val>    - print/[set] current value [uA]
 	  - regulator mode <id>        - print/[set] operating mode id
 	  - regulator enable           - enable the regulator output
 	  - regulator disable          - disable the regulator output
 	  The '-f' (force) option can be used for set the value which exceeds
 	  the limits, which are found in device-tree and are kept in regulator's
 	  uclass platdata structure.
 endmenu
 menu "Security commands"
 config CMD_AES
 	bool "Enable the 'aes' command"
 	select AES
 	help
 	  This provides a means to encrypt and decrypt data using the AES
 	  (Advanced Encryption Standard). This algorithm uses a symetric key
 	  and is widely used as a streaming cipher. Different key lengths are
 	  supported by the algorithm but this command only supports 128 bits
 	  at present.
 config CMD_BLOB
 	bool "Enable the 'blob' command"
 	help
 	  This is used with the Freescale secure boot mechanism.
 	  Freescale's SEC block has built-in Blob Protocol which provides
 	  a method for protecting user-defined data across system power
 	  cycles. SEC block protects data in a data structure called a Blob,
 	  which provides both confidentiality and integrity protection.
 	  Encapsulating data as a blob
 	  Each time that the Blob Protocol is used to protect data, a
 	  different randomly generated key is used to encrypt the data.
 	  This random key is itself encrypted using a key which is derived
 	  from SoC's non-volatile secret key and a 16 bit Key identifier.
 	  The resulting encrypted key along with encrypted data is called a
 	  blob. The non-volatile secure key is available for use only during
 	  secure boot.
 	  During decapsulation, the reverse process is performed to get back
 	  the original data.
 	  Sub-commands:
             blob enc - encapsulating data as a cryptgraphic blob
 	    blob dec - decapsulating cryptgraphic blob to get the data
 	  Syntax:
 	  blob enc src dst len km
 	  Encapsulate and create blob of data $len bytes long
 	  at address $src and store the result at address $dst.
 	  $km is the 16 byte key modifier is also required for
 	  generation/use as key for cryptographic operation. Key
 	  modifier should be 16 byte long.
 	  blob dec src dst len km
 	  Decapsulate the  blob of data at address $src and
 	  store result of $len byte at addr $dst.
 	  $km is the 16 byte key modifier is also required for
 	  generation/use as key for cryptographic operation. Key
 	  modifier should be 16 byte long.
 config CMD_HASH
 	bool "Support 'hash' command"
 	select HASH
 	help
 	  This provides a way to hash data in memory using various supported
 	  algorithms (such as SHA1, MD5, CRC32). The computed digest can be
 	  saved to memory or to an environment variable. It is also possible
 	  to verify a hash against data in memory.
 config CMD_TPM
 	bool "Enable the 'tpm' command"
 	depends on TPM
 	help
 	  This provides a means to talk to a TPM from the command line. A wide
 	  range of commands if provided - see 'tpm help' for details. The
 	  command requires a suitable TPM on your board and the correct driver
 	  must be enabled.
 config CMD_TPM_TEST
 	bool "Enable the 'tpm test' command"
 	depends on CMD_TPM
 	help
 	  This provides a a series of tests to confirm that the TPM is working
 	  correctly. The tests cover initialisation, non-volatile RAM, extend,
 	  global lock and checking that timing is within expectations. The
 	  tests pass correctly on Infineon TPMs but may need to be adjusted
 	  for other devices.
 endmenu
 menu "Firmware commands"
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC
 	default y
 	help
 	  Enable command-line access to the Chrome OS EC (Embedded
 	  Controller). This provides the 'crosec' command which has
 	  a number of sub-commands for performing EC tasks such as
 	  updating its flash, accessing a small saved context area
 	  and talking to the I2C bus behind the EC (if there is one).
 endmenu
 menu "Filesystem commands"
 config CMD_CBFS
 	bool "Enable the 'cbfs' command"
 	depends on FS_CBFS
 	help
 	  Define this to enable support for reading from a Coreboot
 	  filesystem. This is a ROM-based filesystem used for accessing files
 	  on systems that use coreboot as the first boot-loader and then load
 	  U-Boot to actually boot the Operating System. Available commands are
 	  cbfsinit, cbfsinfo, cbfsls and cbfsload.
 config CMD_CRAMFS
 	bool "Enable the 'cramfs' command"
 	depends on FS_CRAMFS
 	help
 	  This provides commands for dealing with CRAMFS (Compressed ROM
 	  filesystem). CRAMFS is useful when space is tight since files are
 	  compressed. Two commands are provided:
 	     cramfsls   - lists files in a cramfs image
 	     cramfsload - loads a file from a cramfs image
 config CMD_EXT2
 	bool "ext2 command support"
 	help
 	  Enables EXT2 FS command
 config CMD_EXT4
 	bool "ext4 command support"
 	help
 	  Enables EXT4 FS command
 config CMD_EXT4_WRITE
 	depends on CMD_EXT4
 	bool "ext4 write command support"
 	help
 	  Enables EXT4 FS write command
 config CMD_FAT
 	bool "FAT command support"
 	help
 	  Support for the FAT fs
 config CMD_FS_GENERIC
 	bool "filesystem commands"
 	help
 	  Enables filesystem commands (e.g. load, ls) that work for multiple
 	  fs types.
 config CMD_FS_UUID
 	bool "fsuuid command"
 	help
 	  Enables fsuuid command for filesystem UUID.
 config CMD_MTDPARTS
 	depends on ARCH_SUNXI
 	bool "MTD partition support"
 	help
 	  MTD partition support
 config MTDIDS_DEFAULT
 	string "Default MTD IDs"
 	depends on CMD_MTDPARTS
 	help
 	  Defines a default MTD ID
 config MTDPARTS_DEFAULT
 	string "Default MTD partition scheme"
 	depends on CMD_MTDPARTS
 	help
 	  Defines a default MTD partitioning scheme in the Linux MTD command
 	  line partitions format
 endmenu
 menu "Debug commands"
 config CMD_BEDBUG
 	bool "bedbug"
 	help
 	  The bedbug (emBEDded deBUGger) command provides debugging features
 	  for some PowerPC processors. For details please see the
 	  docuemntation in doc/README.beddbug
 config CMD_DIAG
 	bool "diag - Board diagnostics"
 	help
 	  This command provides access to board diagnostic tests. These are
 	  called Power-on Self Tests (POST). The command allows listing of
 	  available tests and running either all the tests, or specific tests
 	  identified by name.
 endmenu
 config CMD_UBI
 	tristate "Enable UBI - Unsorted block images commands"
 	select CRC32
 	select MTD_UBI
 	default y if NAND_SUNXI
 	help
 	  UBI is a software layer above MTD layer which admits use of LVM-like
 	  logical volumes on top of MTD devices, hides some complexities of
 	  flash chips like wear and bad blocks and provides some other useful
 	  capabilities. Please, consult the MTD web site for more details
 	  (www.linux-mtd.infradead.org). Activate this option if you want
 	  to use U-Boot UBI commands.
 config CMD_UBIFS
 	tristate "Enable UBIFS - Unsorted block images filesystem commands"
 	depends on CMD_UBI
 	select CRC32
 	select RBTREE if ARCH_SUNXI
 	select LZO if ARCH_SUNXI
 	default y if NAND_SUNXI
 	help
 	  UBIFS is a file system for flash devices which works on top of UBI.
 endmenu

cmd/pcmcia.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2000-2006	2	* (C) Copyright 2000-2006
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*	6	*
7	********************************************************************	7	********************************************************************
8	*	8	*
9	* Lots of code copied from:	9	* Lots of code copied from:
10	*	10	*
11	* m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.	11	* m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
12	* (C) 1999-2000 Magnus Damm <damm@bitsmart.com>	12	* (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
13	*	13	*
14	* "The ExCA standard specifies that socket controllers should provide	14	* "The ExCA standard specifies that socket controllers should provide
15	* two IO and five memory windows per socket, which can be independently	15	* two IO and five memory windows per socket, which can be independently
16	* configured and positioned in the host address space and mapped to	16	* configured and positioned in the host address space and mapped to
17	* arbitrary segments of card address space. " - David A Hinds. 1999	17	* arbitrary segments of card address space. " - David A Hinds. 1999
18	*	18	*
19	* This controller does _not_ meet the ExCA standard.	19	* This controller does _not_ meet the ExCA standard.
20	*	20	*
21	* m8xx pcmcia controller brief info:	21	* m8xx pcmcia controller brief info:
22	* + 8 windows (attrib, mem, i/o)	22	* + 8 windows (attrib, mem, i/o)
23	* + up to two slots (SLOT_A and SLOT_B)	23	* + up to two slots (SLOT_A and SLOT_B)
24	* + inputpins, outputpins, event and mask registers.	24	* + inputpins, outputpins, event and mask registers.
25	* - no offset register. sigh.	25	* - no offset register. sigh.
26	*	26	*
27	* Because of the lacking offset register we must map the whole card.	27	* Because of the lacking offset register we must map the whole card.
28	* We assign each memory window PCMCIA_MEM_WIN_SIZE address space.	28	* We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
29	* Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO	29	* Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
30	* * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.	30	* * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
31	* The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.	31	* The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
32	* They are maximum 64KByte each...	32	* They are maximum 64KByte each...
33	*/	33	*/
34		34
35	/* #define DEBUG 1 */	35	/* #define DEBUG 1 */
36		36
37	/*	37	/*
38	* PCMCIA support	38	* PCMCIA support
39	*/	39	*/
40	#include <common.h>	40	#include <common.h>
41	#include <command.h>	41	#include <command.h>
42	#include <config.h>	42	#include <config.h>
43	#include <pcmcia.h>	43	#include <pcmcia.h>
44	#include <asm/io.h>	44	#include <asm/io.h>
45		45
46	/* -------------------------------------------------------------------- */	46	/* -------------------------------------------------------------------- */
47		47
48	#if defined(CONFIG_CMD_PCMCIA)	48	#if defined(CONFIG_CMD_PCMCIA)
49		49
50	extern int pcmcia_on (void);	50	extern int pcmcia_on (void);
51	extern int pcmcia_off (void);	51	extern int pcmcia_off (void);
52		52
53	int do_pinit (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	53	int do_pinit (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
54	{	54	{
55	int rcode = 0;	55	int rcode = 0;
56		56
57	if (argc != 2) {	57	if (argc != 2) {
58	printf ("Usage: pinit {on \| off}\n");	58	printf ("Usage: pinit {on \| off}\n");
59	return 1;	59	return 1;
60	}	60	}
61	if (strcmp(argv[1],"on") == 0) {	61	if (strcmp(argv[1],"on") == 0) {
62	rcode = pcmcia_on ();	62	rcode = pcmcia_on ();
63	} else if (strcmp(argv[1],"off") == 0) {	63	} else if (strcmp(argv[1],"off") == 0) {
64	rcode = pcmcia_off ();	64	rcode = pcmcia_off ();
65	} else {	65	} else {
66	printf ("Usage: pinit {on \| off}\n");	66	printf ("Usage: pinit {on \| off}\n");
67	return 1;	67	return 1;
68	}	68	}
69		69
70	return rcode;	70	return rcode;
71	}	71	}
72		72
73	U_BOOT_CMD(	73	U_BOOT_CMD(
74	pinit, 2, 0, do_pinit,	74	pinit, 2, 0, do_pinit,
75	"PCMCIA sub-system",	75	"PCMCIA sub-system",
76	"on - power on PCMCIA socket\n"	76	"on - power on PCMCIA socket\n"
77	"pinit off - power off PCMCIA socket"	77	"pinit off - power off PCMCIA socket"
78	);	78	);
79		79
80	#endif	80	#endif
81		81
82	/* -------------------------------------------------------------------- */	82	/* -------------------------------------------------------------------- */
83		83
84	#undef CHECK_IDE_DEVICE	84	#undef CHECK_IDE_DEVICE
85		85
86	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)	86	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
87	#define CHECK_IDE_DEVICE	87	#define CHECK_IDE_DEVICE
88	#endif	88	#endif
89		89
90	#if defined(CONFIG_PXA_PCMCIA)	90	#if defined(CONFIG_PXA_PCMCIA)
91	#define CHECK_IDE_DEVICE	91	#define CHECK_IDE_DEVICE
92	#endif	92	#endif
93		93
94	#ifdef CHECK_IDE_DEVICE	94	#ifdef CHECK_IDE_DEVICE
95		95
96	int ide_devices_found;	96	int ide_devices_found;
97	static uchar *known_cards[] = {	97	static uchar *known_cards[] = {
98	(uchar *)"ARGOSY PnPIDE D5",	98	(uchar *)"ARGOSY PnPIDE D5",
99	NULL	99	NULL
100	};	100	};
101		101
102	#define MAX_TUPEL_SZ 512	102	#define MAX_TUPEL_SZ 512
103	#define MAX_FEATURES 4	103	#define MAX_FEATURES 4
104		104
105	#define MAX_IDENT_CHARS 64	105	#define MAX_IDENT_CHARS 64
106	#define MAX_IDENT_FIELDS 4	106	#define MAX_IDENT_FIELDS 4
107		107
108	#define indent "\t "	108	#define indent "\t "
109		109
110	static void print_funcid (int func)	110	static void print_funcid (int func)
111	{	111	{
112	puts (indent);	112	puts (indent);
113	switch (func) {	113	switch (func) {
114	case CISTPL_FUNCID_MULTI:	114	case CISTPL_FUNCID_MULTI:
115	puts (" Multi-Function");	115	puts (" Multi-Function");
116	break;	116	break;
117	case CISTPL_FUNCID_MEMORY:	117	case CISTPL_FUNCID_MEMORY:
118	puts (" Memory");	118	puts (" Memory");
119	break;	119	break;
120	case CISTPL_FUNCID_SERIAL:	120	case CISTPL_FUNCID_SERIAL:
121	puts (" Serial Port");	121	puts (" Serial Port");
122	break;	122	break;
123	case CISTPL_FUNCID_PARALLEL:	123	case CISTPL_FUNCID_PARALLEL:
124	puts (" Parallel Port");	124	puts (" Parallel Port");
125	break;	125	break;
126	case CISTPL_FUNCID_FIXED:	126	case CISTPL_FUNCID_FIXED:
127	puts (" Fixed Disk");	127	puts (" Fixed Disk");
128	break;	128	break;
129	case CISTPL_FUNCID_VIDEO:	129	case CISTPL_FUNCID_VIDEO:
130	puts (" Video Adapter");	130	puts (" Video Adapter");
131	break;	131	break;
132	case CISTPL_FUNCID_NETWORK:	132	case CISTPL_FUNCID_NETWORK:
133	puts (" Network Adapter");	133	puts (" Network Adapter");
134	break;	134	break;
135	case CISTPL_FUNCID_AIMS:	135	case CISTPL_FUNCID_AIMS:
136	puts (" AIMS Card");	136	puts (" AIMS Card");
137	break;	137	break;
138	case CISTPL_FUNCID_SCSI:	138	case CISTPL_FUNCID_SCSI:
139	puts (" SCSI Adapter");	139	puts (" SCSI Adapter");
140	break;	140	break;
141	default:	141	default:
142	puts (" Unknown");	142	puts (" Unknown");
143	break;	143	break;
144	}	144	}
145	puts (" Card\n");	145	puts (" Card\n");
146	}	146	}
147		147
148	static void print_fixed (volatile uchar *p)	148	static void print_fixed (volatile uchar *p)
149	{	149	{
150	if (p == NULL)	150	if (p == NULL)
151	return;	151	return;
152		152
153	puts(indent);	153	puts(indent);
154		154
155	switch (*p) {	155	switch (*p) {
156	case CISTPL_FUNCE_IDE_IFACE:	156	case CISTPL_FUNCE_IDE_IFACE:
157	{ uchar iface = *(p+2);	157	{ uchar iface = *(p+2);
158		158
159	puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");	159	puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
160	puts (" interface ");	160	puts (" interface ");
161	break;	161	break;
162	}	162	}
163	case CISTPL_FUNCE_IDE_MASTER:	163	case CISTPL_FUNCE_IDE_MASTER:
164	case CISTPL_FUNCE_IDE_SLAVE:	164	case CISTPL_FUNCE_IDE_SLAVE:
165	{ uchar f1 = *(p+2);	165	{ uchar f1 = *(p+2);
166	uchar f2 = *(p+4);	166	uchar f2 = *(p+4);
167		167
168	puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");	168	puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
169		169
170	if (f1 & CISTPL_IDE_UNIQUE)	170	if (f1 & CISTPL_IDE_UNIQUE)
171	puts (" [unique]");	171	puts (" [unique]");
172		172
173	puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");	173	puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
174		174
175	if (f2 & CISTPL_IDE_HAS_SLEEP)	175	if (f2 & CISTPL_IDE_HAS_SLEEP)
176	puts (" [sleep]");	176	puts (" [sleep]");
177		177
178	if (f2 & CISTPL_IDE_HAS_STANDBY)	178	if (f2 & CISTPL_IDE_HAS_STANDBY)
179	puts (" [standby]");	179	puts (" [standby]");
180		180
181	if (f2 & CISTPL_IDE_HAS_IDLE)	181	if (f2 & CISTPL_IDE_HAS_IDLE)
182	puts (" [idle]");	182	puts (" [idle]");
183		183
184	if (f2 & CISTPL_IDE_LOW_POWER)	184	if (f2 & CISTPL_IDE_LOW_POWER)
185	puts (" [low power]");	185	puts (" [low power]");
186		186
187	if (f2 & CISTPL_IDE_REG_INHIBIT)	187	if (f2 & CISTPL_IDE_REG_INHIBIT)
188	puts (" [reg inhibit]");	188	puts (" [reg inhibit]");
189		189
190	if (f2 & CISTPL_IDE_HAS_INDEX)	190	if (f2 & CISTPL_IDE_HAS_INDEX)
191	puts (" [index]");	191	puts (" [index]");
192		192
193	if (f2 & CISTPL_IDE_IOIS16)	193	if (f2 & CISTPL_IDE_IOIS16)
194	puts (" [IOis16]");	194	puts (" [IOis16]");
195		195
196	break;	196	break;
197	}	197	}
198	}	198	}
199	putc ('\n');	199	putc ('\n');
200	}	200	}
201		201
202	static int identify (volatile uchar *p)	202	static int identify (volatile uchar *p)
203	{	203	{
204	uchar id_str[MAX_IDENT_CHARS];	204	uchar id_str[MAX_IDENT_CHARS];
205	uchar data;	205	uchar data;
206	uchar *t;	206	uchar *t;
207	uchar **card;	207	uchar **card;
208	int i, done;	208	int i, done;
209		209
210	if (p == NULL)	210	if (p == NULL)
211	return (0); /* Don't know */	211	return (0); /* Don't know */
212		212
213	t = id_str;	213	t = id_str;
214	done =0;	214	done =0;
215		215
216	for (i=0; i<=4 && !done; ++i, p+=2) {	216	for (i=0; i<=4 && !done; ++i, p+=2) {
217	while ((data = *p) != '\0') {	217	while ((data = *p) != '\0') {
218	if (data == 0xFF) {	218	if (data == 0xFF) {
219	done = 1;	219	done = 1;
220	break;	220	break;
221	}	221	}
222	*t++ = data;	222	*t++ = data;
223	if (t == &id_str[MAX_IDENT_CHARS-1]) {	223	if (t == &id_str[MAX_IDENT_CHARS-1]) {
224	done = 1;	224	done = 1;
225	break;	225	break;
226	}	226	}
227	p += 2;	227	p += 2;
228	}	228	}
229	if (!done)	229	if (!done)
230	*t++ = ' ';	230	*t++ = ' ';
231	}	231	}
232	*t = '\0';	232	*t = '\0';
233	while (--t > id_str) {	233	while (--t > id_str) {
234	if (*t == ' ')	234	if (*t == ' ')
235	*t = '\0';	235	*t = '\0';
236	else	236	else
237	break;	237	break;
238	}	238	}
239	puts ((char *)id_str);	239	puts ((char *)id_str);
240	putc ('\n');	240	putc ('\n');
241		241
242	for (card=known_cards; *card; ++card) {	242	for (card=known_cards; *card; ++card) {
243	debug ("## Compare against \"%s\"\n", *card);	243	debug ("## Compare against \"%s\"\n", *card);
244	if (strcmp((char )card, (char )id_str) == 0) { / found! */	244	if (strcmp((char )card, (char )id_str) == 0) { / found! */
245	debug ("## CARD FOUND ##\n");	245	debug ("## CARD FOUND ##\n");
246	return (1);	246	return (1);
247	}	247	}
248	}	248	}
249		249
250	return (0); /* don't know */	250	return (0); /* don't know */
251	}	251	}
252		252
253	int check_ide_device (int slot)	253	int check_ide_device (int slot)
254	{	254	{
255	volatile uchar *ident = NULL;	255	volatile uchar *ident = NULL;
256	volatile uchar *feature_p[MAX_FEATURES];	256	volatile uchar *feature_p[MAX_FEATURES];
257	volatile uchar p, start, *addr;	257	volatile uchar p, start, *addr;
258	int n_features = 0;	258	int n_features = 0;
259	uchar func_id = ~0;	259	uchar func_id = ~0;
260	uchar code, len;	260	uchar code, len;
261	ushort config_base = 0;	261	ushort config_base = 0;
262	int found = 0;	262	int found = 0;
263	int i;	263	int i;
264		264
265	addr = (volatile uchar *)(CONFIG_SYS_PCMCIA_MEM_ADDR +	265	addr = (volatile uchar *)(CONFIG_SYS_PCMCIA_MEM_ADDR +
266	CONFIG_SYS_PCMCIA_MEM_SIZE * (slot * 4));	266	CONFIG_SYS_PCMCIA_MEM_SIZE * (slot * 4));
267	debug ("PCMCIA MEM: %08lX\n", (ulong)addr);	267	debug ("PCMCIA MEM: %08lX\n", (ulong)addr);
268		268
269	start = p = (volatile uchar *) addr;	269	start = p = (volatile uchar *) addr;
270		270
271	while ((p - start) < MAX_TUPEL_SZ) {	271	while ((p - start) < MAX_TUPEL_SZ) {
272		272
273	code = *p; p += 2;	273	code = *p; p += 2;
274		274
275	if (code == 0xFF) { /* End of chain */	275	if (code == 0xFF) { /* End of chain */
276	break;	276	break;
277	}	277	}
278		278
279	len = *p; p += 2;	279	len = *p; p += 2;
280	#if defined(DEBUG) && (DEBUG > 1)	280	#if defined(DEBUG) && (DEBUG > 1)
281	{ volatile uchar *q = p;	281	{ volatile uchar *q = p;
282	printf ("\nTuple code %02x length %d\n\tData:",	282	printf ("\nTuple code %02x length %d\n\tData:",
283	code, len);	283	code, len);
284		284
285	for (i = 0; i < len; ++i) {	285	for (i = 0; i < len; ++i) {
286	printf (" %02x", *q);	286	printf (" %02x", *q);
287	q+= 2;	287	q+= 2;
288	}	288	}
289	}	289	}
290	#endif /* DEBUG */	290	#endif /* DEBUG */
291	switch (code) {	291	switch (code) {
292	case CISTPL_VERS_1:	292	case CISTPL_VERS_1:
293	ident = p + 4;	293	ident = p + 4;
294	break;	294	break;
295	case CISTPL_FUNCID:	295	case CISTPL_FUNCID:
296	/* Fix for broken SanDisk which may have 0x80 bit set */	296	/* Fix for broken SanDisk which may have 0x80 bit set */
297	func_id = *p & 0x7F;	297	func_id = *p & 0x7F;
298	break;	298	break;
299	case CISTPL_FUNCE:	299	case CISTPL_FUNCE:
300	if (n_features < MAX_FEATURES)	300	if (n_features < MAX_FEATURES)
301	feature_p[n_features++] = p;	301	feature_p[n_features++] = p;
302	break;	302	break;
303	case CISTPL_CONFIG:	303	case CISTPL_CONFIG:
304	config_base = ((p+6) << 8) + ((p+4));	304	config_base = ((p+6) << 8) + ((p+4));
305	debug ("\n## Config_base = %04x ###\n", config_base);	305	debug ("\n## Config_base = %04x ###\n", config_base);
306	default:	306	default:
307	break;	307	break;
308	}	308	}
309	p += 2 * len;	309	p += 2 * len;
310	}	310	}
311		311
312	found = identify (ident);	312	found = identify (ident);
313		313
314	if (func_id != ((uchar)~0)) {	314	if (func_id != ((uchar)~0)) {
315	print_funcid (func_id);	315	print_funcid (func_id);
316		316
317	if (func_id == CISTPL_FUNCID_FIXED)	317	if (func_id == CISTPL_FUNCID_FIXED)
318	found = 1;	318	found = 1;
319	else	319	else
320	return (1); /* no disk drive */	320	return (1); /* no disk drive */
321	}	321	}
322		322
323	for (i=0; i<n_features; ++i) {	323	for (i=0; i<n_features; ++i) {
324	print_fixed (feature_p[i]);	324	print_fixed (feature_p[i]);
325	}	325	}
326		326
327	if (!found) {	327	if (!found) {
328	printf ("unknown card type\n");	328	printf ("unknown card type\n");
329	return (1);	329	return (1);
330	}	330	}
331		331
332	ide_devices_found \|= (1 << slot);	332	ide_devices_found \|= (1 << slot);
333		333
334	/* set I/O area in config reg -> only valid for ARGOSY D5!!! */	334	/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
335	((uchar )(addr + config_base)) = 1;	335	((uchar )(addr + config_base)) = 1;
336	#if 0	336	#if 0
337	printf("\n## Config_base = %04x ###\n", config_base);	337	printf("\n## Config_base = %04x ###\n", config_base);
338	printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);	338	printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);
339	printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2));	339	printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2));
340	printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4));	340	printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4));
341	printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6));	341	printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6));
342	#endif	342	#endif
343	return (0);	343	return (0);
344	}	344	}
345		345
346	#endif /* CHECK_IDE_DEVICE */	346	#endif /* CHECK_IDE_DEVICE */
347		347

common/Makefile

Diff comments View file @ fc843a0

 #
 # (C) Copyright 2004-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 # core
 ifndef CONFIG_SPL_BUILD
 obj-y += init/
 obj-y += main.o
 obj-y += exports.o
 obj-$(CONFIG_HASH) += hash.o
 obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
 obj-$(CONFIG_AUTOBOOT) += autoboot.o
 # This option is not just y/n - it can have a numeric value
 ifdef CONFIG_BOOT_RETRY_TIME
 obj-y += bootretry.o
 endif
 # boards
 obj-y += board_f.o
 obj-y += board_r.o
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
 # environment
 obj-y += env_attr.o
 obj-y += env_callback.o
 obj-y += env_flags.o
 obj-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
 extra-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
 extra-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
 obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
 obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
 obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
 obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
 obj-$(CONFIG_ENV_IS_IN_SATA) += env_sata.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
 obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += fdt_support.o
 obj-$(CONFIG_MII) += miiphyutil.o
 obj-$(CONFIG_CMD_MII) += miiphyutil.o
 obj-$(CONFIG_PHYLIB) += miiphyutil.o
 ifdef CONFIG_CMD_USB
 obj-y += usb.o usb_hub.o
 obj-$(CONFIG_USB_STORAGE) += usb_storage.o
 endif
 # others
 obj-$(CONFIG_BOOTSTAGE) += bootstage.o
 obj-$(CONFIG_CONSOLE_MUX) += iomux.o
 obj-$(CONFIG_MTD_NOR_FLASH) += flash.o
 obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
 obj-$(CONFIG_I2C_EDID) += edid.o
 obj-$(CONFIG_KALLSYMS) += kallsyms.o
 obj-y += splash.o
 obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o
 ifndef CONFIG_DM_VIDEO
 obj-$(CONFIG_LCD) += lcd.o lcd_console.o
 endif
 obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
 obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
 obj-$(CONFIG_LYNXKDI) += lynxkdi.o
 obj-$(CONFIG_MENU) += menu.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_UPDATE_TFTP) += update.o
 obj-$(CONFIG_DFU_TFTP) += update.o
 obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
 obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o
 endif # !CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o
 obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
 obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
 obj-$(CONFIG_SPL_OF_LIBFDT) += fdt_support.o
 ifdef CONFIG_SPL_USB_HOST_SUPPORT
 obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
 obj-$(CONFIG_USB_STORAGE) += usb_storage.o
 endif
 # environment
 ifdef CONFIG_TPL_BUILD
 obj-$(CONFIG_TPL_ENV_SUPPORT) += env_attr.o
 obj-$(CONFIG_TPL_ENV_SUPPORT) += env_flags.o
 obj-$(CONFIG_TPL_ENV_SUPPORT) += env_callback.o
 else
 obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
 obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
 obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
 endif
 ifneq ($(CONFIG_TPL_ENV_SUPPORT)$(CONFIG_SPL_ENV_SUPPORT),)
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
 obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
 obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 endif
 ifdef CONFIG_SPL_SATA_SUPPORT
 obj-$(CONFIG_SCSI) += scsi.o
 endif
 endif
 #environment
 obj-y += env_common.o
 #others
 obj-$(CONFIG_DDR_SPD) += ddr_spd.o
 obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o
 obj-$(CONFIG_HWCONFIG) += hwconfig.o
 obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TPL_BUILD
 obj-$(CONFIG_TPL_SERIAL_SUPPORT) += console.o
 else
 obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o
 endif
 else
 obj-y += console.o
 endif
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-y += dlmalloc.o
 ifdef CONFIG_SYS_MALLOC_F_LEN
 obj-y += malloc_simple.o
 endif
-obj-$(CONFIG_CMD_IDE) += ide.o
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
 obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
 obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
 obj-y += stdio.o
 # This option is not just y/n - it can have a numeric value
 ifdef CONFIG_FASTBOOT_FLASH
 obj-y += image-sparse.o
 ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
 obj-y += fb_mmc.o
 endif
 ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
 obj-y += fb_nand.o
 endif
 endif
 ifdef CONFIG_CMD_EEPROM_LAYOUT
 obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
 endif
 obj-y += cli.o
 obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
 obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
 obj-y += s_record.o
 obj-y += xyzModem.o
 CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)

common/board_r.c

Diff comments View file @ fc843a0

 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2002-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 /* TODO: can we just include all these headers whether needed or not? */
 #if defined(CONFIG_CMD_BEDBUG)
 #include <bedbug/type.h>
 #endif
 #include <command.h>
 #include <console.h>
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>
 #endif
 #include <dm.h>
 #include <environment.h>
 #include <fdtdec.h>
-#if defined(CONFIG_CMD_IDE)
 #include <ide.h>
-#endif
 #include <initcall.h>
 #include <init_helpers.h>
 #ifdef CONFIG_PS2KBD
 #include <keyboard.h>
 #endif
 #if defined(CONFIG_CMD_KGDB)
 #include <kgdb.h>
 #endif
 #include <logbuff.h>
 #include <malloc.h>
 #include <mapmem.h>
 #ifdef CONFIG_BITBANGMII
 #include <miiphy.h>
 #endif
 #include <mmc.h>
 #include <nand.h>
 #include <onenand_uboot.h>
 #include <scsi.h>
 #include <serial.h>
 #include <spi.h>
 #include <stdio_dev.h>
 #include <timer.h>
 #include <trace.h>
 #include <watchdog.h>
 #ifdef CONFIG_ADDR_MAP
 #include <asm/mmu.h>
 #endif
 #include <asm/sections.h>
 #include <dm/root.h>
 #include <linux/compiler.h>
 #include <linux/err.h>
 #ifdef CONFIG_AVR32
 #include <asm/arch/mmu.h>
 #endif
 #include <efi_loader.h>
 DECLARE_GLOBAL_DATA_PTR;
 ulong monitor_flash_len;
 __weak int board_flash_wp_on(void)
 {
 	/*
 	 * Most flashes can't be detected when write protection is enabled,
 	 * so provide a way to let U-Boot gracefully ignore write protected
 	 * devices.
 	 */
 	return 0;
 }
 __weak void cpu_secondary_init_r(void)
 {
 }
 static int initr_secondary_cpu(void)
 {
 	/*
 	 * after non-volatile devices & environment is setup and cpu code have
 	 * another round to deal with any initialization that might require
 	 * full access to the environment or loading of some image (firmware)
 	 * from a non-volatile device
 	 */
 	/* TODO: maybe define this for all archs? */
 	cpu_secondary_init_r();
 	return 0;
 }
 static int initr_trace(void)
 {
 #ifdef CONFIG_TRACE
 	trace_init(gd->trace_buff, CONFIG_TRACE_BUFFER_SIZE);
 #endif
 	return 0;
 }
 static int initr_reloc(void)
 {
 	/* tell others: relocation done */
 	gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT;
 	return 0;
 }
 #ifdef CONFIG_ARM
 /*
  * Some of these functions are needed purely because the functions they
  * call return void. If we change them to return 0, these stubs can go away.
  */
 static int initr_caches(void)
 {
 	/* Enable caches */
 	enable_caches();
 	return 0;
 }
 #endif
 __weak int fixup_cpu(void)
 {
 	return 0;
 }
 static int initr_reloc_global_data(void)
 {
 #ifdef __ARM__
 	monitor_flash_len = _end - __image_copy_start;
 #elif defined(CONFIG_NDS32)
 	monitor_flash_len = (ulong)&_end - (ulong)&_start;
 #elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
 	monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
 #endif
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	/*
 	 * The gd->cpu pointer is set to an address in flash before relocation.
 	 * We need to update it to point to the same CPU entry in RAM.
 	 * TODO: why not just add gd->reloc_ofs?
 	 */
 	gd->arch.cpu += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;
 	/*
 	 * If we didn't know the cpu mask & # cores, we can save them of
 	 * now rather than 'computing' them constantly
 	 */
 	fixup_cpu();
 #endif
 #ifdef CONFIG_SYS_EXTRA_ENV_RELOC
 	/*
 	 * Some systems need to relocate the env_addr pointer early because the
 	 * location it points to will get invalidated before env_relocate is
 	 * called.  One example is on systems that might use a L2 or L3 cache
 	 * in SRAM mode and initialize that cache from SRAM mode back to being
 	 * a cache in cpu_init_r.
 	 */
 	gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;
 #endif
 #ifdef CONFIG_OF_EMBED
 	/*
 	* The fdt_blob needs to be moved to new relocation address
 	* incase of FDT blob is embedded with in image
 	*/
 	gd->fdt_blob += gd->reloc_off;
 #endif
 #ifdef CONFIG_EFI_LOADER
 	efi_runtime_relocate(gd->relocaddr, NULL);
 #endif
 	return 0;
 }
 static int initr_serial(void)
 {
 	serial_initialize();
 	return 0;
 }
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
 static int initr_trap(void)
 {
 	/*
 	 * Setup trap handlers
 	 */
 #if defined(CONFIG_PPC)
 	trap_init(gd->relocaddr);
 #else
 	trap_init(CONFIG_SYS_SDRAM_BASE);
 #endif
 	return 0;
 }
 #endif
 #ifdef CONFIG_ADDR_MAP
 static int initr_addr_map(void)
 {
 	init_addr_map();
 	return 0;
 }
 #endif
 #ifdef CONFIG_LOGBUFFER
 unsigned long logbuffer_base(void)
 {
 	return gd->ram_top - LOGBUFF_LEN;
 }
 static int initr_logbuffer(void)
 {
 	logbuff_init_ptrs();
 	return 0;
 }
 #endif
 #ifdef CONFIG_POST
 static int initr_post_backlog(void)
 {
 	post_output_backlog();
 	return 0;
 }
 #endif
 #ifdef CONFIG_SYS_DELAYED_ICACHE
 static int initr_icache_enable(void)
 {
 	return 0;
 }
 #endif
 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
 static int initr_unlock_ram_in_cache(void)
 {
 	unlock_ram_in_cache();	/* it's time to unlock D-cache in e500 */
 	return 0;
 }
 #endif
 #ifdef CONFIG_PCI
 static int initr_pci(void)
 {
 #ifndef CONFIG_DM_PCI
 	pci_init();
 #endif
 	return 0;
 }
 #endif
 static int initr_barrier(void)
 {
 #ifdef CONFIG_PPC
 	/* TODO: Can we not use dmb() macros for this? */
 	asm("sync ; isync");
 #endif
 	return 0;
 }
 static int initr_malloc(void)
 {
 	ulong malloc_start;
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
 	      gd->malloc_ptr / 1024);
 #endif
 	/* The malloc area is immediately below the monitor copy in DRAM */
 	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
 	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
 			TOTAL_MALLOC_LEN);
 	return 0;
 }
 static int initr_console_record(void)
 {
 #if defined(CONFIG_CONSOLE_RECORD)
 	return console_record_init();
 #else
 	return 0;
 #endif
 }
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 static int initr_noncached(void)
 {
 	noncached_init();
 	return 0;
 }
 #endif
 #ifdef CONFIG_DM
 static int initr_dm(void)
 {
 	int ret;
 	/* Save the pre-reloc driver model and start a new one */
 	gd->dm_root_f = gd->dm_root;
 	gd->dm_root = NULL;
 #ifdef CONFIG_TIMER
 	gd->timer = NULL;
 #endif
 	ret = dm_init_and_scan(false);
 	if (ret)
 		return ret;
 #ifdef CONFIG_TIMER_EARLY
 	ret = dm_timer_init();
 	if (ret)
 		return ret;
 #endif
 	return 0;
 }
 #endif
 static int initr_bootstage(void)
 {
 	/* We cannot do this before initr_dm() */
 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
 	return 0;
 }
 __weak int power_init_board(void)
 {
 	return 0;
 }
 static int initr_announce(void)
 {
 	debug("Now running in RAM - U-Boot at: %08lx\n", gd->relocaddr);
 	return 0;
 }
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 static int initr_manual_reloc_cmdtable(void)
 {
 	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
 		       ll_entry_count(cmd_tbl_t, cmd));
 	return 0;
 }
 #endif
 #if defined(CONFIG_MTD_NOR_FLASH)
 static int initr_flash(void)
 {
 	ulong flash_size = 0;
 	bd_t *bd = gd->bd;
 	puts("Flash: ");
 	if (board_flash_wp_on())
 		printf("Uninitialized - Write Protect On\n");
 	else
 		flash_size = flash_init();
 	print_size(flash_size, "");
 #ifdef CONFIG_SYS_FLASH_CHECKSUM
 	/*
 	* Compute and print flash CRC if flashchecksum is set to 'y'
 	*
 	* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
 	*/
 	if (getenv_yesno("flashchecksum") == 1) {
 		printf("  CRC: %08X", crc32(0,
 			(const unsigned char *) CONFIG_SYS_FLASH_BASE,
 			flash_size));
 	}
 #endif /* CONFIG_SYS_FLASH_CHECKSUM */
 	putc('\n');
 	/* update start of FLASH memory    */
 #ifdef CONFIG_SYS_FLASH_BASE
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
 #endif
 	/* size of FLASH memory (final value) */
 	bd->bi_flashsize = flash_size;
 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 	/* Make a update of the Memctrl. */
 	update_flash_size(flash_size);
 #endif
 #if defined(CONFIG_OXC) || defined(CONFIG_RMU)
 	/* flash mapped at end of memory map */
 	bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
 #elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
 	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for monitor */
 #endif
 	return 0;
 }
 #endif
 #if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI)
 static int initr_spi(void)
 {
 	/* PPC does this here */
 #ifdef CONFIG_SPI
 #if !defined(CONFIG_ENV_IS_IN_EEPROM)
 	spi_init_f();
 #endif
 	spi_init_r();
 #endif
 	return 0;
 }
 #endif
 #ifdef CONFIG_CMD_NAND
 /* go init the NAND */
 static int initr_nand(void)
 {
 	puts("NAND:  ");
 	nand_init();
 	printf("%lu MiB\n", nand_size() / 1024);
 	return 0;
 }
 #endif
 #if defined(CONFIG_CMD_ONENAND)
 /* go init the NAND */
 static int initr_onenand(void)
 {
 	puts("NAND:  ");
 	onenand_init();
 	return 0;
 }
 #endif
 #ifdef CONFIG_MMC
 static int initr_mmc(void)
 {
 	puts("MMC:   ");
 	mmc_initialize(gd->bd);
 	return 0;
 }
 #endif
 #ifdef CONFIG_HAS_DATAFLASH
 static int initr_dataflash(void)
 {
 	AT91F_DataflashInit();
 	dataflash_print_info();
 	return 0;
 }
 #endif
 /*
  * Tell if it's OK to load the environment early in boot.
  *
  * If CONFIG_OF_CONTROL is defined, we'll check with the FDT to see
  * if this is OK (defaulting to saying it's OK).
  *
  * NOTE: Loading the environment early can be a bad idea if security is
  *       important, since no verification is done on the environment.
  *
  * @return 0 if environment should not be loaded, !=0 if it is ok to load
  */
 static int should_load_env(void)
 {
 #ifdef CONFIG_OF_CONTROL
 	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
 #elif defined CONFIG_DELAY_ENVIRONMENT
 	return 0;
 #else
 	return 1;
 #endif
 }
 static int initr_env(void)
 {
 	/* initialize environment */
 	if (should_load_env())
 		env_relocate();
 	else
 		set_default_env(NULL);
 #ifdef CONFIG_OF_CONTROL
 	setenv_addr("fdtcontroladdr", gd->fdt_blob);
 #endif
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 	return 0;
 }
 #ifdef CONFIG_SYS_BOOTPARAMS_LEN
 static int initr_malloc_bootparams(void)
 {
 	gd->bd->bi_boot_params = (ulong)malloc(CONFIG_SYS_BOOTPARAMS_LEN);
 	if (!gd->bd->bi_boot_params) {
 		puts("WARNING: Cannot allocate space for boot parameters\n");
 		return -ENOMEM;
 	}
 	return 0;
 }
 #endif
 static int initr_jumptable(void)
 {
 	jumptable_init();
 	return 0;
 }
 #if defined(CONFIG_API)
 static int initr_api(void)
 {
 	/* Initialize API */
 	api_init();
 	return 0;
 }
 #endif
 /* enable exceptions */
 #if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
 static int initr_enable_interrupts(void)
 {
 	enable_interrupts();
 	return 0;
 }
 #endif
 #ifdef CONFIG_CMD_NET
 static int initr_ethaddr(void)
 {
 	bd_t *bd = gd->bd;
 	/* kept around for legacy kernels only ... ignore the next section */
 	eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
 #ifdef CONFIG_HAS_ETH1
 	eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
 #endif
 #ifdef CONFIG_HAS_ETH2
 	eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
 #endif
 #ifdef CONFIG_HAS_ETH3
 	eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
 #endif
 #ifdef CONFIG_HAS_ETH4
 	eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
 #endif
 #ifdef CONFIG_HAS_ETH5
 	eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
 #endif
 	return 0;
 }
 #endif /* CONFIG_CMD_NET */
 #ifdef CONFIG_CMD_KGDB
 static int initr_kgdb(void)
 {
 	puts("KGDB:  ");
 	kgdb_init();
 	return 0;
 }
 #endif
 #if defined(CONFIG_LED_STATUS)
 static int initr_status_led(void)
 {
 #if defined(CONFIG_LED_STATUS_BOOT)
 	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING);
 #else
 	status_led_init();
 #endif
 	return 0;
 }
 #endif
 #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
 static int initr_scsi(void)
 {
 	puts("SCSI:  ");
 	scsi_init();
 	return 0;
 }
 #endif
 #ifdef CONFIG_BITBANGMII
 static int initr_bbmii(void)
 {
 	bb_miiphy_init();
 	return 0;
 }
 #endif
 #ifdef CONFIG_CMD_NET
 static int initr_net(void)
 {
 	puts("Net:   ");
 	eth_initialize();
 #if defined(CONFIG_RESET_PHY_R)
 	debug("Reset Ethernet PHY\n");
 	reset_phy();
 #endif
 	return 0;
 }
 #endif
 #ifdef CONFIG_POST
 static int initr_post(void)
 {
 	post_run(NULL, POST_RAM | post_bootmode_get(0));
 	return 0;
 }
 #endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
 static int initr_pcmcia(void)
 {
 	puts("PCMCIA:");
 	pcmcia_init();
 	return 0;
 }
 #endif
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
 static int initr_ide(void)
 {
 #ifdef	CONFIG_IDE_8xx_PCCARD
 	puts("PCMCIA:");
 #else
 	puts("IDE:   ");
 #endif
 #if defined(CONFIG_START_IDE)
 	if (board_start_ide())
 		ide_init();
 #else
 	ide_init();
 #endif
 	return 0;
 }
 #endif
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
 /*
  * Export available size of memory for Linux, taking into account the
  * protected RAM at top of memory
  */
 int initr_mem(void)
 {
 	ulong pram = 0;
 	char memsz[32];
 # ifdef CONFIG_PRAM
 	pram = getenv_ulong("pram", 10, CONFIG_PRAM);
 # endif
 # if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
 	/* Also take the logbuffer into account (pram is in kB) */
 	pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
 # endif
 	sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram));
 	setenv("mem", memsz);
 	return 0;
 }
 #endif
 #ifdef CONFIG_CMD_BEDBUG
 static int initr_bedbug(void)
 {
 	bedbug_init();
 	return 0;
 }
 #endif
 #ifdef CONFIG_PS2KBD
 static int initr_kbd(void)
 {
 	puts("PS/2:  ");
 	kbd_init();
 	return 0;
 }
 #endif
 static int run_main_loop(void)
 {
 #ifdef CONFIG_SANDBOX
 	sandbox_main_loop_init();
 #endif
 	/* main_loop() can return to retry autoboot, if so just run it again */
 	for (;;)
 		main_loop();
 	return 0;
 }
 /*
  * Over time we hope to remove these functions with code fragments and
  * stub funtcions, and instead call the relevant function directly.
  *
  * We also hope to remove most of the driver-related init and do it if/when
  * the driver is later used.
  *
  * TODO: perhaps reset the watchdog in the initcall function after each call?
  */
 static init_fnc_t init_sequence_r[] = {
 	initr_trace,
 	initr_reloc,
 	/* TODO: could x86/PPC have this also perhaps? */
 #ifdef CONFIG_ARM
 	initr_caches,
 	/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
 	 *	 A temporary mapping of IFC high region is since removed,
 	 *	 so environmental variables in NOR flash is not availble
 	 *	 until board_init() is called below to remap IFC to high
 	 *	 region.
 	 */
 #endif
 	initr_reloc_global_data,
 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
 	initr_unlock_ram_in_cache,
 #endif
 	initr_barrier,
 	initr_malloc,
 	initr_console_record,
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 	initr_noncached,
 #endif
 	bootstage_relocate,
 #ifdef CONFIG_DM
 	initr_dm,
 #endif
 	initr_bootstage,
 #if defined(CONFIG_ARM) || defined(CONFIG_NDS32)
 	board_init,	/* Setup chipselects */
 #endif
 	/*
 	 * TODO: printing of the clock inforamtion of the board is now
 	 * implemented as part of bdinfo command. Currently only support for
 	 * davinci SOC's is added. Remove this check once all the board
 	 * implement this.
 	 */
 #ifdef CONFIG_CLOCKS
 	set_cpu_clk_info, /* Setup clock information */
 #endif
 #ifdef CONFIG_EFI_LOADER
 	efi_memory_init,
 #endif
 	stdio_init_tables,
 	initr_serial,
 	initr_announce,
 	INIT_FUNC_WATCHDOG_RESET
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 	initr_manual_reloc_cmdtable,
 #endif
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
 	initr_trap,
 #endif
 #ifdef CONFIG_ADDR_MAP
 	initr_addr_map,
 #endif
 #if defined(CONFIG_BOARD_EARLY_INIT_R)
 	board_early_init_r,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #ifdef CONFIG_LOGBUFFER
 	initr_logbuffer,
 #endif
 #ifdef CONFIG_POST
 	initr_post_backlog,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #ifdef CONFIG_SYS_DELAYED_ICACHE
 	initr_icache_enable,
 #endif
 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
 	/*
 	 * Do early PCI configuration _before_ the flash gets initialised,
 	 * because PCU ressources are crucial for flash access on some boards.
 	 */
 	initr_pci,
 #endif
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 	arch_early_init_r,
 #endif
 	power_init_board,
 #ifdef CONFIG_MTD_NOR_FLASH
 	initr_flash,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
 	/* initialize higher level parts of CPU like time base and timers */
 	cpu_init_r,
 #endif
 #ifdef CONFIG_PPC
 	initr_spi,
 #endif
 #ifdef CONFIG_CMD_NAND
 	initr_nand,
 #endif
 #ifdef CONFIG_CMD_ONENAND
 	initr_onenand,
 #endif
 #ifdef CONFIG_MMC
 	initr_mmc,
 #endif
 #ifdef CONFIG_HAS_DATAFLASH
 	initr_dataflash,
 #endif
 	initr_env,
 #ifdef CONFIG_SYS_BOOTPARAMS_LEN
 	initr_malloc_bootparams,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 	initr_secondary_cpu,
 #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
 	mac_read_from_eeprom,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
 	/*
 	 * Do pci configuration
 	 */
 	initr_pci,
 #endif
 	stdio_add_devices,
 	initr_jumptable,
 #ifdef CONFIG_API
 	initr_api,
 #endif
 	console_init_r,		/* fully init console as a device */
 #ifdef CONFIG_DISPLAY_BOARDINFO_LATE
 	show_board_info,
 #endif
 #ifdef CONFIG_ARCH_MISC_INIT
 	arch_misc_init,		/* miscellaneous arch-dependent init */
 #endif
 #ifdef CONFIG_MISC_INIT_R
 	misc_init_r,		/* miscellaneous platform-dependent init */
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #ifdef CONFIG_CMD_KGDB
 	initr_kgdb,
 #endif
 	interrupt_init,
 #if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
 	initr_enable_interrupts,
 #endif
 #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || defined(CONFIG_M68K)
 	timer_init,		/* initialize timer */
 #endif
 #if defined(CONFIG_LED_STATUS)
 	initr_status_led,
 #endif
 	/* PPC has a udelay(20) here dating from 2002. Why? */
 #ifdef CONFIG_CMD_NET
 	initr_ethaddr,
 #endif
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif
 #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
 	INIT_FUNC_WATCHDOG_RESET
 	initr_scsi,
 #endif
 #ifdef CONFIG_BITBANGMII
 	initr_bbmii,
 #endif
 #ifdef CONFIG_CMD_NET
 	INIT_FUNC_WATCHDOG_RESET
 	initr_net,
 #endif
 #ifdef CONFIG_POST
 	initr_post,
 #endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
 	initr_pcmcia,
 #endif
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
 	initr_ide,
 #endif
 #ifdef CONFIG_LAST_STAGE_INIT
 	INIT_FUNC_WATCHDOG_RESET
 	/*
 	 * Some parts can be only initialized if all others (like
 	 * Interrupts) are up and running (i.e. the PC-style ISA
 	 * keyboard).
 	 */
 	last_stage_init,
 #endif
 #ifdef CONFIG_CMD_BEDBUG
 	INIT_FUNC_WATCHDOG_RESET
 	initr_bedbug,
 #endif
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
 	initr_mem,
 #endif
 #ifdef CONFIG_PS2KBD
 	initr_kbd,
 #endif
 	run_main_loop,
 };
 void board_init_r(gd_t *new_gd, ulong dest_addr)
 {
 	/*
 	 * Set up the new global data pointer. So far only x86 does this
 	 * here.
 	 * TODO(sjg@chromium.org): Consider doing this for all archs, or
 	 * dropping the new_gd parameter.
 	 */
 #if CONFIG_IS_ENABLED(X86_64)
 	arch_setup_gd(new_gd);
 #endif
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 	int i;
 #endif
 #ifdef CONFIG_AVR32
 	mmu_init_r(dest_addr);
 #endif
 #if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
 	gd = new_gd;
 #endif
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 	for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
 		init_sequence_r[i] += gd->reloc_off;
 #endif
 	if (initcall_run_list(init_sequence_r))
 		hang();
 	/* NOTREACHED - run_main_loop() does not return */
 	hang();
 }

common/ide.c

View file @ fc843a0

1	/*		File was deleted
2	* (C) Copyright 2000-2011
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*
5	* SPDX-License-Identifier: GPL-2.0+
6	*/
7
8	#include <common.h>
9	#include <ata.h>
10	#include <dm.h>
11	#include <ide.h>
12	#include <watchdog.h>
13	#include <asm/io.h>
14
15	#ifdef __PPC__
16	# define EIEIO __asm__ volatile ("eieio")
17	# define SYNC __asm__ volatile ("sync")
18	#else
19	# define EIEIO /* nothing */
20	# define SYNC /* nothing */
21	#endif
22
23	/* Current offset for IDE0 / IDE1 bus access */
24	ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
25	#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
26	CONFIG_SYS_ATA_IDE0_OFFSET,
27	#endif
28	#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
29	CONFIG_SYS_ATA_IDE1_OFFSET,
30	#endif
31	};
32
33	static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
34
35	struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
36
37	#define IDE_TIME_OUT 2000 /* 2 sec timeout */
38
39	#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
40
41	#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
42
43	#ifndef CONFIG_SYS_ATA_PORT_ADDR
44	#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
45	#endif
46
47	#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
48	# define DEVICE_LED(x) 0
49	# define LED_IDE1 1
50	# define LED_IDE2 2
51	#endif
52
53	#ifdef CONFIG_IDE_RESET
54	extern void ide_set_reset(int idereset);
55
56	static void ide_reset(void)
57	{
58	int i;
59
60	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
61	ide_bus_ok[i] = 0;
62	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
63	ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
64
65	ide_set_reset(1); /* assert reset */
66
67	/* the reset signal shall be asserted for et least 25 us */
68	udelay(25);
69
70	WATCHDOG_RESET();
71
72	/* de-assert RESET signal */
73	ide_set_reset(0);
74
75	/* wait 250 ms */
76	for (i = 0; i < 250; ++i)
77	udelay(1000);
78	}
79	#else
80	#define ide_reset() /* dummy */
81	#endif /* CONFIG_IDE_RESET */
82
83	/*
84	* Wait until Busy bit is off, or timeout (in ms)
85	* Return last status
86	*/
87	static uchar ide_wait(int dev, ulong t)
88	{
89	ulong delay = 10 * t; /* poll every 100 us */
90	uchar c;
91
92	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
93	udelay(100);
94	if (delay-- == 0)
95	break;
96	}
97	return c;
98	}
99
100	/*
101	* copy src to dest, skipping leading and trailing blanks and null
102	* terminate the string
103	* "len" is the size of available memory including the terminating '\0'
104	*/
105	static void ident_cpy(unsigned char dst, unsigned char src,
106	unsigned int len)
107	{
108	unsigned char end, last;
109
110	last = dst;
111	end = src + len - 1;
112
113	/* reserve space for '\0' */
114	if (len < 2)
115	goto OUT;
116
117	/* skip leading white space */
118	while ((src) && (src < end) && (src == ' '))
119	++src;
120
121	/* copy string, omitting trailing white space */
122	while ((*src) && (src < end)) {
123	dst++ = src;
124	if (*src++ != ' ')
125	last = dst;
126	}
127	OUT:
128	*last = '\0';
129	}
130
131	#ifdef CONFIG_ATAPI
132	/****************************************************************************
133	* ATAPI Support
134	*/
135
136	#if defined(CONFIG_IDE_SWAP_IO)
137	/* since ATAPI may use commands with not 4 bytes alligned length
138	* we have our own transfer functions, 2 bytes alligned */
139	__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
140	{
141	ushort *dbuf;
142	volatile ushort *pbuf;
143
144	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
145	dbuf = (ushort *)sect_buf;
146
147	debug("in output data shorts base for read is %lx\n",
148	(unsigned long) pbuf);
149
150	while (shorts--) {
151	EIEIO;
152	pbuf = dbuf++;
153	}
154	}
155
156	__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
157	{
158	ushort *dbuf;
159	volatile ushort *pbuf;
160
161	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
162	dbuf = (ushort *)sect_buf;
163
164	debug("in input data shorts base for read is %lx\n",
165	(unsigned long) pbuf);
166
167	while (shorts--) {
168	EIEIO;
169	dbuf++ = pbuf;
170	}
171	}
172
173	#else /* ! CONFIG_IDE_SWAP_IO */
174	__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
175	{
176	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
177	}
178
179	__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
180	{
181	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
182	}
183
184	#endif /* CONFIG_IDE_SWAP_IO */
185
186	/*
187	* Wait until (Status & mask) == res, or timeout (in ms)
188	* Return last status
189	* This is used since some ATAPI CD ROMs clears their Busy Bit first
190	* and then they set their DRQ Bit
191	*/
192	static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
193	{
194	ulong delay = 10 * t; /* poll every 100 us */
195	uchar c;
196
197	/* prevents to read the status before valid */
198	c = ide_inb(dev, ATA_DEV_CTL);
199
200	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
201	/* break if error occurs (doesn't make sense to wait more) */
202	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
203	break;
204	udelay(100);
205	if (delay-- == 0)
206	break;
207	}
208	return c;
209	}
210
211	/*
212	* issue an atapi command
213	*/
214	unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
215	unsigned char *buffer, int buflen)
216	{
217	unsigned char c, err, mask, res;
218	int n;
219
220	ide_led(DEVICE_LED(device), 1); /* LED on */
221
222	/* Select device
223	*/
224	mask = ATA_STAT_BUSY \| ATA_STAT_DRQ;
225	res = 0;
226	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
227	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
228	if ((c & mask) != res) {
229	printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
230	c);
231	err = 0xFF;
232	goto AI_OUT;
233	}
234	/* write taskfile */
235	ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
236	ide_outb(device, ATA_SECT_CNT, 0);
237	ide_outb(device, ATA_SECT_NUM, 0);
238	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
239	ide_outb(device, ATA_CYL_HIGH,
240	(unsigned char) ((buflen >> 8) & 0xFF));
241	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
242
243	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
244	udelay(50);
245
246	mask = ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR;
247	res = ATA_STAT_DRQ;
248	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
249
250	if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
251	printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
252	device, c);
253	err = 0xFF;
254	goto AI_OUT;
255	}
256
257	/* write command block */
258	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
259
260	/* ATAPI Command written wait for completition */
261	udelay(5000); /* device must set bsy */
262
263	mask = ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR;
264	/*
265	* if no data wait for DRQ = 0 BSY = 0
266	* if data wait for DRQ = 1 BSY = 0
267	*/
268	res = 0;
269	if (buflen)
270	res = ATA_STAT_DRQ;
271	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
272	if ((c & mask) != res) {
273	if (c & ATA_STAT_ERR) {
274	err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
275	debug("atapi_issue 1 returned sense key %X status %02X\n",
276	err, c);
277	} else {
278	printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
279	ccb[0], c);
280	err = 0xFF;
281	}
282	goto AI_OUT;
283	}
284	n = ide_inb(device, ATA_CYL_HIGH);
285	n <<= 8;
286	n += ide_inb(device, ATA_CYL_LOW);
287	if (n > buflen) {
288	printf("ERROR, transfer bytes %d requested only %d\n", n,
289	buflen);
290	err = 0xff;
291	goto AI_OUT;
292	}
293	if ((n == 0) && (buflen < 0)) {
294	printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
295	err = 0xff;
296	goto AI_OUT;
297	}
298	if (n != buflen) {
299	debug("WARNING, transfer bytes %d not equal with requested %d\n",
300	n, buflen);
301	}
302	if (n != 0) { /* data transfer */
303	debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
304	/* we transfer shorts */
305	n >>= 1;
306	/* ok now decide if it is an in or output */
307	if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
308	debug("Write to device\n");
309	ide_output_data_shorts(device, (unsigned short *)buffer,
310	n);
311	} else {
312	debug("Read from device @ %p shorts %d\n", buffer, n);
313	ide_input_data_shorts(device, (unsigned short *)buffer,
314	n);
315	}
316	}
317	udelay(5000); /* seems that some CD ROMs need this... */
318	mask = ATA_STAT_BUSY \| ATA_STAT_ERR;
319	res = 0;
320	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
321	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
322	err = (ide_inb(device, ATA_ERROR_REG) >> 4);
323	debug("atapi_issue 2 returned sense key %X status %X\n", err,
324	c);
325	} else {
326	err = 0;
327	}
328	AI_OUT:
329	ide_led(DEVICE_LED(device), 0); /* LED off */
330	return err;
331	}
332
333	/*
334	* sending the command to atapi_issue. If an status other than good
335	* returns, an request_sense will be issued
336	*/
337
338	#define ATAPI_DRIVE_NOT_READY 100
339	#define ATAPI_UNIT_ATTN 10
340
341	unsigned char atapi_issue_autoreq(int device,
342	unsigned char *ccb,
343	int ccblen,
344	unsigned char *buffer, int buflen)
345	{
346	unsigned char sense_data[18], sense_ccb[12];
347	unsigned char res, key, asc, ascq;
348	int notready, unitattn;
349
350	unitattn = ATAPI_UNIT_ATTN;
351	notready = ATAPI_DRIVE_NOT_READY;
352
353	retry:
354	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
355	if (res == 0)
356	return 0; /* Ok */
357
358	if (res == 0xFF)
359	return 0xFF; /* error */
360
361	debug("(auto_req)atapi_issue returned sense key %X\n", res);
362
363	memset(sense_ccb, 0, sizeof(sense_ccb));
364	memset(sense_data, 0, sizeof(sense_data));
365	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
366	sense_ccb[4] = 18; /* allocation Length */
367
368	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
369	key = (sense_data[2] & 0xF);
370	asc = (sense_data[12]);
371	ascq = (sense_data[13]);
372
373	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
374	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
375	sense_data[0], key, asc, ascq);
376
377	if ((key == 0))
378	return 0; /* ok device ready */
379
380	if ((key == 6) \|\| (asc == 0x29) \|\| (asc == 0x28)) { /* Unit Attention */
381	if (unitattn-- > 0) {
382	udelay(200 * 1000);
383	goto retry;
384	}
385	printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
386	goto error;
387	}
388	if ((asc == 0x4) && (ascq == 0x1)) {
389	/* not ready, but will be ready soon */
390	if (notready-- > 0) {
391	udelay(200 * 1000);
392	goto retry;
393	}
394	printf("Drive not ready, tried %d times\n",
395	ATAPI_DRIVE_NOT_READY);
396	goto error;
397	}
398	if (asc == 0x3a) {
399	debug("Media not present\n");
400	goto error;
401	}
402
403	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
404	ascq);
405	error:
406	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
407	return 0xFF;
408	}
409
410	/*
411	* atapi_read:
412	* we transfer only one block per command, since the multiple DRQ per
413	* command is not yet implemented
414	*/
415	#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
416	#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
417	#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
418
419	ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
420	void *buffer)
421	{
422	int device = block_dev->devnum;
423	ulong n = 0;
424	unsigned char ccb[12]; /* Command descriptor block */
425	ulong cnt;
426
427	debug("atapi_read dev %d start " LBAF " blocks " LBAF
428	" buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
429
430	do {
431	if (blkcnt > ATAPI_READ_MAX_BLOCK)
432	cnt = ATAPI_READ_MAX_BLOCK;
433	else
434	cnt = blkcnt;
435
436	ccb[0] = ATAPI_CMD_READ_12;
437	ccb[1] = 0; /* reserved */
438	ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
439	ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
440	ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
441	ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
442	ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
443	ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
444	ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
445	ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
446	ccb[10] = 0; /* reserved */
447	ccb[11] = 0; /* reserved */
448
449	if (atapi_issue_autoreq(device, ccb, 12,
450	(unsigned char *)buffer,
451	cnt * ATAPI_READ_BLOCK_SIZE)
452	== 0xFF) {
453	return n;
454	}
455	n += cnt;
456	blkcnt -= cnt;
457	blknr += cnt;
458	buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
459	} while (blkcnt > 0);
460	return n;
461	}
462
463	static void atapi_inquiry(struct blk_desc *dev_desc)
464	{
465	unsigned char ccb[12]; /* Command descriptor block */
466	unsigned char iobuf[64]; /* temp buf */
467	unsigned char c;
468	int device;
469
470	device = dev_desc->devnum;
471	dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
472	dev_desc->block_read = atapi_read;
473
474	memset(ccb, 0, sizeof(ccb));
475	memset(iobuf, 0, sizeof(iobuf));
476
477	ccb[0] = ATAPI_CMD_INQUIRY;
478	ccb[4] = 40; /* allocation Legnth */
479	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
480
481	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
482	if (c != 0)
483	return;
484
485	/* copy device ident strings */
486	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
487	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
488	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
489
490	dev_desc->lun = 0;
491	dev_desc->lba = 0;
492	dev_desc->blksz = 0;
493	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
494	dev_desc->type = iobuf[0] & 0x1f;
495
496	if ((iobuf[1] & 0x80) == 0x80)
497	dev_desc->removable = 1;
498	else
499	dev_desc->removable = 0;
500
501	memset(ccb, 0, sizeof(ccb));
502	memset(iobuf, 0, sizeof(iobuf));
503	ccb[0] = ATAPI_CMD_START_STOP;
504	ccb[4] = 0x03; /* start */
505
506	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
507
508	debug("ATAPI_CMD_START_STOP returned %x\n", c);
509	if (c != 0)
510	return;
511
512	memset(ccb, 0, sizeof(ccb));
513	memset(iobuf, 0, sizeof(iobuf));
514	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
515
516	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
517	if (c != 0)
518	return;
519
520	memset(ccb, 0, sizeof(ccb));
521	memset(iobuf, 0, sizeof(iobuf));
522	ccb[0] = ATAPI_CMD_READ_CAP;
523	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
524	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
525	if (c != 0)
526	return;
527
528	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
529	iobuf[0], iobuf[1], iobuf[2], iobuf[3],
530	iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
531
532	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
533	((unsigned long) iobuf[1] << 16) +
534	((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
535	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
536	((unsigned long) iobuf[5] << 16) +
537	((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
538	dev_desc->log2blksz = LOG2(dev_desc->blksz);
539	#ifdef CONFIG_LBA48
540	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
541	dev_desc->lba48 = 0;
542	#endif
543	return;
544	}
545
546	#endif /* CONFIG_ATAPI */
547
548	static void ide_ident(struct blk_desc *dev_desc)
549	{
550	unsigned char c;
551	hd_driveid_t iop;
552
553	#ifdef CONFIG_ATAPI
554	int retries = 0;
555	#endif
556	int device;
557
558	device = dev_desc->devnum;
559	printf(" Device %d: ", device);
560
561	ide_led(DEVICE_LED(device), 1); /* LED on */
562	/* Select device
563	*/
564	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
565	dev_desc->if_type = IF_TYPE_IDE;
566	#ifdef CONFIG_ATAPI
567
568	retries = 0;
569
570	/* Warning: This will be tricky to read */
571	while (retries <= 1) {
572	/* check signature */
573	if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
574	(ide_inb(device, ATA_SECT_NUM) == 0x01) &&
575	(ide_inb(device, ATA_CYL_LOW) == 0x14) &&
576	(ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
577	/* ATAPI Signature found */
578	dev_desc->if_type = IF_TYPE_ATAPI;
579	/*
580	* Start Ident Command
581	*/
582	ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
583	/*
584	* Wait for completion - ATAPI devices need more time
585	* to become ready
586	*/
587	c = ide_wait(device, ATAPI_TIME_OUT);
588	} else
589	#endif
590	{
591	/*
592	* Start Ident Command
593	*/
594	ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
595
596	/*
597	* Wait for completion
598	*/
599	c = ide_wait(device, IDE_TIME_OUT);
600	}
601	ide_led(DEVICE_LED(device), 0); /* LED off */
602
603	if (((c & ATA_STAT_DRQ) == 0) \|\|
604	((c & (ATA_STAT_FAULT \| ATA_STAT_ERR)) != 0)) {
605	#ifdef CONFIG_ATAPI
606	{
607	/*
608	* Need to soft reset the device
609	* in case it's an ATAPI...
610	*/
611	debug("Retrying...\n");
612	ide_outb(device, ATA_DEV_HD,
613	ATA_LBA \| ATA_DEVICE(device));
614	udelay(100000);
615	ide_outb(device, ATA_COMMAND, 0x08);
616	udelay(500000); /* 500 ms */
617	}
618	/*
619	* Select device
620	*/
621	ide_outb(device, ATA_DEV_HD,
622	ATA_LBA \| ATA_DEVICE(device));
623	retries++;
624	#else
625	return;
626	#endif
627	}
628	#ifdef CONFIG_ATAPI
629	else
630	break;
631	} /* see above - ugly to read */
632
633	if (retries == 2) /* Not found */
634	return;
635	#endif
636
637	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
638
639	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
640	sizeof(dev_desc->revision));
641	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
642	sizeof(dev_desc->vendor));
643	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
644	sizeof(dev_desc->product));
645	#ifdef __LITTLE_ENDIAN
646	/*
647	* firmware revision, model, and serial number have Big Endian Byte
648	* order in Word. Convert all three to little endian.
649	*
650	* See CF+ and CompactFlash Specification Revision 2.0:
651	* 6.2.1.6: Identify Drive, Table 39 for more details
652	*/
653
654	strswab(dev_desc->revision);
655	strswab(dev_desc->vendor);
656	strswab(dev_desc->product);
657	#endif /* __LITTLE_ENDIAN */
658
659	if ((iop.config & 0x0080) == 0x0080)
660	dev_desc->removable = 1;
661	else
662	dev_desc->removable = 0;
663
664	#ifdef CONFIG_ATAPI
665	if (dev_desc->if_type == IF_TYPE_ATAPI) {
666	atapi_inquiry(dev_desc);
667	return;
668	}
669	#endif /* CONFIG_ATAPI */
670
671	#ifdef __BIG_ENDIAN
672	/* swap shorts */
673	dev_desc->lba = (iop.lba_capacity << 16) \| (iop.lba_capacity >> 16);
674	#else /* ! __BIG_ENDIAN */
675	/*
676	* do not swap shorts on little endian
677	*
678	* See CF+ and CompactFlash Specification Revision 2.0:
679	* 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
680	*/
681	dev_desc->lba = iop.lba_capacity;
682	#endif /* __BIG_ENDIAN */
683
684	#ifdef CONFIG_LBA48
685	if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
686	dev_desc->lba48 = 1;
687	dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] \|
688	((unsigned long long) iop.lba48_capacity[1] << 16) \|
689	((unsigned long long) iop.lba48_capacity[2] << 32) \|
690	((unsigned long long) iop.lba48_capacity[3] << 48);
691	} else {
692	dev_desc->lba48 = 0;
693	}
694	#endif /* CONFIG_LBA48 */
695	/* assuming HD */
696	dev_desc->type = DEV_TYPE_HARDDISK;
697	dev_desc->blksz = ATA_BLOCKSIZE;
698	dev_desc->log2blksz = LOG2(dev_desc->blksz);
699	dev_desc->lun = 0; /* just to fill something in... */
700
701	#if 0 /* only used to test the powersaving mode,
702	* if enabled, the drive goes after 5 sec
703	* in standby mode */
704	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
705	c = ide_wait(device, IDE_TIME_OUT);
706	ide_outb(device, ATA_SECT_CNT, 1);
707	ide_outb(device, ATA_LBA_LOW, 0);
708	ide_outb(device, ATA_LBA_MID, 0);
709	ide_outb(device, ATA_LBA_HIGH, 0);
710	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
711	ide_outb(device, ATA_COMMAND, 0xe3);
712	udelay(50);
713	c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
714	#endif
715	}
716
717	__weak void ide_led(uchar led, uchar status)
718	{
719	#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
720	static uchar led_buffer; /* Buffer for current LED status */
721
722	uchar *led_port = LED_PORT;
723
724	if (status) /* switch LED on */
725	led_buffer \|= led;
726	else /* switch LED off */
727	led_buffer &= ~led;
728
729	*led_port = led_buffer;
730	#endif
731	}
732
733	__weak void ide_outb(int dev, int port, unsigned char val)
734	{
735	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
736	dev, port, val,
737	(ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
738
739	#if defined(CONFIG_IDE_AHB)
740	if (port) {
741	/* write command */
742	ide_write_register(dev, port, val);
743	} else {
744	/* write data */
745	outb(val, (ATA_CURR_BASE(dev)));
746	}
747	#else
748	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
749	#endif
750	}
751
752	__weak unsigned char ide_inb(int dev, int port)
753	{
754	uchar val;
755
756	#if defined(CONFIG_IDE_AHB)
757	val = ide_read_register(dev, port);
758	#else
759	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
760	#endif
761
762	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
763	dev, port,
764	(ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
765	return val;
766	}
767
768	void ide_init(void)
769	{
770	unsigned char c;
771	int i, bus;
772
773	#ifdef CONFIG_IDE_8xx_PCCARD
774	extern int ide_devices_found; /* Initialized in check_ide_device() */
775	#endif /* CONFIG_IDE_8xx_PCCARD */
776
777	#ifdef CONFIG_IDE_PREINIT
778	WATCHDOG_RESET();
779
780	if (ide_preinit()) {
781	puts("ide_preinit failed\n");
782	return;
783	}
784	#endif /* CONFIG_IDE_PREINIT */
785
786	WATCHDOG_RESET();
787
788	/*
789	* Reset the IDE just to be sure.
790	* Light LED's to show
791	*/
792	ide_led((LED_IDE1 \| LED_IDE2), 1); /* LED's on */
793
794	/* ATAPI Drives seems to need a proper IDE Reset */
795	ide_reset();
796
797	#ifdef CONFIG_IDE_INIT_POSTRESET
798	WATCHDOG_RESET();
799
800	if (ide_init_postreset()) {
801	puts("ide_preinit_postreset failed\n");
802	return;
803	}
804	#endif /* CONFIG_IDE_INIT_POSTRESET */
805
806	/*
807	* Wait for IDE to get ready.
808	* According to spec, this can take up to 31 seconds!
809	*/
810	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
811	int dev =
812	bus * (CONFIG_SYS_IDE_MAXDEVICE /
813	CONFIG_SYS_IDE_MAXBUS);
814
815	#ifdef CONFIG_IDE_8xx_PCCARD
816	/* Skip non-ide devices from probing */
817	if ((ide_devices_found & (1 << bus)) == 0) {
818	ide_led((LED_IDE1 \| LED_IDE2), 0); /* LED's off */
819	continue;
820	}
821	#endif
822	printf("Bus %d: ", bus);
823
824	ide_bus_ok[bus] = 0;
825
826	/* Select device
827	*/
828	udelay(100000); /* 100 ms */
829	ide_outb(dev, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(dev));
830	udelay(100000); /* 100 ms */
831	i = 0;
832	do {
833	udelay(10000); /* 10 ms */
834
835	c = ide_inb(dev, ATA_STATUS);
836	i++;
837	if (i > (ATA_RESET_TIME * 100)) {
838	puts(" Timeout \n");
839	/* LED's off */
840	ide_led((LED_IDE1 \| LED_IDE2), 0);
841	return;
842	}
843	if ((i >= 100) && ((i % 100) == 0))
844	putc('.');
845
846	} while (c & ATA_STAT_BUSY);
847
848	if (c & (ATA_STAT_BUSY \| ATA_STAT_FAULT)) {
849	puts("not available ");
850	debug("Status = 0x%02X ", c);
851	#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
852	} else if ((c & ATA_STAT_READY) == 0) {
853	puts("not available ");
854	debug("Status = 0x%02X ", c);
855	#endif
856	} else {
857	puts("OK ");
858	ide_bus_ok[bus] = 1;
859	}
860	WATCHDOG_RESET();
861	}
862
863	putc('\n');
864
865	ide_led((LED_IDE1 \| LED_IDE2), 0); /* LED's off */
866
867	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
868	int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
869	ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
870	ide_dev_desc[i].if_type = IF_TYPE_IDE;
871	ide_dev_desc[i].devnum = i;
872	ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
873	ide_dev_desc[i].blksz = 0;
874	ide_dev_desc[i].log2blksz =
875	LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
876	ide_dev_desc[i].lba = 0;
877	#ifndef CONFIG_BLK
878	ide_dev_desc[i].block_read = ide_read;
879	ide_dev_desc[i].block_write = ide_write;
880	#endif
881	if (!ide_bus_ok[IDE_BUS(i)])
882	continue;
883	ide_led(led, 1); /* LED on */
884	ide_ident(&ide_dev_desc[i]);
885	ide_led(led, 0); /* LED off */
886	dev_print(&ide_dev_desc[i]);
887
888	if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
889	/* initialize partition type */
890	part_init(&ide_dev_desc[i]);
891	}
892	}
893	WATCHDOG_RESET();
894	}
895
896	/* We only need to swap data if we are running on a big endian cpu. */
897	#if defined(__LITTLE_ENDIAN)
898	__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
899	{
900	ide_input_data(dev, sect_buf, words);
901	}
902	#else
903	__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
904	{
905	volatile ushort *pbuf =
906	(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
907	ushort dbuf = (ushort )sect_buf;
908
909	debug("in input swap data base for read is %lx\n",
910	(unsigned long) pbuf);
911
912	while (words--) {
913	#ifdef __MIPS__
914	dbuf++ = swab16p((u16 )pbuf);
915	dbuf++ = swab16p((u16 )pbuf);
916	#else
917	*dbuf++ = ld_le16(pbuf);
918	*dbuf++ = ld_le16(pbuf);
919	#endif /* !MIPS */
920	}
921	}
922	#endif /* __LITTLE_ENDIAN */
923
924
925	#if defined(CONFIG_IDE_SWAP_IO)
926	__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
927	{
928	ushort *dbuf;
929	volatile ushort *pbuf;
930
931	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
932	dbuf = (ushort *)sect_buf;
933	while (words--) {
934	EIEIO;
935	pbuf = dbuf++;
936	EIEIO;
937	pbuf = dbuf++;
938	}
939	}
940	#else /* ! CONFIG_IDE_SWAP_IO */
941	__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
942	{
943	#if defined(CONFIG_IDE_AHB)
944	ide_write_data(dev, sect_buf, words);
945	#else
946	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
947	#endif
948	}
949	#endif /* CONFIG_IDE_SWAP_IO */
950
951	#if defined(CONFIG_IDE_SWAP_IO)
952	__weak void ide_input_data(int dev, ulong *sect_buf, int words)
953	{
954	ushort *dbuf;
955	volatile ushort *pbuf;
956
957	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
958	dbuf = (ushort *)sect_buf;
959
960	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
961
962	while (words--) {
963	EIEIO;
964	dbuf++ = pbuf;
965	EIEIO;
966	dbuf++ = pbuf;
967	}
968	}
969	#else /* ! CONFIG_IDE_SWAP_IO */
970	__weak void ide_input_data(int dev, ulong *sect_buf, int words)
971	{
972	#if defined(CONFIG_IDE_AHB)
973	ide_read_data(dev, sect_buf, words);
974	#else
975	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
976	#endif
977	}
978
979	#endif /* CONFIG_IDE_SWAP_IO */
980
981	#ifdef CONFIG_BLK
982	ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
983	void *buffer)
984	#else
985	ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
986	void *buffer)
987	#endif
988	{
989	#ifdef CONFIG_BLK
990	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
991	#endif
992	int device = block_dev->devnum;
993	ulong n = 0;
994	unsigned char c;
995	unsigned char pwrsave = 0; /* power save */
996
997	#ifdef CONFIG_LBA48
998	unsigned char lba48 = 0;
999
1000	if (blknr & 0x0000fffff0000000ULL) {
1001	/* more than 28 bits used, use 48bit mode */
1002	lba48 = 1;
1003	}
1004	#endif
1005	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
1006	device, blknr, blkcnt, (ulong) buffer);
1007
1008	ide_led(DEVICE_LED(device), 1); /* LED on */
1009
1010	/* Select device
1011	*/
1012	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
1013	c = ide_wait(device, IDE_TIME_OUT);
1014
1015	if (c & ATA_STAT_BUSY) {
1016	printf("IDE read: device %d not ready\n", device);
1017	goto IDE_READ_E;
1018	}
1019
1020	/* first check if the drive is in Powersaving mode, if yes,
1021	* increase the timeout value */
1022	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
1023	udelay(50);
1024
1025	c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
1026
1027	if (c & ATA_STAT_BUSY) {
1028	printf("IDE read: device %d not ready\n", device);
1029	goto IDE_READ_E;
1030	}
1031	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
1032	printf("No Powersaving mode %X\n", c);
1033	} else {
1034	c = ide_inb(device, ATA_SECT_CNT);
1035	debug("Powersaving %02X\n", c);
1036	if (c == 0)
1037	pwrsave = 1;
1038	}
1039
1040
1041	while (blkcnt-- > 0) {
1042	c = ide_wait(device, IDE_TIME_OUT);
1043
1044	if (c & ATA_STAT_BUSY) {
1045	printf("IDE read: device %d not ready\n", device);
1046	break;
1047	}
1048	#ifdef CONFIG_LBA48
1049	if (lba48) {
1050	/* write high bits */
1051	ide_outb(device, ATA_SECT_CNT, 0);
1052	ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
1053	#ifdef CONFIG_SYS_64BIT_LBA
1054	ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
1055	ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
1056	#else
1057	ide_outb(device, ATA_LBA_MID, 0);
1058	ide_outb(device, ATA_LBA_HIGH, 0);
1059	#endif
1060	}
1061	#endif
1062	ide_outb(device, ATA_SECT_CNT, 1);
1063	ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
1064	ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
1065	ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
1066
1067	#ifdef CONFIG_LBA48
1068	if (lba48) {
1069	ide_outb(device, ATA_DEV_HD,
1070	ATA_LBA \| ATA_DEVICE(device));
1071	ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
1072
1073	} else
1074	#endif
1075	{
1076	ide_outb(device, ATA_DEV_HD, ATA_LBA \|
1077	ATA_DEVICE(device) \| ((blknr >> 24) & 0xF));
1078	ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
1079	}
1080
1081	udelay(50);
1082
1083	if (pwrsave) {
1084	/* may take up to 4 sec */
1085	c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
1086	pwrsave = 0;
1087	} else {
1088	/* can't take over 500 ms */
1089	c = ide_wait(device, IDE_TIME_OUT);
1090	}
1091
1092	if ((c & (ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR)) !=
1093	ATA_STAT_DRQ) {
1094	printf("Error (no IRQ) dev %d blk " LBAF
1095	": status %#02x\n", device, blknr, c);
1096	break;
1097	}
1098
1099	ide_input_data(device, buffer, ATA_SECTORWORDS);
1100	(void) ide_inb(device, ATA_STATUS); /* clear IRQ */
1101
1102	++n;
1103	++blknr;
1104	buffer += ATA_BLOCKSIZE;
1105	}
1106	IDE_READ_E:
1107	ide_led(DEVICE_LED(device), 0); /* LED off */
1108	return n;
1109	}
1110
1111	#ifdef CONFIG_BLK
1112	ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
1113	const void *buffer)
1114	#else
1115	ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
1116	const void *buffer)
1117	#endif
1118	{
1119	#ifdef CONFIG_BLK
1120	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
1121	#endif
1122	int device = block_dev->devnum;
1123	ulong n = 0;
1124	unsigned char c;
1125
1126	#ifdef CONFIG_LBA48
1127	unsigned char lba48 = 0;
1128
1129	if (blknr & 0x0000fffff0000000ULL) {
1130	/* more than 28 bits used, use 48bit mode */
1131	lba48 = 1;
1132	}
1133	#endif
1134
1135	ide_led(DEVICE_LED(device), 1); /* LED on */
1136
1137	/* Select device
1138	*/
1139	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
1140
1141	while (blkcnt-- > 0) {
1142	c = ide_wait(device, IDE_TIME_OUT);
1143
1144	if (c & ATA_STAT_BUSY) {
1145	printf("IDE read: device %d not ready\n", device);
1146	goto WR_OUT;
1147	}
1148	#ifdef CONFIG_LBA48
1149	if (lba48) {
1150	/* write high bits */
1151	ide_outb(device, ATA_SECT_CNT, 0);
1152	ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
1153	#ifdef CONFIG_SYS_64BIT_LBA
1154	ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
1155	ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
1156	#else
1157	ide_outb(device, ATA_LBA_MID, 0);
1158	ide_outb(device, ATA_LBA_HIGH, 0);
1159	#endif
1160	}
1161	#endif
1162	ide_outb(device, ATA_SECT_CNT, 1);
1163	ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
1164	ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
1165	ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
1166
1167	#ifdef CONFIG_LBA48
1168	if (lba48) {
1169	ide_outb(device, ATA_DEV_HD,
1170	ATA_LBA \| ATA_DEVICE(device));
1171	ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
1172
1173	} else
1174	#endif
1175	{
1176	ide_outb(device, ATA_DEV_HD, ATA_LBA \|
1177	ATA_DEVICE(device) \| ((blknr >> 24) & 0xF));
1178	ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
1179	}
1180
1181	udelay(50);
1182
1183	/* can't take over 500 ms */
1184	c = ide_wait(device, IDE_TIME_OUT);
1185
1186	if ((c & (ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR)) !=
1187	ATA_STAT_DRQ) {
1188	printf("Error (no IRQ) dev %d blk " LBAF
1189	": status %#02x\n", device, blknr, c);
1190	goto WR_OUT;
1191	}
1192
1193	ide_output_data(device, buffer, ATA_SECTORWORDS);
1194	c = ide_inb(device, ATA_STATUS); /* clear IRQ */
1195	++n;
1196	++blknr;
1197	buffer += ATA_BLOCKSIZE;
1198	}
1199	WR_OUT:
1200	ide_led(DEVICE_LED(device), 0); /* LED off */
1201	return n;
1202	}
1203
1204	#if defined(CONFIG_OF_IDE_FIXUP)
1205	int ide_device_present(int dev)
1206	{
1207	if (dev >= CONFIG_SYS_IDE_MAXBUS)
1208	return 0;
1209	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
1210	}
1211	#endif
1212
1213	#ifdef CONFIG_BLK
1214	static const struct blk_ops ide_blk_ops = {
1215	.read = ide_read,
1216	.write = ide_write,
1217	};
1218
1219	U_BOOT_DRIVER(ide_blk) = {
1220	.name = "ide_blk",
1221	.id = UCLASS_BLK,
1222	.ops = &ide_blk_ops,
1223	};
1224	#else
1225	U_BOOT_LEGACY_BLK(ide) = {
1226	.if_typename = "ide",
1227	.if_type = IF_TYPE_IDE,
1228	.max_devs = CONFIG_SYS_IDE_MAXDEVICE,
1229	.desc = ide_dev_desc,
1230	};
1231	#endif
1232		1	/*

drivers/block/Kconfig

Diff comments View file @ fc843a0

 config BLK
 	bool "Support block devices"
 	depends on DM
 	default y if DM_MMC
 	help
 	  Enable support for block devices, such as SCSI, MMC and USB
 	  flash sticks. These provide a block-level interface which permits
 	  reading, writing and (in some cases) erasing blocks. Block
 	  devices often have a partition table which allows the device to
 	  be partitioned into several areas, called 'partitions' in U-Boot.
 	  A filesystem can be placed in each partition.
 config AHCI
 	bool "Support SATA controllers with driver model"
 	depends on DM
 	help
 	  This enables a uclass for disk controllers in U-Boot. Various driver
 	  types can use this, such as AHCI/SATA. It does not provide any standard
 	  operations at present. The block device interface has not been converted
 	  to driver model.
 config DM_SCSI
 	bool "Support SCSI controllers with driver model"
 	depends on BLK
 	help
 	  This option enables the SCSI (Small Computer System Interface) uclass
 	  which supports SCSI and SATA HDDs. For every device configuration
 	  (IDs/LUNs) a block device is created with RAW read/write and
 	  filesystem support.
 config BLOCK_CACHE
 	bool "Use block device cache"
 	default n
 	help
 	  This option enables a disk-block cache for all block devices.
 	  This is most useful when accessing filesystems under U-Boot since
 	  it will prevent repeated reads from directory structures and other
 	  filesystem data structures.
 menu "SATA/SCSI device support"
 config SATA_CEVA
 	bool "Ceva Sata controller"
 	depends on AHCI
 	depends on DM_SCSI
 	help
 	  This option enables Ceva Sata controller hard IP available on Xilinx
 	  ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
 	  AHCI 1.3 specifications with hot-plug detect feature.
 config DWC_AHCI
 	bool "Enable Synopsys DWC AHCI driver support"
 	select SCSI_AHCI
 	select PHY
 	depends on DM_SCSI
 	help
 	  Enable this driver to support Sata devices through
 	  Synopsys DWC AHCI module.
 endmenu
+config IDE
+	bool "Support IDE controllers"
+	help
+	  Enables support for IDE (Integrated Drive Electronics) hard drives.
+	  This allows access to raw blocks and filesystems on an IDE drive
+	  from U-Boot. See also CMD_IDE which provides an 'ide' command for
+	  performing various IDE operations.

drivers/block/Makefile

Diff comments View file @ fc843a0

 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 obj-$(CONFIG_BLK) += blk-uclass.o
 ifndef CONFIG_BLK
 obj-y += blk_legacy.o
 endif
 obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
 obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o
+obj-$(CONFIG_IDE) += ide.o
 obj-$(CONFIG_IDE_FTIDE020) += ftide020.o
 obj-$(CONFIG_LIBATA) += libata.o
 obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_MX51_PATA) += mxc_ata.o
 obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
 obj-$(CONFIG_SATA_DWC) += sata_dwc.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
 obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o sata_sandbox.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o

drivers/block/ide.c

Diff comments View file @ fc843a0

File was created	1	/*
	2	* (C) Copyright 2000-2011
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <ata.h>
	10	#include <dm.h>
	11	#include <ide.h>
	12	#include <watchdog.h>
	13	#include <asm/io.h>
	14
	15	#ifdef __PPC__
	16	# define EIEIO __asm__ volatile ("eieio")
	17	# define SYNC __asm__ volatile ("sync")
	18	#else
	19	# define EIEIO /* nothing */
	20	# define SYNC /* nothing */
	21	#endif
	22
	23	/* Current offset for IDE0 / IDE1 bus access */
	24	ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
	25	#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
	26	CONFIG_SYS_ATA_IDE0_OFFSET,
	27	#endif
	28	#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
	29	CONFIG_SYS_ATA_IDE1_OFFSET,
	30	#endif
	31	};
	32
	33	static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
	34
	35	struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
	36
	37	#define IDE_TIME_OUT 2000 /* 2 sec timeout */
	38
	39	#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
	40
	41	#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
	42
	43	#ifndef CONFIG_SYS_ATA_PORT_ADDR
	44	#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
	45	#endif
	46
	47	#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
	48	# define DEVICE_LED(x) 0
	49	# define LED_IDE1 1
	50	# define LED_IDE2 2
	51	#endif
	52
	53	#ifdef CONFIG_IDE_RESET
	54	extern void ide_set_reset(int idereset);
	55
	56	static void ide_reset(void)
	57	{
	58	int i;
	59
	60	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
	61	ide_bus_ok[i] = 0;
	62	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
	63	ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
	64
	65	ide_set_reset(1); /* assert reset */
	66
	67	/* the reset signal shall be asserted for et least 25 us */
	68	udelay(25);
	69
	70	WATCHDOG_RESET();
	71
	72	/* de-assert RESET signal */
	73	ide_set_reset(0);
	74
	75	/* wait 250 ms */
	76	for (i = 0; i < 250; ++i)
	77	udelay(1000);
	78	}
	79	#else
	80	#define ide_reset() /* dummy */
	81	#endif /* CONFIG_IDE_RESET */
	82
	83	/*
	84	* Wait until Busy bit is off, or timeout (in ms)
	85	* Return last status
	86	*/
	87	static uchar ide_wait(int dev, ulong t)
	88	{
	89	ulong delay = 10 * t; /* poll every 100 us */
	90	uchar c;
	91
	92	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
	93	udelay(100);
	94	if (delay-- == 0)
	95	break;
	96	}
	97	return c;
	98	}
	99
	100	/*
	101	* copy src to dest, skipping leading and trailing blanks and null
	102	* terminate the string
	103	* "len" is the size of available memory including the terminating '\0'
	104	*/
	105	static void ident_cpy(unsigned char dst, unsigned char src,
	106	unsigned int len)
	107	{
	108	unsigned char end, last;
	109
	110	last = dst;
	111	end = src + len - 1;
	112
	113	/* reserve space for '\0' */
	114	if (len < 2)
	115	goto OUT;
	116
	117	/* skip leading white space */
	118	while ((src) && (src < end) && (src == ' '))
	119	++src;
	120
	121	/* copy string, omitting trailing white space */
	122	while ((*src) && (src < end)) {
	123	dst++ = src;
	124	if (*src++ != ' ')
	125	last = dst;
	126	}
	127	OUT:
	128	*last = '\0';
	129	}
	130
	131	#ifdef CONFIG_ATAPI
	132	/****************************************************************************
	133	* ATAPI Support
	134	*/
	135
	136	#if defined(CONFIG_IDE_SWAP_IO)
	137	/* since ATAPI may use commands with not 4 bytes alligned length
	138	* we have our own transfer functions, 2 bytes alligned */
	139	__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
	140	{
	141	ushort *dbuf;
	142	volatile ushort *pbuf;
	143
	144	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
	145	dbuf = (ushort *)sect_buf;
	146
	147	debug("in output data shorts base for read is %lx\n",
	148	(unsigned long) pbuf);
	149
	150	while (shorts--) {
	151	EIEIO;
	152	pbuf = dbuf++;
	153	}
	154	}
	155
	156	__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
	157	{
	158	ushort *dbuf;
	159	volatile ushort *pbuf;
	160
	161	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
	162	dbuf = (ushort *)sect_buf;
	163
	164	debug("in input data shorts base for read is %lx\n",
	165	(unsigned long) pbuf);
	166
	167	while (shorts--) {
	168	EIEIO;
	169	dbuf++ = pbuf;
	170	}
	171	}
	172
	173	#else /* ! CONFIG_IDE_SWAP_IO */
	174	__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
	175	{
	176	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
	177	}
	178
	179	__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
	180	{
	181	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
	182	}
	183
	184	#endif /* CONFIG_IDE_SWAP_IO */
	185
	186	/*
	187	* Wait until (Status & mask) == res, or timeout (in ms)
	188	* Return last status
	189	* This is used since some ATAPI CD ROMs clears their Busy Bit first
	190	* and then they set their DRQ Bit
	191	*/
	192	static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
	193	{
	194	ulong delay = 10 * t; /* poll every 100 us */
	195	uchar c;
	196
	197	/* prevents to read the status before valid */
	198	c = ide_inb(dev, ATA_DEV_CTL);
	199
	200	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
	201	/* break if error occurs (doesn't make sense to wait more) */
	202	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
	203	break;
	204	udelay(100);
	205	if (delay-- == 0)
	206	break;
	207	}
	208	return c;
	209	}
	210
	211	/*
	212	* issue an atapi command
	213	*/
	214	unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
	215	unsigned char *buffer, int buflen)
	216	{
	217	unsigned char c, err, mask, res;
	218	int n;
	219
	220	ide_led(DEVICE_LED(device), 1); /* LED on */
	221
	222	/* Select device
	223	*/
	224	mask = ATA_STAT_BUSY \| ATA_STAT_DRQ;
	225	res = 0;
	226	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	227	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
	228	if ((c & mask) != res) {
	229	printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
	230	c);
	231	err = 0xFF;
	232	goto AI_OUT;
	233	}
	234	/* write taskfile */
	235	ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
	236	ide_outb(device, ATA_SECT_CNT, 0);
	237	ide_outb(device, ATA_SECT_NUM, 0);
	238	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
	239	ide_outb(device, ATA_CYL_HIGH,
	240	(unsigned char) ((buflen >> 8) & 0xFF));
	241	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	242
	243	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
	244	udelay(50);
	245
	246	mask = ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR;
	247	res = ATA_STAT_DRQ;
	248	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
	249
	250	if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
	251	printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
	252	device, c);
	253	err = 0xFF;
	254	goto AI_OUT;
	255	}
	256
	257	/* write command block */
	258	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
	259
	260	/* ATAPI Command written wait for completition */
	261	udelay(5000); /* device must set bsy */
	262
	263	mask = ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR;
	264	/*
	265	* if no data wait for DRQ = 0 BSY = 0
	266	* if data wait for DRQ = 1 BSY = 0
	267	*/
	268	res = 0;
	269	if (buflen)
	270	res = ATA_STAT_DRQ;
	271	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
	272	if ((c & mask) != res) {
	273	if (c & ATA_STAT_ERR) {
	274	err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
	275	debug("atapi_issue 1 returned sense key %X status %02X\n",
	276	err, c);
	277	} else {
	278	printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
	279	ccb[0], c);
	280	err = 0xFF;
	281	}
	282	goto AI_OUT;
	283	}
	284	n = ide_inb(device, ATA_CYL_HIGH);
	285	n <<= 8;
	286	n += ide_inb(device, ATA_CYL_LOW);
	287	if (n > buflen) {
	288	printf("ERROR, transfer bytes %d requested only %d\n", n,
	289	buflen);
	290	err = 0xff;
	291	goto AI_OUT;
	292	}
	293	if ((n == 0) && (buflen < 0)) {
	294	printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
	295	err = 0xff;
	296	goto AI_OUT;
	297	}
	298	if (n != buflen) {
	299	debug("WARNING, transfer bytes %d not equal with requested %d\n",
	300	n, buflen);
	301	}
	302	if (n != 0) { /* data transfer */
	303	debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
	304	/* we transfer shorts */
	305	n >>= 1;
	306	/* ok now decide if it is an in or output */
	307	if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
	308	debug("Write to device\n");
	309	ide_output_data_shorts(device, (unsigned short *)buffer,
	310	n);
	311	} else {
	312	debug("Read from device @ %p shorts %d\n", buffer, n);
	313	ide_input_data_shorts(device, (unsigned short *)buffer,
	314	n);
	315	}
	316	}
	317	udelay(5000); /* seems that some CD ROMs need this... */
	318	mask = ATA_STAT_BUSY \| ATA_STAT_ERR;
	319	res = 0;
	320	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
	321	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
	322	err = (ide_inb(device, ATA_ERROR_REG) >> 4);
	323	debug("atapi_issue 2 returned sense key %X status %X\n", err,
	324	c);
	325	} else {
	326	err = 0;
	327	}
	328	AI_OUT:
	329	ide_led(DEVICE_LED(device), 0); /* LED off */
	330	return err;
	331	}
	332
	333	/*
	334	* sending the command to atapi_issue. If an status other than good
	335	* returns, an request_sense will be issued
	336	*/
	337
	338	#define ATAPI_DRIVE_NOT_READY 100
	339	#define ATAPI_UNIT_ATTN 10
	340
	341	unsigned char atapi_issue_autoreq(int device,
	342	unsigned char *ccb,
	343	int ccblen,
	344	unsigned char *buffer, int buflen)
	345	{
	346	unsigned char sense_data[18], sense_ccb[12];
	347	unsigned char res, key, asc, ascq;
	348	int notready, unitattn;
	349
	350	unitattn = ATAPI_UNIT_ATTN;
	351	notready = ATAPI_DRIVE_NOT_READY;
	352
	353	retry:
	354	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
	355	if (res == 0)
	356	return 0; /* Ok */
	357
	358	if (res == 0xFF)
	359	return 0xFF; /* error */
	360
	361	debug("(auto_req)atapi_issue returned sense key %X\n", res);
	362
	363	memset(sense_ccb, 0, sizeof(sense_ccb));
	364	memset(sense_data, 0, sizeof(sense_data));
	365	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
	366	sense_ccb[4] = 18; /* allocation Length */
	367
	368	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
	369	key = (sense_data[2] & 0xF);
	370	asc = (sense_data[12]);
	371	ascq = (sense_data[13]);
	372
	373	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
	374	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
	375	sense_data[0], key, asc, ascq);
	376
	377	if ((key == 0))
	378	return 0; /* ok device ready */
	379
	380	if ((key == 6) \|\| (asc == 0x29) \|\| (asc == 0x28)) { /* Unit Attention */
	381	if (unitattn-- > 0) {
	382	udelay(200 * 1000);
	383	goto retry;
	384	}
	385	printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
	386	goto error;
	387	}
	388	if ((asc == 0x4) && (ascq == 0x1)) {
	389	/* not ready, but will be ready soon */
	390	if (notready-- > 0) {
	391	udelay(200 * 1000);
	392	goto retry;
	393	}
	394	printf("Drive not ready, tried %d times\n",
	395	ATAPI_DRIVE_NOT_READY);
	396	goto error;
	397	}
	398	if (asc == 0x3a) {
	399	debug("Media not present\n");
	400	goto error;
	401	}
	402
	403	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
	404	ascq);
	405	error:
	406	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
	407	return 0xFF;
	408	}
	409
	410	/*
	411	* atapi_read:
	412	* we transfer only one block per command, since the multiple DRQ per
	413	* command is not yet implemented
	414	*/
	415	#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
	416	#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
	417	#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
	418
	419	ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
	420	void *buffer)
	421	{
	422	int device = block_dev->devnum;
	423	ulong n = 0;
	424	unsigned char ccb[12]; /* Command descriptor block */
	425	ulong cnt;
	426
	427	debug("atapi_read dev %d start " LBAF " blocks " LBAF
	428	" buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
	429
	430	do {
	431	if (blkcnt > ATAPI_READ_MAX_BLOCK)
	432	cnt = ATAPI_READ_MAX_BLOCK;
	433	else
	434	cnt = blkcnt;
	435
	436	ccb[0] = ATAPI_CMD_READ_12;
	437	ccb[1] = 0; /* reserved */
	438	ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
	439	ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
	440	ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
	441	ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
	442	ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
	443	ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
	444	ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
	445	ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
	446	ccb[10] = 0; /* reserved */
	447	ccb[11] = 0; /* reserved */
	448
	449	if (atapi_issue_autoreq(device, ccb, 12,
	450	(unsigned char *)buffer,
	451	cnt * ATAPI_READ_BLOCK_SIZE)
	452	== 0xFF) {
	453	return n;
	454	}
	455	n += cnt;
	456	blkcnt -= cnt;
	457	blknr += cnt;
	458	buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
	459	} while (blkcnt > 0);
	460	return n;
	461	}
	462
	463	static void atapi_inquiry(struct blk_desc *dev_desc)
	464	{
	465	unsigned char ccb[12]; /* Command descriptor block */
	466	unsigned char iobuf[64]; /* temp buf */
	467	unsigned char c;
	468	int device;
	469
	470	device = dev_desc->devnum;
	471	dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
	472	dev_desc->block_read = atapi_read;
	473
	474	memset(ccb, 0, sizeof(ccb));
	475	memset(iobuf, 0, sizeof(iobuf));
	476
	477	ccb[0] = ATAPI_CMD_INQUIRY;
	478	ccb[4] = 40; /* allocation Legnth */
	479	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
	480
	481	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
	482	if (c != 0)
	483	return;
	484
	485	/* copy device ident strings */
	486	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
	487	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
	488	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
	489
	490	dev_desc->lun = 0;
	491	dev_desc->lba = 0;
	492	dev_desc->blksz = 0;
	493	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
	494	dev_desc->type = iobuf[0] & 0x1f;
	495
	496	if ((iobuf[1] & 0x80) == 0x80)
	497	dev_desc->removable = 1;
	498	else
	499	dev_desc->removable = 0;
	500
	501	memset(ccb, 0, sizeof(ccb));
	502	memset(iobuf, 0, sizeof(iobuf));
	503	ccb[0] = ATAPI_CMD_START_STOP;
	504	ccb[4] = 0x03; /* start */
	505
	506	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
	507
	508	debug("ATAPI_CMD_START_STOP returned %x\n", c);
	509	if (c != 0)
	510	return;
	511
	512	memset(ccb, 0, sizeof(ccb));
	513	memset(iobuf, 0, sizeof(iobuf));
	514	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
	515
	516	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
	517	if (c != 0)
	518	return;
	519
	520	memset(ccb, 0, sizeof(ccb));
	521	memset(iobuf, 0, sizeof(iobuf));
	522	ccb[0] = ATAPI_CMD_READ_CAP;
	523	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
	524	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
	525	if (c != 0)
	526	return;
	527
	528	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
	529	iobuf[0], iobuf[1], iobuf[2], iobuf[3],
	530	iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
	531
	532	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
	533	((unsigned long) iobuf[1] << 16) +
	534	((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
	535	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
	536	((unsigned long) iobuf[5] << 16) +
	537	((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
	538	dev_desc->log2blksz = LOG2(dev_desc->blksz);
	539	#ifdef CONFIG_LBA48
	540	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
	541	dev_desc->lba48 = 0;
	542	#endif
	543	return;
	544	}
	545
	546	#endif /* CONFIG_ATAPI */
	547
	548	static void ide_ident(struct blk_desc *dev_desc)
	549	{
	550	unsigned char c;
	551	hd_driveid_t iop;
	552
	553	#ifdef CONFIG_ATAPI
	554	int retries = 0;
	555	#endif
	556	int device;
	557
	558	device = dev_desc->devnum;
	559	printf(" Device %d: ", device);
	560
	561	ide_led(DEVICE_LED(device), 1); /* LED on */
	562	/* Select device
	563	*/
	564	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	565	dev_desc->if_type = IF_TYPE_IDE;
	566	#ifdef CONFIG_ATAPI
	567
	568	retries = 0;
	569
	570	/* Warning: This will be tricky to read */
	571	while (retries <= 1) {
	572	/* check signature */
	573	if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
	574	(ide_inb(device, ATA_SECT_NUM) == 0x01) &&
	575	(ide_inb(device, ATA_CYL_LOW) == 0x14) &&
	576	(ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
	577	/* ATAPI Signature found */
	578	dev_desc->if_type = IF_TYPE_ATAPI;
	579	/*
	580	* Start Ident Command
	581	*/
	582	ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
	583	/*
	584	* Wait for completion - ATAPI devices need more time
	585	* to become ready
	586	*/
	587	c = ide_wait(device, ATAPI_TIME_OUT);
	588	} else
	589	#endif
	590	{
	591	/*
	592	* Start Ident Command
	593	*/
	594	ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
	595
	596	/*
	597	* Wait for completion
	598	*/
	599	c = ide_wait(device, IDE_TIME_OUT);
	600	}
	601	ide_led(DEVICE_LED(device), 0); /* LED off */
	602
	603	if (((c & ATA_STAT_DRQ) == 0) \|\|
	604	((c & (ATA_STAT_FAULT \| ATA_STAT_ERR)) != 0)) {
	605	#ifdef CONFIG_ATAPI
	606	{
	607	/*
	608	* Need to soft reset the device
	609	* in case it's an ATAPI...
	610	*/
	611	debug("Retrying...\n");
	612	ide_outb(device, ATA_DEV_HD,
	613	ATA_LBA \| ATA_DEVICE(device));
	614	udelay(100000);
	615	ide_outb(device, ATA_COMMAND, 0x08);
	616	udelay(500000); /* 500 ms */
	617	}
	618	/*
	619	* Select device
	620	*/
	621	ide_outb(device, ATA_DEV_HD,
	622	ATA_LBA \| ATA_DEVICE(device));
	623	retries++;
	624	#else
	625	return;
	626	#endif
	627	}
	628	#ifdef CONFIG_ATAPI
	629	else
	630	break;
	631	} /* see above - ugly to read */
	632
	633	if (retries == 2) /* Not found */
	634	return;
	635	#endif
	636
	637	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
	638
	639	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
	640	sizeof(dev_desc->revision));
	641	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
	642	sizeof(dev_desc->vendor));
	643	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
	644	sizeof(dev_desc->product));
	645	#ifdef __LITTLE_ENDIAN
	646	/*
	647	* firmware revision, model, and serial number have Big Endian Byte
	648	* order in Word. Convert all three to little endian.
	649	*
	650	* See CF+ and CompactFlash Specification Revision 2.0:
	651	* 6.2.1.6: Identify Drive, Table 39 for more details
	652	*/
	653
	654	strswab(dev_desc->revision);
	655	strswab(dev_desc->vendor);
	656	strswab(dev_desc->product);
	657	#endif /* __LITTLE_ENDIAN */
	658
	659	if ((iop.config & 0x0080) == 0x0080)
	660	dev_desc->removable = 1;
	661	else
	662	dev_desc->removable = 0;
	663
	664	#ifdef CONFIG_ATAPI
	665	if (dev_desc->if_type == IF_TYPE_ATAPI) {
	666	atapi_inquiry(dev_desc);
	667	return;
	668	}
	669	#endif /* CONFIG_ATAPI */
	670
	671	#ifdef __BIG_ENDIAN
	672	/* swap shorts */
	673	dev_desc->lba = (iop.lba_capacity << 16) \| (iop.lba_capacity >> 16);
	674	#else /* ! __BIG_ENDIAN */
	675	/*
	676	* do not swap shorts on little endian
	677	*
	678	* See CF+ and CompactFlash Specification Revision 2.0:
	679	* 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
	680	*/
	681	dev_desc->lba = iop.lba_capacity;
	682	#endif /* __BIG_ENDIAN */
	683
	684	#ifdef CONFIG_LBA48
	685	if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
	686	dev_desc->lba48 = 1;
	687	dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] \|
	688	((unsigned long long) iop.lba48_capacity[1] << 16) \|
	689	((unsigned long long) iop.lba48_capacity[2] << 32) \|
	690	((unsigned long long) iop.lba48_capacity[3] << 48);
	691	} else {
	692	dev_desc->lba48 = 0;
	693	}
	694	#endif /* CONFIG_LBA48 */
	695	/* assuming HD */
	696	dev_desc->type = DEV_TYPE_HARDDISK;
	697	dev_desc->blksz = ATA_BLOCKSIZE;
	698	dev_desc->log2blksz = LOG2(dev_desc->blksz);
	699	dev_desc->lun = 0; /* just to fill something in... */
	700
	701	#if 0 /* only used to test the powersaving mode,
	702	* if enabled, the drive goes after 5 sec
	703	* in standby mode */
	704	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	705	c = ide_wait(device, IDE_TIME_OUT);
	706	ide_outb(device, ATA_SECT_CNT, 1);
	707	ide_outb(device, ATA_LBA_LOW, 0);
	708	ide_outb(device, ATA_LBA_MID, 0);
	709	ide_outb(device, ATA_LBA_HIGH, 0);
	710	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	711	ide_outb(device, ATA_COMMAND, 0xe3);
	712	udelay(50);
	713	c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
	714	#endif
	715	}
	716
	717	__weak void ide_led(uchar led, uchar status)
	718	{
	719	#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
	720	static uchar led_buffer; /* Buffer for current LED status */
	721
	722	uchar *led_port = LED_PORT;
	723
	724	if (status) /* switch LED on */
	725	led_buffer \|= led;
	726	else /* switch LED off */
	727	led_buffer &= ~led;
	728
	729	*led_port = led_buffer;
	730	#endif
	731	}
	732
	733	__weak void ide_outb(int dev, int port, unsigned char val)
	734	{
	735	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
	736	dev, port, val,
	737	(ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
	738
	739	#if defined(CONFIG_IDE_AHB)
	740	if (port) {
	741	/* write command */
	742	ide_write_register(dev, port, val);
	743	} else {
	744	/* write data */
	745	outb(val, (ATA_CURR_BASE(dev)));
	746	}
	747	#else
	748	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
	749	#endif
	750	}
	751
	752	__weak unsigned char ide_inb(int dev, int port)
	753	{
	754	uchar val;
	755
	756	#if defined(CONFIG_IDE_AHB)
	757	val = ide_read_register(dev, port);
	758	#else
	759	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
	760	#endif
	761
	762	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
	763	dev, port,
	764	(ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
	765	return val;
	766	}
	767
	768	void ide_init(void)
	769	{
	770	unsigned char c;
	771	int i, bus;
	772
	773	#ifdef CONFIG_IDE_8xx_PCCARD
	774	extern int ide_devices_found; /* Initialized in check_ide_device() */
	775	#endif /* CONFIG_IDE_8xx_PCCARD */
	776
	777	#ifdef CONFIG_IDE_PREINIT
	778	WATCHDOG_RESET();
	779
	780	if (ide_preinit()) {
	781	puts("ide_preinit failed\n");
	782	return;
	783	}
	784	#endif /* CONFIG_IDE_PREINIT */
	785
	786	WATCHDOG_RESET();
	787
	788	/*
	789	* Reset the IDE just to be sure.
	790	* Light LED's to show
	791	*/
	792	ide_led((LED_IDE1 \| LED_IDE2), 1); /* LED's on */
	793
	794	/* ATAPI Drives seems to need a proper IDE Reset */
	795	ide_reset();
	796
	797	#ifdef CONFIG_IDE_INIT_POSTRESET
	798	WATCHDOG_RESET();
	799
	800	if (ide_init_postreset()) {
	801	puts("ide_preinit_postreset failed\n");
	802	return;
	803	}
	804	#endif /* CONFIG_IDE_INIT_POSTRESET */
	805
	806	/*
	807	* Wait for IDE to get ready.
	808	* According to spec, this can take up to 31 seconds!
	809	*/
	810	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
	811	int dev =
	812	bus * (CONFIG_SYS_IDE_MAXDEVICE /
	813	CONFIG_SYS_IDE_MAXBUS);
	814
	815	#ifdef CONFIG_IDE_8xx_PCCARD
	816	/* Skip non-ide devices from probing */
	817	if ((ide_devices_found & (1 << bus)) == 0) {
	818	ide_led((LED_IDE1 \| LED_IDE2), 0); /* LED's off */
	819	continue;
	820	}
	821	#endif
	822	printf("Bus %d: ", bus);
	823
	824	ide_bus_ok[bus] = 0;
	825
	826	/* Select device
	827	*/
	828	udelay(100000); /* 100 ms */
	829	ide_outb(dev, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(dev));
	830	udelay(100000); /* 100 ms */
	831	i = 0;
	832	do {
	833	udelay(10000); /* 10 ms */
	834
	835	c = ide_inb(dev, ATA_STATUS);
	836	i++;
	837	if (i > (ATA_RESET_TIME * 100)) {
	838	puts(" Timeout \n");
	839	/* LED's off */
	840	ide_led((LED_IDE1 \| LED_IDE2), 0);
	841	return;
	842	}
	843	if ((i >= 100) && ((i % 100) == 0))
	844	putc('.');
	845
	846	} while (c & ATA_STAT_BUSY);
	847
	848	if (c & (ATA_STAT_BUSY \| ATA_STAT_FAULT)) {
	849	puts("not available ");
	850	debug("Status = 0x%02X ", c);
	851	#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
	852	} else if ((c & ATA_STAT_READY) == 0) {
	853	puts("not available ");
	854	debug("Status = 0x%02X ", c);
	855	#endif
	856	} else {
	857	puts("OK ");
	858	ide_bus_ok[bus] = 1;
	859	}
	860	WATCHDOG_RESET();
	861	}
	862
	863	putc('\n');
	864
	865	ide_led((LED_IDE1 \| LED_IDE2), 0); /* LED's off */
	866
	867	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
	868	int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
	869	ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
	870	ide_dev_desc[i].if_type = IF_TYPE_IDE;
	871	ide_dev_desc[i].devnum = i;
	872	ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
	873	ide_dev_desc[i].blksz = 0;
	874	ide_dev_desc[i].log2blksz =
	875	LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
	876	ide_dev_desc[i].lba = 0;
	877	#ifndef CONFIG_BLK
	878	ide_dev_desc[i].block_read = ide_read;
	879	ide_dev_desc[i].block_write = ide_write;
	880	#endif
	881	if (!ide_bus_ok[IDE_BUS(i)])
	882	continue;
	883	ide_led(led, 1); /* LED on */
	884	ide_ident(&ide_dev_desc[i]);
	885	ide_led(led, 0); /* LED off */
	886	dev_print(&ide_dev_desc[i]);
	887
	888	if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
	889	/* initialize partition type */
	890	part_init(&ide_dev_desc[i]);
	891	}
	892	}
	893	WATCHDOG_RESET();
	894	}
	895
	896	/* We only need to swap data if we are running on a big endian cpu. */
	897	#if defined(__LITTLE_ENDIAN)
	898	__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
	899	{
	900	ide_input_data(dev, sect_buf, words);
	901	}
	902	#else
	903	__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
	904	{
	905	volatile ushort *pbuf =
	906	(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
	907	ushort dbuf = (ushort )sect_buf;
	908
	909	debug("in input swap data base for read is %lx\n",
	910	(unsigned long) pbuf);
	911
	912	while (words--) {
	913	#ifdef __MIPS__
	914	dbuf++ = swab16p((u16 )pbuf);
	915	dbuf++ = swab16p((u16 )pbuf);
	916	#else
	917	*dbuf++ = ld_le16(pbuf);
	918	*dbuf++ = ld_le16(pbuf);
	919	#endif /* !MIPS */
	920	}
	921	}
	922	#endif /* __LITTLE_ENDIAN */
	923
	924
	925	#if defined(CONFIG_IDE_SWAP_IO)
	926	__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
	927	{
	928	ushort *dbuf;
	929	volatile ushort *pbuf;
	930
	931	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
	932	dbuf = (ushort *)sect_buf;
	933	while (words--) {
	934	EIEIO;
	935	pbuf = dbuf++;
	936	EIEIO;
	937	pbuf = dbuf++;
	938	}
	939	}
	940	#else /* ! CONFIG_IDE_SWAP_IO */
	941	__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
	942	{
	943	#if defined(CONFIG_IDE_AHB)
	944	ide_write_data(dev, sect_buf, words);
	945	#else
	946	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
	947	#endif
	948	}
	949	#endif /* CONFIG_IDE_SWAP_IO */
	950
	951	#if defined(CONFIG_IDE_SWAP_IO)
	952	__weak void ide_input_data(int dev, ulong *sect_buf, int words)
	953	{
	954	ushort *dbuf;
	955	volatile ushort *pbuf;
	956
	957	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
	958	dbuf = (ushort *)sect_buf;
	959
	960	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
	961
	962	while (words--) {
	963	EIEIO;
	964	dbuf++ = pbuf;
	965	EIEIO;
	966	dbuf++ = pbuf;
	967	}
	968	}
	969	#else /* ! CONFIG_IDE_SWAP_IO */
	970	__weak void ide_input_data(int dev, ulong *sect_buf, int words)
	971	{
	972	#if defined(CONFIG_IDE_AHB)
	973	ide_read_data(dev, sect_buf, words);
	974	#else
	975	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
	976	#endif
	977	}
	978
	979	#endif /* CONFIG_IDE_SWAP_IO */
	980
	981	#ifdef CONFIG_BLK
	982	ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
	983	void *buffer)
	984	#else
	985	ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
	986	void *buffer)
	987	#endif
	988	{
	989	#ifdef CONFIG_BLK
	990	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
	991	#endif
	992	int device = block_dev->devnum;
	993	ulong n = 0;
	994	unsigned char c;
	995	unsigned char pwrsave = 0; /* power save */
	996
	997	#ifdef CONFIG_LBA48
	998	unsigned char lba48 = 0;
	999
	1000	if (blknr & 0x0000fffff0000000ULL) {
	1001	/* more than 28 bits used, use 48bit mode */
	1002	lba48 = 1;
	1003	}
	1004	#endif
	1005	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
	1006	device, blknr, blkcnt, (ulong) buffer);
	1007
	1008	ide_led(DEVICE_LED(device), 1); /* LED on */
	1009
	1010	/* Select device
	1011	*/
	1012	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	1013	c = ide_wait(device, IDE_TIME_OUT);
	1014
	1015	if (c & ATA_STAT_BUSY) {
	1016	printf("IDE read: device %d not ready\n", device);
	1017	goto IDE_READ_E;
	1018	}
	1019
	1020	/* first check if the drive is in Powersaving mode, if yes,
	1021	* increase the timeout value */
	1022	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
	1023	udelay(50);
	1024
	1025	c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
	1026
	1027	if (c & ATA_STAT_BUSY) {
	1028	printf("IDE read: device %d not ready\n", device);
	1029	goto IDE_READ_E;
	1030	}
	1031	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
	1032	printf("No Powersaving mode %X\n", c);
	1033	} else {
	1034	c = ide_inb(device, ATA_SECT_CNT);
	1035	debug("Powersaving %02X\n", c);
	1036	if (c == 0)
	1037	pwrsave = 1;
	1038	}
	1039
	1040
	1041	while (blkcnt-- > 0) {
	1042	c = ide_wait(device, IDE_TIME_OUT);
	1043
	1044	if (c & ATA_STAT_BUSY) {
	1045	printf("IDE read: device %d not ready\n", device);
	1046	break;
	1047	}
	1048	#ifdef CONFIG_LBA48
	1049	if (lba48) {
	1050	/* write high bits */
	1051	ide_outb(device, ATA_SECT_CNT, 0);
	1052	ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
	1053	#ifdef CONFIG_SYS_64BIT_LBA
	1054	ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
	1055	ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
	1056	#else
	1057	ide_outb(device, ATA_LBA_MID, 0);
	1058	ide_outb(device, ATA_LBA_HIGH, 0);
	1059	#endif
	1060	}
	1061	#endif
	1062	ide_outb(device, ATA_SECT_CNT, 1);
	1063	ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
	1064	ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
	1065	ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
	1066
	1067	#ifdef CONFIG_LBA48
	1068	if (lba48) {
	1069	ide_outb(device, ATA_DEV_HD,
	1070	ATA_LBA \| ATA_DEVICE(device));
	1071	ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
	1072
	1073	} else
	1074	#endif
	1075	{
	1076	ide_outb(device, ATA_DEV_HD, ATA_LBA \|
	1077	ATA_DEVICE(device) \| ((blknr >> 24) & 0xF));
	1078	ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
	1079	}
	1080
	1081	udelay(50);
	1082
	1083	if (pwrsave) {
	1084	/* may take up to 4 sec */
	1085	c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
	1086	pwrsave = 0;
	1087	} else {
	1088	/* can't take over 500 ms */
	1089	c = ide_wait(device, IDE_TIME_OUT);
	1090	}
	1091
	1092	if ((c & (ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR)) !=
	1093	ATA_STAT_DRQ) {
	1094	printf("Error (no IRQ) dev %d blk " LBAF
	1095	": status %#02x\n", device, blknr, c);
	1096	break;
	1097	}
	1098
	1099	ide_input_data(device, buffer, ATA_SECTORWORDS);
	1100	(void) ide_inb(device, ATA_STATUS); /* clear IRQ */
	1101
	1102	++n;
	1103	++blknr;
	1104	buffer += ATA_BLOCKSIZE;
	1105	}
	1106	IDE_READ_E:
	1107	ide_led(DEVICE_LED(device), 0); /* LED off */
	1108	return n;
	1109	}
	1110
	1111	#ifdef CONFIG_BLK
	1112	ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
	1113	const void *buffer)
	1114	#else
	1115	ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
	1116	const void *buffer)
	1117	#endif
	1118	{
	1119	#ifdef CONFIG_BLK
	1120	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
	1121	#endif
	1122	int device = block_dev->devnum;
	1123	ulong n = 0;
	1124	unsigned char c;
	1125
	1126	#ifdef CONFIG_LBA48
	1127	unsigned char lba48 = 0;
	1128
	1129	if (blknr & 0x0000fffff0000000ULL) {
	1130	/* more than 28 bits used, use 48bit mode */
	1131	lba48 = 1;
	1132	}
	1133	#endif
	1134
	1135	ide_led(DEVICE_LED(device), 1); /* LED on */
	1136
	1137	/* Select device
	1138	*/
	1139	ide_outb(device, ATA_DEV_HD, ATA_LBA \| ATA_DEVICE(device));
	1140
	1141	while (blkcnt-- > 0) {
	1142	c = ide_wait(device, IDE_TIME_OUT);
	1143
	1144	if (c & ATA_STAT_BUSY) {
	1145	printf("IDE read: device %d not ready\n", device);
	1146	goto WR_OUT;
	1147	}
	1148	#ifdef CONFIG_LBA48
	1149	if (lba48) {
	1150	/* write high bits */
	1151	ide_outb(device, ATA_SECT_CNT, 0);
	1152	ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
	1153	#ifdef CONFIG_SYS_64BIT_LBA
	1154	ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
	1155	ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
	1156	#else
	1157	ide_outb(device, ATA_LBA_MID, 0);
	1158	ide_outb(device, ATA_LBA_HIGH, 0);
	1159	#endif
	1160	}
	1161	#endif
	1162	ide_outb(device, ATA_SECT_CNT, 1);
	1163	ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
	1164	ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
	1165	ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
	1166
	1167	#ifdef CONFIG_LBA48
	1168	if (lba48) {
	1169	ide_outb(device, ATA_DEV_HD,
	1170	ATA_LBA \| ATA_DEVICE(device));
	1171	ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
	1172
	1173	} else
	1174	#endif
	1175	{
	1176	ide_outb(device, ATA_DEV_HD, ATA_LBA \|
	1177	ATA_DEVICE(device) \| ((blknr >> 24) & 0xF));
	1178	ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
	1179	}
	1180
	1181	udelay(50);
	1182
	1183	/* can't take over 500 ms */
	1184	c = ide_wait(device, IDE_TIME_OUT);
	1185
	1186	if ((c & (ATA_STAT_DRQ \| ATA_STAT_BUSY \| ATA_STAT_ERR)) !=
	1187	ATA_STAT_DRQ) {
	1188	printf("Error (no IRQ) dev %d blk " LBAF
	1189	": status %#02x\n", device, blknr, c);
	1190	goto WR_OUT;
	1191	}
	1192
	1193	ide_output_data(device, buffer, ATA_SECTORWORDS);
	1194	c = ide_inb(device, ATA_STATUS); /* clear IRQ */
	1195	++n;
	1196	++blknr;
	1197	buffer += ATA_BLOCKSIZE;
	1198	}
	1199	WR_OUT:
	1200	ide_led(DEVICE_LED(device), 0); /* LED off */
	1201	return n;
	1202	}
	1203
	1204	#if defined(CONFIG_OF_IDE_FIXUP)
	1205	int ide_device_present(int dev)
	1206	{
	1207	if (dev >= CONFIG_SYS_IDE_MAXBUS)
	1208	return 0;
	1209	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
	1210	}
	1211	#endif
	1212
	1213	#ifdef CONFIG_BLK
	1214	static const struct blk_ops ide_blk_ops = {
	1215	.read = ide_read,
	1216	.write = ide_write,
	1217	};
	1218
	1219	U_BOOT_DRIVER(ide_blk) = {
	1220	.name = "ide_blk",
	1221	.id = UCLASS_BLK,
	1222	.ops = &ide_blk_ops,
	1223	};
	1224	#else
	1225	U_BOOT_LEGACY_BLK(ide) = {
	1226	.if_typename = "ide",
	1227	.if_type = IF_TYPE_IDE,
	1228	.max_devs = CONFIG_SYS_IDE_MAXDEVICE,
	1229	.desc = ide_dev_desc,
	1230	};
	1231	#endif
	1232

drivers/block/sil680.c

Diff comments View file @ fc843a0

drivers/pcmcia/marubun_pcmcia.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Marubun MR-SHPC-01 PCMCIA controller device driver	2	* Marubun MR-SHPC-01 PCMCIA controller device driver
3	*	3	*
4	* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>	4	* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	#include <common.h>	9	#include <common.h>
10	#include <config.h>	10	#include <config.h>
11	#include <pcmcia.h>	11	#include <pcmcia.h>
12	#include <asm/io.h>	12	#include <asm/io.h>
13		13
14	#undef CONFIG_PCMCIA	14	#undef CONFIG_PCMCIA
15		15
16	#if defined(CONFIG_CMD_PCMCIA)	16	#if defined(CONFIG_CMD_PCMCIA)
17	#define CONFIG_PCMCIA	17	#define CONFIG_PCMCIA
18	#endif	18	#endif
19		19
20	#if defined(CONFIG_CMD_IDE)	20	#if defined(CONFIG_IDE)
21	#define CONFIG_PCMCIA	21	#define CONFIG_PCMCIA
22	#endif	22	#endif
23		23
24	#if defined(CONFIG_PCMCIA)	24	#if defined(CONFIG_PCMCIA)
25		25
26	/* MR-SHPC-01 register */	26	/* MR-SHPC-01 register */
27	#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4)	27	#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4)
28	#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6)	28	#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6)
29	#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8)	29	#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8)
30	#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10)	30	#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10)
31	#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12)	31	#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12)
32	#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14)	32	#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14)
33	#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16)	33	#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16)
34	#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18)	34	#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18)
35	#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20)	35	#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20)
36	#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22)	36	#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22)
37	#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24)	37	#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24)
38	#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26)	38	#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26)
39	#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28)	39	#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28)
40	#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)	40	#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)
41		41
42	int pcmcia_on (void)	42	int pcmcia_on (void)
43	{	43	{
44	printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");	44	printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
45		45
46	/* Init */	46	/* Init */
47	outw( 0x0000 , MRSHPC_MODE );	47	outw( 0x0000 , MRSHPC_MODE );
48		48
49	if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */	49	if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */
50	if ((inw(MRSHPC_CSR) & 0x0080) == 0){	50	if ((inw(MRSHPC_CSR) & 0x0080) == 0){
51	outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */	51	outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
52	}else{	52	}else{
53	outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */	53	outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */
54	}	54	}
55	udelay( 100000 ); /* wait for power on */	55	udelay( 100000 ); /* wait for power on */
56	}else{	56	}else{
57	return 1;	57	return 1;
58	}	58	}
59	/*	59	/*
60	* PC-Card window open	60	* PC-Card window open
61	* flag == COMMON/ATTRIBUTE/IO	61	* flag == COMMON/ATTRIBUTE/IO
62	*/	62	*/
63	/* common window open */	63	/* common window open */
64	outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */	64	outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
65	if ((inw(MRSHPC_CSR) & 0x4000) != 0)	65	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
66	outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */	66	outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
67	else	67	else
68	outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */	68	outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
69		69
70	/* attribute window open */	70	/* attribute window open */
71	outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */	71	outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
72	if ((inw(MRSHPC_CSR) & 0x4000) != 0)	72	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
73	outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */	73	outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
74	else	74	else
75	outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */	75	outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
76		76
77	/* I/O window open */	77	/* I/O window open */
78	outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */	78	outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
79	outw(0x0008,MRSHPC_CDCR); /* I/O card mode */	79	outw(0x0008,MRSHPC_CDCR); /* I/O card mode */
80	if ((inw(MRSHPC_CSR) & 0x4000) != 0)	80	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
81	outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */	81	outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
82	else	82	else
83	outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */	83	outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
84		84
85	outw(0x0000,MRSHPC_ISR);	85	outw(0x0000,MRSHPC_ISR);
86	outw(0x2000,MRSHPC_ICR);	86	outw(0x2000,MRSHPC_ICR);
87	outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));	87	outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));
88	outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));	88	outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));
89		89
90	return 0;	90	return 0;
91	}	91	}
92		92
93	int pcmcia_off (void)	93	int pcmcia_off (void)
94	{	94	{
95	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");	95	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
96		96
97	return 0;	97	return 0;
98	}	98	}
99		99
100	#endif /* CONFIG_PCMCIA */	100	#endif /* CONFIG_PCMCIA */
101		101

drivers/pcmcia/mpc8xx_pcmcia.c

Diff comments View file @ fc843a0

1	#include <common.h>	1	#include <common.h>
2	#include <mpc8xx.h>	2	#include <mpc8xx.h>
3	#include <pcmcia.h>	3	#include <pcmcia.h>
4	#include <linux/compiler.h>	4	#include <linux/compiler.h>
5		5
6	#undef CONFIG_PCMCIA	6	#undef CONFIG_PCMCIA
7		7
8	#if defined(CONFIG_CMD_PCMCIA)	8	#if defined(CONFIG_CMD_PCMCIA)
9	#define CONFIG_PCMCIA	9	#define CONFIG_PCMCIA
10	#endif	10	#endif
11		11
12	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)	12	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
13	#define CONFIG_PCMCIA	13	#define CONFIG_PCMCIA
14	#endif	14	#endif
15		15
16	#if defined(CONFIG_PCMCIA)	16	#if defined(CONFIG_PCMCIA)
17		17
18	#if defined(CONFIG_IDE_8xx_PCCARD)	18	#if defined(CONFIG_IDE_8xx_PCCARD)
19	extern int check_ide_device (int slot);	19	extern int check_ide_device (int slot);
20	#endif	20	#endif
21		21
22	extern int pcmcia_hardware_enable (int slot);	22	extern int pcmcia_hardware_enable (int slot);
23	extern int pcmcia_voltage_set(int slot, int vcc, int vpp);	23	extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
24		24
25	#if defined(CONFIG_CMD_PCMCIA)	25	#if defined(CONFIG_CMD_PCMCIA)
26	extern int pcmcia_hardware_disable(int slot);	26	extern int pcmcia_hardware_disable(int slot);
27	#endif	27	#endif
28		28
29	static u_int m8xx_get_graycode(u_int size);	29	static u_int m8xx_get_graycode(u_int size);
30	#if 0 /* Disabled */	30	#if 0 /* Disabled */
31	static u_int m8xx_get_speed(u_int ns, u_int is_io);	31	static u_int m8xx_get_speed(u_int ns, u_int is_io);
32	#endif	32	#endif
33		33
34	/* look up table for pgcrx registers */	34	/* look up table for pgcrx registers */
35	u_int *pcmcia_pgcrx[2] = {	35	u_int *pcmcia_pgcrx[2] = {
36	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,	36	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,
37	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,	37	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,
38	};	38	};
39		39
40	/*	40	/*
41	* Search this table to see if the windowsize is	41	* Search this table to see if the windowsize is
42	* supported...	42	* supported...
43	*/	43	*/
44		44
45	#define M8XX_SIZES_NO 32	45	#define M8XX_SIZES_NO 32
46		46
47	static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =	47	static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
48	{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,	48	{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
49	0x00000080, 0x00000040, 0x00000010, 0x00000020,	49	0x00000080, 0x00000040, 0x00000010, 0x00000020,
50	0x00008000, 0x00004000, 0x00001000, 0x00002000,	50	0x00008000, 0x00004000, 0x00001000, 0x00002000,
51	0x00000100, 0x00000200, 0x00000800, 0x00000400,	51	0x00000100, 0x00000200, 0x00000800, 0x00000400,
52		52
53	0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,	53	0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
54	0x01000000, 0x02000000, 0xffffffff, 0x04000000,	54	0x01000000, 0x02000000, 0xffffffff, 0x04000000,
55	0x00010000, 0x00020000, 0x00080000, 0x00040000,	55	0x00010000, 0x00020000, 0x00080000, 0x00040000,
56	0x00800000, 0x00400000, 0x00100000, 0x00200000 };	56	0x00800000, 0x00400000, 0x00100000, 0x00200000 };
57		57
58		58
59	/* -------------------------------------------------------------------- */	59	/* -------------------------------------------------------------------- */
60		60
61	#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \	61	#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \
62	\| PCMCIA_SST(4) \	62	\| PCMCIA_SST(4) \
63	\| PCMCIA_SL(9))	63	\| PCMCIA_SL(9))
64		64
65	/* -------------------------------------------------------------------- */	65	/* -------------------------------------------------------------------- */
66		66
67	int pcmcia_on (void)	67	int pcmcia_on (void)
68	{	68	{
69	u_long reg, base;	69	u_long reg, base;
70	pcmcia_win_t *win;	70	pcmcia_win_t *win;
71	u_int rc, slot;	71	u_int rc, slot;
72	__maybe_unused u_int slotbit;	72	__maybe_unused u_int slotbit;
73	int i;	73	int i;
74		74
75	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");	75	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
76		76
77	/* intialize the fixed memory windows */	77	/* intialize the fixed memory windows */
78	win = (pcmcia_win_t )(&((immap_t )CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);	78	win = (pcmcia_win_t )(&((immap_t )CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
79	base = CONFIG_SYS_PCMCIA_MEM_ADDR;	79	base = CONFIG_SYS_PCMCIA_MEM_ADDR;
80		80
81	if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {	81	if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {
82	printf ("Cannot set window size to 0x%08x\n",	82	printf ("Cannot set window size to 0x%08x\n",
83	CONFIG_SYS_PCMCIA_MEM_SIZE);	83	CONFIG_SYS_PCMCIA_MEM_SIZE);
84	return (1);	84	return (1);
85	}	85	}
86		86
87	slotbit = PCMCIA_SLOT_x;	87	slotbit = PCMCIA_SLOT_x;
88	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {	88	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
89	win->br = base;	89	win->br = base;
90		90
91	#if (PCMCIA_SOCKETS_NO == 2)	91	#if (PCMCIA_SOCKETS_NO == 2)
92	if (i == 4) /* Another slot starting from win 4 */	92	if (i == 4) /* Another slot starting from win 4 */
93	slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);	93	slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
94	#endif	94	#endif
95	switch (i) {	95	switch (i) {
96	#ifdef CONFIG_IDE_8xx_PCCARD	96	#ifdef CONFIG_IDE_8xx_PCCARD
97	case 4:	97	case 4:
98	case 0: { /* map attribute memory */	98	case 0: { /* map attribute memory */
99	win->or = ( PCMCIA_BSIZE_64M	99	win->or = ( PCMCIA_BSIZE_64M
100	\| PCMCIA_PPS_8	100	\| PCMCIA_PPS_8
101	\| PCMCIA_PRS_ATTR	101	\| PCMCIA_PRS_ATTR
102	\| slotbit	102	\| slotbit
103	\| PCMCIA_PV	103	\| PCMCIA_PV
104	\| CONFIG_SYS_PCMCIA_TIMING );	104	\| CONFIG_SYS_PCMCIA_TIMING );
105	break;	105	break;
106	}	106	}
107	case 5:	107	case 5:
108	case 1: { /* map I/O window for data reg */	108	case 1: { /* map I/O window for data reg */
109	win->or = ( PCMCIA_BSIZE_1K	109	win->or = ( PCMCIA_BSIZE_1K
110	\| PCMCIA_PPS_16	110	\| PCMCIA_PPS_16
111	\| PCMCIA_PRS_IO	111	\| PCMCIA_PRS_IO
112	\| slotbit	112	\| slotbit
113	\| PCMCIA_PV	113	\| PCMCIA_PV
114	\| CONFIG_SYS_PCMCIA_TIMING );	114	\| CONFIG_SYS_PCMCIA_TIMING );
115	break;	115	break;
116	}	116	}
117	case 6:	117	case 6:
118	case 2: { /* map I/O window for cmd/ctrl reg block */	118	case 2: { /* map I/O window for cmd/ctrl reg block */
119	win->or = ( PCMCIA_BSIZE_1K	119	win->or = ( PCMCIA_BSIZE_1K
120	\| PCMCIA_PPS_8	120	\| PCMCIA_PPS_8
121	\| PCMCIA_PRS_IO	121	\| PCMCIA_PRS_IO
122	\| slotbit	122	\| slotbit
123	\| PCMCIA_PV	123	\| PCMCIA_PV
124	\| CONFIG_SYS_PCMCIA_TIMING );	124	\| CONFIG_SYS_PCMCIA_TIMING );
125	break;	125	break;
126	}	126	}
127	#endif /* CONFIG_IDE_8xx_PCCARD */	127	#endif /* CONFIG_IDE_8xx_PCCARD */
128	default: /* set to not valid */	128	default: /* set to not valid */
129	win->or = 0;	129	win->or = 0;
130	break;	130	break;
131	}	131	}
132		132
133	debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",	133	debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
134	i, win->br, win->or);	134	i, win->br, win->or);
135	base += CONFIG_SYS_PCMCIA_MEM_SIZE;	135	base += CONFIG_SYS_PCMCIA_MEM_SIZE;
136	++win;	136	++win;
137	}	137	}
138		138
139	for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {	139	for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
140	/* turn off voltage */	140	/* turn off voltage */
141	if ((rc = pcmcia_voltage_set(slot, 0, 0)))	141	if ((rc = pcmcia_voltage_set(slot, 0, 0)))
142	continue;	142	continue;
143		143
144	/* Enable external hardware */	144	/* Enable external hardware */
145	if ((rc = pcmcia_hardware_enable(slot)))	145	if ((rc = pcmcia_hardware_enable(slot)))
146	continue;	146	continue;
147		147
148	#ifdef CONFIG_IDE_8xx_PCCARD	148	#ifdef CONFIG_IDE_8xx_PCCARD
149	if ((rc = check_ide_device(i)))	149	if ((rc = check_ide_device(i)))
150	continue;	150	continue;
151	#endif	151	#endif
152	}	152	}
153	return rc;	153	return rc;
154	}	154	}
155		155
156	#if defined(CONFIG_CMD_PCMCIA)	156	#if defined(CONFIG_CMD_PCMCIA)
157	int pcmcia_off (void)	157	int pcmcia_off (void)
158	{	158	{
159	int i;	159	int i;
160	pcmcia_win_t *win;	160	pcmcia_win_t *win;
161		161
162	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");	162	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
163		163
164	/* clear interrupt state, and disable interrupts */	164	/* clear interrupt state, and disable interrupts */
165	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);	165	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
166	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);	166	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
167		167
168	/* turn off interrupt and disable CxOE */	168	/* turn off interrupt and disable CxOE */
169	PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;	169	PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
170		170
171	/* turn off memory windows */	171	/* turn off memory windows */
172	win = (pcmcia_win_t )(&((immap_t )CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);	172	win = (pcmcia_win_t )(&((immap_t )CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
173		173
174	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {	174	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
175	/* disable memory window */	175	/* disable memory window */
176	win->or = 0;	176	win->or = 0;
177	++win;	177	++win;
178	}	178	}
179		179
180	/* turn off voltage */	180	/* turn off voltage */
181	pcmcia_voltage_set(_slot_, 0, 0);	181	pcmcia_voltage_set(_slot_, 0, 0);
182		182
183	/* disable external hardware */	183	/* disable external hardware */
184	printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");	184	printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
185	pcmcia_hardware_disable(_slot_);	185	pcmcia_hardware_disable(_slot_);
186	return 0;	186	return 0;
187	}	187	}
188	#endif	188	#endif
189		189
190		190
191	static u_int m8xx_get_graycode(u_int size)	191	static u_int m8xx_get_graycode(u_int size)
192	{	192	{
193	u_int k;	193	u_int k;
194		194
195	for (k = 0; k < M8XX_SIZES_NO; k++) {	195	for (k = 0; k < M8XX_SIZES_NO; k++) {
196	if(m8xx_size_to_gray[k] == size)	196	if(m8xx_size_to_gray[k] == size)
197	break;	197	break;
198	}	198	}
199		199
200	if((k == M8XX_SIZES_NO) \|\| (m8xx_size_to_gray[k] == -1))	200	if((k == M8XX_SIZES_NO) \|\| (m8xx_size_to_gray[k] == -1))
201	k = -1;	201	k = -1;
202		202
203	return k;	203	return k;
204	}	204	}
205		205
206	#if 0	206	#if 0
207		207
208	static u_int m8xx_get_speed(u_int ns, u_int is_io)	208	static u_int m8xx_get_speed(u_int ns, u_int is_io)
209	{	209	{
210	u_int reg, clocks, psst, psl, psht;	210	u_int reg, clocks, psst, psl, psht;
211		211
212	if(!ns) {	212	if(!ns) {
213		213
214	/*	214	/*
215	* We get called with IO maps setup to 0ns	215	* We get called with IO maps setup to 0ns
216	* if not specified by the user.	216	* if not specified by the user.
217	* They should be 255ns.	217	* They should be 255ns.
218	*/	218	*/
219		219
220	if(is_io)	220	if(is_io)
221	ns = 255;	221	ns = 255;
222	else	222	else
223	ns = 100; /* fast memory if 0 */	223	ns = 100; /* fast memory if 0 */
224	}	224	}
225		225
226	/*	226	/*
227	* In PSST, PSL, PSHT fields we tell the controller	227	* In PSST, PSL, PSHT fields we tell the controller
228	* timing parameters in CLKOUT clock cycles.	228	* timing parameters in CLKOUT clock cycles.
229	* CLKOUT is the same as GCLK2_50.	229	* CLKOUT is the same as GCLK2_50.
230	*/	230	*/
231		231
232	/* how we want to adjust the timing - in percent */	232	/* how we want to adjust the timing - in percent */
233		233
234	#define ADJ 180 /* 80 % longer accesstime - to be sure */	234	#define ADJ 180 /* 80 % longer accesstime - to be sure */
235		235
236	clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;	236	clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
237	clocks = (clocks * ADJ) / (100*1000);	237	clocks = (clocks * ADJ) / (100*1000);
238		238
239	if(clocks >= PCMCIA_BMT_LIMIT) {	239	if(clocks >= PCMCIA_BMT_LIMIT) {
240	DEBUG(0, "Max access time limit reached\n");	240	DEBUG(0, "Max access time limit reached\n");
241	clocks = PCMCIA_BMT_LIMIT-1;	241	clocks = PCMCIA_BMT_LIMIT-1;
242	}	242	}
243		243
244	psst = clocks / 7; /* setup time */	244	psst = clocks / 7; /* setup time */
245	psht = clocks / 7; /* hold time */	245	psht = clocks / 7; /* hold time */
246	psl = (clocks * 5) / 7; /* strobe length */	246	psl = (clocks * 5) / 7; /* strobe length */
247		247
248	psst += clocks - (psst + psht + psl);	248	psst += clocks - (psst + psht + psl);
249		249
250	reg = psst << 12;	250	reg = psst << 12;
251	reg \|= psl << 7;	251	reg \|= psl << 7;
252	reg \|= psht << 16;	252	reg \|= psht << 16;
253		253
254	return reg;	254	return reg;
255	}	255	}
256	#endif /* 0 */	256	#endif /* 0 */
257		257
258	#endif /* CONFIG_PCMCIA */	258	#endif /* CONFIG_PCMCIA */
259		259

drivers/pcmcia/tqm8xx_pcmcia.c

Diff comments View file @ fc843a0

1	/* -------------------------------------------------------------------- */	1	/* -------------------------------------------------------------------- */
2	/* TQM8xxL Boards by TQ Components */	2	/* TQM8xxL Boards by TQ Components */
3	/* SC8xx Boards by SinoVee Microsystems */	3	/* SC8xx Boards by SinoVee Microsystems */
4	/* -------------------------------------------------------------------- */	4	/* -------------------------------------------------------------------- */
5	#include <common.h>	5	#include <common.h>
6	#include <asm/io.h>	6	#include <asm/io.h>
7	#ifdef CONFIG_8xx	7	#ifdef CONFIG_8xx
8	#include <mpc8xx.h>	8	#include <mpc8xx.h>
9	#endif	9	#endif
10	#include <pcmcia.h>	10	#include <pcmcia.h>
11		11
12	#undef CONFIG_PCMCIA	12	#undef CONFIG_PCMCIA
13		13
14	#if defined(CONFIG_CMD_PCMCIA)	14	#if defined(CONFIG_CMD_PCMCIA)
15	#define CONFIG_PCMCIA	15	#define CONFIG_PCMCIA
16	#endif	16	#endif
17		17
18	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)	18	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
19	#define CONFIG_PCMCIA	19	#define CONFIG_PCMCIA
20	#endif	20	#endif
21		21
22	#if defined(CONFIG_PCMCIA) \	22	#if defined(CONFIG_PCMCIA) \
23	&& defined(CONFIG_TQM8xxL)	23	&& defined(CONFIG_TQM8xxL)
24		24
25	#if defined(CONFIG_TQM8xxL)	25	#if defined(CONFIG_TQM8xxL)
26	#define PCMCIA_BOARD_MSG "TQM8xxL"	26	#define PCMCIA_BOARD_MSG "TQM8xxL"
27	#endif	27	#endif
28		28
29	static inline void power_config(int slot)	29	static inline void power_config(int slot)
30	{	30	{
31	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	31	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
32	/*	32	/*
33	* Configure Port C pins for	33	* Configure Port C pins for
34	* 5 Volts Enable and 3 Volts enable	34	* 5 Volts Enable and 3 Volts enable
35	*/	35	*/
36	clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 \| 0x0004);	36	clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 \| 0x0004);
37	clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 \| 0x0004);	37	clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 \| 0x0004);
38	}	38	}
39		39
40	static inline void power_off(int slot)	40	static inline void power_off(int slot)
41	{	41	{
42	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	42	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
43	clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 \| 0x0004);	43	clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 \| 0x0004);
44	}	44	}
45		45
46	static inline void power_on_5_0(int slot)	46	static inline void power_on_5_0(int slot)
47	{	47	{
48	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	48	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
49	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004);	49	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004);
50	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 \| 0x0004);	50	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 \| 0x0004);
51	}	51	}
52		52
53	static inline void power_on_3_3(int slot)	53	static inline void power_on_3_3(int slot)
54	{	54	{
55	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	55	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
56	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);	56	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);
57	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 \| 0x0004);	57	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 \| 0x0004);
58	}	58	}
59		59
60	/*	60	/*
61	* Function to retrieve the PIPR register, used for debuging purposes.	61	* Function to retrieve the PIPR register, used for debuging purposes.
62	*/	62	*/
63	static inline uint32_t debug_get_pipr(void)	63	static inline uint32_t debug_get_pipr(void)
64	{	64	{
65	uint32_t pipr = 0;	65	uint32_t pipr = 0;
66	#ifdef DEBUG	66	#ifdef DEBUG
67	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	67	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
68	pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);	68	pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
69	#endif	69	#endif
70	return pipr;	70	return pipr;
71	}	71	}
72		72
73		73
74	static inline int check_card_is_absent(int slot)	74	static inline int check_card_is_absent(int slot)
75	{	75	{
76	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	76	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
77	uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);	77	uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
78	return pipr & (0x18000000 >> (slot << 4));	78	return pipr & (0x18000000 >> (slot << 4));
79	}	79	}
80		80
81	#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE	81	#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
82		82
83	int pcmcia_hardware_enable(int slot)	83	int pcmcia_hardware_enable(int slot)
84	{	84	{
85	immap_t immap = (immap_t )CONFIG_SYS_IMMR;	85	immap_t immap = (immap_t )CONFIG_SYS_IMMR;
86	uint reg, mask;	86	uint reg, mask;
87		87
88	debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);	88	debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
89		89
90	udelay(10000);	90	udelay(10000);
91		91
92	/*	92	/*
93	* Configure SIUMCR to enable PCMCIA port B	93	* Configure SIUMCR to enable PCMCIA port B
94	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)	94	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
95	*/	95	*/
96		96
97	/* Set DBGC to 00 */	97	/* Set DBGC to 00 */
98	clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11);	98	clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11);
99		99
100	/* Clear interrupt state, and disable interrupts */	100	/* Clear interrupt state, and disable interrupts */
101	out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot));	101	out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot));
102	clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot));	102	clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot));
103		103
104	/*	104	/*
105	* Disable interrupts, DMA, and PCMCIA buffers	105	* Disable interrupts, DMA, and PCMCIA buffers
106	* (isolate the interface) and assert RESET signal	106	* (isolate the interface) and assert RESET signal
107	*/	107	*/
108	debug("Disable PCMCIA buffers and assert RESET\n");	108	debug("Disable PCMCIA buffers and assert RESET\n");
109	reg = 0;	109	reg = 0;
110	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */	110	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */
111	reg \|= NSCU_GCRX_CXOE;	111	reg \|= NSCU_GCRX_CXOE;
112		112
113	PCMCIA_PGCRX(slot) = reg;	113	PCMCIA_PGCRX(slot) = reg;
114	udelay(500);	114	udelay(500);
115		115
116	power_config(slot);	116	power_config(slot);
117	power_off(slot);	117	power_off(slot);
118		118
119	/*	119	/*
120	* Make sure there is a card in the slot, then configure the interface.	120	* Make sure there is a card in the slot, then configure the interface.
121	*/	121	*/
122	udelay(10000);	122	udelay(10000);
123	reg = debug_get_pipr();	123	reg = debug_get_pipr();
124	debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,	124	debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
125	&immap->im_pcmcia.pcmc_pipr, reg);	125	&immap->im_pcmcia.pcmc_pipr, reg);
126		126
127	if (check_card_is_absent(slot)) {	127	if (check_card_is_absent(slot)) {
128	printf (" No Card found\n");	128	printf (" No Card found\n");
129	return (1);	129	return (1);
130	}	130	}
131		131
132	/*	132	/*
133	* Power On.	133	* Power On.
134	*/	134	*/
135	mask = PCMCIA_VS1(slot) \| PCMCIA_VS2(slot);	135	mask = PCMCIA_VS1(slot) \| PCMCIA_VS2(slot);
136	reg = in_be32(&immap->im_pcmcia.pcmc_pipr);	136	reg = in_be32(&immap->im_pcmcia.pcmc_pipr);
137	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",	137	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
138	reg,	138	reg,
139	(reg & PCMCIA_VS1(slot)) ? "n" : "ff",	139	(reg & PCMCIA_VS1(slot)) ? "n" : "ff",
140	(reg & PCMCIA_VS2(slot)) ? "n" : "ff");	140	(reg & PCMCIA_VS2(slot)) ? "n" : "ff");
141		141
142	if ((reg & mask) == mask) {	142	if ((reg & mask) == mask) {
143	power_on_5_0(slot);	143	power_on_5_0(slot);
144	puts (" 5.0V card found: ");	144	puts (" 5.0V card found: ");
145	} else {	145	} else {
146	power_on_3_3(slot);	146	power_on_3_3(slot);
147	puts (" 3.3V card found: ");	147	puts (" 3.3V card found: ");
148	}	148	}
149		149
150	#if 0	150	#if 0
151	/* VCC switch error flag, PCMCIA slot INPACK_ pin */	151	/* VCC switch error flag, PCMCIA slot INPACK_ pin */
152	cp->cp_pbdir &= ~(0x0020 \| 0x0010);	152	cp->cp_pbdir &= ~(0x0020 \| 0x0010);
153	cp->cp_pbpar &= ~(0x0020 \| 0x0010);	153	cp->cp_pbpar &= ~(0x0020 \| 0x0010);
154	udelay(500000);	154	udelay(500000);
155	#endif	155	#endif
156		156
157	udelay(1000);	157	udelay(1000);
158	debug("Enable PCMCIA buffers and stop RESET\n");	158	debug("Enable PCMCIA buffers and stop RESET\n");
159	reg = PCMCIA_PGCRX(slot);	159	reg = PCMCIA_PGCRX(slot);
160	reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */	160	reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
161	reg \|= __MY_PCMCIA_GCRX_CXOE; /* active low */	161	reg \|= __MY_PCMCIA_GCRX_CXOE; /* active low */
162	reg &= ~NSCU_GCRX_CXOE;	162	reg &= ~NSCU_GCRX_CXOE;
163		163
164	PCMCIA_PGCRX(slot) = reg;	164	PCMCIA_PGCRX(slot) = reg;
165		165
166	udelay(250000); /* some cards need >150 ms to come up :-( */	166	udelay(250000); /* some cards need >150 ms to come up :-( */
167		167
168	debug("# hardware_enable done\n");	168	debug("# hardware_enable done\n");
169		169
170	return (0);	170	return (0);
171	}	171	}
172		172
173		173
174	#if defined(CONFIG_CMD_PCMCIA)	174	#if defined(CONFIG_CMD_PCMCIA)
175	int pcmcia_hardware_disable(int slot)	175	int pcmcia_hardware_disable(int slot)
176	{	176	{
177	u_long reg;	177	u_long reg;
178		178
179	debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);	179	debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
180		180
181	/* remove all power */	181	/* remove all power */
182	power_off(slot);	182	power_off(slot);
183		183
184	debug("Disable PCMCIA buffers and assert RESET\n");	184	debug("Disable PCMCIA buffers and assert RESET\n");
185	reg = 0;	185	reg = 0;
186	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */	186	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */
187	reg \|= NSCU_GCRX_CXOE; /* active low */	187	reg \|= NSCU_GCRX_CXOE; /* active low */
188		188
189	PCMCIA_PGCRX(slot) = reg;	189	PCMCIA_PGCRX(slot) = reg;
190		190
191	udelay(10000);	191	udelay(10000);
192		192
193	return (0);	193	return (0);
194	}	194	}
195	#endif	195	#endif
196		196
197	int pcmcia_voltage_set(int slot, int vcc, int vpp)	197	int pcmcia_voltage_set(int slot, int vcc, int vpp)
198	{	198	{
199	u_long reg;	199	u_long reg;
200	uint32_t pipr = 0;	200	uint32_t pipr = 0;
201		201
202	debug("voltage_set: " PCMCIA_BOARD_MSG	202	debug("voltage_set: " PCMCIA_BOARD_MSG
203	" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",	203	" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
204	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);	204	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
205		205
206	/*	206	/*
207	* Disable PCMCIA buffers (isolate the interface)	207	* Disable PCMCIA buffers (isolate the interface)
208	* and assert RESET signal	208	* and assert RESET signal
209	*/	209	*/
210	debug("Disable PCMCIA buffers and assert RESET\n");	210	debug("Disable PCMCIA buffers and assert RESET\n");
211	reg = PCMCIA_PGCRX(slot);	211	reg = PCMCIA_PGCRX(slot);
212	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */	212	reg \|= __MY_PCMCIA_GCRX_CXRESET; /* active high */
213	reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */	213	reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
214	reg \|= NSCU_GCRX_CXOE; /* active low */	214	reg \|= NSCU_GCRX_CXOE; /* active low */
215		215
216	PCMCIA_PGCRX(slot) = reg;	216	PCMCIA_PGCRX(slot) = reg;
217	udelay(500);	217	udelay(500);
218		218
219	debug("PCMCIA power OFF\n");	219	debug("PCMCIA power OFF\n");
220	power_config(slot);	220	power_config(slot);
221	power_off(slot);	221	power_off(slot);
222		222
223	switch(vcc) {	223	switch(vcc) {
224	case 0: break;	224	case 0: break;
225	case 33: power_on_3_3(slot); break;	225	case 33: power_on_3_3(slot); break;
226	case 50: power_on_5_0(slot); break;	226	case 50: power_on_5_0(slot); break;
227	default: goto done;	227	default: goto done;
228	}	228	}
229		229
230	/* Checking supported voltages */	230	/* Checking supported voltages */
231	pipr = debug_get_pipr();	231	pipr = debug_get_pipr();
232	debug("PIPR: 0x%x --> %s\n", pipr,	232	debug("PIPR: 0x%x --> %s\n", pipr,
233	(pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");	233	(pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
234		234
235	if (vcc)	235	if (vcc)
236	debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");	236	debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
237	else	237	else
238	debug("PCMCIA powered down\n");	238	debug("PCMCIA powered down\n");
239		239
240	done:	240	done:
241	debug("Enable PCMCIA buffers and stop RESET\n");	241	debug("Enable PCMCIA buffers and stop RESET\n");
242	reg = PCMCIA_PGCRX(slot);	242	reg = PCMCIA_PGCRX(slot);
243	reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */	243	reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
244	reg \|= __MY_PCMCIA_GCRX_CXOE; /* active low */	244	reg \|= __MY_PCMCIA_GCRX_CXOE; /* active low */
245	reg &= ~NSCU_GCRX_CXOE; /* active low */	245	reg &= ~NSCU_GCRX_CXOE; /* active low */
246		246
247	PCMCIA_PGCRX(slot) = reg;	247	PCMCIA_PGCRX(slot) = reg;
248	udelay(500);	248	udelay(500);
249		249
250	debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');	250	debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
251	return 0;	251	return 0;
252	}	252	}
253		253
254	#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */	254	#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */
255		255

fs/fat/fat.c

Diff comments View file @ fc843a0

1	/*	1	/*
2	* fat.c	2	* fat.c
3	*	3	*
4	* R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg	4	* R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg
5	*	5	*
6	* 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6	6	* 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
7	* 2003-03-10 - kharris@nexus-tech.net - ported to uboot	7	* 2003-03-10 - kharris@nexus-tech.net - ported to uboot
8	*	8	*
9	* SPDX-License-Identifier: GPL-2.0+	9	* SPDX-License-Identifier: GPL-2.0+
10	*/	10	*/
11		11
12	#include <common.h>	12	#include <common.h>
13	#include <blk.h>	13	#include <blk.h>
14	#include <config.h>	14	#include <config.h>
15	#include <exports.h>	15	#include <exports.h>
16	#include <fat.h>	16	#include <fat.h>
17	#include <asm/byteorder.h>	17	#include <asm/byteorder.h>
18	#include <part.h>	18	#include <part.h>
19	#include <malloc.h>	19	#include <malloc.h>
20	#include <memalign.h>	20	#include <memalign.h>
21	#include <linux/compiler.h>	21	#include <linux/compiler.h>
22	#include <linux/ctype.h>	22	#include <linux/ctype.h>
23		23
24	#ifdef CONFIG_SUPPORT_VFAT	24	#ifdef CONFIG_SUPPORT_VFAT
25	static const int vfat_enabled = 1;	25	static const int vfat_enabled = 1;
26	#else	26	#else
27	static const int vfat_enabled = 0;	27	static const int vfat_enabled = 0;
28	#endif	28	#endif
29		29
30	/*	30	/*
31	* Convert a string to lowercase.	31	* Convert a string to lowercase.
32	*/	32	*/
33	static void downcase(char *str)	33	static void downcase(char *str)
34	{	34	{
35	while (*str != '\0') {	35	while (*str != '\0') {
36	str = tolower(str);	36	str = tolower(str);
37	str++;	37	str++;
38	}	38	}
39	}	39	}
40		40
41	static struct blk_desc *cur_dev;	41	static struct blk_desc *cur_dev;
42	static disk_partition_t cur_part_info;	42	static disk_partition_t cur_part_info;
43		43
44	#define DOS_BOOT_MAGIC_OFFSET 0x1fe	44	#define DOS_BOOT_MAGIC_OFFSET 0x1fe
45	#define DOS_FS_TYPE_OFFSET 0x36	45	#define DOS_FS_TYPE_OFFSET 0x36
46	#define DOS_FS32_TYPE_OFFSET 0x52	46	#define DOS_FS32_TYPE_OFFSET 0x52
47		47
48	static int disk_read(__u32 block, __u32 nr_blocks, void *buf)	48	static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
49	{	49	{
50	ulong ret;	50	ulong ret;
51		51
52	if (!cur_dev)	52	if (!cur_dev)
53	return -1;	53	return -1;
54		54
55	ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf);	55	ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf);
56		56
57	if (nr_blocks && ret == 0)	57	if (nr_blocks && ret == 0)
58	return -1;	58	return -1;
59		59
60	return ret;	60	return ret;
61	}	61	}
62		62
63	int fat_set_blk_dev(struct blk_desc dev_desc, disk_partition_t info)	63	int fat_set_blk_dev(struct blk_desc dev_desc, disk_partition_t info)
64	{	64	{
65	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);	65	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
66		66
67	cur_dev = dev_desc;	67	cur_dev = dev_desc;
68	cur_part_info = *info;	68	cur_part_info = *info;
69		69
70	/* Make sure it has a valid FAT header */	70	/* Make sure it has a valid FAT header */
71	if (disk_read(0, 1, buffer) != 1) {	71	if (disk_read(0, 1, buffer) != 1) {
72	cur_dev = NULL;	72	cur_dev = NULL;
73	return -1;	73	return -1;
74	}	74	}
75		75
76	/* Check if it's actually a DOS volume */	76	/* Check if it's actually a DOS volume */
77	if (memcmp(buffer + DOS_BOOT_MAGIC_OFFSET, "\x55\xAA", 2)) {	77	if (memcmp(buffer + DOS_BOOT_MAGIC_OFFSET, "\x55\xAA", 2)) {
78	cur_dev = NULL;	78	cur_dev = NULL;
79	return -1;	79	return -1;
80	}	80	}
81		81
82	/* Check for FAT12/FAT16/FAT32 filesystem */	82	/* Check for FAT12/FAT16/FAT32 filesystem */
83	if (!memcmp(buffer + DOS_FS_TYPE_OFFSET, "FAT", 3))	83	if (!memcmp(buffer + DOS_FS_TYPE_OFFSET, "FAT", 3))
84	return 0;	84	return 0;
85	if (!memcmp(buffer + DOS_FS32_TYPE_OFFSET, "FAT32", 5))	85	if (!memcmp(buffer + DOS_FS32_TYPE_OFFSET, "FAT32", 5))
86	return 0;	86	return 0;
87		87
88	cur_dev = NULL;	88	cur_dev = NULL;
89	return -1;	89	return -1;
90	}	90	}
91		91
92	int fat_register_device(struct blk_desc *dev_desc, int part_no)	92	int fat_register_device(struct blk_desc *dev_desc, int part_no)
93	{	93	{
94	disk_partition_t info;	94	disk_partition_t info;
95		95
96	/* First close any currently found FAT filesystem */	96	/* First close any currently found FAT filesystem */
97	cur_dev = NULL;	97	cur_dev = NULL;
98		98
99	/* Read the partition table, if present */	99	/* Read the partition table, if present */
100	if (part_get_info(dev_desc, part_no, &info)) {	100	if (part_get_info(dev_desc, part_no, &info)) {
101	if (part_no != 0) {	101	if (part_no != 0) {
102	printf(" Partition %d not valid on device %d \n",	102	printf(" Partition %d not valid on device %d \n",
103	part_no, dev_desc->devnum);	103	part_no, dev_desc->devnum);
104	return -1;	104	return -1;
105	}	105	}
106		106
107	info.start = 0;	107	info.start = 0;
108	info.size = dev_desc->lba;	108	info.size = dev_desc->lba;
109	info.blksz = dev_desc->blksz;	109	info.blksz = dev_desc->blksz;
110	info.name[0] = 0;	110	info.name[0] = 0;
111	info.type[0] = 0;	111	info.type[0] = 0;
112	info.bootable = 0;	112	info.bootable = 0;
113	#if CONFIG_IS_ENABLED(PARTITION_UUIDS)	113	#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
114	info.uuid[0] = 0;	114	info.uuid[0] = 0;
115	#endif	115	#endif
116	}	116	}
117		117
118	return fat_set_blk_dev(dev_desc, &info);	118	return fat_set_blk_dev(dev_desc, &info);
119	}	119	}
120		120
121	/*	121	/*
122	* Get the first occurence of a directory delimiter ('/' or '\') in a string.	122	* Get the first occurence of a directory delimiter ('/' or '\') in a string.
123	* Return index into string if found, -1 otherwise.	123	* Return index into string if found, -1 otherwise.
124	*/	124	*/
125	static int dirdelim(char *str)	125	static int dirdelim(char *str)
126	{	126	{
127	char *start = str;	127	char *start = str;
128		128
129	while (*str != '\0') {	129	while (*str != '\0') {
130	if (ISDIRDELIM(*str))	130	if (ISDIRDELIM(*str))
131	return str - start;	131	return str - start;
132	str++;	132	str++;
133	}	133	}
134	return -1;	134	return -1;
135	}	135	}
136		136
137	/*	137	/*
138	* Extract zero terminated short name from a directory entry.	138	* Extract zero terminated short name from a directory entry.
139	*/	139	*/
140	static void get_name(dir_entry dirent, char s_name)	140	static void get_name(dir_entry dirent, char s_name)
141	{	141	{
142	char *ptr;	142	char *ptr;
143		143
144	memcpy(s_name, dirent->name, 8);	144	memcpy(s_name, dirent->name, 8);
145	s_name[8] = '\0';	145	s_name[8] = '\0';
146	ptr = s_name;	146	ptr = s_name;
147	while (ptr && ptr != ' ')	147	while (ptr && ptr != ' ')
148	ptr++;	148	ptr++;
149	if (dirent->ext[0] && dirent->ext[0] != ' ') {	149	if (dirent->ext[0] && dirent->ext[0] != ' ') {
150	*ptr = '.';	150	*ptr = '.';
151	ptr++;	151	ptr++;
152	memcpy(ptr, dirent->ext, 3);	152	memcpy(ptr, dirent->ext, 3);
153	ptr[3] = '\0';	153	ptr[3] = '\0';
154	while (ptr && ptr != ' ')	154	while (ptr && ptr != ' ')
155	ptr++;	155	ptr++;
156	}	156	}
157	*ptr = '\0';	157	*ptr = '\0';
158	if (*s_name == DELETED_FLAG)	158	if (*s_name == DELETED_FLAG)
159	*s_name = '\0';	159	*s_name = '\0';
160	else if (*s_name == aRING)	160	else if (*s_name == aRING)
161	*s_name = DELETED_FLAG;	161	*s_name = DELETED_FLAG;
162	downcase(s_name);	162	downcase(s_name);
163	}	163	}
164		164
165	static int flush_dirty_fat_buffer(fsdata *mydata);	165	static int flush_dirty_fat_buffer(fsdata *mydata);
166	#if !defined(CONFIG_FAT_WRITE)	166	#if !defined(CONFIG_FAT_WRITE)
167	/* Stub for read only operation */	167	/* Stub for read only operation */
168	int flush_dirty_fat_buffer(fsdata *mydata)	168	int flush_dirty_fat_buffer(fsdata *mydata)
169	{	169	{
170	(void)(mydata);	170	(void)(mydata);
171	return 0;	171	return 0;
172	}	172	}
173	#endif	173	#endif
174		174
175	/*	175	/*
176	* Get the entry at index 'entry' in a FAT (12/16/32) table.	176	* Get the entry at index 'entry' in a FAT (12/16/32) table.
177	* On failure 0x00 is returned.	177	* On failure 0x00 is returned.
178	*/	178	*/
179	static __u32 get_fatent(fsdata *mydata, __u32 entry)	179	static __u32 get_fatent(fsdata *mydata, __u32 entry)
180	{	180	{
181	__u32 bufnum;	181	__u32 bufnum;
182	__u32 offset, off8;	182	__u32 offset, off8;
183	__u32 ret = 0x00;	183	__u32 ret = 0x00;
184		184
185	if (CHECK_CLUST(entry, mydata->fatsize)) {	185	if (CHECK_CLUST(entry, mydata->fatsize)) {
186	printf("Error: Invalid FAT entry: 0x%08x\n", entry);	186	printf("Error: Invalid FAT entry: 0x%08x\n", entry);
187	return ret;	187	return ret;
188	}	188	}
189		189
190	switch (mydata->fatsize) {	190	switch (mydata->fatsize) {
191	case 32:	191	case 32:
192	bufnum = entry / FAT32BUFSIZE;	192	bufnum = entry / FAT32BUFSIZE;
193	offset = entry - bufnum * FAT32BUFSIZE;	193	offset = entry - bufnum * FAT32BUFSIZE;
194	break;	194	break;
195	case 16:	195	case 16:
196	bufnum = entry / FAT16BUFSIZE;	196	bufnum = entry / FAT16BUFSIZE;
197	offset = entry - bufnum * FAT16BUFSIZE;	197	offset = entry - bufnum * FAT16BUFSIZE;
198	break;	198	break;
199	case 12:	199	case 12:
200	bufnum = entry / FAT12BUFSIZE;	200	bufnum = entry / FAT12BUFSIZE;
201	offset = entry - bufnum * FAT12BUFSIZE;	201	offset = entry - bufnum * FAT12BUFSIZE;
202	break;	202	break;
203		203
204	default:	204	default:
205	/* Unsupported FAT size */	205	/* Unsupported FAT size */
206	return ret;	206	return ret;
207	}	207	}
208		208
209	debug("FAT%d: entry: 0x%08x = %d, offset: 0x%04x = %d\n",	209	debug("FAT%d: entry: 0x%08x = %d, offset: 0x%04x = %d\n",
210	mydata->fatsize, entry, entry, offset, offset);	210	mydata->fatsize, entry, entry, offset, offset);
211		211
212	/* Read a new block of FAT entries into the cache. */	212	/* Read a new block of FAT entries into the cache. */
213	if (bufnum != mydata->fatbufnum) {	213	if (bufnum != mydata->fatbufnum) {
214	__u32 getsize = FATBUFBLOCKS;	214	__u32 getsize = FATBUFBLOCKS;
215	__u8 *bufptr = mydata->fatbuf;	215	__u8 *bufptr = mydata->fatbuf;
216	__u32 fatlength = mydata->fatlength;	216	__u32 fatlength = mydata->fatlength;
217	__u32 startblock = bufnum * FATBUFBLOCKS;	217	__u32 startblock = bufnum * FATBUFBLOCKS;
218		218
219	/* Cap length if fatlength is not a multiple of FATBUFBLOCKS */	219	/* Cap length if fatlength is not a multiple of FATBUFBLOCKS */
220	if (startblock + getsize > fatlength)	220	if (startblock + getsize > fatlength)
221	getsize = fatlength - startblock;	221	getsize = fatlength - startblock;
222		222
223	startblock += mydata->fat_sect; /* Offset from start of disk */	223	startblock += mydata->fat_sect; /* Offset from start of disk */
224		224
225	/* Write back the fatbuf to the disk */	225	/* Write back the fatbuf to the disk */
226	if (flush_dirty_fat_buffer(mydata) < 0)	226	if (flush_dirty_fat_buffer(mydata) < 0)
227	return -1;	227	return -1;
228		228
229	if (disk_read(startblock, getsize, bufptr) < 0) {	229	if (disk_read(startblock, getsize, bufptr) < 0) {
230	debug("Error reading FAT blocks\n");	230	debug("Error reading FAT blocks\n");
231	return ret;	231	return ret;
232	}	232	}
233	mydata->fatbufnum = bufnum;	233	mydata->fatbufnum = bufnum;
234	}	234	}
235		235
236	/* Get the actual entry from the table */	236	/* Get the actual entry from the table */
237	switch (mydata->fatsize) {	237	switch (mydata->fatsize) {
238	case 32:	238	case 32:
239	ret = FAT2CPU32(((__u32 *) mydata->fatbuf)[offset]);	239	ret = FAT2CPU32(((__u32 *) mydata->fatbuf)[offset]);
240	break;	240	break;
241	case 16:	241	case 16:
242	ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);	242	ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);
243	break;	243	break;
244	case 12:	244	case 12:
245	off8 = (offset * 3) / 2;	245	off8 = (offset * 3) / 2;
246	/* fatbut + off8 may be unaligned, read in byte granularity */	246	/* fatbut + off8 may be unaligned, read in byte granularity */
247	ret = mydata->fatbuf[off8] + (mydata->fatbuf[off8 + 1] << 8);	247	ret = mydata->fatbuf[off8] + (mydata->fatbuf[off8 + 1] << 8);
248		248
249	if (offset & 0x1)	249	if (offset & 0x1)
250	ret >>= 4;	250	ret >>= 4;
251	ret &= 0xfff;	251	ret &= 0xfff;
252	}	252	}
253	debug("FAT%d: ret: 0x%08x, entry: 0x%08x, offset: 0x%04x\n",	253	debug("FAT%d: ret: 0x%08x, entry: 0x%08x, offset: 0x%04x\n",
254	mydata->fatsize, ret, entry, offset);	254	mydata->fatsize, ret, entry, offset);
255		255
256	return ret;	256	return ret;
257	}	257	}
258		258
259	/*	259	/*
260	* Read at most 'size' bytes from the specified cluster into 'buffer'.	260	* Read at most 'size' bytes from the specified cluster into 'buffer'.
261	* Return 0 on success, -1 otherwise.	261	* Return 0 on success, -1 otherwise.
262	*/	262	*/
263	static int	263	static int
264	get_cluster(fsdata mydata, __u32 clustnum, __u8 buffer, unsigned long size)	264	get_cluster(fsdata mydata, __u32 clustnum, __u8 buffer, unsigned long size)
265	{	265	{
266	__u32 idx = 0;	266	__u32 idx = 0;
267	__u32 startsect;	267	__u32 startsect;
268	int ret;	268	int ret;
269		269
270	if (clustnum > 0) {	270	if (clustnum > 0) {
271	startsect = mydata->data_begin +	271	startsect = mydata->data_begin +
272	clustnum * mydata->clust_size;	272	clustnum * mydata->clust_size;
273	} else {	273	} else {
274	startsect = mydata->rootdir_sect;	274	startsect = mydata->rootdir_sect;
275	}	275	}
276		276
277	debug("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);	277	debug("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);
278		278
279	if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {	279	if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
280	ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);	280	ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
281		281
282	printf("FAT: Misaligned buffer address (%p)\n", buffer);	282	printf("FAT: Misaligned buffer address (%p)\n", buffer);
283		283
284	while (size >= mydata->sect_size) {	284	while (size >= mydata->sect_size) {
285	ret = disk_read(startsect++, 1, tmpbuf);	285	ret = disk_read(startsect++, 1, tmpbuf);
286	if (ret != 1) {	286	if (ret != 1) {
287	debug("Error reading data (got %d)\n", ret);	287	debug("Error reading data (got %d)\n", ret);
288	return -1;	288	return -1;
289	}	289	}
290		290
291	memcpy(buffer, tmpbuf, mydata->sect_size);	291	memcpy(buffer, tmpbuf, mydata->sect_size);
292	buffer += mydata->sect_size;	292	buffer += mydata->sect_size;
293	size -= mydata->sect_size;	293	size -= mydata->sect_size;
294	}	294	}
295	} else {	295	} else {
296	idx = size / mydata->sect_size;	296	idx = size / mydata->sect_size;
297	ret = disk_read(startsect, idx, buffer);	297	ret = disk_read(startsect, idx, buffer);
298	if (ret != idx) {	298	if (ret != idx) {
299	debug("Error reading data (got %d)\n", ret);	299	debug("Error reading data (got %d)\n", ret);
300	return -1;	300	return -1;
301	}	301	}
302	startsect += idx;	302	startsect += idx;
303	idx *= mydata->sect_size;	303	idx *= mydata->sect_size;
304	buffer += idx;	304	buffer += idx;
305	size -= idx;	305	size -= idx;
306	}	306	}
307	if (size) {	307	if (size) {
308	ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);	308	ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
309		309
310	ret = disk_read(startsect, 1, tmpbuf);	310	ret = disk_read(startsect, 1, tmpbuf);
311	if (ret != 1) {	311	if (ret != 1) {
312	debug("Error reading data (got %d)\n", ret);	312	debug("Error reading data (got %d)\n", ret);
313	return -1;	313	return -1;
314	}	314	}
315		315
316	memcpy(buffer, tmpbuf, size);	316	memcpy(buffer, tmpbuf, size);
317	}	317	}
318		318
319	return 0;	319	return 0;
320	}	320	}
321		321
322	/*	322	/*
323	* Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr'	323	* Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr'
324	* into 'buffer'.	324	* into 'buffer'.
325	* Update the number of bytes read in *gotsize or return -1 on fatal errors.	325	* Update the number of bytes read in *gotsize or return -1 on fatal errors.
326	*/	326	*/
327	__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]	327	__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]
328	__aligned(ARCH_DMA_MINALIGN);	328	__aligned(ARCH_DMA_MINALIGN);
329		329
330	static int get_contents(fsdata mydata, dir_entry dentptr, loff_t pos,	330	static int get_contents(fsdata mydata, dir_entry dentptr, loff_t pos,
331	__u8 buffer, loff_t maxsize, loff_t gotsize)	331	__u8 buffer, loff_t maxsize, loff_t gotsize)
332	{	332	{
333	loff_t filesize = FAT2CPU32(dentptr->size);	333	loff_t filesize = FAT2CPU32(dentptr->size);
334	unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;	334	unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
335	__u32 curclust = START(dentptr);	335	__u32 curclust = START(dentptr);
336	__u32 endclust, newclust;	336	__u32 endclust, newclust;
337	loff_t actsize;	337	loff_t actsize;
338		338
339	*gotsize = 0;	339	*gotsize = 0;
340	debug("Filesize: %llu bytes\n", filesize);	340	debug("Filesize: %llu bytes\n", filesize);
341		341
342	if (pos >= filesize) {	342	if (pos >= filesize) {
343	debug("Read position past EOF: %llu\n", pos);	343	debug("Read position past EOF: %llu\n", pos);
344	return 0;	344	return 0;
345	}	345	}
346		346
347	if (maxsize > 0 && filesize > pos + maxsize)	347	if (maxsize > 0 && filesize > pos + maxsize)
348	filesize = pos + maxsize;	348	filesize = pos + maxsize;
349		349
350	debug("%llu bytes\n", filesize);	350	debug("%llu bytes\n", filesize);
351		351
352	actsize = bytesperclust;	352	actsize = bytesperclust;
353		353
354	/* go to cluster at pos */	354	/* go to cluster at pos */
355	while (actsize <= pos) {	355	while (actsize <= pos) {
356	curclust = get_fatent(mydata, curclust);	356	curclust = get_fatent(mydata, curclust);
357	if (CHECK_CLUST(curclust, mydata->fatsize)) {	357	if (CHECK_CLUST(curclust, mydata->fatsize)) {
358	debug("curclust: 0x%x\n", curclust);	358	debug("curclust: 0x%x\n", curclust);
359	debug("Invalid FAT entry\n");	359	debug("Invalid FAT entry\n");
360	return 0;	360	return 0;
361	}	361	}
362	actsize += bytesperclust;	362	actsize += bytesperclust;
363	}	363	}
364		364
365	/* actsize > pos */	365	/* actsize > pos */
366	actsize -= bytesperclust;	366	actsize -= bytesperclust;
367	filesize -= actsize;	367	filesize -= actsize;
368	pos -= actsize;	368	pos -= actsize;
369		369
370	/* align to beginning of next cluster if any */	370	/* align to beginning of next cluster if any */
371	if (pos) {	371	if (pos) {
372	actsize = min(filesize, (loff_t)bytesperclust);	372	actsize = min(filesize, (loff_t)bytesperclust);
373	if (get_cluster(mydata, curclust, get_contents_vfatname_block,	373	if (get_cluster(mydata, curclust, get_contents_vfatname_block,
374	(int)actsize) != 0) {	374	(int)actsize) != 0) {
375	printf("Error reading cluster\n");	375	printf("Error reading cluster\n");
376	return -1;	376	return -1;
377	}	377	}
378	filesize -= actsize;	378	filesize -= actsize;
379	actsize -= pos;	379	actsize -= pos;
380	memcpy(buffer, get_contents_vfatname_block + pos, actsize);	380	memcpy(buffer, get_contents_vfatname_block + pos, actsize);
381	*gotsize += actsize;	381	*gotsize += actsize;
382	if (!filesize)	382	if (!filesize)
383	return 0;	383	return 0;
384	buffer += actsize;	384	buffer += actsize;
385		385
386	curclust = get_fatent(mydata, curclust);	386	curclust = get_fatent(mydata, curclust);
387	if (CHECK_CLUST(curclust, mydata->fatsize)) {	387	if (CHECK_CLUST(curclust, mydata->fatsize)) {
388	debug("curclust: 0x%x\n", curclust);	388	debug("curclust: 0x%x\n", curclust);
389	debug("Invalid FAT entry\n");	389	debug("Invalid FAT entry\n");
390	return 0;	390	return 0;
391	}	391	}
392	}	392	}
393		393
394	actsize = bytesperclust;	394	actsize = bytesperclust;
395	endclust = curclust;	395	endclust = curclust;
396		396
397	do {	397	do {
398	/* search for consecutive clusters */	398	/* search for consecutive clusters */
399	while (actsize < filesize) {	399	while (actsize < filesize) {
400	newclust = get_fatent(mydata, endclust);	400	newclust = get_fatent(mydata, endclust);
401	if ((newclust - 1) != endclust)	401	if ((newclust - 1) != endclust)
402	goto getit;	402	goto getit;
403	if (CHECK_CLUST(newclust, mydata->fatsize)) {	403	if (CHECK_CLUST(newclust, mydata->fatsize)) {
404	debug("curclust: 0x%x\n", newclust);	404	debug("curclust: 0x%x\n", newclust);
405	debug("Invalid FAT entry\n");	405	debug("Invalid FAT entry\n");
406	return 0;	406	return 0;
407	}	407	}
408	endclust = newclust;	408	endclust = newclust;
409	actsize += bytesperclust;	409	actsize += bytesperclust;
410	}	410	}
411		411
412	/* get remaining bytes */	412	/* get remaining bytes */
413	actsize = filesize;	413	actsize = filesize;
414	if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {	414	if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
415	printf("Error reading cluster\n");	415	printf("Error reading cluster\n");
416	return -1;	416	return -1;
417	}	417	}
418	*gotsize += actsize;	418	*gotsize += actsize;
419	return 0;	419	return 0;
420	getit:	420	getit:
421	if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {	421	if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
422	printf("Error reading cluster\n");	422	printf("Error reading cluster\n");
423	return -1;	423	return -1;
424	}	424	}
425	*gotsize += (int)actsize;	425	*gotsize += (int)actsize;
426	filesize -= actsize;	426	filesize -= actsize;
427	buffer += actsize;	427	buffer += actsize;
428		428
429	curclust = get_fatent(mydata, endclust);	429	curclust = get_fatent(mydata, endclust);
430	if (CHECK_CLUST(curclust, mydata->fatsize)) {	430	if (CHECK_CLUST(curclust, mydata->fatsize)) {
431	debug("curclust: 0x%x\n", curclust);	431	debug("curclust: 0x%x\n", curclust);
432	printf("Invalid FAT entry\n");	432	printf("Invalid FAT entry\n");
433	return 0;	433	return 0;
434	}	434	}
435	actsize = bytesperclust;	435	actsize = bytesperclust;
436	endclust = curclust;	436	endclust = curclust;
437	} while (1);	437	} while (1);
438	}	438	}
439		439
440	/*	440	/*
441	* Extract the file name information from 'slotptr' into 'l_name',	441	* Extract the file name information from 'slotptr' into 'l_name',
442	* starting at l_name[*idx].	442	* starting at l_name[*idx].
443	* Return 1 if terminator (zero byte) is found, 0 otherwise.	443	* Return 1 if terminator (zero byte) is found, 0 otherwise.
444	*/	444	*/
445	static int slot2str(dir_slot slotptr, char l_name, int *idx)	445	static int slot2str(dir_slot slotptr, char l_name, int *idx)
446	{	446	{
447	int j;	447	int j;
448		448
449	for (j = 0; j <= 8; j += 2) {	449	for (j = 0; j <= 8; j += 2) {
450	l_name[*idx] = slotptr->name0_4[j];	450	l_name[*idx] = slotptr->name0_4[j];
451	if (l_name[*idx] == 0x00)	451	if (l_name[*idx] == 0x00)
452	return 1;	452	return 1;
453	(*idx)++;	453	(*idx)++;
454	}	454	}
455	for (j = 0; j <= 10; j += 2) {	455	for (j = 0; j <= 10; j += 2) {
456	l_name[*idx] = slotptr->name5_10[j];	456	l_name[*idx] = slotptr->name5_10[j];
457	if (l_name[*idx] == 0x00)	457	if (l_name[*idx] == 0x00)
458	return 1;	458	return 1;
459	(*idx)++;	459	(*idx)++;
460	}	460	}
461	for (j = 0; j <= 2; j += 2) {	461	for (j = 0; j <= 2; j += 2) {
462	l_name[*idx] = slotptr->name11_12[j];	462	l_name[*idx] = slotptr->name11_12[j];
463	if (l_name[*idx] == 0x00)	463	if (l_name[*idx] == 0x00)
464	return 1;	464	return 1;
465	(*idx)++;	465	(*idx)++;
466	}	466	}
467		467
468	return 0;	468	return 0;
469	}	469	}
470		470
471	/*	471	/*
472	* Extract the full long filename starting at 'retdent' (which is really	472	* Extract the full long filename starting at 'retdent' (which is really
473	* a slot) into 'l_name'. If successful also copy the real directory entry	473	* a slot) into 'l_name'. If successful also copy the real directory entry
474	* into 'retdent'	474	* into 'retdent'
475	* Return 0 on success, -1 otherwise.	475	* Return 0 on success, -1 otherwise.
476	*/	476	*/
477	static int	477	static int
478	get_vfatname(fsdata mydata, int curclust, __u8 cluster,	478	get_vfatname(fsdata mydata, int curclust, __u8 cluster,
479	dir_entry retdent, char l_name)	479	dir_entry retdent, char l_name)
480	{	480	{
481	dir_entry *realdent;	481	dir_entry *realdent;
482	dir_slot slotptr = (dir_slot )retdent;	482	dir_slot slotptr = (dir_slot )retdent;
483	__u8 buflimit = cluster + mydata->sect_size ((curclust == 0) ?	483	__u8 buflimit = cluster + mydata->sect_size ((curclust == 0) ?
484	PREFETCH_BLOCKS :	484	PREFETCH_BLOCKS :
485	mydata->clust_size);	485	mydata->clust_size);
486	__u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;	486	__u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;
487	int idx = 0;	487	int idx = 0;
488		488
489	if (counter > VFAT_MAXSEQ) {	489	if (counter > VFAT_MAXSEQ) {
490	debug("Error: VFAT name is too long\n");	490	debug("Error: VFAT name is too long\n");
491	return -1;	491	return -1;
492	}	492	}
493		493
494	while ((__u8 *)slotptr < buflimit) {	494	while ((__u8 *)slotptr < buflimit) {
495	if (counter == 0)	495	if (counter == 0)
496	break;	496	break;
497	if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter)	497	if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter)
498	return -1;	498	return -1;
499	slotptr++;	499	slotptr++;
500	counter--;	500	counter--;
501	}	501	}
502		502
503	if ((__u8 *)slotptr >= buflimit) {	503	if ((__u8 *)slotptr >= buflimit) {
504	dir_slot *slotptr2;	504	dir_slot *slotptr2;
505		505
506	if (curclust == 0)	506	if (curclust == 0)
507	return -1;	507	return -1;
508	curclust = get_fatent(mydata, curclust);	508	curclust = get_fatent(mydata, curclust);
509	if (CHECK_CLUST(curclust, mydata->fatsize)) {	509	if (CHECK_CLUST(curclust, mydata->fatsize)) {
510	debug("curclust: 0x%x\n", curclust);	510	debug("curclust: 0x%x\n", curclust);
511	printf("Invalid FAT entry\n");	511	printf("Invalid FAT entry\n");
512	return -1;	512	return -1;
513	}	513	}
514		514
515	if (get_cluster(mydata, curclust, get_contents_vfatname_block,	515	if (get_cluster(mydata, curclust, get_contents_vfatname_block,
516	mydata->clust_size * mydata->sect_size) != 0) {	516	mydata->clust_size * mydata->sect_size) != 0) {
517	debug("Error: reading directory block\n");	517	debug("Error: reading directory block\n");
518	return -1;	518	return -1;
519	}	519	}
520		520
521	slotptr2 = (dir_slot *)get_contents_vfatname_block;	521	slotptr2 = (dir_slot *)get_contents_vfatname_block;
522	while (counter > 0) {	522	while (counter > 0) {
523	if (((slotptr2->id & ~LAST_LONG_ENTRY_MASK)	523	if (((slotptr2->id & ~LAST_LONG_ENTRY_MASK)
524	& 0xff) != counter)	524	& 0xff) != counter)
525	return -1;	525	return -1;
526	slotptr2++;	526	slotptr2++;
527	counter--;	527	counter--;
528	}	528	}
529		529
530	/* Save the real directory entry */	530	/* Save the real directory entry */
531	realdent = (dir_entry *)slotptr2;	531	realdent = (dir_entry *)slotptr2;
532	while ((__u8 *)slotptr2 > get_contents_vfatname_block) {	532	while ((__u8 *)slotptr2 > get_contents_vfatname_block) {
533	slotptr2--;	533	slotptr2--;
534	slot2str(slotptr2, l_name, &idx);	534	slot2str(slotptr2, l_name, &idx);
535	}	535	}
536	} else {	536	} else {
537	/* Save the real directory entry */	537	/* Save the real directory entry */
538	realdent = (dir_entry *)slotptr;	538	realdent = (dir_entry *)slotptr;
539	}	539	}
540		540
541	do {	541	do {
542	slotptr--;	542	slotptr--;
543	if (slot2str(slotptr, l_name, &idx))	543	if (slot2str(slotptr, l_name, &idx))
544	break;	544	break;
545	} while (!(slotptr->id & LAST_LONG_ENTRY_MASK));	545	} while (!(slotptr->id & LAST_LONG_ENTRY_MASK));
546		546
547	l_name[idx] = '\0';	547	l_name[idx] = '\0';
548	if (*l_name == DELETED_FLAG)	548	if (*l_name == DELETED_FLAG)
549	*l_name = '\0';	549	*l_name = '\0';
550	else if (*l_name == aRING)	550	else if (*l_name == aRING)
551	*l_name = DELETED_FLAG;	551	*l_name = DELETED_FLAG;
552	downcase(l_name);	552	downcase(l_name);
553		553
554	/* Return the real directory entry */	554	/* Return the real directory entry */
555	memcpy(retdent, realdent, sizeof(dir_entry));	555	memcpy(retdent, realdent, sizeof(dir_entry));
556		556
557	return 0;	557	return 0;
558	}	558	}
559		559
560	/* Calculate short name checksum */	560	/* Calculate short name checksum */
561	static __u8 mkcksum(const char name[8], const char ext[3])	561	static __u8 mkcksum(const char name[8], const char ext[3])
562	{	562	{
563	int i;	563	int i;
564		564
565	__u8 ret = 0;	565	__u8 ret = 0;
566		566
567	for (i = 0; i < 8; i++)	567	for (i = 0; i < 8; i++)
568	ret = (((ret & 1) << 7) \| ((ret & 0xfe) >> 1)) + name[i];	568	ret = (((ret & 1) << 7) \| ((ret & 0xfe) >> 1)) + name[i];
569	for (i = 0; i < 3; i++)	569	for (i = 0; i < 3; i++)
570	ret = (((ret & 1) << 7) \| ((ret & 0xfe) >> 1)) + ext[i];	570	ret = (((ret & 1) << 7) \| ((ret & 0xfe) >> 1)) + ext[i];
571		571
572	return ret;	572	return ret;
573	}	573	}
574		574
575	/*	575	/*
576	* Get the directory entry associated with 'filename' from the directory	576	* Get the directory entry associated with 'filename' from the directory
577	* starting at 'startsect'	577	* starting at 'startsect'
578	*/	578	*/
579	__u8 get_dentfromdir_block[MAX_CLUSTSIZE]	579	__u8 get_dentfromdir_block[MAX_CLUSTSIZE]
580	__aligned(ARCH_DMA_MINALIGN);	580	__aligned(ARCH_DMA_MINALIGN);
581		581
582	static dir_entry get_dentfromdir(fsdata mydata, int startsect,	582	static dir_entry get_dentfromdir(fsdata mydata, int startsect,
583	char filename, dir_entry retdent,	583	char filename, dir_entry retdent,
584	int dols)	584	int dols)
585	{	585	{
586	__u16 prevcksum = 0xffff;	586	__u16 prevcksum = 0xffff;
587	__u32 curclust = START(retdent);	587	__u32 curclust = START(retdent);
588	int files = 0, dirs = 0;	588	int files = 0, dirs = 0;
589		589
590	debug("get_dentfromdir: %s\n", filename);	590	debug("get_dentfromdir: %s\n", filename);
591		591
592	while (1) {	592	while (1) {
593	dir_entry *dentptr;	593	dir_entry *dentptr;
594		594
595	int i;	595	int i;
596		596
597	if (get_cluster(mydata, curclust, get_dentfromdir_block,	597	if (get_cluster(mydata, curclust, get_dentfromdir_block,
598	mydata->clust_size * mydata->sect_size) != 0) {	598	mydata->clust_size * mydata->sect_size) != 0) {
599	debug("Error: reading directory block\n");	599	debug("Error: reading directory block\n");
600	return NULL;	600	return NULL;
601	}	601	}
602		602
603	dentptr = (dir_entry *)get_dentfromdir_block;	603	dentptr = (dir_entry *)get_dentfromdir_block;
604		604
605	for (i = 0; i < DIRENTSPERCLUST; i++) {	605	for (i = 0; i < DIRENTSPERCLUST; i++) {
606	char s_name[14], l_name[VFAT_MAXLEN_BYTES];	606	char s_name[14], l_name[VFAT_MAXLEN_BYTES];
607		607
608	l_name[0] = '\0';	608	l_name[0] = '\0';
609	if (dentptr->name[0] == DELETED_FLAG) {	609	if (dentptr->name[0] == DELETED_FLAG) {
610	dentptr++;	610	dentptr++;
611	continue;	611	continue;
612	}	612	}
613	if ((dentptr->attr & ATTR_VOLUME)) {	613	if ((dentptr->attr & ATTR_VOLUME)) {
614	if (vfat_enabled &&	614	if (vfat_enabled &&
615	(dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&	615	(dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
616	(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {	616	(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
617	prevcksum = ((dir_slot *)dentptr)->alias_checksum;	617	prevcksum = ((dir_slot *)dentptr)->alias_checksum;
618	get_vfatname(mydata, curclust,	618	get_vfatname(mydata, curclust,
619	get_dentfromdir_block,	619	get_dentfromdir_block,
620	dentptr, l_name);	620	dentptr, l_name);
621	if (dols) {	621	if (dols) {
622	int isdir;	622	int isdir;
623	char dirc;	623	char dirc;
624	int doit = 0;	624	int doit = 0;
625		625
626	isdir = (dentptr->attr & ATTR_DIR);	626	isdir = (dentptr->attr & ATTR_DIR);
627		627
628	if (isdir) {	628	if (isdir) {
629	dirs++;	629	dirs++;
630	dirc = '/';	630	dirc = '/';
631	doit = 1;	631	doit = 1;
632	} else {	632	} else {
633	dirc = ' ';	633	dirc = ' ';
634	if (l_name[0] != 0) {	634	if (l_name[0] != 0) {
635	files++;	635	files++;
636	doit = 1;	636	doit = 1;
637	}	637	}
638	}	638	}
639	if (doit) {	639	if (doit) {
640	if (dirc == ' ') {	640	if (dirc == ' ') {
641	printf(" %8u %s%c\n",	641	printf(" %8u %s%c\n",
642	FAT2CPU32(dentptr->size),	642	FAT2CPU32(dentptr->size),
643	l_name,	643	l_name,
644	dirc);	644	dirc);
645	} else {	645	} else {
646	printf(" %s%c\n",	646	printf(" %s%c\n",
647	l_name,	647	l_name,
648	dirc);	648	dirc);
649	}	649	}
650	}	650	}
651	dentptr++;	651	dentptr++;
652	continue;	652	continue;
653	}	653	}
654	debug("vfatname: \|%s\|\n", l_name);	654	debug("vfatname: \|%s\|\n", l_name);
655	} else {	655	} else {
656	/* Volume label or VFAT entry */	656	/* Volume label or VFAT entry */
657	dentptr++;	657	dentptr++;
658	continue;	658	continue;
659	}	659	}
660	}	660	}
661	if (dentptr->name[0] == 0) {	661	if (dentptr->name[0] == 0) {
662	if (dols) {	662	if (dols) {
663	printf("\n%d file(s), %d dir(s)\n\n",	663	printf("\n%d file(s), %d dir(s)\n\n",
664	files, dirs);	664	files, dirs);
665	}	665	}
666	debug("Dentname == NULL - %d\n", i);	666	debug("Dentname == NULL - %d\n", i);
667	return NULL;	667	return NULL;
668	}	668	}
669	if (vfat_enabled) {	669	if (vfat_enabled) {
670	__u8 csum = mkcksum(dentptr->name, dentptr->ext);	670	__u8 csum = mkcksum(dentptr->name, dentptr->ext);
671	if (dols && csum == prevcksum) {	671	if (dols && csum == prevcksum) {
672	prevcksum = 0xffff;	672	prevcksum = 0xffff;
673	dentptr++;	673	dentptr++;
674	continue;	674	continue;
675	}	675	}
676	}	676	}
677		677
678	get_name(dentptr, s_name);	678	get_name(dentptr, s_name);
679	if (dols) {	679	if (dols) {
680	int isdir = (dentptr->attr & ATTR_DIR);	680	int isdir = (dentptr->attr & ATTR_DIR);
681	char dirc;	681	char dirc;
682	int doit = 0;	682	int doit = 0;
683		683
684	if (isdir) {	684	if (isdir) {
685	dirs++;	685	dirs++;
686	dirc = '/';	686	dirc = '/';
687	doit = 1;	687	doit = 1;
688	} else {	688	} else {
689	dirc = ' ';	689	dirc = ' ';
690	if (s_name[0] != 0) {	690	if (s_name[0] != 0) {
691	files++;	691	files++;
692	doit = 1;	692	doit = 1;
693	}	693	}
694	}	694	}
695		695
696	if (doit) {	696	if (doit) {
697	if (dirc == ' ') {	697	if (dirc == ' ') {
698	printf(" %8u %s%c\n",	698	printf(" %8u %s%c\n",
699	FAT2CPU32(dentptr->size),	699	FAT2CPU32(dentptr->size),
700	s_name, dirc);	700	s_name, dirc);
701	} else {	701	} else {
702	printf(" %s%c\n",	702	printf(" %s%c\n",
703	s_name, dirc);	703	s_name, dirc);
704	}	704	}
705	}	705	}
706		706
707	dentptr++;	707	dentptr++;
708	continue;	708	continue;
709	}	709	}
710		710
711	if (strcmp(filename, s_name)	711	if (strcmp(filename, s_name)
712	&& strcmp(filename, l_name)) {	712	&& strcmp(filename, l_name)) {
713	debug("Mismatch: \|%s\|%s\|\n", s_name, l_name);	713	debug("Mismatch: \|%s\|%s\|\n", s_name, l_name);
714	dentptr++;	714	dentptr++;
715	continue;	715	continue;
716	}	716	}
717		717
718	memcpy(retdent, dentptr, sizeof(dir_entry));	718	memcpy(retdent, dentptr, sizeof(dir_entry));
719		719
720	debug("DentName: %s", s_name);	720	debug("DentName: %s", s_name);
721	debug(", start: 0x%x", START(dentptr));	721	debug(", start: 0x%x", START(dentptr));
722	debug(", size: 0x%x %s\n",	722	debug(", size: 0x%x %s\n",
723	FAT2CPU32(dentptr->size),	723	FAT2CPU32(dentptr->size),
724	(dentptr->attr & ATTR_DIR) ? "(DIR)" : "");	724	(dentptr->attr & ATTR_DIR) ? "(DIR)" : "");
725		725
726	return retdent;	726	return retdent;
727	}	727	}
728		728
729	curclust = get_fatent(mydata, curclust);	729	curclust = get_fatent(mydata, curclust);
730	if (CHECK_CLUST(curclust, mydata->fatsize)) {	730	if (CHECK_CLUST(curclust, mydata->fatsize)) {
731	debug("curclust: 0x%x\n", curclust);	731	debug("curclust: 0x%x\n", curclust);
732	printf("Invalid FAT entry\n");	732	printf("Invalid FAT entry\n");
733	return NULL;	733	return NULL;
734	}	734	}
735	}	735	}
736		736
737	return NULL;	737	return NULL;
738	}	738	}
739		739
740	/*	740	/*
741	* Read boot sector and volume info from a FAT filesystem	741	* Read boot sector and volume info from a FAT filesystem
742	*/	742	*/
743	static int	743	static int
744	read_bootsectandvi(boot_sector bs, volume_info volinfo, int *fatsize)	744	read_bootsectandvi(boot_sector bs, volume_info volinfo, int *fatsize)
745	{	745	{
746	__u8 *block;	746	__u8 *block;
747	volume_info *vistart;	747	volume_info *vistart;
748	int ret = 0;	748	int ret = 0;
749		749
750	if (cur_dev == NULL) {	750	if (cur_dev == NULL) {
751	debug("Error: no device selected\n");	751	debug("Error: no device selected\n");
752	return -1;	752	return -1;
753	}	753	}
754		754
755	block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);	755	block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
756	if (block == NULL) {	756	if (block == NULL) {
757	debug("Error: allocating block\n");	757	debug("Error: allocating block\n");
758	return -1;	758	return -1;
759	}	759	}
760		760
761	if (disk_read(0, 1, block) < 0) {	761	if (disk_read(0, 1, block) < 0) {
762	debug("Error: reading block\n");	762	debug("Error: reading block\n");
763	goto fail;	763	goto fail;
764	}	764	}
765		765
766	memcpy(bs, block, sizeof(boot_sector));	766	memcpy(bs, block, sizeof(boot_sector));
767	bs->reserved = FAT2CPU16(bs->reserved);	767	bs->reserved = FAT2CPU16(bs->reserved);
768	bs->fat_length = FAT2CPU16(bs->fat_length);	768	bs->fat_length = FAT2CPU16(bs->fat_length);
769	bs->secs_track = FAT2CPU16(bs->secs_track);	769	bs->secs_track = FAT2CPU16(bs->secs_track);
770	bs->heads = FAT2CPU16(bs->heads);	770	bs->heads = FAT2CPU16(bs->heads);
771	bs->total_sect = FAT2CPU32(bs->total_sect);	771	bs->total_sect = FAT2CPU32(bs->total_sect);
772		772
773	/* FAT32 entries */	773	/* FAT32 entries */
774	if (bs->fat_length == 0) {	774	if (bs->fat_length == 0) {
775	/* Assume FAT32 */	775	/* Assume FAT32 */
776	bs->fat32_length = FAT2CPU32(bs->fat32_length);	776	bs->fat32_length = FAT2CPU32(bs->fat32_length);
777	bs->flags = FAT2CPU16(bs->flags);	777	bs->flags = FAT2CPU16(bs->flags);
778	bs->root_cluster = FAT2CPU32(bs->root_cluster);	778	bs->root_cluster = FAT2CPU32(bs->root_cluster);
779	bs->info_sector = FAT2CPU16(bs->info_sector);	779	bs->info_sector = FAT2CPU16(bs->info_sector);
780	bs->backup_boot = FAT2CPU16(bs->backup_boot);	780	bs->backup_boot = FAT2CPU16(bs->backup_boot);
781	vistart = (volume_info *)(block + sizeof(boot_sector));	781	vistart = (volume_info *)(block + sizeof(boot_sector));
782	*fatsize = 32;	782	*fatsize = 32;
783	} else {	783	} else {
784	vistart = (volume_info *)&(bs->fat32_length);	784	vistart = (volume_info *)&(bs->fat32_length);
785	*fatsize = 0;	785	*fatsize = 0;
786	}	786	}
787	memcpy(volinfo, vistart, sizeof(volume_info));	787	memcpy(volinfo, vistart, sizeof(volume_info));
788		788
789	if (*fatsize == 32) {	789	if (*fatsize == 32) {
790	if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0)	790	if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0)
791	goto exit;	791	goto exit;
792	} else {	792	} else {
793	if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) {	793	if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) {
794	*fatsize = 12;	794	*fatsize = 12;
795	goto exit;	795	goto exit;
796	}	796	}
797	if (strncmp(FAT16_SIGN, vistart->fs_type, SIGNLEN) == 0) {	797	if (strncmp(FAT16_SIGN, vistart->fs_type, SIGNLEN) == 0) {
798	*fatsize = 16;	798	*fatsize = 16;
799	goto exit;	799	goto exit;
800	}	800	}
801	}	801	}
802		802
803	debug("Error: broken fs_type sign\n");	803	debug("Error: broken fs_type sign\n");
804	fail:	804	fail:
805	ret = -1;	805	ret = -1;
806	exit:	806	exit:
807	free(block);	807	free(block);
808	return ret;	808	return ret;
809	}	809	}
810		810
811	__u8 do_fat_read_at_block[MAX_CLUSTSIZE]	811	__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
812	__aligned(ARCH_DMA_MINALIGN);	812	__aligned(ARCH_DMA_MINALIGN);
813		813
814	int do_fat_read_at(const char filename, loff_t pos, void buffer,	814	int do_fat_read_at(const char filename, loff_t pos, void buffer,
815	loff_t maxsize, int dols, int dogetsize, loff_t *size)	815	loff_t maxsize, int dols, int dogetsize, loff_t *size)
816	{	816	{
817	char fnamecopy[2048];	817	char fnamecopy[2048];
818	boot_sector bs;	818	boot_sector bs;
819	volume_info volinfo;	819	volume_info volinfo;
820	fsdata datablock;	820	fsdata datablock;
821	fsdata *mydata = &datablock;	821	fsdata *mydata = &datablock;
822	dir_entry *dentptr = NULL;	822	dir_entry *dentptr = NULL;
823	__u16 prevcksum = 0xffff;	823	__u16 prevcksum = 0xffff;
824	char *subname = "";	824	char *subname = "";
825	__u32 cursect;	825	__u32 cursect;
826	int idx, isdir = 0;	826	int idx, isdir = 0;
827	int files = 0, dirs = 0;	827	int files = 0, dirs = 0;
828	int ret = -1;	828	int ret = -1;
829	int firsttime;	829	int firsttime;
830	__u32 root_cluster = 0;	830	__u32 root_cluster = 0;
831	__u32 read_blk;	831	__u32 read_blk;
832	int rootdir_size = 0;	832	int rootdir_size = 0;
833	int buffer_blk_cnt;	833	int buffer_blk_cnt;
834	int do_read;	834	int do_read;
835	__u8 *dir_ptr;	835	__u8 *dir_ptr;
836		836
837	if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {	837	if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
838	debug("Error: reading boot sector\n");	838	debug("Error: reading boot sector\n");
839	return -1;	839	return -1;
840	}	840	}
841		841
842	if (mydata->fatsize == 32) {	842	if (mydata->fatsize == 32) {
843	root_cluster = bs.root_cluster;	843	root_cluster = bs.root_cluster;
844	mydata->fatlength = bs.fat32_length;	844	mydata->fatlength = bs.fat32_length;
845	} else {	845	} else {
846	mydata->fatlength = bs.fat_length;	846	mydata->fatlength = bs.fat_length;
847	}	847	}
848		848
849	mydata->fat_sect = bs.reserved;	849	mydata->fat_sect = bs.reserved;
850		850
851	cursect = mydata->rootdir_sect	851	cursect = mydata->rootdir_sect
852	= mydata->fat_sect + mydata->fatlength * bs.fats;	852	= mydata->fat_sect + mydata->fatlength * bs.fats;
853		853
854	mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];	854	mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
855	mydata->clust_size = bs.cluster_size;	855	mydata->clust_size = bs.cluster_size;
856	if (mydata->sect_size != cur_part_info.blksz) {	856	if (mydata->sect_size != cur_part_info.blksz) {
857	printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n",	857	printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n",
858	mydata->sect_size, cur_part_info.blksz);	858	mydata->sect_size, cur_part_info.blksz);
859	return -1;	859	return -1;
860	}	860	}
861		861
862	if (mydata->fatsize == 32) {	862	if (mydata->fatsize == 32) {
863	mydata->data_begin = mydata->rootdir_sect -	863	mydata->data_begin = mydata->rootdir_sect -
864	(mydata->clust_size * 2);	864	(mydata->clust_size * 2);
865	} else {	865	} else {
866	rootdir_size = ((bs.dir_entries[1] * (int)256 +	866	rootdir_size = ((bs.dir_entries[1] * (int)256 +
867	bs.dir_entries[0]) *	867	bs.dir_entries[0]) *
868	sizeof(dir_entry)) /	868	sizeof(dir_entry)) /
869	mydata->sect_size;	869	mydata->sect_size;
870	mydata->data_begin = mydata->rootdir_sect +	870	mydata->data_begin = mydata->rootdir_sect +
871	rootdir_size -	871	rootdir_size -
872	(mydata->clust_size * 2);	872	(mydata->clust_size * 2);
873	}	873	}
874		874
875	mydata->fatbufnum = -1;	875	mydata->fatbufnum = -1;
876	mydata->fat_dirty = 0;	876	mydata->fat_dirty = 0;
877	mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);	877	mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
878	if (mydata->fatbuf == NULL) {	878	if (mydata->fatbuf == NULL) {
879	debug("Error: allocating memory\n");	879	debug("Error: allocating memory\n");
880	return -1;	880	return -1;
881	}	881	}
882		882
883	if (vfat_enabled)	883	if (vfat_enabled)
884	debug("VFAT Support enabled\n");	884	debug("VFAT Support enabled\n");
885		885
886	debug("FAT%d, fat_sect: %d, fatlength: %d\n",	886	debug("FAT%d, fat_sect: %d, fatlength: %d\n",
887	mydata->fatsize, mydata->fat_sect, mydata->fatlength);	887	mydata->fatsize, mydata->fat_sect, mydata->fatlength);
888	debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"	888	debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
889	"Data begins at: %d\n",	889	"Data begins at: %d\n",
890	root_cluster,	890	root_cluster,
891	mydata->rootdir_sect,	891	mydata->rootdir_sect,
892	mydata->rootdir_sect * mydata->sect_size, mydata->data_begin);	892	mydata->rootdir_sect * mydata->sect_size, mydata->data_begin);
893	debug("Sector size: %d, cluster size: %d\n", mydata->sect_size,	893	debug("Sector size: %d, cluster size: %d\n", mydata->sect_size,
894	mydata->clust_size);	894	mydata->clust_size);
895		895
896	/* "cwd" is always the root... */	896	/* "cwd" is always the root... */
897	while (ISDIRDELIM(*filename))	897	while (ISDIRDELIM(*filename))
898	filename++;	898	filename++;
899		899
900	/* Make a copy of the filename and convert it to lowercase */	900	/* Make a copy of the filename and convert it to lowercase */
901	strcpy(fnamecopy, filename);	901	strcpy(fnamecopy, filename);
902	downcase(fnamecopy);	902	downcase(fnamecopy);
903		903
904	root_reparse:	904	root_reparse:
905	if (*fnamecopy == '\0') {	905	if (*fnamecopy == '\0') {
906	if (!dols)	906	if (!dols)
907	goto exit;	907	goto exit;
908		908
909	dols = LS_ROOT;	909	dols = LS_ROOT;
910	} else if ((idx = dirdelim(fnamecopy)) >= 0) {	910	} else if ((idx = dirdelim(fnamecopy)) >= 0) {
911	isdir = 1;	911	isdir = 1;
912	fnamecopy[idx] = '\0';	912	fnamecopy[idx] = '\0';
913	subname = fnamecopy + idx + 1;	913	subname = fnamecopy + idx + 1;
914		914
915	/* Handle multiple delimiters */	915	/* Handle multiple delimiters */
916	while (ISDIRDELIM(*subname))	916	while (ISDIRDELIM(*subname))
917	subname++;	917	subname++;
918	} else if (dols) {	918	} else if (dols) {
919	isdir = 1;	919	isdir = 1;
920	}	920	}
921		921
922	buffer_blk_cnt = 0;	922	buffer_blk_cnt = 0;
923	firsttime = 1;	923	firsttime = 1;
924	while (1) {	924	while (1) {
925	int i;	925	int i;
926		926
927	if (mydata->fatsize == 32 \|\| firsttime) {	927	if (mydata->fatsize == 32 \|\| firsttime) {
928	dir_ptr = do_fat_read_at_block;	928	dir_ptr = do_fat_read_at_block;
929	firsttime = 0;	929	firsttime = 0;
930	} else {	930	} else {
931	/**	931	/**
932	* FAT16 sector buffer modification:	932	* FAT16 sector buffer modification:
933	* Each loop, the second buffered block is moved to	933	* Each loop, the second buffered block is moved to
934	* the buffer begin, and two next sectors are read	934	* the buffer begin, and two next sectors are read
935	* next to the previously moved one. So the sector	935	* next to the previously moved one. So the sector
936	* buffer keeps always 3 sectors for fat16.	936	* buffer keeps always 3 sectors for fat16.
937	* And the current sector is the buffer second sector	937	* And the current sector is the buffer second sector
938	* beside the "firsttime" read, when it is the first one.	938	* beside the "firsttime" read, when it is the first one.
939	*	939	*
940	* PREFETCH_BLOCKS is 2 for FAT16 == loop[0:1]	940	* PREFETCH_BLOCKS is 2 for FAT16 == loop[0:1]
941	* n = computed root dir sector	941	* n = computed root dir sector
942	* loop \| cursect-1 \| cursect \| cursect+1 \|	942	* loop \| cursect-1 \| cursect \| cursect+1 \|
943	* 0 \| sector n+0 \| sector n+1 \| none \|	943	* 0 \| sector n+0 \| sector n+1 \| none \|
944	* 1 \| none \| sector n+0 \| sector n+1 \|	944	* 1 \| none \| sector n+0 \| sector n+1 \|
945	* 0 \| sector n+1 \| sector n+2 \| sector n+3 \|	945	* 0 \| sector n+1 \| sector n+2 \| sector n+3 \|
946	* 1 \| sector n+3 \| ...	946	* 1 \| sector n+3 \| ...
947	*/	947	*/
948	dir_ptr = (do_fat_read_at_block + mydata->sect_size);	948	dir_ptr = (do_fat_read_at_block + mydata->sect_size);
949	memcpy(do_fat_read_at_block, dir_ptr, mydata->sect_size);	949	memcpy(do_fat_read_at_block, dir_ptr, mydata->sect_size);
950	}	950	}
951		951
952	do_read = 1;	952	do_read = 1;
953		953
954	if (mydata->fatsize == 32 && buffer_blk_cnt)	954	if (mydata->fatsize == 32 && buffer_blk_cnt)
955	do_read = 0;	955	do_read = 0;
956		956
957	if (do_read) {	957	if (do_read) {
958	read_blk = (mydata->fatsize == 32) ?	958	read_blk = (mydata->fatsize == 32) ?
959	mydata->clust_size : PREFETCH_BLOCKS;	959	mydata->clust_size : PREFETCH_BLOCKS;
960		960
961	debug("FAT read(sect=%d, cnt:%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",	961	debug("FAT read(sect=%d, cnt:%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
962	cursect, read_blk, mydata->clust_size, DIRENTSPERBLOCK);	962	cursect, read_blk, mydata->clust_size, DIRENTSPERBLOCK);
963		963
964	if (disk_read(cursect, read_blk, dir_ptr) < 0) {	964	if (disk_read(cursect, read_blk, dir_ptr) < 0) {
965	debug("Error: reading rootdir block\n");	965	debug("Error: reading rootdir block\n");
966	goto exit;	966	goto exit;
967	}	967	}
968		968
969	dentptr = (dir_entry *)dir_ptr;	969	dentptr = (dir_entry *)dir_ptr;
970	}	970	}
971		971
972	for (i = 0; i < DIRENTSPERBLOCK; i++) {	972	for (i = 0; i < DIRENTSPERBLOCK; i++) {
973	char s_name[14], l_name[VFAT_MAXLEN_BYTES];	973	char s_name[14], l_name[VFAT_MAXLEN_BYTES];
974	__u8 csum;	974	__u8 csum;
975		975
976	l_name[0] = '\0';	976	l_name[0] = '\0';
977	if (dentptr->name[0] == DELETED_FLAG) {	977	if (dentptr->name[0] == DELETED_FLAG) {
978	dentptr++;	978	dentptr++;
979	continue;	979	continue;
980	}	980	}
981		981
982	if (vfat_enabled)	982	if (vfat_enabled)
983	csum = mkcksum(dentptr->name, dentptr->ext);	983	csum = mkcksum(dentptr->name, dentptr->ext);
984		984
985	if (dentptr->attr & ATTR_VOLUME) {	985	if (dentptr->attr & ATTR_VOLUME) {
986	if (vfat_enabled &&	986	if (vfat_enabled &&
987	(dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&	987	(dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
988	(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {	988	(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
989	prevcksum =	989	prevcksum =
990	((dir_slot *)dentptr)->alias_checksum;	990	((dir_slot *)dentptr)->alias_checksum;
991		991
992	get_vfatname(mydata,	992	get_vfatname(mydata,
993	root_cluster,	993	root_cluster,
994	dir_ptr,	994	dir_ptr,
995	dentptr, l_name);	995	dentptr, l_name);
996		996
997	if (dols == LS_ROOT) {	997	if (dols == LS_ROOT) {
998	char dirc;	998	char dirc;
999	int doit = 0;	999	int doit = 0;
1000	int isdir =	1000	int isdir =
1001	(dentptr->attr & ATTR_DIR);	1001	(dentptr->attr & ATTR_DIR);
1002		1002
1003	if (isdir) {	1003	if (isdir) {
1004	dirs++;	1004	dirs++;
1005	dirc = '/';	1005	dirc = '/';
1006	doit = 1;	1006	doit = 1;
1007	} else {	1007	} else {
1008	dirc = ' ';	1008	dirc = ' ';
1009	if (l_name[0] != 0) {	1009	if (l_name[0] != 0) {
1010	files++;	1010	files++;
1011	doit = 1;	1011	doit = 1;
1012	}	1012	}
1013	}	1013	}
1014	if (doit) {	1014	if (doit) {
1015	if (dirc == ' ') {	1015	if (dirc == ' ') {
1016	printf(" %8u %s%c\n",	1016	printf(" %8u %s%c\n",
1017	FAT2CPU32(dentptr->size),	1017	FAT2CPU32(dentptr->size),
1018	l_name,	1018	l_name,
1019	dirc);	1019	dirc);
1020	} else {	1020	} else {
1021	printf(" %s%c\n",	1021	printf(" %s%c\n",
1022	l_name,	1022	l_name,
1023	dirc);	1023	dirc);
1024	}	1024	}
1025	}	1025	}
1026	dentptr++;	1026	dentptr++;
1027	continue;	1027	continue;
1028	}	1028	}
1029	debug("Rootvfatname: \|%s\|\n",	1029	debug("Rootvfatname: \|%s\|\n",
1030	l_name);	1030	l_name);
1031	} else {	1031	} else {
1032	/* Volume label or VFAT entry */	1032	/* Volume label or VFAT entry */
1033	dentptr++;	1033	dentptr++;
1034	continue;	1034	continue;
1035	}	1035	}
1036	} else if (dentptr->name[0] == 0) {	1036	} else if (dentptr->name[0] == 0) {
1037	debug("RootDentname == NULL - %d\n", i);	1037	debug("RootDentname == NULL - %d\n", i);
1038	if (dols == LS_ROOT) {	1038	if (dols == LS_ROOT) {
1039	printf("\n%d file(s), %d dir(s)\n\n",	1039	printf("\n%d file(s), %d dir(s)\n\n",
1040	files, dirs);	1040	files, dirs);
1041	ret = 0;	1041	ret = 0;
1042	}	1042	}
1043	goto exit;	1043	goto exit;
1044	}	1044	}
1045	else if (vfat_enabled &&	1045	else if (vfat_enabled &&
1046	dols == LS_ROOT && csum == prevcksum) {	1046	dols == LS_ROOT && csum == prevcksum) {
1047	prevcksum = 0xffff;	1047	prevcksum = 0xffff;
1048	dentptr++;	1048	dentptr++;
1049	continue;	1049	continue;
1050	}	1050	}
1051		1051
1052	get_name(dentptr, s_name);	1052	get_name(dentptr, s_name);
1053		1053
1054	if (dols == LS_ROOT) {	1054	if (dols == LS_ROOT) {
1055	int isdir = (dentptr->attr & ATTR_DIR);	1055	int isdir = (dentptr->attr & ATTR_DIR);
1056	char dirc;	1056	char dirc;
1057	int doit = 0;	1057	int doit = 0;
1058		1058
1059	if (isdir) {	1059	if (isdir) {
1060	dirc = '/';	1060	dirc = '/';
1061	if (s_name[0] != 0) {	1061	if (s_name[0] != 0) {
1062	dirs++;	1062	dirs++;
1063	doit = 1;	1063	doit = 1;
1064	}	1064	}
1065	} else {	1065	} else {
1066	dirc = ' ';	1066	dirc = ' ';
1067	if (s_name[0] != 0) {	1067	if (s_name[0] != 0) {
1068	files++;	1068	files++;
1069	doit = 1;	1069	doit = 1;
1070	}	1070	}
1071	}	1071	}
1072	if (doit) {	1072	if (doit) {
1073	if (dirc == ' ') {	1073	if (dirc == ' ') {
1074	printf(" %8u %s%c\n",	1074	printf(" %8u %s%c\n",
1075	FAT2CPU32(dentptr->size),	1075	FAT2CPU32(dentptr->size),
1076	s_name, dirc);	1076	s_name, dirc);
1077	} else {	1077	} else {
1078	printf(" %s%c\n",	1078	printf(" %s%c\n",
1079	s_name, dirc);	1079	s_name, dirc);
1080	}	1080	}
1081	}	1081	}
1082	dentptr++;	1082	dentptr++;
1083	continue;	1083	continue;
1084	}	1084	}
1085		1085
1086	if (strcmp(fnamecopy, s_name)	1086	if (strcmp(fnamecopy, s_name)
1087	&& strcmp(fnamecopy, l_name)) {	1087	&& strcmp(fnamecopy, l_name)) {
1088	debug("RootMismatch: \|%s\|%s\|\n", s_name,	1088	debug("RootMismatch: \|%s\|%s\|\n", s_name,
1089	l_name);	1089	l_name);
1090	dentptr++;	1090	dentptr++;
1091	continue;	1091	continue;
1092	}	1092	}
1093		1093
1094	if (isdir && !(dentptr->attr & ATTR_DIR))	1094	if (isdir && !(dentptr->attr & ATTR_DIR))
1095	goto exit;	1095	goto exit;
1096		1096
1097	debug("RootName: %s", s_name);	1097	debug("RootName: %s", s_name);
1098	debug(", start: 0x%x", START(dentptr));	1098	debug(", start: 0x%x", START(dentptr));
1099	debug(", size: 0x%x %s\n",	1099	debug(", size: 0x%x %s\n",
1100	FAT2CPU32(dentptr->size),	1100	FAT2CPU32(dentptr->size),
1101	isdir ? "(DIR)" : "");	1101	isdir ? "(DIR)" : "");
1102		1102
1103	goto rootdir_done; /* We got a match */	1103	goto rootdir_done; /* We got a match */
1104	}	1104	}
1105	debug("END LOOP: buffer_blk_cnt=%d clust_size=%d\n", buffer_blk_cnt,	1105	debug("END LOOP: buffer_blk_cnt=%d clust_size=%d\n", buffer_blk_cnt,
1106	mydata->clust_size);	1106	mydata->clust_size);
1107		1107
1108	/*	1108	/*
1109	* On FAT32 we must fetch the FAT entries for the next	1109	* On FAT32 we must fetch the FAT entries for the next
1110	* root directory clusters when a cluster has been	1110	* root directory clusters when a cluster has been
1111	* completely processed.	1111	* completely processed.
1112	*/	1112	*/
1113	++buffer_blk_cnt;	1113	++buffer_blk_cnt;
1114	int rootdir_end = 0;	1114	int rootdir_end = 0;
1115	if (mydata->fatsize == 32) {	1115	if (mydata->fatsize == 32) {
1116	if (buffer_blk_cnt == mydata->clust_size) {	1116	if (buffer_blk_cnt == mydata->clust_size) {
1117	int nxtsect = 0;	1117	int nxtsect = 0;
1118	int nxt_clust = 0;	1118	int nxt_clust = 0;
1119		1119
1120	nxt_clust = get_fatent(mydata, root_cluster);	1120	nxt_clust = get_fatent(mydata, root_cluster);
1121	rootdir_end = CHECK_CLUST(nxt_clust, 32);	1121	rootdir_end = CHECK_CLUST(nxt_clust, 32);
1122		1122
1123	nxtsect = mydata->data_begin +	1123	nxtsect = mydata->data_begin +
1124	(nxt_clust * mydata->clust_size);	1124	(nxt_clust * mydata->clust_size);
1125		1125
1126	root_cluster = nxt_clust;	1126	root_cluster = nxt_clust;
1127		1127
1128	cursect = nxtsect;	1128	cursect = nxtsect;
1129	buffer_blk_cnt = 0;	1129	buffer_blk_cnt = 0;
1130	}	1130	}
1131	} else {	1131	} else {
1132	if (buffer_blk_cnt == PREFETCH_BLOCKS)	1132	if (buffer_blk_cnt == PREFETCH_BLOCKS)
1133	buffer_blk_cnt = 0;	1133	buffer_blk_cnt = 0;
1134		1134
1135	rootdir_end = (++cursect - mydata->rootdir_sect >=	1135	rootdir_end = (++cursect - mydata->rootdir_sect >=
1136	rootdir_size);	1136	rootdir_size);
1137	}	1137	}
1138		1138
1139	/* If end of rootdir reached */	1139	/* If end of rootdir reached */
1140	if (rootdir_end) {	1140	if (rootdir_end) {
1141	if (dols == LS_ROOT) {	1141	if (dols == LS_ROOT) {
1142	printf("\n%d file(s), %d dir(s)\n\n",	1142	printf("\n%d file(s), %d dir(s)\n\n",
1143	files, dirs);	1143	files, dirs);
1144	*size = 0;	1144	*size = 0;
1145	}	1145	}
1146	goto exit;	1146	goto exit;
1147	}	1147	}
1148	}	1148	}
1149	rootdir_done:	1149	rootdir_done:
1150		1150
1151	firsttime = 1;	1151	firsttime = 1;
1152		1152
1153	while (isdir) {	1153	while (isdir) {
1154	int startsect = mydata->data_begin	1154	int startsect = mydata->data_begin
1155	+ START(dentptr) * mydata->clust_size;	1155	+ START(dentptr) * mydata->clust_size;
1156	dir_entry dent;	1156	dir_entry dent;
1157	char *nextname = NULL;	1157	char *nextname = NULL;
1158		1158
1159	dent = *dentptr;	1159	dent = *dentptr;
1160	dentptr = &dent;	1160	dentptr = &dent;
1161		1161
1162	idx = dirdelim(subname);	1162	idx = dirdelim(subname);
1163		1163
1164	if (idx >= 0) {	1164	if (idx >= 0) {
1165	subname[idx] = '\0';	1165	subname[idx] = '\0';
1166	nextname = subname + idx + 1;	1166	nextname = subname + idx + 1;
1167	/* Handle multiple delimiters */	1167	/* Handle multiple delimiters */
1168	while (ISDIRDELIM(*nextname))	1168	while (ISDIRDELIM(*nextname))
1169	nextname++;	1169	nextname++;
1170	if (dols && *nextname == '\0')	1170	if (dols && *nextname == '\0')
1171	firsttime = 0;	1171	firsttime = 0;
1172	} else {	1172	} else {
1173	if (dols && firsttime) {	1173	if (dols && firsttime) {
1174	firsttime = 0;	1174	firsttime = 0;
1175	} else {	1175	} else {
1176	isdir = 0;	1176	isdir = 0;
1177	}	1177	}
1178	}	1178	}
1179		1179
1180	if (get_dentfromdir(mydata, startsect, subname, dentptr,	1180	if (get_dentfromdir(mydata, startsect, subname, dentptr,
1181	isdir ? 0 : dols) == NULL) {	1181	isdir ? 0 : dols) == NULL) {
1182	if (dols && !isdir)	1182	if (dols && !isdir)
1183	*size = 0;	1183	*size = 0;
1184	goto exit;	1184	goto exit;
1185	}	1185	}
1186		1186
1187	if (isdir && !(dentptr->attr & ATTR_DIR))	1187	if (isdir && !(dentptr->attr & ATTR_DIR))
1188	goto exit;	1188	goto exit;
1189		1189
1190	/*	1190	/*
1191	* If we are looking for a directory, and found a directory	1191	* If we are looking for a directory, and found a directory
1192	* type entry, and the entry is for the root directory (as	1192	* type entry, and the entry is for the root directory (as
1193	* denoted by a cluster number of 0), jump back to the start	1193	* denoted by a cluster number of 0), jump back to the start
1194	* of the function, since at least on FAT12/16, the root dir	1194	* of the function, since at least on FAT12/16, the root dir
1195	* lives in a hard-coded location and needs special handling	1195	* lives in a hard-coded location and needs special handling
1196	* to parse, rather than simply following the cluster linked	1196	* to parse, rather than simply following the cluster linked
1197	* list in the FAT, like other directories.	1197	* list in the FAT, like other directories.
1198	*/	1198	*/
1199	if (isdir && (dentptr->attr & ATTR_DIR) && !START(dentptr)) {	1199	if (isdir && (dentptr->attr & ATTR_DIR) && !START(dentptr)) {
1200	/*	1200	/*
1201	* Modify the filename to remove the prefix that gets	1201	* Modify the filename to remove the prefix that gets
1202	* back to the root directory, so the initial root dir	1202	* back to the root directory, so the initial root dir
1203	* parsing code can continue from where we are without	1203	* parsing code can continue from where we are without
1204	* confusion.	1204	* confusion.
1205	*/	1205	*/
1206	strcpy(fnamecopy, nextname ?: "");	1206	strcpy(fnamecopy, nextname ?: "");
1207	/*	1207	/*
1208	* Set up state the same way as the function does when	1208	* Set up state the same way as the function does when
1209	* first started. This is required for the root dir	1209	* first started. This is required for the root dir
1210	* parsing code operates in its expected environment.	1210	* parsing code operates in its expected environment.
1211	*/	1211	*/
1212	subname = "";	1212	subname = "";
1213	cursect = mydata->rootdir_sect;	1213	cursect = mydata->rootdir_sect;
1214	isdir = 0;	1214	isdir = 0;
1215	goto root_reparse;	1215	goto root_reparse;
1216	}	1216	}
1217		1217
1218	if (idx >= 0)	1218	if (idx >= 0)
1219	subname = nextname;	1219	subname = nextname;
1220	}	1220	}
1221		1221
1222	if (dogetsize) {	1222	if (dogetsize) {
1223	*size = FAT2CPU32(dentptr->size);	1223	*size = FAT2CPU32(dentptr->size);
1224	ret = 0;	1224	ret = 0;
1225	} else {	1225	} else {
1226	ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size);	1226	ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size);
1227	}	1227	}
1228	debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size);	1228	debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size);
1229		1229
1230	exit:	1230	exit:
1231	free(mydata->fatbuf);	1231	free(mydata->fatbuf);
1232	return ret;	1232	return ret;
1233	}	1233	}
1234		1234
1235	int do_fat_read(const char filename, void buffer, loff_t maxsize, int dols,	1235	int do_fat_read(const char filename, void buffer, loff_t maxsize, int dols,
1236	loff_t *actread)	1236	loff_t *actread)
1237	{	1237	{
1238	return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread);	1238	return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread);
1239	}	1239	}
1240		1240
1241	int file_fat_detectfs(void)	1241	int file_fat_detectfs(void)
1242	{	1242	{
1243	boot_sector bs;	1243	boot_sector bs;
1244	volume_info volinfo;	1244	volume_info volinfo;
1245	int fatsize;	1245	int fatsize;
1246	char vol_label[12];	1246	char vol_label[12];
1247		1247
1248	if (cur_dev == NULL) {	1248	if (cur_dev == NULL) {
1249	printf("No current device\n");	1249	printf("No current device\n");
1250	return 1;	1250	return 1;
1251	}	1251	}
1252		1252
1253	#if defined(CONFIG_CMD_IDE) \|\| \	1253	#if defined(CONFIG_IDE) \|\| \
1254	defined(CONFIG_CMD_SATA) \|\| \	1254	defined(CONFIG_CMD_SATA) \|\| \
1255	defined(CONFIG_SCSI) \|\| \	1255	defined(CONFIG_SCSI) \|\| \
1256	defined(CONFIG_CMD_USB) \|\| \	1256	defined(CONFIG_CMD_USB) \|\| \
1257	defined(CONFIG_MMC)	1257	defined(CONFIG_MMC)
1258	printf("Interface: ");	1258	printf("Interface: ");
1259	switch (cur_dev->if_type) {	1259	switch (cur_dev->if_type) {
1260	case IF_TYPE_IDE:	1260	case IF_TYPE_IDE:
1261	printf("IDE");	1261	printf("IDE");
1262	break;	1262	break;
1263	case IF_TYPE_SATA:	1263	case IF_TYPE_SATA:
1264	printf("SATA");	1264	printf("SATA");
1265	break;	1265	break;
1266	case IF_TYPE_SCSI:	1266	case IF_TYPE_SCSI:
1267	printf("SCSI");	1267	printf("SCSI");
1268	break;	1268	break;
1269	case IF_TYPE_ATAPI:	1269	case IF_TYPE_ATAPI:
1270	printf("ATAPI");	1270	printf("ATAPI");
1271	break;	1271	break;
1272	case IF_TYPE_USB:	1272	case IF_TYPE_USB:
1273	printf("USB");	1273	printf("USB");
1274	break;	1274	break;
1275	case IF_TYPE_DOC:	1275	case IF_TYPE_DOC:
1276	printf("DOC");	1276	printf("DOC");
1277	break;	1277	break;
1278	case IF_TYPE_MMC:	1278	case IF_TYPE_MMC:
1279	printf("MMC");	1279	printf("MMC");
1280	break;	1280	break;
1281	default:	1281	default:
1282	printf("Unknown");	1282	printf("Unknown");
1283	}	1283	}
1284		1284
1285	printf("\n Device %d: ", cur_dev->devnum);	1285	printf("\n Device %d: ", cur_dev->devnum);
1286	dev_print(cur_dev);	1286	dev_print(cur_dev);
1287	#endif	1287	#endif
1288		1288
1289	if (read_bootsectandvi(&bs, &volinfo, &fatsize)) {	1289	if (read_bootsectandvi(&bs, &volinfo, &fatsize)) {
1290	printf("\nNo valid FAT fs found\n");	1290	printf("\nNo valid FAT fs found\n");
1291	return 1;	1291	return 1;
1292	}	1292	}
1293		1293
1294	memcpy(vol_label, volinfo.volume_label, 11);	1294	memcpy(vol_label, volinfo.volume_label, 11);
1295	vol_label[11] = '\0';	1295	vol_label[11] = '\0';
1296	volinfo.fs_type[5] = '\0';	1296	volinfo.fs_type[5] = '\0';
1297		1297
1298	printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label);	1298	printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label);
1299		1299
1300	return 0;	1300	return 0;
1301	}	1301	}
1302		1302
1303	int file_fat_ls(const char *dir)	1303	int file_fat_ls(const char *dir)
1304	{	1304	{
1305	loff_t size;	1305	loff_t size;
1306		1306
1307	return do_fat_read(dir, NULL, 0, LS_YES, &size);	1307	return do_fat_read(dir, NULL, 0, LS_YES, &size);
1308	}	1308	}
1309		1309
1310	int fat_exists(const char *filename)	1310	int fat_exists(const char *filename)
1311	{	1311	{
1312	int ret;	1312	int ret;
1313	loff_t size;	1313	loff_t size;
1314		1314
1315	ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size);	1315	ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size);
1316	return ret == 0;	1316	return ret == 0;
1317	}	1317	}
1318		1318
1319	int fat_size(const char filename, loff_t size)	1319	int fat_size(const char filename, loff_t size)
1320	{	1320	{
1321	return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size);	1321	return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size);
1322	}	1322	}
1323		1323
1324	int file_fat_read_at(const char filename, loff_t pos, void buffer,	1324	int file_fat_read_at(const char filename, loff_t pos, void buffer,
1325	loff_t maxsize, loff_t *actread)	1325	loff_t maxsize, loff_t *actread)
1326	{	1326	{
1327	printf("reading %s\n", filename);	1327	printf("reading %s\n", filename);
1328	return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0,	1328	return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0,
1329	actread);	1329	actread);
1330	}	1330	}
1331		1331
1332	int file_fat_read(const char filename, void buffer, int maxsize)	1332	int file_fat_read(const char filename, void buffer, int maxsize)
1333	{	1333	{
1334	loff_t actread;	1334	loff_t actread;
1335	int ret;	1335	int ret;
1336		1336
1337	ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread);	1337	ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread);
1338	if (ret)	1338	if (ret)
1339	return ret;	1339	return ret;
1340	else	1340	else
1341	return actread;	1341	return actread;
1342	}	1342	}
1343		1343
1344	int fat_read_file(const char filename, void buf, loff_t offset, loff_t len,	1344	int fat_read_file(const char filename, void buf, loff_t offset, loff_t len,
1345	loff_t *actread)	1345	loff_t *actread)
1346	{	1346	{
1347	int ret;	1347	int ret;
1348		1348
1349	ret = file_fat_read_at(filename, offset, buf, len, actread);	1349	ret = file_fat_read_at(filename, offset, buf, len, actread);
1350	if (ret)	1350	if (ret)
1351	printf(" Unable to read file %s \n", filename);	1351	printf(" Unable to read file %s \n", filename);
1352		1352
1353	return ret;	1353	return ret;
1354	}	1354	}
1355		1355
1356	void fat_close(void)	1356	void fat_close(void)
1357	{	1357	{
1358	}	1358	}
1359		1359

include/config_distro_bootcmd.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2014	2	* (C) Copyright 2014
3	* NVIDIA Corporation <www.nvidia.com>	3	* NVIDIA Corporation <www.nvidia.com>
4	*	4	*
5	* Copyright 2014 Red Hat, Inc.	5	* Copyright 2014 Red Hat, Inc.
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H	10	#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
11	#define _CONFIG_CMD_DISTRO_BOOTCMD_H	11	#define _CONFIG_CMD_DISTRO_BOOTCMD_H
12		12
13	/*	13	/*
14	* A note on error handling: It is possible for BOOT_TARGET_DEVICES to	14	* A note on error handling: It is possible for BOOT_TARGET_DEVICES to
15	* reference a device that is not enabled in the U-Boot configuration, e.g.	15	* reference a device that is not enabled in the U-Boot configuration, e.g.
16	* it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given	16	* it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given
17	* that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor	17	* that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor
18	* at compile time, it's not possible to detect and report such problems via	18	* at compile time, it's not possible to detect and report such problems via
19	* a simple #ifdef/#error combination. Still, the code needs to report errors.	19	* a simple #ifdef/#error combination. Still, the code needs to report errors.
20	* The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to	20	* The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to
21	* reference a non-existent symbol, and have the name of that symbol encode	21	* reference a non-existent symbol, and have the name of that symbol encode
22	* the error message. Consequently, this file contains references to e.g.	22	* the error message. Consequently, this file contains references to e.g.
23	* BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the	23	* BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the
24	* prevalence of capitals here, this looks like a pre-processor macro and	24	* prevalence of capitals here, this looks like a pre-processor macro and
25	* hence seems like it should be all capitals, but it's really an error	25	* hence seems like it should be all capitals, but it's really an error
26	* message that includes some other pre-processor symbols in the text.	26	* message that includes some other pre-processor symbols in the text.
27	*/	27	*/
28		28
29	#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \	29	#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \
30	"if " #devtypel " dev ${devnum}; then " \	30	"if " #devtypel " dev ${devnum}; then " \
31	"setenv devtype " #devtypel "; " \	31	"setenv devtype " #devtypel "; " \
32	"run scan_dev_for_boot_part; " \	32	"run scan_dev_for_boot_part; " \
33	"fi\0"	33	"fi\0"
34		34
35	#define BOOTENV_SHARED_BLKDEV(devtypel) \	35	#define BOOTENV_SHARED_BLKDEV(devtypel) \
36	#devtypel "_boot=" \	36	#devtypel "_boot=" \
37	BOOTENV_SHARED_BLKDEV_BODY(devtypel)	37	BOOTENV_SHARED_BLKDEV_BODY(devtypel)
38		38
39	#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \	39	#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \
40	"bootcmd_" #devtypel #instance "=" \	40	"bootcmd_" #devtypel #instance "=" \
41	"setenv devnum " #instance "; " \	41	"setenv devnum " #instance "; " \
42	"run " #devtypel "_boot\0"	42	"run " #devtypel "_boot\0"
43		43
44	#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \	44	#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \
45	#devtypel #instance " "	45	#devtypel #instance " "
46		46
47	#ifdef CONFIG_SANDBOX	47	#ifdef CONFIG_SANDBOX
48	#define BOOTENV_SHARED_HOST BOOTENV_SHARED_BLKDEV(host)	48	#define BOOTENV_SHARED_HOST BOOTENV_SHARED_BLKDEV(host)
49	#define BOOTENV_DEV_HOST BOOTENV_DEV_BLKDEV	49	#define BOOTENV_DEV_HOST BOOTENV_DEV_BLKDEV
50	#define BOOTENV_DEV_NAME_HOST BOOTENV_DEV_NAME_BLKDEV	50	#define BOOTENV_DEV_NAME_HOST BOOTENV_DEV_NAME_BLKDEV
51	#else	51	#else
52	#define BOOTENV_SHARED_HOST	52	#define BOOTENV_SHARED_HOST
53	#define BOOTENV_DEV_HOST \	53	#define BOOTENV_DEV_HOST \
54	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX	54	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
55	#define BOOTENV_DEV_NAME_HOST \	55	#define BOOTENV_DEV_NAME_HOST \
56	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX	56	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
57	#endif	57	#endif
58		58
59	#ifdef CONFIG_CMD_MMC	59	#ifdef CONFIG_CMD_MMC
60	#define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc)	60	#define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc)
61	#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV	61	#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV
62	#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV	62	#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV
63	#else	63	#else
64	#define BOOTENV_SHARED_MMC	64	#define BOOTENV_SHARED_MMC
65	#define BOOTENV_DEV_MMC \	65	#define BOOTENV_DEV_MMC \
66	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC	66	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
67	#define BOOTENV_DEV_NAME_MMC \	67	#define BOOTENV_DEV_NAME_MMC \
68	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC	68	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
69	#endif	69	#endif
70		70
71	#ifdef CONFIG_CMD_UBIFS	71	#ifdef CONFIG_CMD_UBIFS
72	#define BOOTENV_SHARED_UBIFS \	72	#define BOOTENV_SHARED_UBIFS \
73	"ubifs_boot=" \	73	"ubifs_boot=" \
74	"if ubi part UBI && ubifsmount ubi${devnum}:boot; then " \	74	"if ubi part UBI && ubifsmount ubi${devnum}:boot; then " \
75	"setenv devtype ubi; " \	75	"setenv devtype ubi; " \
76	"setenv bootpart 0; " \	76	"setenv bootpart 0; " \
77	"run scan_dev_for_boot; " \	77	"run scan_dev_for_boot; " \
78	"fi\0"	78	"fi\0"
79	#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV	79	#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV
80	#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV	80	#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV
81	#else	81	#else
82	#define BOOTENV_SHARED_UBIFS	82	#define BOOTENV_SHARED_UBIFS
83	#define BOOTENV_DEV_UBIFS \	83	#define BOOTENV_DEV_UBIFS \
84	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS	84	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
85	#define BOOTENV_DEV_NAME_UBIFS \	85	#define BOOTENV_DEV_NAME_UBIFS \
86	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS	86	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
87	#endif	87	#endif
88		88
89	#ifdef CONFIG_EFI_LOADER	89	#ifdef CONFIG_EFI_LOADER
90	#if defined(CONFIG_ARM64)	90	#if defined(CONFIG_ARM64)
91	#define BOOTEFI_NAME "bootaa64.efi"	91	#define BOOTEFI_NAME "bootaa64.efi"
92	#elif defined(CONFIG_ARM)	92	#elif defined(CONFIG_ARM)
93	#define BOOTEFI_NAME "bootarm.efi"	93	#define BOOTEFI_NAME "bootarm.efi"
94	#endif	94	#endif
95	#endif	95	#endif
96		96
97	#ifdef BOOTEFI_NAME	97	#ifdef BOOTEFI_NAME
98	#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)	98	#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
99	/*	99	/*
100	* On 32bit ARM systems there is a reasonable number of systems that follow	100	* On 32bit ARM systems there is a reasonable number of systems that follow
101	* the $soc-$board$boardver.dtb name scheme for their device trees. Use that	101	* the $soc-$board$boardver.dtb name scheme for their device trees. Use that
102	* scheme if we don't have an explicit fdtfile variable.	102	* scheme if we don't have an explicit fdtfile variable.
103	*/	103	*/
104	#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \	104	#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
105	"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \	105	"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
106	"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \	106	"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
107	"fi; "	107	"fi; "
108	#else	108	#else
109	#define BOOTENV_EFI_SET_FDTFILE_FALLBACK	109	#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
110	#endif	110	#endif
111		111
112		112
113	#define BOOTENV_SHARED_EFI \	113	#define BOOTENV_SHARED_EFI \
114	"boot_efi_binary=" \	114	"boot_efi_binary=" \
115	"load ${devtype} ${devnum}:${distro_bootpart} " \	115	"load ${devtype} ${devnum}:${distro_bootpart} " \
116	"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \	116	"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \
117	"if fdt addr ${fdt_addr_r}; then " \	117	"if fdt addr ${fdt_addr_r}; then " \
118	"bootefi ${kernel_addr_r} ${fdt_addr_r};" \	118	"bootefi ${kernel_addr_r} ${fdt_addr_r};" \
119	"else " \	119	"else " \
120	"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \	120	"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
121	"fi\0" \	121	"fi\0" \
122	\	122	\
123	"load_efi_dtb=" \	123	"load_efi_dtb=" \
124	"load ${devtype} ${devnum}:${distro_bootpart} " \	124	"load ${devtype} ${devnum}:${distro_bootpart} " \
125	"${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \	125	"${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \
126	\	126	\
127	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \	127	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \
128	"scan_dev_for_efi=" \	128	"scan_dev_for_efi=" \
129	"setenv efi_fdtfile ${fdtfile}; " \	129	"setenv efi_fdtfile ${fdtfile}; " \
130	BOOTENV_EFI_SET_FDTFILE_FALLBACK \	130	BOOTENV_EFI_SET_FDTFILE_FALLBACK \
131	"for prefix in ${efi_dtb_prefixes}; do " \	131	"for prefix in ${efi_dtb_prefixes}; do " \
132	"if test -e ${devtype} " \	132	"if test -e ${devtype} " \
133	"${devnum}:${distro_bootpart} " \	133	"${devnum}:${distro_bootpart} " \
134	"${prefix}${efi_fdtfile}; then " \	134	"${prefix}${efi_fdtfile}; then " \
135	"run load_efi_dtb; " \	135	"run load_efi_dtb; " \
136	"fi;" \	136	"fi;" \
137	"done;" \	137	"done;" \
138	"if test -e ${devtype} ${devnum}:${distro_bootpart} " \	138	"if test -e ${devtype} ${devnum}:${distro_bootpart} " \
139	"efi/boot/"BOOTEFI_NAME"; then " \	139	"efi/boot/"BOOTEFI_NAME"; then " \
140	"echo Found EFI removable media binary " \	140	"echo Found EFI removable media binary " \
141	"efi/boot/"BOOTEFI_NAME"; " \	141	"efi/boot/"BOOTEFI_NAME"; " \
142	"run boot_efi_binary; " \	142	"run boot_efi_binary; " \
143	"echo EFI LOAD FAILED: continuing...; " \	143	"echo EFI LOAD FAILED: continuing...; " \
144	"fi; " \	144	"fi; " \
145	"setenv efi_fdtfile\0"	145	"setenv efi_fdtfile\0"
146	#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"	146	#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
147	#else	147	#else
148	#define BOOTENV_SHARED_EFI	148	#define BOOTENV_SHARED_EFI
149	#define SCAN_DEV_FOR_EFI	149	#define SCAN_DEV_FOR_EFI
150	#endif	150	#endif
151		151
152	#ifdef CONFIG_CMD_SATA	152	#ifdef CONFIG_CMD_SATA
153	#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata)	153	#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata)
154	#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV	154	#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV
155	#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV	155	#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV
156	#else	156	#else
157	#define BOOTENV_SHARED_SATA	157	#define BOOTENV_SHARED_SATA
158	#define BOOTENV_DEV_SATA \	158	#define BOOTENV_DEV_SATA \
159	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA	159	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
160	#define BOOTENV_DEV_NAME_SATA \	160	#define BOOTENV_DEV_NAME_SATA \
161	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA	161	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
162	#endif	162	#endif
163		163
164	#ifdef CONFIG_SCSI	164	#ifdef CONFIG_SCSI
165	#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "	165	#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
166	#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "	166	#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
167	#define BOOTENV_SHARED_SCSI \	167	#define BOOTENV_SHARED_SCSI \
168	"scsi_init=" \	168	"scsi_init=" \
169	"if ${scsi_need_init}; then " \	169	"if ${scsi_need_init}; then " \
170	"setenv scsi_need_init false; " \	170	"setenv scsi_need_init false; " \
171	"scsi scan; " \	171	"scsi scan; " \
172	"fi\0" \	172	"fi\0" \
173	\	173	\
174	"scsi_boot=" \	174	"scsi_boot=" \
175	BOOTENV_RUN_SCSI_INIT \	175	BOOTENV_RUN_SCSI_INIT \
176	BOOTENV_SHARED_BLKDEV_BODY(scsi)	176	BOOTENV_SHARED_BLKDEV_BODY(scsi)
177	#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV	177	#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV
178	#define BOOTENV_DEV_NAME_SCSI BOOTENV_DEV_NAME_BLKDEV	178	#define BOOTENV_DEV_NAME_SCSI BOOTENV_DEV_NAME_BLKDEV
179	#else	179	#else
180	#define BOOTENV_RUN_SCSI_INIT	180	#define BOOTENV_RUN_SCSI_INIT
181	#define BOOTENV_SET_SCSI_NEED_INIT	181	#define BOOTENV_SET_SCSI_NEED_INIT
182	#define BOOTENV_SHARED_SCSI	182	#define BOOTENV_SHARED_SCSI
183	#define BOOTENV_DEV_SCSI \	183	#define BOOTENV_DEV_SCSI \
184	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI	184	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
185	#define BOOTENV_DEV_NAME_SCSI \	185	#define BOOTENV_DEV_NAME_SCSI \
186	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI	186	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
187	#endif	187	#endif
188		188
189	#ifdef CONFIG_CMD_IDE	189	#ifdef CONFIG_IDE
190	#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide)	190	#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide)
191	#define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV	191	#define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV
192	#define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV	192	#define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV
193	#else	193	#else
194	#define BOOTENV_SHARED_IDE	194	#define BOOTENV_SHARED_IDE
195	#define BOOTENV_DEV_IDE \	195	#define BOOTENV_DEV_IDE \
196	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE	196	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
197	#define BOOTENV_DEV_NAME_IDE \	197	#define BOOTENV_DEV_NAME_IDE \
198	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE	198	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
199	#endif	199	#endif
200		200
201	#if defined(CONFIG_CMD_PCI_ENUM) \|\| defined(CONFIG_DM_PCI)	201	#if defined(CONFIG_CMD_PCI_ENUM) \|\| defined(CONFIG_DM_PCI)
202	#define BOOTENV_RUN_NET_PCI_ENUM "run boot_net_pci_enum; "	202	#define BOOTENV_RUN_NET_PCI_ENUM "run boot_net_pci_enum; "
203	#define BOOTENV_SHARED_PCI \	203	#define BOOTENV_SHARED_PCI \
204	"boot_net_pci_enum=pci enum\0"	204	"boot_net_pci_enum=pci enum\0"
205	#else	205	#else
206	#define BOOTENV_RUN_NET_PCI_ENUM	206	#define BOOTENV_RUN_NET_PCI_ENUM
207	#define BOOTENV_SHARED_PCI	207	#define BOOTENV_SHARED_PCI
208	#endif	208	#endif
209		209
210	#ifdef CONFIG_CMD_USB	210	#ifdef CONFIG_CMD_USB
211	#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "	211	#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "
212	#define BOOTENV_SHARED_USB \	212	#define BOOTENV_SHARED_USB \
213	"boot_net_usb_start=usb start\0" \	213	"boot_net_usb_start=usb start\0" \
214	"usb_boot=" \	214	"usb_boot=" \
215	"usb start; " \	215	"usb start; " \
216	BOOTENV_SHARED_BLKDEV_BODY(usb)	216	BOOTENV_SHARED_BLKDEV_BODY(usb)
217	#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV	217	#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV
218	#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV	218	#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV
219	#else	219	#else
220	#define BOOTENV_RUN_NET_USB_START	220	#define BOOTENV_RUN_NET_USB_START
221	#define BOOTENV_SHARED_USB	221	#define BOOTENV_SHARED_USB
222	#define BOOTENV_DEV_USB \	222	#define BOOTENV_DEV_USB \
223	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB	223	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
224	#define BOOTENV_DEV_NAME_USB \	224	#define BOOTENV_DEV_NAME_USB \
225	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB	225	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
226	#endif	226	#endif
227		227
228	#if defined(CONFIG_CMD_DHCP)	228	#if defined(CONFIG_CMD_DHCP)
229	#if defined(CONFIG_EFI_LOADER)	229	#if defined(CONFIG_EFI_LOADER)
230	#if defined(CONFIG_ARM64)	230	#if defined(CONFIG_ARM64)
231	#define BOOTENV_EFI_PXE_ARCH "0xb"	231	#define BOOTENV_EFI_PXE_ARCH "0xb"
232	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"	232	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
233	#elif defined(CONFIG_ARM)	233	#elif defined(CONFIG_ARM)
234	#define BOOTENV_EFI_PXE_ARCH "0xa"	234	#define BOOTENV_EFI_PXE_ARCH "0xa"
235	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"	235	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
236	#elif defined(CONFIG_X86)	236	#elif defined(CONFIG_X86)
237	/* Always assume we're running 64bit */	237	/* Always assume we're running 64bit */
238	#define BOOTENV_EFI_PXE_ARCH "0x7"	238	#define BOOTENV_EFI_PXE_ARCH "0x7"
239	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"	239	#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
240	#else	240	#else
241	#error Please specify an EFI client identifier	241	#error Please specify an EFI client identifier
242	#endif	242	#endif
243		243
244	/*	244	/*
245	* Ask the dhcp server for an EFI binary. If we get one, check for a	245	* Ask the dhcp server for an EFI binary. If we get one, check for a
246	* device tree in the same folder. Then boot everything. If the file was	246	* device tree in the same folder. Then boot everything. If the file was
247	* not an EFI binary, we just return from the bootefi command and continue.	247	* not an EFI binary, we just return from the bootefi command and continue.
248	*/	248	*/
249	#define BOOTENV_EFI_RUN_DHCP \	249	#define BOOTENV_EFI_RUN_DHCP \
250	"setenv efi_fdtfile ${fdtfile}; " \	250	"setenv efi_fdtfile ${fdtfile}; " \
251	BOOTENV_EFI_SET_FDTFILE_FALLBACK \	251	BOOTENV_EFI_SET_FDTFILE_FALLBACK \
252	"setenv efi_old_vci ${bootp_vci};" \	252	"setenv efi_old_vci ${bootp_vci};" \
253	"setenv efi_old_arch ${bootp_arch};" \	253	"setenv efi_old_arch ${bootp_arch};" \
254	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \	254	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \
255	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \	255	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \
256	"if dhcp ${kernel_addr_r}; then " \	256	"if dhcp ${kernel_addr_r}; then " \
257	"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \	257	"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \
258	"if fdt addr ${fdt_addr_r}; then " \	258	"if fdt addr ${fdt_addr_r}; then " \
259	"bootefi ${kernel_addr_r} ${fdt_addr_r}; " \	259	"bootefi ${kernel_addr_r} ${fdt_addr_r}; " \
260	"else " \	260	"else " \
261	"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \	261	"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
262	"fi;" \	262	"fi;" \
263	"fi;" \	263	"fi;" \
264	"setenv bootp_vci ${efi_old_vci};" \	264	"setenv bootp_vci ${efi_old_vci};" \
265	"setenv bootp_arch ${efi_old_arch};" \	265	"setenv bootp_arch ${efi_old_arch};" \
266	"setenv efi_fdtfile;" \	266	"setenv efi_fdtfile;" \
267	"setenv efi_old_arch;" \	267	"setenv efi_old_arch;" \
268	"setenv efi_old_vci;"	268	"setenv efi_old_vci;"
269	#else	269	#else
270	#define BOOTENV_EFI_RUN_DHCP	270	#define BOOTENV_EFI_RUN_DHCP
271	#endif	271	#endif
272	#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \	272	#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
273	"bootcmd_dhcp=" \	273	"bootcmd_dhcp=" \
274	BOOTENV_RUN_NET_USB_START \	274	BOOTENV_RUN_NET_USB_START \
275	BOOTENV_RUN_NET_PCI_ENUM \	275	BOOTENV_RUN_NET_PCI_ENUM \
276	"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \	276	"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
277	"source ${scriptaddr}; " \	277	"source ${scriptaddr}; " \
278	"fi;" \	278	"fi;" \
279	BOOTENV_EFI_RUN_DHCP \	279	BOOTENV_EFI_RUN_DHCP \
280	"\0"	280	"\0"
281	#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \	281	#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
282	"dhcp "	282	"dhcp "
283	#else	283	#else
284	#define BOOTENV_DEV_DHCP \	284	#define BOOTENV_DEV_DHCP \
285	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP	285	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
286	#define BOOTENV_DEV_NAME_DHCP \	286	#define BOOTENV_DEV_NAME_DHCP \
287	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP	287	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
288	#endif	288	#endif
289		289
290	#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)	290	#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
291	#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \	291	#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \
292	"bootcmd_pxe=" \	292	"bootcmd_pxe=" \
293	BOOTENV_RUN_NET_USB_START \	293	BOOTENV_RUN_NET_USB_START \
294	BOOTENV_RUN_NET_PCI_ENUM \	294	BOOTENV_RUN_NET_PCI_ENUM \
295	"dhcp; " \	295	"dhcp; " \
296	"if pxe get; then " \	296	"if pxe get; then " \
297	"pxe boot; " \	297	"pxe boot; " \
298	"fi\0"	298	"fi\0"
299	#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \	299	#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \
300	"pxe "	300	"pxe "
301	#else	301	#else
302	#define BOOTENV_DEV_PXE \	302	#define BOOTENV_DEV_PXE \
303	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE	303	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
304	#define BOOTENV_DEV_NAME_PXE \	304	#define BOOTENV_DEV_NAME_PXE \
305	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE	305	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
306	#endif	306	#endif
307		307
308	#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \	308	#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \
309	BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance)	309	BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance)
310	#define BOOTENV_BOOT_TARGETS \	310	#define BOOTENV_BOOT_TARGETS \
311	"boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"	311	"boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
312		312
313	#define BOOTENV_DEV(devtypeu, devtypel, instance) \	313	#define BOOTENV_DEV(devtypeu, devtypel, instance) \
314	BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance)	314	BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance)
315	#define BOOTENV \	315	#define BOOTENV \
316	BOOTENV_SHARED_HOST \	316	BOOTENV_SHARED_HOST \
317	BOOTENV_SHARED_MMC \	317	BOOTENV_SHARED_MMC \
318	BOOTENV_SHARED_PCI \	318	BOOTENV_SHARED_PCI \
319	BOOTENV_SHARED_USB \	319	BOOTENV_SHARED_USB \
320	BOOTENV_SHARED_SATA \	320	BOOTENV_SHARED_SATA \
321	BOOTENV_SHARED_SCSI \	321	BOOTENV_SHARED_SCSI \
322	BOOTENV_SHARED_IDE \	322	BOOTENV_SHARED_IDE \
323	BOOTENV_SHARED_UBIFS \	323	BOOTENV_SHARED_UBIFS \
324	BOOTENV_SHARED_EFI \	324	BOOTENV_SHARED_EFI \
325	"boot_prefixes=/ /boot/\0" \	325	"boot_prefixes=/ /boot/\0" \
326	"boot_scripts=boot.scr.uimg boot.scr\0" \	326	"boot_scripts=boot.scr.uimg boot.scr\0" \
327	"boot_script_dhcp=boot.scr.uimg\0" \	327	"boot_script_dhcp=boot.scr.uimg\0" \
328	BOOTENV_BOOT_TARGETS \	328	BOOTENV_BOOT_TARGETS \
329	\	329	\
330	"boot_extlinux=" \	330	"boot_extlinux=" \
331	"sysboot ${devtype} ${devnum}:${distro_bootpart} any " \	331	"sysboot ${devtype} ${devnum}:${distro_bootpart} any " \
332	"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \	332	"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
333	\	333	\
334	"scan_dev_for_extlinux=" \	334	"scan_dev_for_extlinux=" \
335	"if test -e ${devtype} " \	335	"if test -e ${devtype} " \
336	"${devnum}:${distro_bootpart} " \	336	"${devnum}:${distro_bootpart} " \
337	"${prefix}extlinux/extlinux.conf; then " \	337	"${prefix}extlinux/extlinux.conf; then " \
338	"echo Found ${prefix}extlinux/extlinux.conf; " \	338	"echo Found ${prefix}extlinux/extlinux.conf; " \
339	"run boot_extlinux; " \	339	"run boot_extlinux; " \
340	"echo SCRIPT FAILED: continuing...; " \	340	"echo SCRIPT FAILED: continuing...; " \
341	"fi\0" \	341	"fi\0" \
342	\	342	\
343	"boot_a_script=" \	343	"boot_a_script=" \
344	"load ${devtype} ${devnum}:${distro_bootpart} " \	344	"load ${devtype} ${devnum}:${distro_bootpart} " \
345	"${scriptaddr} ${prefix}${script}; " \	345	"${scriptaddr} ${prefix}${script}; " \
346	"source ${scriptaddr}\0" \	346	"source ${scriptaddr}\0" \
347	\	347	\
348	"scan_dev_for_scripts=" \	348	"scan_dev_for_scripts=" \
349	"for script in ${boot_scripts}; do " \	349	"for script in ${boot_scripts}; do " \
350	"if test -e ${devtype} " \	350	"if test -e ${devtype} " \
351	"${devnum}:${distro_bootpart} " \	351	"${devnum}:${distro_bootpart} " \
352	"${prefix}${script}; then " \	352	"${prefix}${script}; then " \
353	"echo Found U-Boot script " \	353	"echo Found U-Boot script " \
354	"${prefix}${script}; " \	354	"${prefix}${script}; " \
355	"run boot_a_script; " \	355	"run boot_a_script; " \
356	"echo SCRIPT FAILED: continuing...; " \	356	"echo SCRIPT FAILED: continuing...; " \
357	"fi; " \	357	"fi; " \
358	"done\0" \	358	"done\0" \
359	\	359	\
360	"scan_dev_for_boot=" \	360	"scan_dev_for_boot=" \
361	"echo Scanning ${devtype} " \	361	"echo Scanning ${devtype} " \
362	"${devnum}:${distro_bootpart}...; " \	362	"${devnum}:${distro_bootpart}...; " \
363	"for prefix in ${boot_prefixes}; do " \	363	"for prefix in ${boot_prefixes}; do " \
364	"run scan_dev_for_extlinux; " \	364	"run scan_dev_for_extlinux; " \
365	"run scan_dev_for_scripts; " \	365	"run scan_dev_for_scripts; " \
366	"done;" \	366	"done;" \
367	SCAN_DEV_FOR_EFI \	367	SCAN_DEV_FOR_EFI \
368	"\0" \	368	"\0" \
369	\	369	\
370	"scan_dev_for_boot_part=" \	370	"scan_dev_for_boot_part=" \
371	"part list ${devtype} ${devnum} -bootable devplist; " \	371	"part list ${devtype} ${devnum} -bootable devplist; " \
372	"env exists devplist \|\| setenv devplist 1; " \	372	"env exists devplist \|\| setenv devplist 1; " \
373	"for distro_bootpart in ${devplist}; do " \	373	"for distro_bootpart in ${devplist}; do " \
374	"if fstype ${devtype} " \	374	"if fstype ${devtype} " \
375	"${devnum}:${distro_bootpart} " \	375	"${devnum}:${distro_bootpart} " \
376	"bootfstype; then " \	376	"bootfstype; then " \
377	"run scan_dev_for_boot; " \	377	"run scan_dev_for_boot; " \
378	"fi; " \	378	"fi; " \
379	"done\0" \	379	"done\0" \
380	\	380	\
381	BOOT_TARGET_DEVICES(BOOTENV_DEV) \	381	BOOT_TARGET_DEVICES(BOOTENV_DEV) \
382	\	382	\
383	"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \	383	"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \
384	"for target in ${boot_targets}; do " \	384	"for target in ${boot_targets}; do " \
385	"run bootcmd_${target}; " \	385	"run bootcmd_${target}; " \
386	"done\0"	386	"done\0"
387		387
388	#ifndef CONFIG_BOOTCOMMAND	388	#ifndef CONFIG_BOOTCOMMAND
389	#define CONFIG_BOOTCOMMAND "run distro_bootcmd"	389	#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
390	#endif	390	#endif
391		391
392	#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */	392	#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */
393		393

include/config_fallbacks.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Copyright 2012 Texas Instruments	2	* Copyright 2012 Texas Instruments
3	*	3	*
4	* This file is licensed under the terms of the GNU General Public	4	* This file is licensed under the terms of the GNU General Public
5	* License Version 2. This file is licensed "as is" without any	5	* License Version 2. This file is licensed "as is" without any
6	* warranty of any kind, whether express or implied.	6	* warranty of any kind, whether express or implied.
7	*/	7	*/
8		8
9	#ifndef __CONFIG_FALLBACKS_H	9	#ifndef __CONFIG_FALLBACKS_H
10	#define __CONFIG_FALLBACKS_H	10	#define __CONFIG_FALLBACKS_H
11		11
12	#ifdef CONFIG_SPL	12	#ifdef CONFIG_SPL
13	#ifdef CONFIG_SPL_PAD_TO	13	#ifdef CONFIG_SPL_PAD_TO
14	#ifdef CONFIG_SPL_MAX_SIZE	14	#ifdef CONFIG_SPL_MAX_SIZE
15	#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE	15	#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
16	#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE	16	#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
17	#endif	17	#endif
18	#endif	18	#endif
19	#else	19	#else
20	#ifdef CONFIG_SPL_MAX_SIZE	20	#ifdef CONFIG_SPL_MAX_SIZE
21	#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE	21	#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
22	#else	22	#else
23	#define CONFIG_SPL_PAD_TO 0	23	#define CONFIG_SPL_PAD_TO 0
24	#endif	24	#endif
25	#endif	25	#endif
26	#endif	26	#endif
27		27
28	#ifndef CONFIG_SYS_BAUDRATE_TABLE	28	#ifndef CONFIG_SYS_BAUDRATE_TABLE
29	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }	29	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
30	#endif	30	#endif
31		31
32	#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)	32	#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
33	#define CONFIG_FS_FAT	33	#define CONFIG_FS_FAT
34	#endif	34	#endif
35		35
36	#if (defined(CONFIG_CMD_EXT4) \|\| defined(CONFIG_CMD_EXT2)) && \	36	#if (defined(CONFIG_CMD_EXT4) \|\| defined(CONFIG_CMD_EXT2)) && \
37	!defined(CONFIG_FS_EXT4)	37	!defined(CONFIG_FS_EXT4)
38	#define CONFIG_FS_EXT4	38	#define CONFIG_FS_EXT4
39	#endif	39	#endif
40		40
41	#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)	41	#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
42	#define CONFIG_EXT4_WRITE	42	#define CONFIG_EXT4_WRITE
43	#endif	43	#endif
44		44
45	/* Rather than repeat this expression each time, add a define for it */	45	/* Rather than repeat this expression each time, add a define for it */
46	#if defined(CONFIG_CMD_IDE) \|\| \	46	#if defined(CONFIG_IDE) \|\| \
47	defined(CONFIG_CMD_SATA) \|\| \	47	defined(CONFIG_CMD_SATA) \|\| \
48	defined(CONFIG_SCSI) \|\| \	48	defined(CONFIG_SCSI) \|\| \
49	defined(CONFIG_CMD_USB) \|\| \	49	defined(CONFIG_CMD_USB) \|\| \
50	defined(CONFIG_CMD_PART) \|\| \	50	defined(CONFIG_CMD_PART) \|\| \
51	defined(CONFIG_CMD_GPT) \|\| \	51	defined(CONFIG_CMD_GPT) \|\| \
52	defined(CONFIG_MMC) \|\| \	52	defined(CONFIG_MMC) \|\| \
53	defined(CONFIG_SYSTEMACE) \|\| \	53	defined(CONFIG_SYSTEMACE) \|\| \
54	defined(CONFIG_SANDBOX)	54	defined(CONFIG_SANDBOX)
55	#define HAVE_BLOCK_DEVICE	55	#define HAVE_BLOCK_DEVICE
56	#endif	56	#endif
57		57
58	#if (CONFIG_IS_ENABLED(PARTITION_UUIDS) \|\| \	58	#if (CONFIG_IS_ENABLED(PARTITION_UUIDS) \|\| \
59	CONFIG_IS_ENABLED(EFI_PARTITION) \|\| \	59	CONFIG_IS_ENABLED(EFI_PARTITION) \|\| \
60	defined(CONFIG_RANDOM_UUID) \|\| \	60	defined(CONFIG_RANDOM_UUID) \|\| \
61	defined(CONFIG_CMD_UUID) \|\| \	61	defined(CONFIG_CMD_UUID) \|\| \
62	defined(CONFIG_BOOTP_PXE)) && \	62	defined(CONFIG_BOOTP_PXE)) && \
63	!defined(CONFIG_LIB_UUID)	63	!defined(CONFIG_LIB_UUID)
64	#define CONFIG_LIB_UUID	64	#define CONFIG_LIB_UUID
65	#endif	65	#endif
66		66
67	#if (defined(CONFIG_RANDOM_UUID) \|\| \	67	#if (defined(CONFIG_RANDOM_UUID) \|\| \
68	defined(CONFIG_CMD_UUID)) && \	68	defined(CONFIG_CMD_UUID)) && \
69	(!defined(CONFIG_LIB_RAND) && \	69	(!defined(CONFIG_LIB_RAND) && \
70	!defined(CONFIG_LIB_HW_RAND))	70	!defined(CONFIG_LIB_HW_RAND))
71	#define CONFIG_LIB_RAND	71	#define CONFIG_LIB_RAND
72	#endif	72	#endif
73		73
74	#ifndef CONFIG_SYS_PBSIZE	74	#ifndef CONFIG_SYS_PBSIZE
75	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128)	75	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128)
76	#endif	76	#endif
77		77
78	#ifndef CONFIG_FIT_SIGNATURE	78	#ifndef CONFIG_FIT_SIGNATURE
79	#define CONFIG_IMAGE_FORMAT_LEGACY	79	#define CONFIG_IMAGE_FORMAT_LEGACY
80	#endif	80	#endif
81		81
82	#ifdef CONFIG_DISABLE_IMAGE_LEGACY	82	#ifdef CONFIG_DISABLE_IMAGE_LEGACY
83	#undef CONFIG_IMAGE_FORMAT_LEGACY	83	#undef CONFIG_IMAGE_FORMAT_LEGACY
84	#endif	84	#endif
85		85
86	#ifdef CONFIG_DM_I2C	86	#ifdef CONFIG_DM_I2C
87	# ifdef CONFIG_SYS_I2C	87	# ifdef CONFIG_SYS_I2C
88	# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"	88	# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
89	# endif	89	# endif
90	#endif	90	#endif
91		91
92	#ifndef CONFIG_CMDLINE	92	#ifndef CONFIG_CMDLINE
93	#undef CONFIG_CMDLINE_EDITING	93	#undef CONFIG_CMDLINE_EDITING
94	#undef CONFIG_SYS_LONGHELP	94	#undef CONFIG_SYS_LONGHELP
95	#endif	95	#endif
96		96
97	#endif /* __CONFIG_FALLBACKS_H */	97	#endif /* __CONFIG_FALLBACKS_H */
98		98

include/configs/M5253DEMO.h

Diff comments View file @ fc843a0

include/configs/edminiv2.h

Diff comments View file @ fc843a0

include/configs/ib62x0.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Copyright (C) 2011-2012	2	* Copyright (C) 2011-2012
3	* Gerald Kerma <dreagle@doukki.net>	3	* Gerald Kerma <dreagle@doukki.net>
4	* Luka Perkov <luka@openwrt.org>	4	* Luka Perkov <luka@openwrt.org>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	#ifndef _CONFIG_IB62x0_H	9	#ifndef _CONFIG_IB62x0_H
10	#define _CONFIG_IB62x0_H	10	#define _CONFIG_IB62x0_H
11		11
12	/*	12	/*
13	* High level configuration options	13	* High level configuration options
14	*/	14	*/
15	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */	15	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
16	#define CONFIG_KW88F6281 /* SOC Name */	16	#define CONFIG_KW88F6281 /* SOC Name */
17	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */	17	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
18		18
19	/* Add target to build it automatically upon "make" */	19	/* Add target to build it automatically upon "make" */
20	#define CONFIG_BUILD_TARGET "u-boot.kwb"	20	#define CONFIG_BUILD_TARGET "u-boot.kwb"
21		21
22	/*	22	/*
23	* Compression configuration	23	* Compression configuration
24	*/	24	*/
25	#define CONFIG_BZIP2	25	#define CONFIG_BZIP2
26	#define CONFIG_LZMA	26	#define CONFIG_LZMA
27		27
28	/*	28	/*
29	* Commands configuration	29	* Commands configuration
30	*/	30	*/
31	#define CONFIG_SYS_MVFS	31	#define CONFIG_SYS_MVFS
32		32
33	/*	33	/*
34	* mv-common.h should be defined after CMD configs since it used them	34	* mv-common.h should be defined after CMD configs since it used them
35	* to enable certain macros	35	* to enable certain macros
36	*/	36	*/
37	#include "mv-common.h"	37	#include "mv-common.h"
38		38
39	/*	39	/*
40	* Environment variables configuration	40	* Environment variables configuration
41	*/	41	*/
42	#ifdef CONFIG_CMD_NAND	42	#ifdef CONFIG_CMD_NAND
43	#define CONFIG_ENV_IS_IN_NAND	43	#define CONFIG_ENV_IS_IN_NAND
44	#define CONFIG_ENV_SECT_SIZE 0x20000	44	#define CONFIG_ENV_SECT_SIZE 0x20000
45	#else	45	#else
46	#define CONFIG_ENV_IS_NOWHERE	46	#define CONFIG_ENV_IS_NOWHERE
47	#endif	47	#endif
48	#define CONFIG_ENV_SIZE 0x20000	48	#define CONFIG_ENV_SIZE 0x20000
49	#define CONFIG_ENV_OFFSET 0xe0000	49	#define CONFIG_ENV_OFFSET 0xe0000
50		50
51	/*	51	/*
52	* Default environment variables	52	* Default environment variables
53	*/	53	*/
54	#define CONFIG_BOOTCOMMAND \	54	#define CONFIG_BOOTCOMMAND \
55	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \	55	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
56	"ubi part root; " \	56	"ubi part root; " \
57	"ubifsmount ubi:rootfs; " \	57	"ubifsmount ubi:rootfs; " \
58	"ubifsload 0x800000 ${kernel}; " \	58	"ubifsload 0x800000 ${kernel}; " \
59	"ubifsload 0x700000 ${fdt}; " \	59	"ubifsload 0x700000 ${fdt}; " \
60	"ubifsumount; " \	60	"ubifsumount; " \
61	"fdt addr 0x700000; fdt resize; fdt chosen; " \	61	"fdt addr 0x700000; fdt resize; fdt chosen; " \
62	"bootz 0x800000 - 0x700000"	62	"bootz 0x800000 - 0x700000"
63		63
64	#define CONFIG_MTDPARTS \	64	#define CONFIG_MTDPARTS \
65	"mtdparts=orion_nand:" \	65	"mtdparts=orion_nand:" \
66	"0xe0000@0x0(uboot)," \	66	"0xe0000@0x0(uboot)," \
67	"0x20000@0xe0000(uboot_env)," \	67	"0x20000@0xe0000(uboot_env)," \
68	"-@0x100000(root)\0"	68	"-@0x100000(root)\0"
69		69
70	#define CONFIG_EXTRA_ENV_SETTINGS \	70	#define CONFIG_EXTRA_ENV_SETTINGS \
71	"console=console=ttyS0,115200\0" \	71	"console=console=ttyS0,115200\0" \
72	"mtdids=nand0=orion_nand\0" \	72	"mtdids=nand0=orion_nand\0" \
73	"mtdparts="CONFIG_MTDPARTS \	73	"mtdparts="CONFIG_MTDPARTS \
74	"kernel=/boot/zImage\0" \	74	"kernel=/boot/zImage\0" \
75	"fdt=/boot/ib62x0.dtb\0" \	75	"fdt=/boot/ib62x0.dtb\0" \
76	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"	76	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
77		77
78	/*	78	/*
79	* Ethernet driver configuration	79	* Ethernet driver configuration
80	*/	80	*/
81	#ifdef CONFIG_CMD_NET	81	#ifdef CONFIG_CMD_NET
82	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */	82	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
83	#define CONFIG_PHY_BASE_ADR 0	83	#define CONFIG_PHY_BASE_ADR 0
84	#undef CONFIG_RESET_PHY_R	84	#undef CONFIG_RESET_PHY_R
85	#endif /* CONFIG_CMD_NET */	85	#endif /* CONFIG_CMD_NET */
86		86
87	/*	87	/*
88	* SATA driver configuration	88	* SATA driver configuration
89	*/	89	*/
90	#ifdef CONFIG_CMD_IDE	90	#ifdef CONFIG_IDE
91	#define __io	91	#define __io
92	#define CONFIG_IDE_PREINIT	92	#define CONFIG_IDE_PREINIT
93	#define CONFIG_MVSATA_IDE_USE_PORT0	93	#define CONFIG_MVSATA_IDE_USE_PORT0
94	#define CONFIG_MVSATA_IDE_USE_PORT1	94	#define CONFIG_MVSATA_IDE_USE_PORT1
95	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET	95	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
96	#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET	96	#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
97	#endif /* CONFIG_CMD_IDE */	97	#endif /* CONFIG_IDE */
98		98
99	/*	99	/*
100	* RTC driver configuration	100	* RTC driver configuration
101	*/	101	*/
102	#ifdef CONFIG_CMD_DATE	102	#ifdef CONFIG_CMD_DATE
103	#define CONFIG_RTC_MV	103	#define CONFIG_RTC_MV
104	#endif /* CONFIG_CMD_DATE */	104	#endif /* CONFIG_CMD_DATE */
105		105
106	#endif /* _CONFIG_IB62x0_H */	106	#endif /* _CONFIG_IB62x0_H */
107		107

include/configs/lsxl.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Copyright (c) 2012 Michael Walle	2	* Copyright (c) 2012 Michael Walle
3	* Michael Walle <michael@walle.cc>	3	* Michael Walle <michael@walle.cc>
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*/	6	*/
7		7
8	#ifndef _CONFIG_LSXL_H	8	#ifndef _CONFIG_LSXL_H
9	#define _CONFIG_LSXL_H	9	#define _CONFIG_LSXL_H
10		10
11	/*	11	/*
12	* Version number information	12	* Version number information
13	*/	13	*/
14	#if defined(CONFIG_LSCHLV2)	14	#if defined(CONFIG_LSCHLV2)
15	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg	15	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
16	#define CONFIG_MACH_TYPE 3006	16	#define CONFIG_MACH_TYPE 3006
17	#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */	17	#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
18	#elif defined(CONFIG_LSXHL)	18	#elif defined(CONFIG_LSXHL)
19	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg	19	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
20	#define CONFIG_MACH_TYPE 2663	20	#define CONFIG_MACH_TYPE 2663
21	/* CONFIG_SYS_TCLK is 200000000 by default */	21	/* CONFIG_SYS_TCLK is 200000000 by default */
22	#else	22	#else
23	#error "unknown board"	23	#error "unknown board"
24	#endif	24	#endif
25		25
26	/*	26	/*
27	* General configuration options	27	* General configuration options
28	*/	28	*/
29	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */	29	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
30	#define CONFIG_KW88F6281 /* SOC Name */	30	#define CONFIG_KW88F6281 /* SOC Name */
31		31
32	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */	32	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
33	#define CONFIG_MISC_INIT_R	33	#define CONFIG_MISC_INIT_R
34	#define CONFIG_SHOW_BOOT_PROGRESS	34	#define CONFIG_SHOW_BOOT_PROGRESS
35		35
36	#define CONFIG_KIRKWOOD_GPIO	36	#define CONFIG_KIRKWOOD_GPIO
37		37
38	/*	38	/*
39	* Commands configuration	39	* Commands configuration
40	*/	40	*/
41		41
42	/*	42	/*
43	* mv-common.h should be defined after CMD configs since it used them	43	* mv-common.h should be defined after CMD configs since it used them
44	* to enable certain macros	44	* to enable certain macros
45	*/	45	*/
46	#include "mv-common.h"	46	#include "mv-common.h"
47		47
48	/* loading initramfs images without uimage header */	48	/* loading initramfs images without uimage header */
49	#define CONFIG_SUPPORT_RAW_INITRD	49	#define CONFIG_SUPPORT_RAW_INITRD
50		50
51	/* ST M25P40 */	51	/* ST M25P40 */
52	#undef CONFIG_ENV_SPI_MAX_HZ	52	#undef CONFIG_ENV_SPI_MAX_HZ
53	#define CONFIG_ENV_SPI_MAX_HZ 25000000	53	#define CONFIG_ENV_SPI_MAX_HZ 25000000
54	#undef CONFIG_SF_DEFAULT_SPEED	54	#undef CONFIG_SF_DEFAULT_SPEED
55	#define CONFIG_SF_DEFAULT_SPEED 25000000	55	#define CONFIG_SF_DEFAULT_SPEED 25000000
56		56
57	/*	57	/*
58	* Environment variables configurations	58	* Environment variables configurations
59	*/	59	*/
60	#ifdef CONFIG_SPI_FLASH	60	#ifdef CONFIG_SPI_FLASH
61	#define CONFIG_SYS_MAX_FLASH_BANKS 1	61	#define CONFIG_SYS_MAX_FLASH_BANKS 1
62	#define CONFIG_SYS_MAX_FLASH_SECT 8	62	#define CONFIG_SYS_MAX_FLASH_SECT 8
63	#define CONFIG_ENV_IS_IN_SPI_FLASH 1	63	#define CONFIG_ENV_IS_IN_SPI_FLASH 1
64	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */	64	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
65	#else	65	#else
66	#define CONFIG_ENV_IS_NOWHERE	66	#define CONFIG_ENV_IS_NOWHERE
67	#endif	67	#endif
68		68
69	#define CONFIG_ENV_SIZE 0x10000 /* 64k */	69	#define CONFIG_ENV_SIZE 0x10000 /* 64k */
70	#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */	70	#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
71		71
72	/*	72	/*
73	* Default environment variables	73	* Default environment variables
74	*/	74	*/
75	#define CONFIG_LOADADDR 0x00800000	75	#define CONFIG_LOADADDR 0x00800000
76	#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}"	76	#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}"
77	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2"	77	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2"
78		78
79	#if defined(CONFIG_LSXHL)	79	#if defined(CONFIG_LSXHL)
80	#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb"	80	#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb"
81	#elif defined(CONFIG_LSCHLV2)	81	#elif defined(CONFIG_LSCHLV2)
82	#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb"	82	#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb"
83	#else	83	#else
84	#error "Unsupported board"	84	#error "Unsupported board"
85	#endif	85	#endif
86		86
87	#define CONFIG_EXTRA_ENV_SETTINGS \	87	#define CONFIG_EXTRA_ENV_SETTINGS \
88	"bootsource=legacy\0" \	88	"bootsource=legacy\0" \
89	"hdpart=0:1\0" \	89	"hdpart=0:1\0" \
90	"kernel_addr=0x00800000\0" \	90	"kernel_addr=0x00800000\0" \
91	"ramdisk_addr=0x01000000\0" \	91	"ramdisk_addr=0x01000000\0" \
92	"fdt_addr=0x00ff0000\0" \	92	"fdt_addr=0x00ff0000\0" \
93	"bootcmd_legacy=ide reset " \	93	"bootcmd_legacy=ide reset " \
94	"&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \	94	"&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \
95	"&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\	95	"&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\
96	"&& bootm ${kernel_addr} ${ramdisk_addr}\0" \	96	"&& bootm ${kernel_addr} ${ramdisk_addr}\0" \
97	"bootcmd_net=bootp ${kernel_addr} vmlinuz " \	97	"bootcmd_net=bootp ${kernel_addr} vmlinuz " \
98	"&& tftpboot ${ramdisk_addr} initrd.img " \	98	"&& tftpboot ${ramdisk_addr} initrd.img " \
99	"&& setenv ramdisk_len ${filesize} " \	99	"&& setenv ramdisk_len ${filesize} " \
100	"&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \	100	"&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \
101	"&& bootz ${kernel_addr} " \	101	"&& bootz ${kernel_addr} " \
102	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \	102	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
103	"bootcmd_hdd=ide reset " \	103	"bootcmd_hdd=ide reset " \
104	"&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \	104	"&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \
105	"&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \	105	"&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \
106	"&& setenv ramdisk_len ${filesize} " \	106	"&& setenv ramdisk_len ${filesize} " \
107	"&& load ide ${hdpart} ${fdt_addr} /dtb " \	107	"&& load ide ${hdpart} ${fdt_addr} /dtb " \
108	"&& bootz ${kernel_addr} " \	108	"&& bootz ${kernel_addr} " \
109	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \	109	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
110	"bootcmd_usb=usb start " \	110	"bootcmd_usb=usb start " \
111	"&& load usb 0:1 ${kernel_addr} /vmlinuz " \	111	"&& load usb 0:1 ${kernel_addr} /vmlinuz " \
112	"&& load usb 0:1 ${ramdisk_addr} /initrd.img " \	112	"&& load usb 0:1 ${ramdisk_addr} /initrd.img " \
113	"&& setenv ramdisk_len ${filesize} " \	113	"&& setenv ramdisk_len ${filesize} " \
114	"&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \	114	"&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \
115	"&& bootz ${kernel_addr} " \	115	"&& bootz ${kernel_addr} " \
116	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \	116	"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
117	"bootcmd_rescue=run config_nc_dhcp; run nc\0" \	117	"bootcmd_rescue=run config_nc_dhcp; run nc\0" \
118	"eraseenv=sf probe 0 " \	118	"eraseenv=sf probe 0 " \
119	"&& sf erase " __stringify(CONFIG_ENV_OFFSET) \	119	"&& sf erase " __stringify(CONFIG_ENV_OFFSET) \
120	" +" __stringify(CONFIG_ENV_SIZE) "\0" \	120	" +" __stringify(CONFIG_ENV_SIZE) "\0" \
121	"config_nc_dhcp=setenv autoload_old ${autoload}; " \	121	"config_nc_dhcp=setenv autoload_old ${autoload}; " \
122	"setenv autoload no " \	122	"setenv autoload no " \
123	"&& bootp " \	123	"&& bootp " \
124	"&& setenv ncip " \	124	"&& setenv ncip " \
125	"&& setenv autoload ${autoload_old}; " \	125	"&& setenv autoload ${autoload_old}; " \
126	"setenv autoload_old\0" \	126	"setenv autoload_old\0" \
127	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \	127	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
128	"setenv ncip; setenv gatewayip; setenv ethact; " \	128	"setenv ncip; setenv gatewayip; setenv ethact; " \
129	"setenv bootfile; setenv dnsip; " \	129	"setenv bootfile; setenv dnsip; " \
130	"setenv bootsource legacy; run ser\0" \	130	"setenv bootsource legacy; run ser\0" \
131	"restore_env=run standard_env; saveenv; reset\0" \	131	"restore_env=run standard_env; saveenv; reset\0" \
132	"ser=setenv stdin serial; setenv stdout serial; " \	132	"ser=setenv stdin serial; setenv stdout serial; " \
133	"setenv stderr serial\0" \	133	"setenv stderr serial\0" \
134	"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \	134	"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \
135	"stdin=serial\0" \	135	"stdin=serial\0" \
136	"stdout=serial\0" \	136	"stdout=serial\0" \
137	"stderr=serial\0"	137	"stderr=serial\0"
138		138
139	/*	139	/*
140	* Ethernet Driver configuration	140	* Ethernet Driver configuration
141	*/	141	*/
142	#ifdef CONFIG_CMD_NET	142	#ifdef CONFIG_CMD_NET
143	#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */	143	#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */
144	#define CONFIG_PHY_BASE_ADR 7	144	#define CONFIG_PHY_BASE_ADR 7
145	#undef CONFIG_RESET_PHY_R	145	#undef CONFIG_RESET_PHY_R
146	#endif /* CONFIG_CMD_NET */	146	#endif /* CONFIG_CMD_NET */
147		147
148	#ifdef CONFIG_CMD_IDE	148	#ifdef CONFIG_IDE
149	#undef CONFIG_IDE_LED	149	#undef CONFIG_IDE_LED
150	#undef CONFIG_SYS_IDE_MAXBUS	150	#undef CONFIG_SYS_IDE_MAXBUS
151	#define CONFIG_SYS_IDE_MAXBUS 1	151	#define CONFIG_SYS_IDE_MAXBUS 1
152	#undef CONFIG_SYS_IDE_MAXDEVICE	152	#undef CONFIG_SYS_IDE_MAXDEVICE
153	#define CONFIG_SYS_IDE_MAXDEVICE 1	153	#define CONFIG_SYS_IDE_MAXDEVICE 1
154	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET	154	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
155	#define CONFIG_SYS_64BIT_LBA	155	#define CONFIG_SYS_64BIT_LBA
156	#endif	156	#endif
157		157
158	#endif /* _CONFIG_LSXL_H */	158	#endif /* _CONFIG_LSXL_H */
159		159

include/configs/mpc5121ads.h

Diff comments View file @ fc843a0

include/configs/nsa310s.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Copyright (C) 2015	2	* Copyright (C) 2015
3	* Gerald Kerma <dreagle@doukki.net>	3	* Gerald Kerma <dreagle@doukki.net>
4	* Tony Dinh <mibodhi@gmail.com>	4	* Tony Dinh <mibodhi@gmail.com>
5	* Luka Perkov <luka.perkov@sartura.hr>	5	* Luka Perkov <luka.perkov@sartura.hr>
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#ifndef _CONFIG_NSA310S_H	10	#ifndef _CONFIG_NSA310S_H
11	#define _CONFIG_NSA310S_H	11	#define _CONFIG_NSA310S_H
12		12
13	/* high level configuration options */	13	/* high level configuration options */
14	#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */	14	#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
15	#define CONFIG_KW88F6192 1 /* SOC Name */	15	#define CONFIG_KW88F6192 1 /* SOC Name */
16	#define CONFIG_KW88F6702 1 /* SOC Name */	16	#define CONFIG_KW88F6702 1 /* SOC Name */
17	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */	17	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
18		18
19	/* add target to build it automatically upon "make" */	19	/* add target to build it automatically upon "make" */
20	#define CONFIG_BUILD_TARGET "u-boot.kwb"	20	#define CONFIG_BUILD_TARGET "u-boot.kwb"
21		21
22	/* compression configuration */	22	/* compression configuration */
23	#define CONFIG_BZIP2	23	#define CONFIG_BZIP2
24	#define CONFIG_LZMA	24	#define CONFIG_LZMA
25		25
26	/* commands configuration */	26	/* commands configuration */
27	#define CONFIG_SYS_MVFS	27	#define CONFIG_SYS_MVFS
28		28
29	/*	29	/*
30	* mv-common.h should be defined after CMD configs since it used them	30	* mv-common.h should be defined after CMD configs since it used them
31	* to enable certain macros	31	* to enable certain macros
32	*/	32	*/
33	#include "mv-common.h"	33	#include "mv-common.h"
34		34
35	/* environment variables configuration */	35	/* environment variables configuration */
36	#ifdef CONFIG_CMD_NAND	36	#ifdef CONFIG_CMD_NAND
37	#define CONFIG_ENV_IS_IN_NAND	37	#define CONFIG_ENV_IS_IN_NAND
38	#define CONFIG_ENV_SECT_SIZE 0x20000	38	#define CONFIG_ENV_SECT_SIZE 0x20000
39	#else	39	#else
40	#define CONFIG_ENV_IS_NOWHERE	40	#define CONFIG_ENV_IS_NOWHERE
41	#endif	41	#endif
42	#define CONFIG_ENV_SIZE 0x20000	42	#define CONFIG_ENV_SIZE 0x20000
43	#define CONFIG_ENV_OFFSET 0xe0000	43	#define CONFIG_ENV_OFFSET 0xe0000
44		44
45	/* default environment variables */	45	/* default environment variables */
46	#define CONFIG_BOOTCOMMAND \	46	#define CONFIG_BOOTCOMMAND \
47	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \	47	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
48	"ubi part root; " \	48	"ubi part root; " \
49	"ubifsmount ubi:rootfs; " \	49	"ubifsmount ubi:rootfs; " \
50	"ubifsload 0x800000 ${kernel}; " \	50	"ubifsload 0x800000 ${kernel}; " \
51	"ubifsload 0x700000 ${fdt}; " \	51	"ubifsload 0x700000 ${fdt}; " \
52	"ubifsumount; " \	52	"ubifsumount; " \
53	"fdt addr 0x700000; fdt resize; fdt chosen; " \	53	"fdt addr 0x700000; fdt resize; fdt chosen; " \
54	"bootz 0x800000 - 0x700000"	54	"bootz 0x800000 - 0x700000"
55		55
56	#define CONFIG_MTDPARTS \	56	#define CONFIG_MTDPARTS \
57	"mtdparts=orion_nand:" \	57	"mtdparts=orion_nand:" \
58	"0xe0000@0x0(uboot)," \	58	"0xe0000@0x0(uboot)," \
59	"0x20000@0xe0000(uboot_env)," \	59	"0x20000@0xe0000(uboot_env)," \
60	"0x100000@0x100000(second_stage_uboot)," \	60	"0x100000@0x100000(second_stage_uboot)," \
61	"-@0x200000(root)\0"	61	"-@0x200000(root)\0"
62		62
63	#define CONFIG_EXTRA_ENV_SETTINGS \	63	#define CONFIG_EXTRA_ENV_SETTINGS \
64	"console=console=ttyS0,115200\0" \	64	"console=console=ttyS0,115200\0" \
65	"mtdids=nand0=orion_nand\0" \	65	"mtdids=nand0=orion_nand\0" \
66	"mtdparts="CONFIG_MTDPARTS \	66	"mtdparts="CONFIG_MTDPARTS \
67	"kernel=/boot/zImage\0" \	67	"kernel=/boot/zImage\0" \
68	"fdt=/boot/nsa310s.dtb\0" \	68	"fdt=/boot/nsa310s.dtb\0" \
69	"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"	69	"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
70		70
71	/* Ethernet driver configuration */	71	/* Ethernet driver configuration */
72	#ifdef CONFIG_CMD_NET	72	#ifdef CONFIG_CMD_NET
73	#define CONFIG_NETCONSOLE	73	#define CONFIG_NETCONSOLE
74	#define CONFIG_NET_MULTI	74	#define CONFIG_NET_MULTI
75	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */	75	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
76	#define CONFIG_PHY_BASE_ADR 1	76	#define CONFIG_PHY_BASE_ADR 1
77	#define CONFIG_PHY_GIGE	77	#define CONFIG_PHY_GIGE
78	#define CONFIG_RESET_PHY_R	78	#define CONFIG_RESET_PHY_R
79	#endif /* CONFIG_CMD_NET */	79	#endif /* CONFIG_CMD_NET */
80		80
81	/* SATA driver configuration */	81	/* SATA driver configuration */
82	#ifdef CONFIG_CMD_IDE	82	#ifdef CONFIG_IDE
83	#define __io	83	#define __io
84	#define CONFIG_IDE_PREINIT	84	#define CONFIG_IDE_PREINIT
85	#define CONFIG_MVSATA_IDE_USE_PORT0	85	#define CONFIG_MVSATA_IDE_USE_PORT0
86	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET	86	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
87	#endif /* CONFIG_CMD_IDE */	87	#endif /* CONFIG_IDE */
88		88
89	/* RTC driver configuration */	89	/* RTC driver configuration */
90	#ifdef CONFIG_CMD_DATE	90	#ifdef CONFIG_CMD_DATE
91	#define CONFIG_RTC_MV	91	#define CONFIG_RTC_MV
92	#endif /* CONFIG_CMD_DATE */	92	#endif /* CONFIG_CMD_DATE */
93		93
94	#endif /* _CONFIG_NSA310S_H */	94	#endif /* _CONFIG_NSA310S_H */
95		95

include/configs/qemu-x86.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>	2	* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	/*	7	/*
8	* board/config.h - configuration options, board specific	8	* board/config.h - configuration options, board specific
9	*/	9	*/
10		10
11	#ifndef __CONFIG_H	11	#ifndef __CONFIG_H
12	#define __CONFIG_H	12	#define __CONFIG_H
13		13
14	#include <configs/x86-common.h>	14	#include <configs/x86-common.h>
15		15
16	#define CONFIG_SYS_MONITOR_LEN (1 << 20)	16	#define CONFIG_SYS_MONITOR_LEN (1 << 20)
17		17
18	#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \	18	#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
19	"stdout=serial,vidconsole\0" \	19	"stdout=serial,vidconsole\0" \
20	"stderr=serial,vidconsole\0"	20	"stderr=serial,vidconsole\0"
21		21
22	/*	22	/*
23	* ATA/SATA support for QEMU x86 targets	23	* ATA/SATA support for QEMU x86 targets
24	* - Only legacy IDE controller is supported for QEMU '-M pc' target	24	* - Only legacy IDE controller is supported for QEMU '-M pc' target
25	* - AHCI controller is supported for QEMU '-M q35' target	25	* - AHCI controller is supported for QEMU '-M q35' target
26	*	26	*
27	* Default configuraion is to support the QEMU default x86 target	27	* Default configuraion is to support the QEMU default x86 target
28	* Undefine CONFIG_CMD_IDE to support q35 target	28	* Undefine CONFIG_IDE to support q35 target
29	*/	29	*/
30	#ifdef CONFIG_CMD_IDE	30	#ifdef CONFIG_IDE
31	#define CONFIG_SYS_IDE_MAXBUS 2	31	#define CONFIG_SYS_IDE_MAXBUS 2
32	#define CONFIG_SYS_IDE_MAXDEVICE 4	32	#define CONFIG_SYS_IDE_MAXDEVICE 4
33	#define CONFIG_SYS_ATA_BASE_ADDR 0	33	#define CONFIG_SYS_ATA_BASE_ADDR 0
34	#define CONFIG_SYS_ATA_DATA_OFFSET 0	34	#define CONFIG_SYS_ATA_DATA_OFFSET 0
35	#define CONFIG_SYS_ATA_REG_OFFSET 0	35	#define CONFIG_SYS_ATA_REG_OFFSET 0
36	#define CONFIG_SYS_ATA_ALT_OFFSET 0	36	#define CONFIG_SYS_ATA_ALT_OFFSET 0
37	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0	37	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
38	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170	38	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
39	#define CONFIG_ATAPI	39	#define CONFIG_ATAPI
40		40
41	#undef CONFIG_SCSI_AHCI	41	#undef CONFIG_SCSI_AHCI
42	#undef CONFIG_SCSI	42	#undef CONFIG_SCSI
43	#else	43	#else
44	#define CONFIG_SCSI_DEV_LIST \	44	#define CONFIG_SCSI_DEV_LIST \
45	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}	45	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
46	#endif	46	#endif
47		47
48	/* GPIO is not supported */	48	/* GPIO is not supported */
49	#undef CONFIG_INTEL_ICH6_GPIO	49	#undef CONFIG_INTEL_ICH6_GPIO
50		50
51	/* SPI is not supported */	51	/* SPI is not supported */
52	#undef CONFIG_ENV_IS_IN_SPI_FLASH	52	#undef CONFIG_ENV_IS_IN_SPI_FLASH
53	#define CONFIG_ENV_IS_NOWHERE	53	#define CONFIG_ENV_IS_NOWHERE
54		54
55	#define CONFIG_SPL_FRAMEWORK	55	#define CONFIG_SPL_FRAMEWORK
56		56
57	#define CONFIG_SPL_TEXT_BASE 0xfffd0000	57	#define CONFIG_SPL_TEXT_BASE 0xfffd0000
58		58
59	#define BOOT_DEVICE_SPI 10	59	#define BOOT_DEVICE_SPI 10
60		60
61	#define CONFIG_SPL_BOARD_LOAD_IMAGE	61	#define CONFIG_SPL_BOARD_LOAD_IMAGE
62	#define BOOT_DEVICE_BOARD 11	62	#define BOOT_DEVICE_BOARD 11
63		63
64	#endif /* __CONFIG_H */	64	#endif /* __CONFIG_H */
65		65

include/configs/r7780mp.h

Diff comments View file @ fc843a0

include/configs/sheevaplug.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2009-2014	2	* (C) Copyright 2009-2014
3	* Gerald Kerma <dreagle@doukki.net>	3	* Gerald Kerma <dreagle@doukki.net>
4	* Marvell Semiconductor <www.marvell.com>	4	* Marvell Semiconductor <www.marvell.com>
5	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>	5	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#ifndef _CONFIG_SHEEVAPLUG_H	10	#ifndef _CONFIG_SHEEVAPLUG_H
11	#define _CONFIG_SHEEVAPLUG_H	11	#define _CONFIG_SHEEVAPLUG_H
12		12
13	/*	13	/*
14	* High Level Configuration Options (easy to change)	14	* High Level Configuration Options (easy to change)
15	*/	15	*/
16	#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */	16	#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
17	#define CONFIG_MACH_SHEEVAPLUG /* Machine type */	17	#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
18		18
19	/*	19	/*
20	* Commands configuration	20	* Commands configuration
21	*/	21	*/
22		22
23	/*	23	/*
24	* Standard filesystems	24	* Standard filesystems
25	*/	25	*/
26	#define CONFIG_SYS_MVFS	26	#define CONFIG_SYS_MVFS
27		27
28	/*	28	/*
29	* mv-plug-common.h should be defined after CMD configs since it used them	29	* mv-plug-common.h should be defined after CMD configs since it used them
30	* to enable certain macros	30	* to enable certain macros
31	*/	31	*/
32	#include "mv-plug-common.h"	32	#include "mv-plug-common.h"
33		33
34	/*	34	/*
35	* Environment variables configurations	35	* Environment variables configurations
36	*/	36	*/
37	#ifdef CONFIG_CMD_NAND	37	#ifdef CONFIG_CMD_NAND
38	#define CONFIG_ENV_IS_IN_NAND 1	38	#define CONFIG_ENV_IS_IN_NAND 1
39	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */	39	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
40	#else	40	#else
41	#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */	41	#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
42	#endif	42	#endif
43	/*	43	/*
44	* max 4k env size is enough, but in case of nand	44	* max 4k env size is enough, but in case of nand
45	* it has to be rounded to sector size	45	* it has to be rounded to sector size
46	*/	46	*/
47	#define CONFIG_ENV_SIZE 0x20000 /* 128k */	47	#define CONFIG_ENV_SIZE 0x20000 /* 128k */
48	#define CONFIG_ENV_ADDR 0x80000	48	#define CONFIG_ENV_ADDR 0x80000
49	#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */	49	#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
50		50
51	/*	51	/*
52	* Default environment variables	52	* Default environment variables
53	*/	53	*/
54	#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \	54	#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
55	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \	55	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
56	"bootm 0x6400000;"	56	"bootm 0x6400000;"
57		57
58	#define CONFIG_MTDPARTS \	58	#define CONFIG_MTDPARTS \
59	"orion_nand:512K(uboot)," \	59	"orion_nand:512K(uboot)," \
60	"512K(env),4M(kernel)," \	60	"512K(env),4M(kernel)," \
61	"-(rootfs)\0"	61	"-(rootfs)\0"
62		62
63	#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \	63	#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
64	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \	64	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
65	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \	65	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
66	"x_bootcmd_usb=usb start\0" \	66	"x_bootcmd_usb=usb start\0" \
67	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"	67	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
68		68
69	#define MTDIDS_DEFAULT "nand0=orion_nand"	69	#define MTDIDS_DEFAULT "nand0=orion_nand"
70		70
71	#define MTDPARTS_DEFAULT \	71	#define MTDPARTS_DEFAULT \
72	"mtdparts="CONFIG_MTDPARTS	72	"mtdparts="CONFIG_MTDPARTS
73		73
74	/*	74	/*
75	* Ethernet Driver configuration	75	* Ethernet Driver configuration
76	*/	76	*/
77	#ifdef CONFIG_CMD_NET	77	#ifdef CONFIG_CMD_NET
78	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */	78	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
79	#define CONFIG_PHY_BASE_ADR 0	79	#define CONFIG_PHY_BASE_ADR 0
80	#endif /* CONFIG_CMD_NET */	80	#endif /* CONFIG_CMD_NET */
81		81
82	/*	82	/*
83	* SDIO/MMC Card Configuration	83	* SDIO/MMC Card Configuration
84	*/	84	*/
85	#ifdef CONFIG_CMD_MMC	85	#ifdef CONFIG_CMD_MMC
86	#define CONFIG_MVEBU_MMC	86	#define CONFIG_MVEBU_MMC
87	#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE	87	#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
88	#endif /* CONFIG_CMD_MMC */	88	#endif /* CONFIG_CMD_MMC */
89		89
90	/*	90	/*
91	* SATA driver configuration	91	* SATA driver configuration
92	*/	92	*/
93	#ifdef CONFIG_CMD_IDE	93	#ifdef CONFIG_IDE
94	#define __io	94	#define __io
95	#define CONFIG_IDE_PREINIT	95	#define CONFIG_IDE_PREINIT
96	#define CONFIG_MVSATA_IDE_USE_PORT0	96	#define CONFIG_MVSATA_IDE_USE_PORT0
97	#define CONFIG_MVSATA_IDE_USE_PORT1	97	#define CONFIG_MVSATA_IDE_USE_PORT1
98	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET	98	#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
99	#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET	99	#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
100	#endif /* CONFIG_CMD_IDE */	100	#endif /* CONFIG_IDE */
101		101
102	#endif /* _CONFIG_SHEEVAPLUG_H */	102	#endif /* _CONFIG_SHEEVAPLUG_H */
103		103

include/pcmcia.h

Diff comments View file @ fc843a0

1	/*	1	/*
2	* (C) Copyright 2000-2004	2	* (C) Copyright 2000-2004
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*/	6	*/
7		7
8	#ifndef _PCMCIA_H	8	#ifndef _PCMCIA_H
9	#define _PCMCIA_H	9	#define _PCMCIA_H
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <config.h>	12	#include <config.h>
13		13
14	/*	14	/*
15	* Allow configuration to select PCMCIA slot,	15	* Allow configuration to select PCMCIA slot,
16	* or try to generate a useful default	16	* or try to generate a useful default
17	*/	17	*/
18	#if defined(CONFIG_CMD_PCMCIA) \|\| \	18	#if defined(CONFIG_CMD_PCMCIA) \|\| \
19	(defined(CONFIG_CMD_IDE) && \	19	(defined(CONFIG_IDE) && \
20	(defined(CONFIG_IDE_8xx_PCCARD) \|\| defined(CONFIG_IDE_8xx_DIRECT) ) )	20	(defined(CONFIG_IDE_8xx_PCCARD) \|\| defined(CONFIG_IDE_8xx_DIRECT) ) )
21		21
22	#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)	22	#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
23		23
24	#if defined(CONFIG_TQM8xxL)	24	#if defined(CONFIG_TQM8xxL)
25	# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */	25	# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26	#else	26	#else
27	# error "PCMCIA Slot not configured"	27	# error "PCMCIA Slot not configured"
28	#endif	28	#endif
29		29
30	#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */	30	#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
31		31
32	/* Make sure exactly one slot is defined - we support only one for now */	32	/* Make sure exactly one slot is defined - we support only one for now */
33	#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)	33	#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
34	#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured	34	#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
35	#endif	35	#endif
36	#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)	36	#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
37	#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured	37	#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
38	#endif	38	#endif
39		39
40	#ifndef PCMCIA_SOCKETS_NO	40	#ifndef PCMCIA_SOCKETS_NO
41	#define PCMCIA_SOCKETS_NO 1	41	#define PCMCIA_SOCKETS_NO 1
42	#endif	42	#endif
43	#ifndef PCMCIA_MEM_WIN_NO	43	#ifndef PCMCIA_MEM_WIN_NO
44	#define PCMCIA_MEM_WIN_NO 4	44	#define PCMCIA_MEM_WIN_NO 4
45	#endif	45	#endif
46	#define PCMCIA_IO_WIN_NO 2	46	#define PCMCIA_IO_WIN_NO 2
47		47
48	/* define _slot_ to be able to optimize macros */	48	/* define _slot_ to be able to optimize macros */
49	#ifdef CONFIG_PCMCIA_SLOT_A	49	#ifdef CONFIG_PCMCIA_SLOT_A
50	# define _slot_ 0	50	# define _slot_ 0
51	# define PCMCIA_SLOT_MSG "slot A"	51	# define PCMCIA_SLOT_MSG "slot A"
52	# define PCMCIA_SLOT_x PCMCIA_PSLOT_A	52	# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
53	#else	53	#else
54	# define _slot_ 1	54	# define _slot_ 1
55	# define PCMCIA_SLOT_MSG "slot B"	55	# define PCMCIA_SLOT_MSG "slot B"
56	# define PCMCIA_SLOT_x PCMCIA_PSLOT_B	56	# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
57	#endif	57	#endif
58		58
59	/*	59	/*
60	* The TQM850L hardware has two pins swapped! Grrrrgh!	60	* The TQM850L hardware has two pins swapped! Grrrrgh!
61	*/	61	*/
62	#ifdef CONFIG_TQM850L	62	#ifdef CONFIG_TQM850L
63	#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE	63	#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
64	#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET	64	#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
65	#else	65	#else
66	#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET	66	#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
67	#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE	67	#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
68	#endif	68	#endif
69		69
70	/*	70	/*
71	* This structure is used to address each window in the PCMCIA controller.	71	* This structure is used to address each window in the PCMCIA controller.
72	*	72	*
73	* Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly	73	* Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
74	* after pcmcia_win_t[n]...	74	* after pcmcia_win_t[n]...
75	*/	75	*/
76		76
77	typedef struct {	77	typedef struct {
78	ulong br;	78	ulong br;
79	ulong or;	79	ulong or;
80	} pcmcia_win_t;	80	} pcmcia_win_t;
81		81
82	/*	82	/*
83	* Definitions for PCMCIA control registers to operate in IDE mode	83	* Definitions for PCMCIA control registers to operate in IDE mode
84	*	84	*
85	* All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)	85	* All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
86	* to be done later (depending on CPU clock)	86	* to be done later (depending on CPU clock)
87	*/	87	*/
88		88
89	/* Window 0:	89	/* Window 0:
90	* Base: 0xFE100000 CS1	90	* Base: 0xFE100000 CS1
91	* Port Size: 2 Bytes	91	* Port Size: 2 Bytes
92	* Port Size: 16 Bit	92	* Port Size: 16 Bit
93	* Common Memory Space	93	* Common Memory Space
94	*/	94	*/
95		95
96	#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000	96	#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
97	#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \	97	#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
98	\| PCMCIA_PPS_16 \	98	\| PCMCIA_PPS_16 \
99	\| PCMCIA_PRS_MEM \	99	\| PCMCIA_PRS_MEM \
100	\| PCMCIA_SLOT_x \	100	\| PCMCIA_SLOT_x \
101	\| PCMCIA_PV \	101	\| PCMCIA_PV \
102	)	102	)
103		103
104	/* Window 1:	104	/* Window 1:
105	* Base: 0xFE100080 CS1	105	* Base: 0xFE100080 CS1
106	* Port Size: 8 Bytes	106	* Port Size: 8 Bytes
107	* Port Size: 8 Bit	107	* Port Size: 8 Bit
108	* Common Memory Space	108	* Common Memory Space
109	*/	109	*/
110		110
111	#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080	111	#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
112	#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \	112	#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
113	\| PCMCIA_PPS_8 \	113	\| PCMCIA_PPS_8 \
114	\| PCMCIA_PRS_MEM \	114	\| PCMCIA_PRS_MEM \
115	\| PCMCIA_SLOT_x \	115	\| PCMCIA_SLOT_x \
116	\| PCMCIA_PV \	116	\| PCMCIA_PV \
117	)	117	)
118		118
119	/* Window 2:	119	/* Window 2:
120	* Base: 0xFE100100 CS2	120	* Base: 0xFE100100 CS2
121	* Port Size: 8 Bytes	121	* Port Size: 8 Bytes
122	* Port Size: 8 Bit	122	* Port Size: 8 Bit
123	* Common Memory Space	123	* Common Memory Space
124	*/	124	*/
125		125
126	#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100	126	#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
127	#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \	127	#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
128	\| PCMCIA_PPS_8 \	128	\| PCMCIA_PPS_8 \
129	\| PCMCIA_PRS_MEM \	129	\| PCMCIA_PRS_MEM \
130	\| PCMCIA_SLOT_x \	130	\| PCMCIA_SLOT_x \
131	\| PCMCIA_PV \	131	\| PCMCIA_PV \
132	)	132	)
133		133
134	/* Window 3:	134	/* Window 3:
135	* not used	135	* not used
136	*/	136	*/
137	#define CONFIG_SYS_PCMCIA_PBR3 0	137	#define CONFIG_SYS_PCMCIA_PBR3 0
138	#define CONFIG_SYS_PCMCIA_POR3 0	138	#define CONFIG_SYS_PCMCIA_POR3 0
139		139
140	/* Window 4:	140	/* Window 4:
141	* Base: 0xFE100C00 CS1	141	* Base: 0xFE100C00 CS1
142	* Port Size: 2 Bytes	142	* Port Size: 2 Bytes
143	* Port Size: 16 Bit	143	* Port Size: 16 Bit
144	* Common Memory Space	144	* Common Memory Space
145	*/	145	*/
146		146
147	#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00	147	#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
148	#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \	148	#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
149	\| PCMCIA_PPS_16 \	149	\| PCMCIA_PPS_16 \
150	\| PCMCIA_PRS_MEM \	150	\| PCMCIA_PRS_MEM \
151	\| PCMCIA_SLOT_x \	151	\| PCMCIA_SLOT_x \
152	\| PCMCIA_PV \	152	\| PCMCIA_PV \
153	)	153	)
154		154
155	/* Window 5:	155	/* Window 5:
156	* Base: 0xFE100C80 CS1	156	* Base: 0xFE100C80 CS1
157	* Port Size: 8 Bytes	157	* Port Size: 8 Bytes
158	* Port Size: 8 Bit	158	* Port Size: 8 Bit
159	* Common Memory Space	159	* Common Memory Space
160	*/	160	*/
161		161
162	#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80	162	#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
163	#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \	163	#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
164	\| PCMCIA_PPS_8 \	164	\| PCMCIA_PPS_8 \
165	\| PCMCIA_PRS_MEM \	165	\| PCMCIA_PRS_MEM \
166	\| PCMCIA_SLOT_x \	166	\| PCMCIA_SLOT_x \
167	\| PCMCIA_PV \	167	\| PCMCIA_PV \
168	)	168	)
169		169
170	/* Window 6:	170	/* Window 6:
171	* Base: 0xFE100D00 CS2	171	* Base: 0xFE100D00 CS2
172	* Port Size: 8 Bytes	172	* Port Size: 8 Bytes
173	* Port Size: 8 Bit	173	* Port Size: 8 Bit
174	* Common Memory Space	174	* Common Memory Space
175	*/	175	*/
176		176
177	#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00	177	#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
178	#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \	178	#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
179	\| PCMCIA_PPS_8 \	179	\| PCMCIA_PPS_8 \
180	\| PCMCIA_PRS_MEM \	180	\| PCMCIA_PRS_MEM \
181	\| PCMCIA_SLOT_x \	181	\| PCMCIA_SLOT_x \
182	\| PCMCIA_PV \	182	\| PCMCIA_PV \
183	)	183	)
184		184
185	/* Window 7:	185	/* Window 7:
186	* not used	186	* not used
187	*/	187	*/
188	#define CONFIG_SYS_PCMCIA_PBR7 0	188	#define CONFIG_SYS_PCMCIA_PBR7 0
189	#define CONFIG_SYS_PCMCIA_POR7 0	189	#define CONFIG_SYS_PCMCIA_POR7 0
190		190
191	/**********************************************************************/	191	/**********************************************************************/
192		192
193	/*	193	/*
194	* CIS Tupel codes	194	* CIS Tupel codes
195	*/	195	*/
196	#define CISTPL_NULL 0x00	196	#define CISTPL_NULL 0x00
197	#define CISTPL_DEVICE 0x01	197	#define CISTPL_DEVICE 0x01
198	#define CISTPL_LONGLINK_CB 0x02	198	#define CISTPL_LONGLINK_CB 0x02
199	#define CISTPL_INDIRECT 0x03	199	#define CISTPL_INDIRECT 0x03
200	#define CISTPL_CONFIG_CB 0x04	200	#define CISTPL_CONFIG_CB 0x04
201	#define CISTPL_CFTABLE_ENTRY_CB 0x05	201	#define CISTPL_CFTABLE_ENTRY_CB 0x05
202	#define CISTPL_LONGLINK_MFC 0x06	202	#define CISTPL_LONGLINK_MFC 0x06
203	#define CISTPL_BAR 0x07	203	#define CISTPL_BAR 0x07
204	#define CISTPL_PWR_MGMNT 0x08	204	#define CISTPL_PWR_MGMNT 0x08
205	#define CISTPL_EXTDEVICE 0x09	205	#define CISTPL_EXTDEVICE 0x09
206	#define CISTPL_CHECKSUM 0x10	206	#define CISTPL_CHECKSUM 0x10
207	#define CISTPL_LONGLINK_A 0x11	207	#define CISTPL_LONGLINK_A 0x11
208	#define CISTPL_LONGLINK_C 0x12	208	#define CISTPL_LONGLINK_C 0x12
209	#define CISTPL_LINKTARGET 0x13	209	#define CISTPL_LINKTARGET 0x13
210	#define CISTPL_NO_LINK 0x14	210	#define CISTPL_NO_LINK 0x14
211	#define CISTPL_VERS_1 0x15	211	#define CISTPL_VERS_1 0x15
212	#define CISTPL_ALTSTR 0x16	212	#define CISTPL_ALTSTR 0x16
213	#define CISTPL_DEVICE_A 0x17	213	#define CISTPL_DEVICE_A 0x17
214	#define CISTPL_JEDEC_C 0x18	214	#define CISTPL_JEDEC_C 0x18
215	#define CISTPL_JEDEC_A 0x19	215	#define CISTPL_JEDEC_A 0x19
216	#define CISTPL_CONFIG 0x1a	216	#define CISTPL_CONFIG 0x1a
217	#define CISTPL_CFTABLE_ENTRY 0x1b	217	#define CISTPL_CFTABLE_ENTRY 0x1b
218	#define CISTPL_DEVICE_OC 0x1c	218	#define CISTPL_DEVICE_OC 0x1c
219	#define CISTPL_DEVICE_OA 0x1d	219	#define CISTPL_DEVICE_OA 0x1d
220	#define CISTPL_DEVICE_GEO 0x1e	220	#define CISTPL_DEVICE_GEO 0x1e
221	#define CISTPL_DEVICE_GEO_A 0x1f	221	#define CISTPL_DEVICE_GEO_A 0x1f
222	#define CISTPL_MANFID 0x20	222	#define CISTPL_MANFID 0x20
223	#define CISTPL_FUNCID 0x21	223	#define CISTPL_FUNCID 0x21
224	#define CISTPL_FUNCE 0x22	224	#define CISTPL_FUNCE 0x22
225	#define CISTPL_SWIL 0x23	225	#define CISTPL_SWIL 0x23
226	#define CISTPL_END 0xff	226	#define CISTPL_END 0xff
227		227
228	/*	228	/*
229	* CIS Function ID codes	229	* CIS Function ID codes
230	*/	230	*/
231	#define CISTPL_FUNCID_MULTI 0x00	231	#define CISTPL_FUNCID_MULTI 0x00
232	#define CISTPL_FUNCID_MEMORY 0x01	232	#define CISTPL_FUNCID_MEMORY 0x01
233	#define CISTPL_FUNCID_SERIAL 0x02	233	#define CISTPL_FUNCID_SERIAL 0x02
234	#define CISTPL_FUNCID_PARALLEL 0x03	234	#define CISTPL_FUNCID_PARALLEL 0x03
235	#define CISTPL_FUNCID_FIXED 0x04	235	#define CISTPL_FUNCID_FIXED 0x04
236	#define CISTPL_FUNCID_VIDEO 0x05	236	#define CISTPL_FUNCID_VIDEO 0x05
237	#define CISTPL_FUNCID_NETWORK 0x06	237	#define CISTPL_FUNCID_NETWORK 0x06
238	#define CISTPL_FUNCID_AIMS 0x07	238	#define CISTPL_FUNCID_AIMS 0x07
239	#define CISTPL_FUNCID_SCSI 0x08	239	#define CISTPL_FUNCID_SCSI 0x08
240		240
241	/*	241	/*
242	* Fixed Disk FUNCE codes	242	* Fixed Disk FUNCE codes
243	*/	243	*/
244	#define CISTPL_IDE_INTERFACE 0x01	244	#define CISTPL_IDE_INTERFACE 0x01
245		245
246	#define CISTPL_FUNCE_IDE_IFACE 0x01	246	#define CISTPL_FUNCE_IDE_IFACE 0x01
247	#define CISTPL_FUNCE_IDE_MASTER 0x02	247	#define CISTPL_FUNCE_IDE_MASTER 0x02
248	#define CISTPL_FUNCE_IDE_SLAVE 0x03	248	#define CISTPL_FUNCE_IDE_SLAVE 0x03
249		249
250	/* First feature byte */	250	/* First feature byte */
251	#define CISTPL_IDE_SILICON 0x04	251	#define CISTPL_IDE_SILICON 0x04
252	#define CISTPL_IDE_UNIQUE 0x08	252	#define CISTPL_IDE_UNIQUE 0x08
253	#define CISTPL_IDE_DUAL 0x10	253	#define CISTPL_IDE_DUAL 0x10
254		254
255	/* Second feature byte */	255	/* Second feature byte */
256	#define CISTPL_IDE_HAS_SLEEP 0x01	256	#define CISTPL_IDE_HAS_SLEEP 0x01
257	#define CISTPL_IDE_HAS_STANDBY 0x02	257	#define CISTPL_IDE_HAS_STANDBY 0x02
258	#define CISTPL_IDE_HAS_IDLE 0x04	258	#define CISTPL_IDE_HAS_IDLE 0x04
259	#define CISTPL_IDE_LOW_POWER 0x08	259	#define CISTPL_IDE_LOW_POWER 0x08
260	#define CISTPL_IDE_REG_INHIBIT 0x10	260	#define CISTPL_IDE_REG_INHIBIT 0x10
261	#define CISTPL_IDE_HAS_INDEX 0x20	261	#define CISTPL_IDE_HAS_INDEX 0x20
262	#define CISTPL_IDE_IOIS16 0x40	262	#define CISTPL_IDE_IOIS16 0x40
263		263
264	#endif	264	#endif
265		265
266	#ifdef CONFIG_8xx	266	#ifdef CONFIG_8xx
267	extern u_int *pcmcia_pgcrx[];	267	extern u_int *pcmcia_pgcrx[];
268	#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])	268	#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
269	#endif	269	#endif
270		270
271	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)	271	#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
272	extern int check_ide_device(int slot);	272	extern int check_ide_device(int slot);
273	#endif	273	#endif
274		274
275	#endif /* _PCMCIA_H */	275	#endif /* _PCMCIA_H */
276		276

1	/*	1	/*
2	* (C) Copyright 2007	2	* (C) Copyright 2007
3	* Gary Jennejohn, DENX Software Engineering, garyj@denx.de.	3	* Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*/	6	*/
7	/* sil680.c - ide support functions for the Sil0680A controller */	7	/* sil680.c - ide support functions for the Sil0680A controller */
8		8
9	/*	9	/*
10	* The following parameters must be defined in the configuration file	10	* The following parameters must be defined in the configuration file
11	* of the target board:	11	* of the target board:
12	*	12	*
13	* #define CONFIG_IDE_SIL680	13	* #define CONFIG_IDE_SIL680
14	*	14	*
15	* #define CONFIG_PCI_PNP	15	* #define CONFIG_PCI_PNP
16	* NOTE it may also be necessary to define this if the default of 8 is	16	* NOTE it may also be necessary to define this if the default of 8 is
17	* incorrect for the target board (e.g. the sequoia board requires 0).	17	* incorrect for the target board (e.g. the sequoia board requires 0).
18	* #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0	18	* #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
19	*	19	*
20	* #define CONFIG_CMD_IDE	20	* #define CONFIG_IDE
21	* #undef CONFIG_IDE_8xx_DIRECT	21	* #undef CONFIG_IDE_8xx_DIRECT
22	* #undef CONFIG_IDE_LED	22	* #undef CONFIG_IDE_LED
23	* #undef CONFIG_IDE_RESET	23	* #undef CONFIG_IDE_RESET
24	* #define CONFIG_IDE_PREINIT	24	* #define CONFIG_IDE_PREINIT
25	* #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit	25	* #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit
26	* #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit	26	* #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit
27	* #define CONFIG_SYS_ATA_BASE_ADDR 0	27	* #define CONFIG_SYS_ATA_BASE_ADDR 0
28	* #define CONFIG_SYS_ATA_IDE0_OFFSET 0	28	* #define CONFIG_SYS_ATA_IDE0_OFFSET 0
29	* #define CONFIG_SYS_ATA_IDE1_OFFSET 0	29	* #define CONFIG_SYS_ATA_IDE1_OFFSET 0
30	* #define CONFIG_SYS_ATA_DATA_OFFSET 0	30	* #define CONFIG_SYS_ATA_DATA_OFFSET 0
31	* #define CONFIG_SYS_ATA_REG_OFFSET 0	31	* #define CONFIG_SYS_ATA_REG_OFFSET 0
32	* #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004	32	* #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004
33	*	33	*
34	* The mapping for PCI IO-space.	34	* The mapping for PCI IO-space.
35	* NOTE this is the value for the sequoia board. Modify to suit.	35	* NOTE this is the value for the sequoia board. Modify to suit.
36	* #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000	36	* #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000
37	*/	37	*/
38		38
39	#include <common.h>	39	#include <common.h>
40	#include <ata.h>	40	#include <ata.h>
41	#include <ide.h>	41	#include <ide.h>
42	#include <pci.h>	42	#include <pci.h>
43		43
44	extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];	44	extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
45		45
46	int ide_preinit (void)	46	int ide_preinit (void)
47	{	47	{
48	int status;	48	int status;
49	pci_dev_t devbusfn;	49	pci_dev_t devbusfn;
50	int l;	50	int l;
51		51
52	status = 1;	52	status = 1;
53	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {	53	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
54	ide_bus_offset[l] = -ATA_STATUS;	54	ide_bus_offset[l] = -ATA_STATUS;
55	}	55	}
56	devbusfn = pci_find_device (0x1095, 0x0680, 0);	56	devbusfn = pci_find_device (0x1095, 0x0680, 0);
57	if (devbusfn != -1) {	57	if (devbusfn != -1) {
58	status = 0;	58	status = 0;
59		59
60	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,	60	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
61	(u32 *) &ide_bus_offset[0]);	61	(u32 *) &ide_bus_offset[0]);
62	ide_bus_offset[0] &= 0xfffffff8;	62	ide_bus_offset[0] &= 0xfffffff8;
63	ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;	63	ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
64	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,	64	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
65	(u32 *) &ide_bus_offset[1]);	65	(u32 *) &ide_bus_offset[1]);
66	ide_bus_offset[1] &= 0xfffffff8;	66	ide_bus_offset[1] &= 0xfffffff8;
67	ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;	67	ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
68	/* init various things - taken from the Linux driver */	68	/* init various things - taken from the Linux driver */
69	/* set PIO mode */	69	/* set PIO mode */
70	pci_write_config_byte(devbusfn, 0x80, 0x00);	70	pci_write_config_byte(devbusfn, 0x80, 0x00);
71	pci_write_config_byte(devbusfn, 0x84, 0x00);	71	pci_write_config_byte(devbusfn, 0x84, 0x00);
72	/* IDE0 */	72	/* IDE0 */
73	pci_write_config_byte(devbusfn, 0xA1, 0x02);	73	pci_write_config_byte(devbusfn, 0xA1, 0x02);
74	pci_write_config_word(devbusfn, 0xA2, 0x328A);	74	pci_write_config_word(devbusfn, 0xA2, 0x328A);
75	pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);	75	pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
76	pci_write_config_dword(devbusfn, 0xA8, 0x43924392);	76	pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
77	pci_write_config_dword(devbusfn, 0xAC, 0x40094009);	77	pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
78	/* IDE1 */	78	/* IDE1 */
79	pci_write_config_byte(devbusfn, 0xB1, 0x02);	79	pci_write_config_byte(devbusfn, 0xB1, 0x02);
80	pci_write_config_word(devbusfn, 0xB2, 0x328A);	80	pci_write_config_word(devbusfn, 0xB2, 0x328A);
81	pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);	81	pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
82	pci_write_config_dword(devbusfn, 0xB8, 0x43924392);	82	pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
83	pci_write_config_dword(devbusfn, 0xBC, 0x40094009);	83	pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
84	}	84	}
85	return (status);	85	return (status);
86	}	86	}
87		87
88	void ide_set_reset (int flag) {	88	void ide_set_reset (int flag) {
89	return;	89	return;
90	}	90	}
91		91

1	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.	1	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
2	* Hayden Fraser (Hayden.Fraser@freescale.com)	2	* Hayden Fraser (Hayden.Fraser@freescale.com)
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#ifndef _M5253DEMO_H	7	#ifndef _M5253DEMO_H
8	#define _M5253DEMO_H	8	#define _M5253DEMO_H
9		9
10	#define CONFIG_M5253DEMO /* define board type */	10	#define CONFIG_M5253DEMO /* define board type */
11		11
12	#define CONFIG_MCFTMR	12	#define CONFIG_MCFTMR
13		13
14	#define CONFIG_MCFUART	14	#define CONFIG_MCFUART
15	#define CONFIG_SYS_UART_PORT (0)	15	#define CONFIG_SYS_UART_PORT (0)
16		16
17	#undef CONFIG_WATCHDOG /* disable watchdog */	17	#undef CONFIG_WATCHDOG /* disable watchdog */
18		18
19		19
20	/* Configuration for environment	20	/* Configuration for environment
21	* Environment is embedded in u-boot in the second sector of the flash	21	* Environment is embedded in u-boot in the second sector of the flash
22	*/	22	*/
23	#ifdef CONFIG_MONITOR_IS_IN_RAM	23	#ifdef CONFIG_MONITOR_IS_IN_RAM
24	# define CONFIG_ENV_OFFSET 0x4000	24	# define CONFIG_ENV_OFFSET 0x4000
25	# define CONFIG_ENV_SECT_SIZE 0x1000	25	# define CONFIG_ENV_SECT_SIZE 0x1000
26	# define CONFIG_ENV_IS_IN_FLASH 1	26	# define CONFIG_ENV_IS_IN_FLASH 1
27	#else	27	#else
28	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)	28	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
29	# define CONFIG_ENV_SECT_SIZE 0x1000	29	# define CONFIG_ENV_SECT_SIZE 0x1000
30	# define CONFIG_ENV_IS_IN_FLASH 1	30	# define CONFIG_ENV_IS_IN_FLASH 1
31	#endif	31	#endif
32		32
33	#define LDS_BOARD_TEXT \	33	#define LDS_BOARD_TEXT \
34	. = DEFINED(env_offset) ? env_offset : .; \	34	. = DEFINED(env_offset) ? env_offset : .; \
35	common/env_embedded.o (.text*);	35	common/env_embedded.o (.text*);
36		36
37	/*	37	/*
38	* Command line configuration.	38	* Command line configuration.
39	*/	39	*/
40		40
41	#ifdef CONFIG_CMD_IDE	41	#ifdef CONFIG_IDE
42	/* ATA */	42	/* ATA */
43	# define CONFIG_IDE_RESET 1	43	# define CONFIG_IDE_RESET 1
44	# define CONFIG_IDE_PREINIT 1	44	# define CONFIG_IDE_PREINIT 1
45	# define CONFIG_ATAPI	45	# define CONFIG_ATAPI
46	# undef CONFIG_LBA48	46	# undef CONFIG_LBA48
47		47
48	# define CONFIG_SYS_IDE_MAXBUS 1	48	# define CONFIG_SYS_IDE_MAXBUS 1
49	# define CONFIG_SYS_IDE_MAXDEVICE 2	49	# define CONFIG_SYS_IDE_MAXDEVICE 2
50		50
51	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)	51	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
52	# define CONFIG_SYS_ATA_IDE0_OFFSET 0	52	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
53		53
54	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */	54	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
55	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */	55	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
56	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */	56	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
57	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */	57	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
58	#endif	58	#endif
59		59
60	#define CONFIG_DRIVER_DM9000	60	#define CONFIG_DRIVER_DM9000
61	#ifdef CONFIG_DRIVER_DM9000	61	#ifdef CONFIG_DRIVER_DM9000
62	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)	62	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
63	# define DM9000_IO CONFIG_DM9000_BASE	63	# define DM9000_IO CONFIG_DM9000_BASE
64	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)	64	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
65	# undef CONFIG_DM9000_DEBUG	65	# undef CONFIG_DM9000_DEBUG
66	# define CONFIG_DM9000_BYTE_SWAPPED	66	# define CONFIG_DM9000_BYTE_SWAPPED
67		67
68	# define CONFIG_OVERWRITE_ETHADDR_ONCE	68	# define CONFIG_OVERWRITE_ETHADDR_ONCE
69		69
70	# define CONFIG_EXTRA_ENV_SETTINGS \	70	# define CONFIG_EXTRA_ENV_SETTINGS \
71	"netdev=eth0\0" \	71	"netdev=eth0\0" \
72	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \	72	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
73	"loadaddr=10000\0" \	73	"loadaddr=10000\0" \
74	"u-boot=u-boot.bin\0" \	74	"u-boot=u-boot.bin\0" \
75	"load=tftp ${loadaddr) ${u-boot}\0" \	75	"load=tftp ${loadaddr) ${u-boot}\0" \
76	"upd=run load; run prog\0" \	76	"upd=run load; run prog\0" \
77	"prog=prot off 0xff800000 0xff82ffff;" \	77	"prog=prot off 0xff800000 0xff82ffff;" \
78	"era 0xff800000 0xff82ffff;" \	78	"era 0xff800000 0xff82ffff;" \
79	"cp.b ${loadaddr} 0xff800000 ${filesize};" \	79	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
80	"save\0" \	80	"save\0" \
81	""	81	""
82	#endif	82	#endif
83		83
84	#define CONFIG_HOSTNAME M5253DEMO	84	#define CONFIG_HOSTNAME M5253DEMO
85		85
86	/* I2C */	86	/* I2C */
87	#define CONFIG_SYS_I2C	87	#define CONFIG_SYS_I2C
88	#define CONFIG_SYS_I2C_FSL	88	#define CONFIG_SYS_I2C_FSL
89	#define CONFIG_SYS_FSL_I2C_SPEED 80000	89	#define CONFIG_SYS_FSL_I2C_SPEED 80000
90	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F	90	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
91	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280	91	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
92	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR	92	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
93	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))	93	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
94	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)	94	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
95	#define CONFIG_SYS_I2C_PINMUX_SET (0)	95	#define CONFIG_SYS_I2C_PINMUX_SET (0)
96		96
97	#define CONFIG_SYS_LONGHELP /* undef to save memory */	97	#define CONFIG_SYS_LONGHELP /* undef to save memory */
98		98
99	#if defined(CONFIG_CMD_KGDB)	99	#if defined(CONFIG_CMD_KGDB)
100	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */	100	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
101	#else	101	#else
102	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	102	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
103	#endif	103	#endif
104	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */	104	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
105	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	105	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
106	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	106	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
107		107
108	#define CONFIG_SYS_LOAD_ADDR 0x00100000	108	#define CONFIG_SYS_LOAD_ADDR 0x00100000
109		109
110	#define CONFIG_SYS_MEMTEST_START 0x400	110	#define CONFIG_SYS_MEMTEST_START 0x400
111	#define CONFIG_SYS_MEMTEST_END 0x380000	111	#define CONFIG_SYS_MEMTEST_END 0x380000
112		112
113	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */	113	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
114	#define CONFIG_SYS_FAST_CLK	114	#define CONFIG_SYS_FAST_CLK
115	#ifdef CONFIG_SYS_FAST_CLK	115	#ifdef CONFIG_SYS_FAST_CLK
116	# define CONFIG_SYS_PLLCR 0x1243E054	116	# define CONFIG_SYS_PLLCR 0x1243E054
117	# define CONFIG_SYS_CLK 140000000	117	# define CONFIG_SYS_CLK 140000000
118	#else	118	#else
119	# define CONFIG_SYS_PLLCR 0x135a4140	119	# define CONFIG_SYS_PLLCR 0x135a4140
120	# define CONFIG_SYS_CLK 70000000	120	# define CONFIG_SYS_CLK 70000000
121	#endif	121	#endif
122		122
123	/*	123	/*
124	* Low Level Configuration Settings	124	* Low Level Configuration Settings
125	* (address mappings, register initial values, etc.)	125	* (address mappings, register initial values, etc.)
126	* You should know what you are doing if you make changes here.	126	* You should know what you are doing if you make changes here.
127	*/	127	*/
128		128
129	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */	129	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
130	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */	130	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
131		131
132	/*	132	/*
133	* Definitions for initial stack pointer and data area (in DPRAM)	133	* Definitions for initial stack pointer and data area (in DPRAM)
134	*/	134	*/
135	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000	135	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
136	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */	136	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
137	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)	137	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
138	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET	138	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
139		139
140	/*	140	/*
141	* Start addresses for the final memory configuration	141	* Start addresses for the final memory configuration
142	* (Set up by the startup code)	142	* (Set up by the startup code)
143	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0	143	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
144	*/	144	*/
145	#define CONFIG_SYS_SDRAM_BASE 0x00000000	145	#define CONFIG_SYS_SDRAM_BASE 0x00000000
146	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */	146	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
147		147
148	#ifdef CONFIG_MONITOR_IS_IN_RAM	148	#ifdef CONFIG_MONITOR_IS_IN_RAM
149	# define CONFIG_SYS_MONITOR_BASE 0x20000	149	# define CONFIG_SYS_MONITOR_BASE 0x20000
150	#else	150	#else
151	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)	151	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
152	#endif	152	#endif
153		153
154	#define CONFIG_SYS_MONITOR_LEN 0x40000	154	#define CONFIG_SYS_MONITOR_LEN 0x40000
155	#define CONFIG_SYS_MALLOC_LEN (256 << 10)	155	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
156	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)	156	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
157		157
158	/*	158	/*
159	* For booting Linux, the board info and command line data	159	* For booting Linux, the board info and command line data
160	* have to be in the first 8 MB of memory, since this is	160	* have to be in the first 8 MB of memory, since this is
161	* the maximum mapped by the Linux kernel during initialization ??	161	* the maximum mapped by the Linux kernel during initialization ??
162	*/	162	*/
163	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))	163	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
164	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)	164	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
165		165
166	/* FLASH organization */	166	/* FLASH organization */
167	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)	167	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
168	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */	168	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
169	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */	169	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
170	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000	170	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
171		171
172	#define FLASH_SST6401B 0x200	172	#define FLASH_SST6401B 0x200
173	#define SST_ID_xF6401B 0x236D236D	173	#define SST_ID_xF6401B 0x236D236D
174		174
175	#undef CONFIG_SYS_FLASH_CFI	175	#undef CONFIG_SYS_FLASH_CFI
176	#ifdef CONFIG_SYS_FLASH_CFI	176	#ifdef CONFIG_SYS_FLASH_CFI
177	/*	177	/*
178	* Unable to use CFI driver, due to incompatible sector erase command by SST.	178	* Unable to use CFI driver, due to incompatible sector erase command by SST.
179	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.	179	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
180	* 0x30 is block erase in SST	180	* 0x30 is block erase in SST
181	*/	181	*/
182	# define CONFIG_FLASH_CFI_DRIVER 1	182	# define CONFIG_FLASH_CFI_DRIVER 1
183	# define CONFIG_SYS_FLASH_SIZE 0x800000	183	# define CONFIG_SYS_FLASH_SIZE 0x800000
184	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT	184	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
185	# define CONFIG_FLASH_CFI_LEGACY	185	# define CONFIG_FLASH_CFI_LEGACY
186	#else	186	#else
187	# define CONFIG_SYS_SST_SECT 2048	187	# define CONFIG_SYS_SST_SECT 2048
188	# define CONFIG_SYS_SST_SECTSZ 0x1000	188	# define CONFIG_SYS_SST_SECTSZ 0x1000
189	# define CONFIG_SYS_FLASH_WRITE_TOUT 500	189	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
190	#endif	190	#endif
191		191
192	/* Cache Configuration */	192	/* Cache Configuration */
193	#define CONFIG_SYS_CACHELINE_SIZE 16	193	#define CONFIG_SYS_CACHELINE_SIZE 16
194		194
195	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \	195	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
196	CONFIG_SYS_INIT_RAM_SIZE - 8)	196	CONFIG_SYS_INIT_RAM_SIZE - 8)
197	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \	197	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
198	CONFIG_SYS_INIT_RAM_SIZE - 4)	198	CONFIG_SYS_INIT_RAM_SIZE - 4)
199	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)	199	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
200	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \	200	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
201	CF_ADDRMASK(8) \| \	201	CF_ADDRMASK(8) \| \
202	CF_ACR_EN \| CF_ACR_SM_ALL)	202	CF_ACR_EN \| CF_ACR_SM_ALL)
203	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \	203	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
204	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \	204	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
205	CF_ACR_EN \| CF_ACR_SM_ALL)	205	CF_ACR_EN \| CF_ACR_SM_ALL)
206	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \	206	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
207	CF_CACR_DBWE)	207	CF_CACR_DBWE)
208		208
209	/* Port configuration */	209	/* Port configuration */
210	#define CONFIG_SYS_FECI2C 0xF0	210	#define CONFIG_SYS_FECI2C 0xF0
211		211
212	#define CONFIG_SYS_CS0_BASE 0xFF800000	212	#define CONFIG_SYS_CS0_BASE 0xFF800000
213	#define CONFIG_SYS_CS0_MASK 0x007F0021	213	#define CONFIG_SYS_CS0_MASK 0x007F0021
214	#define CONFIG_SYS_CS0_CTRL 0x00001D80	214	#define CONFIG_SYS_CS0_CTRL 0x00001D80
215		215
216	#define CONFIG_SYS_CS1_BASE 0xE0000000	216	#define CONFIG_SYS_CS1_BASE 0xE0000000
217	#define CONFIG_SYS_CS1_MASK 0x00000001	217	#define CONFIG_SYS_CS1_MASK 0x00000001
218	#define CONFIG_SYS_CS1_CTRL 0x00003DD8	218	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
219		219
220	/*-----------------------------------------------------------------------	220	/*-----------------------------------------------------------------------
221	* Port configuration	221	* Port configuration
222	*/	222	*/
223	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */	223	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
224	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */	224	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
225	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */	225	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
226	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */	226	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
227	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */	227	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
228	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */	228	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
229	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */	229	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
230		230
231	#endif /* _M5253DEMO_H */	231	#endif /* _M5253DEMO_H */
232		232

1	/*	1	/*
2	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>	2	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
3	*	3	*
4	* Based on original Kirkwood support which is	4	* Based on original Kirkwood support which is
5	* (C) Copyright 2009	5	* (C) Copyright 2009
6	* Marvell Semiconductor <www.marvell.com>	6	* Marvell Semiconductor <www.marvell.com>
7	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>	7	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8	*	8	*
9	* SPDX-License-Identifier: GPL-2.0+	9	* SPDX-License-Identifier: GPL-2.0+
10	*/	10	*/
11		11
12	#ifndef _CONFIG_EDMINIV2_H	12	#ifndef _CONFIG_EDMINIV2_H
13	#define _CONFIG_EDMINIV2_H	13	#define _CONFIG_EDMINIV2_H
14		14
15	/*	15	/*
16	* SPL	16	* SPL
17	*/	17	*/
18		18
19	#define CONFIG_SPL_FRAMEWORK	19	#define CONFIG_SPL_FRAMEWORK
20	#define CONFIG_SPL_TEXT_BASE 0xffff0000	20	#define CONFIG_SPL_TEXT_BASE 0xffff0000
21	#define CONFIG_SPL_MAX_SIZE 0x0000fff0	21	#define CONFIG_SPL_MAX_SIZE 0x0000fff0
22	#define CONFIG_SPL_STACK 0x00020000	22	#define CONFIG_SPL_STACK 0x00020000
23	#define CONFIG_SPL_BSS_START_ADDR 0x00020000	23	#define CONFIG_SPL_BSS_START_ADDR 0x00020000
24	#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff	24	#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
25	#define CONFIG_SYS_SPL_MALLOC_START 0x00040000	25	#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
26	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff	26	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
27	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"	27	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
28	#define CONFIG_SYS_UBOOT_BASE 0xfff90000	28	#define CONFIG_SYS_UBOOT_BASE 0xfff90000
29	#define CONFIG_SYS_UBOOT_START 0x00800000	29	#define CONFIG_SYS_UBOOT_START 0x00800000
30	#define CONFIG_SYS_TEXT_BASE 0x00800000	30	#define CONFIG_SYS_TEXT_BASE 0x00800000
31		31
32	/*	32	/*
33	* High Level Configuration Options (easy to change)	33	* High Level Configuration Options (easy to change)
34	*/	34	*/
35		35
36	#define CONFIG_MARVELL 1	36	#define CONFIG_MARVELL 1
37	#define CONFIG_FEROCEON 1 /* CPU Core subversion */	37	#define CONFIG_FEROCEON 1 /* CPU Core subversion */
38	#define CONFIG_88F5182 1 /* SOC Name */	38	#define CONFIG_88F5182 1 /* SOC Name */
39	#define CONFIG_MACH_EDMINIV2 1 /* Machine type */	39	#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
40		40
41	#include <asm/arch/orion5x.h>	41	#include <asm/arch/orion5x.h>
42	/*	42	/*
43	* CLKs configurations	43	* CLKs configurations
44	*/	44	*/
45		45
46	/*	46	/*
47	* Board-specific values for Orion5x MPP low level init:	47	* Board-specific values for Orion5x MPP low level init:
48	* - MPPs 12 to 15 are SATA LEDs (mode 5)	48	* - MPPs 12 to 15 are SATA LEDs (mode 5)
49	* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for	49	* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
50	* MPP16 to MPP19, mode 0 for others	50	* MPP16 to MPP19, mode 0 for others
51	*/	51	*/
52		52
53	#define ORION5X_MPP0_7 0x00000003	53	#define ORION5X_MPP0_7 0x00000003
54	#define ORION5X_MPP8_15 0x55550000	54	#define ORION5X_MPP8_15 0x55550000
55	#define ORION5X_MPP16_23 0x00005555	55	#define ORION5X_MPP16_23 0x00005555
56		56
57	/*	57	/*
58	* Board-specific values for Orion5x GPIO low level init:	58	* Board-specific values for Orion5x GPIO low level init:
59	* - GPIO3 is input (RTC interrupt)	59	* - GPIO3 is input (RTC interrupt)
60	* - GPIO16 is Power LED control (0 = on, 1 = off)	60	* - GPIO16 is Power LED control (0 = on, 1 = off)
61	* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)	61	* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
62	* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)	62	* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
63	* - GPIO19 is SATA disk power toggle (toggles on 0-to-1)	63	* - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
64	* - GPIO22 is SATA disk power status ()	64	* - GPIO22 is SATA disk power status ()
65	* - GPIO23 is supply status for SATA disk ()	65	* - GPIO23 is supply status for SATA disk ()
66	* - GPIO24 is supply control for board (write 1 to power off)	66	* - GPIO24 is supply control for board (write 1 to power off)
67	* Last GPIO is 25, further bits are supposed to be 0.	67	* Last GPIO is 25, further bits are supposed to be 0.
68	* Enable mask has ones for INPUT, 0 for OUTPUT.	68	* Enable mask has ones for INPUT, 0 for OUTPUT.
69	* Default is LED ON, board ON :)	69	* Default is LED ON, board ON :)
70	*/	70	*/
71		71
72	#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca	72	#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
73	#define ORION5X_GPIO_OUT_VALUE 0x00000000	73	#define ORION5X_GPIO_OUT_VALUE 0x00000000
74	#define ORION5X_GPIO_IN_POLARITY 0x000000d0	74	#define ORION5X_GPIO_IN_POLARITY 0x000000d0
75		75
76	/*	76	/*
77	* NS16550 Configuration	77	* NS16550 Configuration
78	*/	78	*/
79		79
80	#define CONFIG_SYS_NS16550_SERIAL	80	#define CONFIG_SYS_NS16550_SERIAL
81	#define CONFIG_SYS_NS16550_REG_SIZE (-4)	81	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
82	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK	82	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
83	#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE	83	#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
84		84
85	/*	85	/*
86	* Serial Port configuration	86	* Serial Port configuration
87	* The following definitions let you select what serial you want to use	87	* The following definitions let you select what serial you want to use
88	* for your console driver.	88	* for your console driver.
89	*/	89	*/
90		90
91	#define CONFIG_CONS_INDEX 1 /Console on UART0 /	91	#define CONFIG_CONS_INDEX 1 /Console on UART0 /
92	#define CONFIG_SYS_BAUDRATE_TABLE \	92	#define CONFIG_SYS_BAUDRATE_TABLE \
93	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }	93	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
94		94
95	/*	95	/*
96	* FLASH configuration	96	* FLASH configuration
97	*/	97	*/
98		98
99	#define CONFIG_SYS_FLASH_CFI	99	#define CONFIG_SYS_FLASH_CFI
100	#define CONFIG_FLASH_CFI_DRIVER	100	#define CONFIG_FLASH_CFI_DRIVER
101	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */	101	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
102	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */	102	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
103	#define CONFIG_SYS_FLASH_BASE 0xfff80000	103	#define CONFIG_SYS_FLASH_BASE 0xfff80000
104		104
105	/* auto boot */	105	/* auto boot */
106		106
107	/*	107	/*
108	* For booting Linux, the board info and command line data	108	* For booting Linux, the board info and command line data
109	* have to be in the first 8 MB of memory, since this is	109	* have to be in the first 8 MB of memory, since this is
110	* the maximum mapped by the Linux kernel during initialization.	110	* the maximum mapped by the Linux kernel during initialization.
111	*/	111	*/
112	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */	112	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
113	#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */	113	#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
114	#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */	114	#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
115		115
116	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */	116	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
117	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \	117	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
118	+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */	118	+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
119	/*	119	/*
120	* Commands configuration	120	* Commands configuration
121	*/	121	*/
122		122
123	/*	123	/*
124	* Network	124	* Network
125	*/	125	*/
126		126
127	#ifdef CONFIG_CMD_NET	127	#ifdef CONFIG_CMD_NET
128	#define CONFIG_MVGBE /* Enable Marvell GbE Driver */	128	#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
129	#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */	129	#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
130	#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */	130	#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
131	#define CONFIG_PHY_BASE_ADR 0x8	131	#define CONFIG_PHY_BASE_ADR 0x8
132	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */	132	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
133	#define CONFIG_NETCONSOLE /* include NetConsole support */	133	#define CONFIG_NETCONSOLE /* include NetConsole support */
134	#define CONFIG_MII /* expose smi ove miiphy interface */	134	#define CONFIG_MII /* expose smi ove miiphy interface */
135	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */	135	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
136	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */	136	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
137	#endif	137	#endif
138		138
139	/*	139	/*
140	* IDE	140	* IDE
141	*/	141	*/
142	#ifdef CONFIG_CMD_IDE	142	#ifdef CONFIG_IDE
143	#define __io	143	#define __io
144	#define CONFIG_IDE_PREINIT	144	#define CONFIG_IDE_PREINIT
145	/* ED Mini V has an IDE-compatible SATA connector for port 1 */	145	/* ED Mini V has an IDE-compatible SATA connector for port 1 */
146	#define CONFIG_MVSATA_IDE	146	#define CONFIG_MVSATA_IDE
147	#define CONFIG_MVSATA_IDE_USE_PORT1	147	#define CONFIG_MVSATA_IDE_USE_PORT1
148	/* Needs byte-swapping for ATA data register */	148	/* Needs byte-swapping for ATA data register */
149	#define CONFIG_IDE_SWAP_IO	149	#define CONFIG_IDE_SWAP_IO
150	/* Data, registers and alternate blocks are at the same offset */	150	/* Data, registers and alternate blocks are at the same offset */
151	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)	151	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
152	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)	152	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
153	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)	153	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
154	/* Each 8-bit ATA register is aligned to a 4-bytes address */	154	/* Each 8-bit ATA register is aligned to a 4-bytes address */
155	#define CONFIG_SYS_ATA_STRIDE 4	155	#define CONFIG_SYS_ATA_STRIDE 4
156	/* Controller supports 48-bits LBA addressing */	156	/* Controller supports 48-bits LBA addressing */
157	#define CONFIG_LBA48	157	#define CONFIG_LBA48
158	/* A single bus, a single device */	158	/* A single bus, a single device */
159	#define CONFIG_SYS_IDE_MAXBUS 1	159	#define CONFIG_SYS_IDE_MAXBUS 1
160	#define CONFIG_SYS_IDE_MAXDEVICE 1	160	#define CONFIG_SYS_IDE_MAXDEVICE 1
161	/* ATA registers base is at SATA controller base */	161	/* ATA registers base is at SATA controller base */
162	#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE	162	#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
163	/* ATA bus 0 is orion5x port 1 on ED Mini V2 */	163	/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
164	#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET	164	#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
165	/* end of IDE defines */	165	/* end of IDE defines */
166	#endif /* CMD_IDE */	166	#endif /* CMD_IDE */
167		167
168	/*	168	/*
169	* Common USB/EHCI configuration	169	* Common USB/EHCI configuration
170	*/	170	*/
171	#ifdef CONFIG_CMD_USB	171	#ifdef CONFIG_CMD_USB
172	#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE	172	#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
173	#define CONFIG_SUPPORT_VFAT	173	#define CONFIG_SUPPORT_VFAT
174	#endif /* CONFIG_CMD_USB */	174	#endif /* CONFIG_CMD_USB */
175		175
176	/*	176	/*
177	* I2C related stuff	177	* I2C related stuff
178	*/	178	*/
179	#ifdef CONFIG_CMD_I2C	179	#ifdef CONFIG_CMD_I2C
180	#define CONFIG_SYS_I2C	180	#define CONFIG_SYS_I2C
181	#define CONFIG_SYS_I2C_MVTWSI	181	#define CONFIG_SYS_I2C_MVTWSI
182	#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE	182	#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
183	#define CONFIG_SYS_I2C_SLAVE 0x0	183	#define CONFIG_SYS_I2C_SLAVE 0x0
184	#define CONFIG_SYS_I2C_SPEED 100000	184	#define CONFIG_SYS_I2C_SPEED 100000
185	#endif	185	#endif
186		186
187	/*	187	/*
188	* Environment variables configurations	188	* Environment variables configurations
189	*/	189	*/
190	#define CONFIG_ENV_IS_IN_FLASH 1	190	#define CONFIG_ENV_IS_IN_FLASH 1
191	#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */	191	#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
192	#define CONFIG_ENV_SIZE 0x2000	192	#define CONFIG_ENV_SIZE 0x2000
193	#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */	193	#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
194		194
195	/*	195	/*
196	* Size of malloc() pool	196	* Size of malloc() pool
197	*/	197	*/
198	#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */	198	#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
199		199
200	/*	200	/*
201	* Other required minimal configurations	201	* Other required minimal configurations
202	*/	202	*/
203	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */	203	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
204	#define CONFIG_NR_DRAM_BANKS 1	204	#define CONFIG_NR_DRAM_BANKS 1
205		205
206	#define CONFIG_SYS_LOAD_ADDR 0x00800000	206	#define CONFIG_SYS_LOAD_ADDR 0x00800000
207	#define CONFIG_SYS_MEMTEST_START 0x00400000	207	#define CONFIG_SYS_MEMTEST_START 0x00400000
208	#define CONFIG_SYS_MEMTEST_END 0x007fffff	208	#define CONFIG_SYS_MEMTEST_END 0x007fffff
209	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	209	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
210	#define CONFIG_SYS_MAXARGS 16	210	#define CONFIG_SYS_MAXARGS 16
211		211
212	/* Enable command line editing */	212	/* Enable command line editing */
213	#define CONFIG_CMDLINE_EDITING	213	#define CONFIG_CMDLINE_EDITING
214		214
215	/* provide extensive help */	215	/* provide extensive help */
216	#define CONFIG_SYS_LONGHELP	216	#define CONFIG_SYS_LONGHELP
217		217
218	/* additions for new relocation code, must be added to all boards */	218	/* additions for new relocation code, must be added to all boards */
219	#define CONFIG_SYS_SDRAM_BASE 0	219	#define CONFIG_SYS_SDRAM_BASE 0
220	#define CONFIG_SYS_INIT_SP_ADDR \	220	#define CONFIG_SYS_INIT_SP_ADDR \
221	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)	221	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
222		222
223	#endif /* _CONFIG_EDMINIV2_H */	223	#endif /* _CONFIG_EDMINIV2_H */
224		224

1	/*	1	/*
2	* Configuation settings for the Renesas R7780MP board	2	* Configuation settings for the Renesas R7780MP board
3	*	3	*
4	* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>	4	* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5	* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>	5	* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#ifndef __R7780RP_H	10	#ifndef __R7780RP_H
11	#define __R7780RP_H	11	#define __R7780RP_H
12		12
13	#define CONFIG_CPU_SH7780 1	13	#define CONFIG_CPU_SH7780 1
14	#define CONFIG_R7780MP 1	14	#define CONFIG_R7780MP 1
15	#define CONFIG_SYS_R7780MP_OLD_FLASH 1	15	#define CONFIG_SYS_R7780MP_OLD_FLASH 1
16	#define __LITTLE_ENDIAN__ 1	16	#define __LITTLE_ENDIAN__ 1
17		17
18	#define CONFIG_DISPLAY_BOARDINFO	18	#define CONFIG_DISPLAY_BOARDINFO
19		19
20	/*	20	/*
21	* Command line configuration.	21	* Command line configuration.
22	*/	22	*/
23	#define CONFIG_CMD_SDRAM	23	#define CONFIG_CMD_SDRAM
24	#define CONFIG_CMD_PCI	24	#define CONFIG_CMD_PCI
25		25
26	#define CONFIG_SCIF_CONSOLE 1	26	#define CONFIG_SCIF_CONSOLE 1
27	#define CONFIG_CONS_SCIF0 1	27	#define CONFIG_CONS_SCIF0 1
28		28
29	#define CONFIG_BOOTARGS "console=ttySC0,115200"	29	#define CONFIG_BOOTARGS "console=ttySC0,115200"
30	#define CONFIG_ENV_OVERWRITE 1	30	#define CONFIG_ENV_OVERWRITE 1
31		31
32	#define CONFIG_SYS_TEXT_BASE 0x0FFC0000	32	#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
33	#define CONFIG_SYS_SDRAM_BASE (0x08000000)	33	#define CONFIG_SYS_SDRAM_BASE (0x08000000)
34	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)	34	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
35		35
36	#define CONFIG_SYS_LONGHELP	36	#define CONFIG_SYS_LONGHELP
37	#define CONFIG_SYS_CBSIZE 256	37	#define CONFIG_SYS_CBSIZE 256
38	#define CONFIG_SYS_PBSIZE 256	38	#define CONFIG_SYS_PBSIZE 256
39	#define CONFIG_SYS_MAXARGS 16	39	#define CONFIG_SYS_MAXARGS 16
40	#define CONFIG_SYS_BARGSIZE 512	40	#define CONFIG_SYS_BARGSIZE 512
41		41
42	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)	42	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
43	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)	43	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
44		44
45	/* Flash board support */	45	/* Flash board support */
46	#define CONFIG_SYS_FLASH_BASE (0xA0000000)	46	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
47	#ifdef CONFIG_SYS_R7780MP_OLD_FLASH	47	#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
48	/* NOR Flash (S29PL127J60TFI130) */	48	/* NOR Flash (S29PL127J60TFI130) */
49	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT	49	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
50	# define CONFIG_SYS_MAX_FLASH_BANKS (2)	50	# define CONFIG_SYS_MAX_FLASH_BANKS (2)
51	# define CONFIG_SYS_MAX_FLASH_SECT 270	51	# define CONFIG_SYS_MAX_FLASH_SECT 270
52	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\	52	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
53	CONFIG_SYS_FLASH_BASE + 0x100000,\	53	CONFIG_SYS_FLASH_BASE + 0x100000,\
54	CONFIG_SYS_FLASH_BASE + 0x400000,\	54	CONFIG_SYS_FLASH_BASE + 0x400000,\
55	CONFIG_SYS_FLASH_BASE + 0x700000, }	55	CONFIG_SYS_FLASH_BASE + 0x700000, }
56	#else /* CONFIG_SYS_R7780MP_OLD_FLASH */	56	#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
57	/* NOR Flash (Spantion S29GL256P) */	57	/* NOR Flash (Spantion S29GL256P) */
58	# define CONFIG_SYS_MAX_FLASH_BANKS (1)	58	# define CONFIG_SYS_MAX_FLASH_BANKS (1)
59	# define CONFIG_SYS_MAX_FLASH_SECT 256	59	# define CONFIG_SYS_MAX_FLASH_SECT 256
60	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }	60	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
61	#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */	61	#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
62		62
63	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)	63	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
64	/* Address of u-boot image in Flash */	64	/* Address of u-boot image in Flash */
65	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)	65	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
66	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)	66	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
67	/* Size of DRAM reserved for malloc() use */	67	/* Size of DRAM reserved for malloc() use */
68	#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)	68	#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
69		69
70	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)	70	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
71	#define CONFIG_SYS_RX_ETH_BUFFER (8)	71	#define CONFIG_SYS_RX_ETH_BUFFER (8)
72		72
73	#define CONFIG_SYS_FLASH_CFI	73	#define CONFIG_SYS_FLASH_CFI
74	#define CONFIG_FLASH_CFI_DRIVER	74	#define CONFIG_FLASH_CFI_DRIVER
75	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE	75	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
76	#undef CONFIG_SYS_FLASH_QUIET_TEST	76	#undef CONFIG_SYS_FLASH_QUIET_TEST
77	/* print 'E' for empty sector on flinfo */	77	/* print 'E' for empty sector on flinfo */
78	#define CONFIG_SYS_FLASH_EMPTY_INFO	78	#define CONFIG_SYS_FLASH_EMPTY_INFO
79		79
80	#define CONFIG_ENV_IS_IN_FLASH	80	#define CONFIG_ENV_IS_IN_FLASH
81	#define CONFIG_ENV_SECT_SIZE (256 * 1024)	81	#define CONFIG_ENV_SECT_SIZE (256 * 1024)
82	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)	82	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
83	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)	83	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
84	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	84	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
85	#define CONFIG_SYS_FLASH_WRITE_TOUT 500	85	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
86		86
87	/* Board Clock */	87	/* Board Clock */
88	#define CONFIG_SYS_CLK_FREQ 33333333	88	#define CONFIG_SYS_CLK_FREQ 33333333
89	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ	89	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
90	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ	90	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
91	#define CONFIG_SYS_TMU_CLK_DIV 4	91	#define CONFIG_SYS_TMU_CLK_DIV 4
92		92
93	/* PCI Controller */	93	/* PCI Controller */
94	#if defined(CONFIG_CMD_PCI)	94	#if defined(CONFIG_CMD_PCI)
95	#define CONFIG_SH4_PCI	95	#define CONFIG_SH4_PCI
96	#define CONFIG_SH7780_PCI	96	#define CONFIG_SH7780_PCI
97	#define CONFIG_SH7780_PCI_LSR 0x07f00001	97	#define CONFIG_SH7780_PCI_LSR 0x07f00001
98	#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE	98	#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
99	#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE	99	#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
100	#define CONFIG_PCI_SCAN_SHOW 1	100	#define CONFIG_PCI_SCAN_SHOW 1
101	#define __mem_pci	101	#define __mem_pci
102		102
103	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */	103	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
104	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS	104	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
105	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */	105	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
106		106
107	#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */	107	#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
108	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS	108	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
109	#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */	109	#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
110	#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE	110	#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
111	#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE	111	#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
112	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE	112	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
113	#endif /* CONFIG_CMD_PCI */	113	#endif /* CONFIG_CMD_PCI */
114		114
115	#if defined(CONFIG_CMD_NET)	115	#if defined(CONFIG_CMD_NET)
116	/* AX88796L Support(NE2000 base chip) */	116	/* AX88796L Support(NE2000 base chip) */
117	#define CONFIG_DRIVER_AX88796L	117	#define CONFIG_DRIVER_AX88796L
118	#define CONFIG_DRIVER_NE2000_BASE 0xA4100000	118	#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
119	#endif	119	#endif
120		120
121	/* Compact flash Support */	121	/* Compact flash Support */
122	#if defined(CONFIG_CMD_IDE)	122	#if defined(CONFIG_IDE)
123	#define CONFIG_IDE_RESET 1	123	#define CONFIG_IDE_RESET 1
124	#define CONFIG_SYS_PIO_MODE 1	124	#define CONFIG_SYS_PIO_MODE 1
125	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */	125	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
126	#define CONFIG_SYS_IDE_MAXDEVICE 1	126	#define CONFIG_SYS_IDE_MAXDEVICE 1
127	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000	127	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
128	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */	128	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
129	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */	129	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
130	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */	130	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
131	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */	131	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
132	#define CONFIG_IDE_SWAP_IO	132	#define CONFIG_IDE_SWAP_IO
133	#endif /* CONFIG_CMD_IDE */	133	#endif /* CONFIG_IDE */
134		134
135	#endif /* __R7780RP_H */	135	#endif /* __R7780RP_H */
136		136