/*
 * Device Tree Source for K2G EVM
 *
 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
/dts-v1/;

#include "k2g.dtsi"

/ {
	compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
	model = "Texas Instruments K2G General Purpose EVM";

	memory {
		device_type = "memory";
		reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_cma_pool: dsp_common_cma_pool {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
		};

		dsp_common_mpm_area: dsp_reserved_mpm_area {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x20000000 0x00000000 0x20000000>;
			no-map;
			status = "okay";
		};
	};

	mmc0_reg: fixedregulator-mmc0 {
		compatible = "regulator-fixed";
		regulator-name = "mmc0_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	mmc1_reg: fixedregulator-mmc1 {
		compatible = "regulator-fixed";
		regulator-name = "mmc1_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	soc {
		mpm_mem: dspmem {
			compatible = "ti,keystone-dsp-mem";
			reg = <0x0c000000 0x00100000>,
			      <0xa0000000 0x20000000>;
		};
	};
};

&k2g_pinctrl {
	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
		>;
	};

	mmc0_pins: pinmux_mmc0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat3.mmc0_dat3 */
			K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat2.mmc0_dat2 */
			K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat1.mmc0_dat1 */
			K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat0.mmc0_dat0 */
			K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_clk.mmc0_clk */
			K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_cmd.mmc0_cmd */
			K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_sdcd.mmc0_sdcd */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat7.mmc1_dat7 */
			K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat6.mmc1_dat6 */
			K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat5.mmc1_dat5 */
			K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat4.mmc1_dat4 */
			K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
			K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
		>;
	};

	spi1_pins: pinmux_spi1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_scs0.spi1_scs0 */
			K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_clk.spi1_clk */
			K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_miso.spi1_miso */
			K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_mosi.spi1_mosi */
		>;
	};

	dcan0_pins: pinmux_dcan0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE0) /* dcan0tx.dcan0tx */
			K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE0) /* dcan0rx.dcan0rx */
		>;
	};

	dcan1_pins: pinmux_dcan1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE1) /* qspicsn2.dcan1tx */
			K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE1) /* qspicsn3.dcan1rx */
		>;
	};

	nand_pins: pinmux_nand_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1000) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
			K2G_CORE_IOPAD(0x1004) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
			K2G_CORE_IOPAD(0x1008) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
			K2G_CORE_IOPAD(0x100c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
			K2G_CORE_IOPAD(0x1010) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
			K2G_CORE_IOPAD(0x1014) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
			K2G_CORE_IOPAD(0x1018) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
			K2G_CORE_IOPAD(0x101c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
			K2G_CORE_IOPAD(0x1020) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad8.gpmc_ad8 */
			K2G_CORE_IOPAD(0x1024) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad9.gpmc_ad9 */
			K2G_CORE_IOPAD(0x1028) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad10.gpmc_ad10 */
			K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad11.gpmc_ad11 */
			K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad12.gpmc_ad12 */
			K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad13.gpmc_ad13 */
			K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad14.gpmc_ad14 */
			K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_ad15.gpmc_ad15 */
			K2G_CORE_IOPAD(0x1044) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_advnale.gpmc_advnale */
			K2G_CORE_IOPAD(0x1048) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_oenren.gpmc_oenren */
			K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_wen.gpmc_wen */
			K2G_CORE_IOPAD(0x1050) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_beoncle.gpmc_beoncle */
			K2G_CORE_IOPAD(0x1058) (BUFFER_CLASS_B | PIN_PULLUP   | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
			K2G_CORE_IOPAD(0x1060) (BUFFER_CLASS_B | PIN_PULLUP   | MUX_MODE0)	/* gpmc_wpn.gpmc_wpn */
			K2G_CORE_IOPAD(0x1068) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* gpmc_csn0.gpmc_csn0 */
		>;
	};
};

&elm {
	status = "okay";
};

&gpmc {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_pins>;
	status = "okay";
	ranges = <0 0 0x30000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;			/* CS0, I/O window 4 bytes */
		interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
		ti,nand-ecc-opt = "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <40>;
		gpmc,cs-wr-off-ns = <40>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <25>;
		gpmc,adv-wr-off-ns = <25>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <20>;
		gpmc,oe-on-ns = <3>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <30>;
		gpmc,rd-cycle-ns = <40>;
		gpmc,wr-cycle-ns = <40>;
		gpmc,wait-pin = <0>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block
		 */
		#address-cells = <1>;
		#size-cells = <1>;

		nand-on-flash-bbt;
		/* MT29F2G16ABAFAWP - 256MB */
		partition@0 {
			label = "u-boot";
			reg = <0x0 0x100000>;
			read-only;
		};

		partition@100000 {
			label = "params";
			reg = <0x100000 0x80000>;
		};

		partition@180000 {
			label = "ubifs";
			reg = <0x180000 0xfe80000>;
		};
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&dcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_pins>;
	status = "okay";
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	eeprom@50 {
		compatible = "at,24c1024";
		reg = <0x50>;
	};
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&mmc0_reg>;
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&mmc1_reg>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	spi_nor: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <5000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "misc";
			reg = <0x80000 0xf80000>;
		};
	};
};

&keystone_usb0 {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
	status = "okay";
};

&mdio {
	status = "okay";
	ethphy0: ethernet-phy@0 {
		reg = <0>;
		phy-mode = "rgmii-id";
	};
};

&gbe0 {
	phy-handle = <&ethphy0>;
};

&dsp0 {
	memory-region = <&dsp_common_cma_pool>;
};