Commit 032f708bc4f6da868ec49dac48ddf3670d8035d3
Committed by
Wolfram Sang
Wolfram Sang
1 parent
3aacd625f2
Exists in
master
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16 other branches
i2c: piix4: Add support for AMD ML and CZ SMBus changes
The locations of SMBus register base address and enablement bit are changed from AMD ML, which need this patch to be supported. Signed-off-by: Shane Huang <shane.huang@amd.com> Reviewed-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@vger.kernel.org
Showing 3 changed files with 25 additions and 6 deletions Side-by-side Diff
Documentation/i2c/busses/i2c-piix4
| ... | ... | @@ -13,7 +13,7 @@ |
| 13 | 13 | * AMD SP5100 (SB700 derivative found on some server mainboards) |
| 14 | 14 | Datasheet: Publicly available at the AMD website |
| 15 | 15 | http://support.amd.com/us/Embedded_TechDocs/44413.pdf |
| 16 | - * AMD Hudson-2, CZ | |
| 16 | + * AMD Hudson-2, ML, CZ | |
| 17 | 17 | Datasheet: Not publicly available |
| 18 | 18 | * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge |
| 19 | 19 | Datasheet: Publicly available at the SMSC website http://www.smsc.com |
drivers/i2c/busses/Kconfig
drivers/i2c/busses/i2c-piix4.c
| ... | ... | @@ -22,7 +22,7 @@ |
| 22 | 22 | Intel PIIX4, 440MX |
| 23 | 23 | Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 |
| 24 | 24 | ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 |
| 25 | - AMD Hudson-2, CZ | |
| 25 | + AMD Hudson-2, ML, CZ | |
| 26 | 26 | SMSC Victory66 |
| 27 | 27 | |
| 28 | 28 | Note: we assume there can only be one device, with one or more |
| ... | ... | @@ -235,7 +235,8 @@ |
| 235 | 235 | { |
| 236 | 236 | unsigned short piix4_smba; |
| 237 | 237 | unsigned short smba_idx = 0xcd6; |
| 238 | - u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en; | |
| 238 | + u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status; | |
| 239 | + u8 i2ccfg, i2ccfg_offset = 0x10; | |
| 239 | 240 | |
| 240 | 241 | /* SB800 and later SMBus does not support forcing address */ |
| 241 | 242 | if (force || force_addr) { |
| ... | ... | @@ -245,7 +246,15 @@ |
| 245 | 246 | } |
| 246 | 247 | |
| 247 | 248 | /* Determine the address of the SMBus areas */ |
| 248 | - smb_en = (aux) ? 0x28 : 0x2c; | |
| 249 | + if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && | |
| 250 | + PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && | |
| 251 | + PIIX4_dev->revision >= 0x41) || | |
| 252 | + (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && | |
| 253 | + PIIX4_dev->device == 0x790b && | |
| 254 | + PIIX4_dev->revision >= 0x49)) | |
| 255 | + smb_en = 0x00; | |
| 256 | + else | |
| 257 | + smb_en = (aux) ? 0x28 : 0x2c; | |
| 249 | 258 | |
| 250 | 259 | if (!request_region(smba_idx, 2, "smba_idx")) { |
| 251 | 260 | dev_err(&PIIX4_dev->dev, "SMBus base address index region " |
| 252 | 261 | |
| ... | ... | @@ -258,13 +267,22 @@ |
| 258 | 267 | smba_en_hi = inb_p(smba_idx + 1); |
| 259 | 268 | release_region(smba_idx, 2); |
| 260 | 269 | |
| 261 | - if ((smba_en_lo & 1) == 0) { | |
| 270 | + if (!smb_en) { | |
| 271 | + smb_en_status = smba_en_lo & 0x10; | |
| 272 | + piix4_smba = smba_en_hi << 8; | |
| 273 | + if (aux) | |
| 274 | + piix4_smba |= 0x20; | |
| 275 | + } else { | |
| 276 | + smb_en_status = smba_en_lo & 0x01; | |
| 277 | + piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
| 278 | + } | |
| 279 | + | |
| 280 | + if (!smb_en_status) { | |
| 262 | 281 | dev_err(&PIIX4_dev->dev, |
| 263 | 282 | "Host SMBus controller not enabled!\n"); |
| 264 | 283 | return -ENODEV; |
| 265 | 284 | } |
| 266 | 285 | |
| 267 | - piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
| 268 | 286 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
| 269 | 287 | return -ENODEV; |
| 270 | 288 |