Eric Lee / smarc-ti-linux-kernel

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Commit 0980a60fba7a9afa3259390e8af16b6ce486858a

Authored by Chris Wilson
Committed by Daniel Vetter
1 parent b6dfdc9b7f
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

drm/i915: Acquire dpio_lock for VLV sideband programming in DP/HDMI 

Otherwise we get flooded by the kernel warning us that we are doing
long sequences of IO without serialisation. For example,

 WARNING: CPU: 0 PID: 11136 at drivers/gpu/drm/i915/intel_sideband.c:40 vlv_sideband_rw+0x48/0x1ef()
 Modules linked in:
 CPU: 0 PID: 11136 Comm: kworker/u2:0 Tainted: G        W    3.11.0-rc2+ #4
 Call Trace:
  [<c2028564>] ?  warn_slowpath_common+0x63/0x78
  [<c227ad43>] ?  vlv_sideband_rw+0x48/0x1ef
  [<c20285dd>] ?  warn_slowpath_null+0xf/0x13
  [<c227ad43>] ?  vlv_sideband_rw+0x48/0x1ef
  [<c227b060>] ?  vlv_dpio_write+0x1c/0x21
  [<c2262b3b>] ?  intel_dp_set_signal_levels+0x24a/0x385
  [<c2264909>] ?  intel_dp_complete_link_train+0x25/0x1d1
  [<c2264c55>] ?  intel_dp_check_link_status+0xf7/0x106
  [<c2238ced>] ?  i915_hotplug_work_func+0x17b/0x221
  [<c203a204>] ?  process_one_work+0x12e/0x210
  [<c203a5e4>] ?  worker_thread+0x116/0x1ad
  [<c203a4ce>] ?  rescuer_thread+0x1cb/0x1cb
  [<c203d8f5>] ?  kthread+0x67/0x6c
  [<c2457ebb>] ?  ret_from_kernel_thread+0x1b/0x30
  [<c203d88e>] ?  init_completion+0x18/0x18

v2: Retire the locking in vlv_crtc_enable() and do it close to the meat.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Squash in a s/mutex_lock/mutex_unlock/ fixup spotted by the 0
day kernel build/coccinelle and reported by Dan Carpenter.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Showing 3 changed files with 10 additions and 4 deletions Side-by-side Diff

drivers/gpu/drm/i915/intel_display.c
Diff comments   View file @ 0980a60
... ... @@ -3652,8 +3652,6 @@
3652 3652 intel_crtc->active = true;
3653 3653 intel_update_watermarks(dev);
3654 3654  
3655   - mutex_lock(&dev_priv->dpio_lock);
3656   -
3657 3655 for_each_encoder_on_crtc(dev, crtc, encoder)
3658 3656 if (encoder->pre_pll_enable)
3659 3657 encoder->pre_pll_enable(encoder);
... ... @@ -3678,8 +3676,6 @@
3678 3676 intel_crtc_update_cursor(crtc, true);
3679 3677  
3680 3678 intel_update_fbc(dev);
3681   -
3682   - mutex_unlock(&dev_priv->dpio_lock);
3683 3679 }
3684 3680  
3685 3681 static void i9xx_crtc_enable(struct drm_crtc *crtc)
drivers/gpu/drm/i915/intel_dp.c
Diff comments   View file @ 0980a60
... ... @@ -1727,6 +1727,7 @@
1727 1727 int pipe = intel_crtc->pipe;
1728 1728 u32 val;
1729 1729  
  1730 + mutex_lock(&dev_priv->dpio_lock);
1730 1731 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1731 1732 val = 0;
1732 1733 if (pipe)
... ... @@ -1740,6 +1741,7 @@
1740 1741 0x00760018);
1741 1742 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1742 1743 0x00400888);
  1744 + mutex_unlock(&dev_priv->dpio_lock);
1743 1745 }
1744 1746 }
1745 1747  
... ... @@ -1754,6 +1756,7 @@
1754 1756 return;
1755 1757  
1756 1758 /* Program Tx lane resets to default */
  1759 + mutex_lock(&dev_priv->dpio_lock);
1757 1760 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1758 1761 DPIO_PCS_TX_LANE2_RESET |
1759 1762 DPIO_PCS_TX_LANE1_RESET);
... ... @@ -1767,6 +1770,7 @@
1767 1770 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1768 1771 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1769 1772 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
  1773 + mutex_unlock(&dev_priv->dpio_lock);
1770 1774 }
1771 1775  
1772 1776 /*
... ... @@ -1978,6 +1982,7 @@
1978 1982 return 0;
1979 1983 }
1980 1984  
  1985 + mutex_lock(&dev_priv->dpio_lock);
1981 1986 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1982 1987 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1983 1988 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
... ... @@ -1986,6 +1991,7 @@
1986 1991 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1987 1992 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1988 1993 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
  1994 + mutex_unlock(&dev_priv->dpio_lock);
1989 1995  
1990 1996 return 0;
1991 1997 }
drivers/gpu/drm/i915/intel_hdmi.c
Diff comments   View file @ 0980a60
... ... @@ -1019,6 +1019,7 @@
1019 1019 return;
1020 1020  
1021 1021 /* Enable clock channels for this port */
  1022 + mutex_lock(&dev_priv->dpio_lock);
1022 1023 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1023 1024 val = 0;
1024 1025 if (pipe)
... ... @@ -1049,6 +1050,7 @@
1049 1050 0x00760018);
1050 1051 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1051 1052 0x00400888);
  1053 + mutex_unlock(&dev_priv->dpio_lock);
1052 1054 }
1053 1055  
1054 1056 static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
... ... @@ -1062,6 +1064,7 @@
1062 1064 return;
1063 1065  
1064 1066 /* Program Tx lane resets to default */
  1067 + mutex_lock(&dev_priv->dpio_lock);
1065 1068 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1066 1069 DPIO_PCS_TX_LANE2_RESET |
1067 1070 DPIO_PCS_TX_LANE1_RESET);
... ... @@ -1080,6 +1083,7 @@
1080 1083 0x00002000);
1081 1084 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1082 1085 DPIO_TX_OCALINIT_EN);
  1086 + mutex_unlock(&dev_priv->dpio_lock);
1083 1087 }
1084 1088  
1085 1089 static void intel_hdmi_post_disable(struct intel_encoder *encoder)