Commit 09f2e748e02e8133c3effdba371b1dd20a16015d
Committed by
Greg Kroah-Hartman
1 parent
b3b345af59
MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
commit ed4cbc81addbc076b016c5b979fd1a02f0897f0a upstream. activate_mm() and switch_mm() call get_new_mmu_context() which in turn can enable the HTW before the entryhi is changed with the new ASID. Since the latter will enable the HTW in local_flush_tlb_all(), then there is a small timing window where the HTW is running with the new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD hasn't assigned a new one yet. In order to prevent that, we introduce a simple htw counter to avoid starting HTW accidentally due to nested htw_{start,stop}() sequences. Moreover, since various IPI calls can enforce TLB flushing operations on a different core, such an operation may interrupt another htw_{stop,start} in progress leading inconsistent updates of the htw_seq variable. In order to avoid that, we disable the interrupts whenever we update that variable. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9118/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Showing 4 changed files with 32 additions and 8 deletions Side-by-side Diff
arch/mips/include/asm/cpu-info.h
... | ... | @@ -84,6 +84,11 @@ |
84 | 84 | * (shifted by _CACHE_SHIFT) |
85 | 85 | */ |
86 | 86 | unsigned int writecombine; |
87 | + /* | |
88 | + * Simple counter to prevent enabling HTW in nested | |
89 | + * htw_start/htw_stop calls | |
90 | + */ | |
91 | + unsigned int htw_seq; | |
87 | 92 | } __attribute__((aligned(SMP_CACHE_BYTES))); |
88 | 93 | |
89 | 94 | extern struct cpuinfo_mips cpu_data[]; |
arch/mips/include/asm/mmu_context.h
... | ... | @@ -25,7 +25,6 @@ |
25 | 25 | if (cpu_has_htw) { \ |
26 | 26 | write_c0_pwbase(pgd); \ |
27 | 27 | back_to_back_c0_hazard(); \ |
28 | - htw_reset(); \ | |
29 | 28 | } \ |
30 | 29 | } while (0) |
31 | 30 | |
... | ... | @@ -142,6 +141,7 @@ |
142 | 141 | unsigned long flags; |
143 | 142 | local_irq_save(flags); |
144 | 143 | |
144 | + htw_stop(); | |
145 | 145 | /* Check if our ASID is of an older version and thus invalid */ |
146 | 146 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) |
147 | 147 | get_new_mmu_context(next, cpu); |
... | ... | @@ -154,6 +154,7 @@ |
154 | 154 | */ |
155 | 155 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
156 | 156 | cpumask_set_cpu(cpu, mm_cpumask(next)); |
157 | + htw_start(); | |
157 | 158 | |
158 | 159 | local_irq_restore(flags); |
159 | 160 | } |
... | ... | @@ -180,6 +181,7 @@ |
180 | 181 | |
181 | 182 | local_irq_save(flags); |
182 | 183 | |
184 | + htw_stop(); | |
183 | 185 | /* Unconditionally get a new ASID. */ |
184 | 186 | get_new_mmu_context(next, cpu); |
185 | 187 | |
... | ... | @@ -189,6 +191,7 @@ |
189 | 191 | /* mark mmu ownership change */ |
190 | 192 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
191 | 193 | cpumask_set_cpu(cpu, mm_cpumask(next)); |
194 | + htw_start(); | |
192 | 195 | |
193 | 196 | local_irq_restore(flags); |
194 | 197 | } |
... | ... | @@ -203,6 +206,7 @@ |
203 | 206 | unsigned long flags; |
204 | 207 | |
205 | 208 | local_irq_save(flags); |
209 | + htw_stop(); | |
206 | 210 | |
207 | 211 | if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { |
208 | 212 | get_new_mmu_context(mm, cpu); |
... | ... | @@ -211,6 +215,7 @@ |
211 | 215 | /* will get a new context next time */ |
212 | 216 | cpu_context(cpu, mm) = 0; |
213 | 217 | } |
218 | + htw_start(); | |
214 | 219 | local_irq_restore(flags); |
215 | 220 | } |
216 | 221 |
arch/mips/include/asm/pgtable.h
... | ... | @@ -99,19 +99,31 @@ |
99 | 99 | |
100 | 100 | #define htw_stop() \ |
101 | 101 | do { \ |
102 | + unsigned long flags; \ | |
103 | + \ | |
102 | 104 | if (cpu_has_htw) { \ |
103 | - write_c0_pwctl(read_c0_pwctl() & \ | |
104 | - ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \ | |
105 | - back_to_back_c0_hazard(); \ | |
105 | + local_irq_save(flags); \ | |
106 | + if(!raw_current_cpu_data.htw_seq++) { \ | |
107 | + write_c0_pwctl(read_c0_pwctl() & \ | |
108 | + ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \ | |
109 | + back_to_back_c0_hazard(); \ | |
110 | + } \ | |
111 | + local_irq_restore(flags); \ | |
106 | 112 | } \ |
107 | 113 | } while(0) |
108 | 114 | |
109 | 115 | #define htw_start() \ |
110 | 116 | do { \ |
117 | + unsigned long flags; \ | |
118 | + \ | |
111 | 119 | if (cpu_has_htw) { \ |
112 | - write_c0_pwctl(read_c0_pwctl() | \ | |
113 | - (1 << MIPS_PWCTL_PWEN_SHIFT)); \ | |
114 | - back_to_back_c0_hazard(); \ | |
120 | + local_irq_save(flags); \ | |
121 | + if (!--raw_current_cpu_data.htw_seq) { \ | |
122 | + write_c0_pwctl(read_c0_pwctl() | \ | |
123 | + (1 << MIPS_PWCTL_PWEN_SHIFT)); \ | |
124 | + back_to_back_c0_hazard(); \ | |
125 | + } \ | |
126 | + local_irq_restore(flags); \ | |
115 | 127 | } \ |
116 | 128 | } while(0) |
117 | 129 |
arch/mips/kernel/cpu-probe.c
... | ... | @@ -367,8 +367,10 @@ |
367 | 367 | if (config3 & MIPS_CONF3_MSA) |
368 | 368 | c->ases |= MIPS_ASE_MSA; |
369 | 369 | /* Only tested on 32-bit cores */ |
370 | - if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) | |
370 | + if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { | |
371 | + c->htw_seq = 0; | |
371 | 372 | c->options |= MIPS_CPU_HTW; |
373 | + } | |
372 | 374 | |
373 | 375 | return config3 & MIPS_CONF_M; |
374 | 376 | } |