Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 0a4ae727d6aa459247b027387edb6ff99f657792

Authored by Dave Airlie 2014-06-04 11:29:13 +0800

Exists in ti-lsk-linux-4.1.y and in 12 other branches

Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-fixes

The first one is a one liner fixing a stupid typo in the VM handling code and is only relevant if play with one of the VM defines.

The other two switches CIK to use the CPDMA instead of the SDMA for buffer moves, as it turned out the SDMA is still sometimes not 100% reliable.

* 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: use the CP DMA on CIK
  drm/radeon: sync page table updates
  drm/radeon: fix vm buffer size estimation

Showing 2 changed files Inline Diff

drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_vm.c

drivers/gpu/drm/radeon/radeon_asic.c

Diff comments View file @ 0a4ae72

1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28		28
29	#include <linux/console.h>	29	#include <linux/console.h>
30	#include <drm/drmP.h>	30	#include <drm/drmP.h>
31	#include <drm/drm_crtc_helper.h>	31	#include <drm/drm_crtc_helper.h>
32	#include <drm/radeon_drm.h>	32	#include <drm/radeon_drm.h>
33	#include <linux/vgaarb.h>	33	#include <linux/vgaarb.h>
34	#include <linux/vga_switcheroo.h>	34	#include <linux/vga_switcheroo.h>
35	#include "radeon_reg.h"	35	#include "radeon_reg.h"
36	#include "radeon.h"	36	#include "radeon.h"
37	#include "radeon_asic.h"	37	#include "radeon_asic.h"
38	#include "atom.h"	38	#include "atom.h"
39		39
40	/*	40	/*
41	* Registers accessors functions.	41	* Registers accessors functions.
42	*/	42	*/
43	/**	43	/**
44	* radeon_invalid_rreg - dummy reg read function	44	* radeon_invalid_rreg - dummy reg read function
45	*	45	*
46	* @rdev: radeon device pointer	46	* @rdev: radeon device pointer
47	* @reg: offset of register	47	* @reg: offset of register
48	*	48	*
49	* Dummy register read function. Used for register blocks	49	* Dummy register read function. Used for register blocks
50	* that certain asics don't have (all asics).	50	* that certain asics don't have (all asics).
51	* Returns the value in the register.	51	* Returns the value in the register.
52	*/	52	*/
53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)	53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54	{	54	{
55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);	55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56	BUG_ON(1);	56	BUG_ON(1);
57	return 0;	57	return 0;
58	}	58	}
59		59
60	/**	60	/**
61	* radeon_invalid_wreg - dummy reg write function	61	* radeon_invalid_wreg - dummy reg write function
62	*	62	*
63	* @rdev: radeon device pointer	63	* @rdev: radeon device pointer
64	* @reg: offset of register	64	* @reg: offset of register
65	* @v: value to write to the register	65	* @v: value to write to the register
66	*	66	*
67	* Dummy register read function. Used for register blocks	67	* Dummy register read function. Used for register blocks
68	* that certain asics don't have (all asics).	68	* that certain asics don't have (all asics).
69	*/	69	*/
70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71	{	71	{
72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",	72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73	reg, v);	73	reg, v);
74	BUG_ON(1);	74	BUG_ON(1);
75	}	75	}
76		76
77	/**	77	/**
78	* radeon_register_accessor_init - sets up the register accessor callbacks	78	* radeon_register_accessor_init - sets up the register accessor callbacks
79	*	79	*
80	* @rdev: radeon device pointer	80	* @rdev: radeon device pointer
81	*	81	*
82	* Sets up the register accessor callbacks for various register	82	* Sets up the register accessor callbacks for various register
83	* apertures. Not all asics have all apertures (all asics).	83	* apertures. Not all asics have all apertures (all asics).
84	*/	84	*/
85	static void radeon_register_accessor_init(struct radeon_device *rdev)	85	static void radeon_register_accessor_init(struct radeon_device *rdev)
86	{	86	{
87	rdev->mc_rreg = &radeon_invalid_rreg;	87	rdev->mc_rreg = &radeon_invalid_rreg;
88	rdev->mc_wreg = &radeon_invalid_wreg;	88	rdev->mc_wreg = &radeon_invalid_wreg;
89	rdev->pll_rreg = &radeon_invalid_rreg;	89	rdev->pll_rreg = &radeon_invalid_rreg;
90	rdev->pll_wreg = &radeon_invalid_wreg;	90	rdev->pll_wreg = &radeon_invalid_wreg;
91	rdev->pciep_rreg = &radeon_invalid_rreg;	91	rdev->pciep_rreg = &radeon_invalid_rreg;
92	rdev->pciep_wreg = &radeon_invalid_wreg;	92	rdev->pciep_wreg = &radeon_invalid_wreg;
93		93
94	/* Don't change order as we are overridding accessor. */	94	/* Don't change order as we are overridding accessor. */
95	if (rdev->family < CHIP_RV515) {	95	if (rdev->family < CHIP_RV515) {
96	rdev->pcie_reg_mask = 0xff;	96	rdev->pcie_reg_mask = 0xff;
97	} else {	97	} else {
98	rdev->pcie_reg_mask = 0x7ff;	98	rdev->pcie_reg_mask = 0x7ff;
99	}	99	}
100	/* FIXME: not sure here */	100	/* FIXME: not sure here */
101	if (rdev->family <= CHIP_R580) {	101	if (rdev->family <= CHIP_R580) {
102	rdev->pll_rreg = &r100_pll_rreg;	102	rdev->pll_rreg = &r100_pll_rreg;
103	rdev->pll_wreg = &r100_pll_wreg;	103	rdev->pll_wreg = &r100_pll_wreg;
104	}	104	}
105	if (rdev->family >= CHIP_R420) {	105	if (rdev->family >= CHIP_R420) {
106	rdev->mc_rreg = &r420_mc_rreg;	106	rdev->mc_rreg = &r420_mc_rreg;
107	rdev->mc_wreg = &r420_mc_wreg;	107	rdev->mc_wreg = &r420_mc_wreg;
108	}	108	}
109	if (rdev->family >= CHIP_RV515) {	109	if (rdev->family >= CHIP_RV515) {
110	rdev->mc_rreg = &rv515_mc_rreg;	110	rdev->mc_rreg = &rv515_mc_rreg;
111	rdev->mc_wreg = &rv515_mc_wreg;	111	rdev->mc_wreg = &rv515_mc_wreg;
112	}	112	}
113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {	113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
114	rdev->mc_rreg = &rs400_mc_rreg;	114	rdev->mc_rreg = &rs400_mc_rreg;
115	rdev->mc_wreg = &rs400_mc_wreg;	115	rdev->mc_wreg = &rs400_mc_wreg;
116	}	116	}
117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {	117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
118	rdev->mc_rreg = &rs690_mc_rreg;	118	rdev->mc_rreg = &rs690_mc_rreg;
119	rdev->mc_wreg = &rs690_mc_wreg;	119	rdev->mc_wreg = &rs690_mc_wreg;
120	}	120	}
121	if (rdev->family == CHIP_RS600) {	121	if (rdev->family == CHIP_RS600) {
122	rdev->mc_rreg = &rs600_mc_rreg;	122	rdev->mc_rreg = &rs600_mc_rreg;
123	rdev->mc_wreg = &rs600_mc_wreg;	123	rdev->mc_wreg = &rs600_mc_wreg;
124	}	124	}
125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {	125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
126	rdev->mc_rreg = &rs780_mc_rreg;	126	rdev->mc_rreg = &rs780_mc_rreg;
127	rdev->mc_wreg = &rs780_mc_wreg;	127	rdev->mc_wreg = &rs780_mc_wreg;
128	}	128	}
129		129
130	if (rdev->family >= CHIP_BONAIRE) {	130	if (rdev->family >= CHIP_BONAIRE) {
131	rdev->pciep_rreg = &cik_pciep_rreg;	131	rdev->pciep_rreg = &cik_pciep_rreg;
132	rdev->pciep_wreg = &cik_pciep_wreg;	132	rdev->pciep_wreg = &cik_pciep_wreg;
133	} else if (rdev->family >= CHIP_R600) {	133	} else if (rdev->family >= CHIP_R600) {
134	rdev->pciep_rreg = &r600_pciep_rreg;	134	rdev->pciep_rreg = &r600_pciep_rreg;
135	rdev->pciep_wreg = &r600_pciep_wreg;	135	rdev->pciep_wreg = &r600_pciep_wreg;
136	}	136	}
137	}	137	}
138		138
139		139
140	/* helper to disable agp */	140	/* helper to disable agp */
141	/**	141	/**
142	* radeon_agp_disable - AGP disable helper function	142	* radeon_agp_disable - AGP disable helper function
143	*	143	*
144	* @rdev: radeon device pointer	144	* @rdev: radeon device pointer
145	*	145	*
146	* Removes AGP flags and changes the gart callbacks on AGP	146	* Removes AGP flags and changes the gart callbacks on AGP
147	* cards when using the internal gart rather than AGP (all asics).	147	* cards when using the internal gart rather than AGP (all asics).
148	*/	148	*/
149	void radeon_agp_disable(struct radeon_device *rdev)	149	void radeon_agp_disable(struct radeon_device *rdev)
150	{	150	{
151	rdev->flags &= ~RADEON_IS_AGP;	151	rdev->flags &= ~RADEON_IS_AGP;
152	if (rdev->family >= CHIP_R600) {	152	if (rdev->family >= CHIP_R600) {
153	DRM_INFO("Forcing AGP to PCIE mode\n");	153	DRM_INFO("Forcing AGP to PCIE mode\n");
154	rdev->flags \|= RADEON_IS_PCIE;	154	rdev->flags \|= RADEON_IS_PCIE;
155	} else if (rdev->family >= CHIP_RV515 \|\|	155	} else if (rdev->family >= CHIP_RV515 \|\|
156	rdev->family == CHIP_RV380 \|\|	156	rdev->family == CHIP_RV380 \|\|
157	rdev->family == CHIP_RV410 \|\|	157	rdev->family == CHIP_RV410 \|\|
158	rdev->family == CHIP_R423) {	158	rdev->family == CHIP_R423) {
159	DRM_INFO("Forcing AGP to PCIE mode\n");	159	DRM_INFO("Forcing AGP to PCIE mode\n");
160	rdev->flags \|= RADEON_IS_PCIE;	160	rdev->flags \|= RADEON_IS_PCIE;
161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;	161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;	162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163	} else {	163	} else {
164	DRM_INFO("Forcing AGP to PCI mode\n");	164	DRM_INFO("Forcing AGP to PCI mode\n");
165	rdev->flags \|= RADEON_IS_PCI;	165	rdev->flags \|= RADEON_IS_PCI;
166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;	166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;	167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168	}	168	}
169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;	169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170	}	170	}
171		171
172	/*	172	/*
173	* ASIC	173	* ASIC
174	*/	174	*/
175		175
176	static struct radeon_asic_ring r100_gfx_ring = {	176	static struct radeon_asic_ring r100_gfx_ring = {
177	.ib_execute = &r100_ring_ib_execute,	177	.ib_execute = &r100_ring_ib_execute,
178	.emit_fence = &r100_fence_ring_emit,	178	.emit_fence = &r100_fence_ring_emit,
179	.emit_semaphore = &r100_semaphore_ring_emit,	179	.emit_semaphore = &r100_semaphore_ring_emit,
180	.cs_parse = &r100_cs_parse,	180	.cs_parse = &r100_cs_parse,
181	.ring_start = &r100_ring_start,	181	.ring_start = &r100_ring_start,
182	.ring_test = &r100_ring_test,	182	.ring_test = &r100_ring_test,
183	.ib_test = &r100_ib_test,	183	.ib_test = &r100_ib_test,
184	.is_lockup = &r100_gpu_is_lockup,	184	.is_lockup = &r100_gpu_is_lockup,
185	.get_rptr = &r100_gfx_get_rptr,	185	.get_rptr = &r100_gfx_get_rptr,
186	.get_wptr = &r100_gfx_get_wptr,	186	.get_wptr = &r100_gfx_get_wptr,
187	.set_wptr = &r100_gfx_set_wptr,	187	.set_wptr = &r100_gfx_set_wptr,
188	};	188	};
189		189
190	static struct radeon_asic r100_asic = {	190	static struct radeon_asic r100_asic = {
191	.init = &r100_init,	191	.init = &r100_init,
192	.fini = &r100_fini,	192	.fini = &r100_fini,
193	.suspend = &r100_suspend,	193	.suspend = &r100_suspend,
194	.resume = &r100_resume,	194	.resume = &r100_resume,
195	.vga_set_state = &r100_vga_set_state,	195	.vga_set_state = &r100_vga_set_state,
196	.asic_reset = &r100_asic_reset,	196	.asic_reset = &r100_asic_reset,
197	.ioctl_wait_idle = NULL,	197	.ioctl_wait_idle = NULL,
198	.gui_idle = &r100_gui_idle,	198	.gui_idle = &r100_gui_idle,
199	.mc_wait_for_idle = &r100_mc_wait_for_idle,	199	.mc_wait_for_idle = &r100_mc_wait_for_idle,
200	.gart = {	200	.gart = {
201	.tlb_flush = &r100_pci_gart_tlb_flush,	201	.tlb_flush = &r100_pci_gart_tlb_flush,
202	.set_page = &r100_pci_gart_set_page,	202	.set_page = &r100_pci_gart_set_page,
203	},	203	},
204	.ring = {	204	.ring = {
205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
206	},	206	},
207	.irq = {	207	.irq = {
208	.set = &r100_irq_set,	208	.set = &r100_irq_set,
209	.process = &r100_irq_process,	209	.process = &r100_irq_process,
210	},	210	},
211	.display = {	211	.display = {
212	.bandwidth_update = &r100_bandwidth_update,	212	.bandwidth_update = &r100_bandwidth_update,
213	.get_vblank_counter = &r100_get_vblank_counter,	213	.get_vblank_counter = &r100_get_vblank_counter,
214	.wait_for_vblank = &r100_wait_for_vblank,	214	.wait_for_vblank = &r100_wait_for_vblank,
215	.set_backlight_level = &radeon_legacy_set_backlight_level,	215	.set_backlight_level = &radeon_legacy_set_backlight_level,
216	.get_backlight_level = &radeon_legacy_get_backlight_level,	216	.get_backlight_level = &radeon_legacy_get_backlight_level,
217	},	217	},
218	.copy = {	218	.copy = {
219	.blit = &r100_copy_blit,	219	.blit = &r100_copy_blit,
220	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	220	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221	.dma = NULL,	221	.dma = NULL,
222	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	222	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223	.copy = &r100_copy_blit,	223	.copy = &r100_copy_blit,
224	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	224	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225	},	225	},
226	.surface = {	226	.surface = {
227	.set_reg = r100_set_surface_reg,	227	.set_reg = r100_set_surface_reg,
228	.clear_reg = r100_clear_surface_reg,	228	.clear_reg = r100_clear_surface_reg,
229	},	229	},
230	.hpd = {	230	.hpd = {
231	.init = &r100_hpd_init,	231	.init = &r100_hpd_init,
232	.fini = &r100_hpd_fini,	232	.fini = &r100_hpd_fini,
233	.sense = &r100_hpd_sense,	233	.sense = &r100_hpd_sense,
234	.set_polarity = &r100_hpd_set_polarity,	234	.set_polarity = &r100_hpd_set_polarity,
235	},	235	},
236	.pm = {	236	.pm = {
237	.misc = &r100_pm_misc,	237	.misc = &r100_pm_misc,
238	.prepare = &r100_pm_prepare,	238	.prepare = &r100_pm_prepare,
239	.finish = &r100_pm_finish,	239	.finish = &r100_pm_finish,
240	.init_profile = &r100_pm_init_profile,	240	.init_profile = &r100_pm_init_profile,
241	.get_dynpm_state = &r100_pm_get_dynpm_state,	241	.get_dynpm_state = &r100_pm_get_dynpm_state,
242	.get_engine_clock = &radeon_legacy_get_engine_clock,	242	.get_engine_clock = &radeon_legacy_get_engine_clock,
243	.set_engine_clock = &radeon_legacy_set_engine_clock,	243	.set_engine_clock = &radeon_legacy_set_engine_clock,
244	.get_memory_clock = &radeon_legacy_get_memory_clock,	244	.get_memory_clock = &radeon_legacy_get_memory_clock,
245	.set_memory_clock = NULL,	245	.set_memory_clock = NULL,
246	.get_pcie_lanes = NULL,	246	.get_pcie_lanes = NULL,
247	.set_pcie_lanes = NULL,	247	.set_pcie_lanes = NULL,
248	.set_clock_gating = &radeon_legacy_set_clock_gating,	248	.set_clock_gating = &radeon_legacy_set_clock_gating,
249	},	249	},
250	.pflip = {	250	.pflip = {
251	.pre_page_flip = &r100_pre_page_flip,	251	.pre_page_flip = &r100_pre_page_flip,
252	.page_flip = &r100_page_flip,	252	.page_flip = &r100_page_flip,
253	.post_page_flip = &r100_post_page_flip,	253	.post_page_flip = &r100_post_page_flip,
254	},	254	},
255	};	255	};
256		256
257	static struct radeon_asic r200_asic = {	257	static struct radeon_asic r200_asic = {
258	.init = &r100_init,	258	.init = &r100_init,
259	.fini = &r100_fini,	259	.fini = &r100_fini,
260	.suspend = &r100_suspend,	260	.suspend = &r100_suspend,
261	.resume = &r100_resume,	261	.resume = &r100_resume,
262	.vga_set_state = &r100_vga_set_state,	262	.vga_set_state = &r100_vga_set_state,
263	.asic_reset = &r100_asic_reset,	263	.asic_reset = &r100_asic_reset,
264	.ioctl_wait_idle = NULL,	264	.ioctl_wait_idle = NULL,
265	.gui_idle = &r100_gui_idle,	265	.gui_idle = &r100_gui_idle,
266	.mc_wait_for_idle = &r100_mc_wait_for_idle,	266	.mc_wait_for_idle = &r100_mc_wait_for_idle,
267	.gart = {	267	.gart = {
268	.tlb_flush = &r100_pci_gart_tlb_flush,	268	.tlb_flush = &r100_pci_gart_tlb_flush,
269	.set_page = &r100_pci_gart_set_page,	269	.set_page = &r100_pci_gart_set_page,
270	},	270	},
271	.ring = {	271	.ring = {
272	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	272	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
273	},	273	},
274	.irq = {	274	.irq = {
275	.set = &r100_irq_set,	275	.set = &r100_irq_set,
276	.process = &r100_irq_process,	276	.process = &r100_irq_process,
277	},	277	},
278	.display = {	278	.display = {
279	.bandwidth_update = &r100_bandwidth_update,	279	.bandwidth_update = &r100_bandwidth_update,
280	.get_vblank_counter = &r100_get_vblank_counter,	280	.get_vblank_counter = &r100_get_vblank_counter,
281	.wait_for_vblank = &r100_wait_for_vblank,	281	.wait_for_vblank = &r100_wait_for_vblank,
282	.set_backlight_level = &radeon_legacy_set_backlight_level,	282	.set_backlight_level = &radeon_legacy_set_backlight_level,
283	.get_backlight_level = &radeon_legacy_get_backlight_level,	283	.get_backlight_level = &radeon_legacy_get_backlight_level,
284	},	284	},
285	.copy = {	285	.copy = {
286	.blit = &r100_copy_blit,	286	.blit = &r100_copy_blit,
287	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	287	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288	.dma = &r200_copy_dma,	288	.dma = &r200_copy_dma,
289	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	289	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290	.copy = &r100_copy_blit,	290	.copy = &r100_copy_blit,
291	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	291	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
292	},	292	},
293	.surface = {	293	.surface = {
294	.set_reg = r100_set_surface_reg,	294	.set_reg = r100_set_surface_reg,
295	.clear_reg = r100_clear_surface_reg,	295	.clear_reg = r100_clear_surface_reg,
296	},	296	},
297	.hpd = {	297	.hpd = {
298	.init = &r100_hpd_init,	298	.init = &r100_hpd_init,
299	.fini = &r100_hpd_fini,	299	.fini = &r100_hpd_fini,
300	.sense = &r100_hpd_sense,	300	.sense = &r100_hpd_sense,
301	.set_polarity = &r100_hpd_set_polarity,	301	.set_polarity = &r100_hpd_set_polarity,
302	},	302	},
303	.pm = {	303	.pm = {
304	.misc = &r100_pm_misc,	304	.misc = &r100_pm_misc,
305	.prepare = &r100_pm_prepare,	305	.prepare = &r100_pm_prepare,
306	.finish = &r100_pm_finish,	306	.finish = &r100_pm_finish,
307	.init_profile = &r100_pm_init_profile,	307	.init_profile = &r100_pm_init_profile,
308	.get_dynpm_state = &r100_pm_get_dynpm_state,	308	.get_dynpm_state = &r100_pm_get_dynpm_state,
309	.get_engine_clock = &radeon_legacy_get_engine_clock,	309	.get_engine_clock = &radeon_legacy_get_engine_clock,
310	.set_engine_clock = &radeon_legacy_set_engine_clock,	310	.set_engine_clock = &radeon_legacy_set_engine_clock,
311	.get_memory_clock = &radeon_legacy_get_memory_clock,	311	.get_memory_clock = &radeon_legacy_get_memory_clock,
312	.set_memory_clock = NULL,	312	.set_memory_clock = NULL,
313	.get_pcie_lanes = NULL,	313	.get_pcie_lanes = NULL,
314	.set_pcie_lanes = NULL,	314	.set_pcie_lanes = NULL,
315	.set_clock_gating = &radeon_legacy_set_clock_gating,	315	.set_clock_gating = &radeon_legacy_set_clock_gating,
316	},	316	},
317	.pflip = {	317	.pflip = {
318	.pre_page_flip = &r100_pre_page_flip,	318	.pre_page_flip = &r100_pre_page_flip,
319	.page_flip = &r100_page_flip,	319	.page_flip = &r100_page_flip,
320	.post_page_flip = &r100_post_page_flip,	320	.post_page_flip = &r100_post_page_flip,
321	},	321	},
322	};	322	};
323		323
324	static struct radeon_asic_ring r300_gfx_ring = {	324	static struct radeon_asic_ring r300_gfx_ring = {
325	.ib_execute = &r100_ring_ib_execute,	325	.ib_execute = &r100_ring_ib_execute,
326	.emit_fence = &r300_fence_ring_emit,	326	.emit_fence = &r300_fence_ring_emit,
327	.emit_semaphore = &r100_semaphore_ring_emit,	327	.emit_semaphore = &r100_semaphore_ring_emit,
328	.cs_parse = &r300_cs_parse,	328	.cs_parse = &r300_cs_parse,
329	.ring_start = &r300_ring_start,	329	.ring_start = &r300_ring_start,
330	.ring_test = &r100_ring_test,	330	.ring_test = &r100_ring_test,
331	.ib_test = &r100_ib_test,	331	.ib_test = &r100_ib_test,
332	.is_lockup = &r100_gpu_is_lockup,	332	.is_lockup = &r100_gpu_is_lockup,
333	.get_rptr = &r100_gfx_get_rptr,	333	.get_rptr = &r100_gfx_get_rptr,
334	.get_wptr = &r100_gfx_get_wptr,	334	.get_wptr = &r100_gfx_get_wptr,
335	.set_wptr = &r100_gfx_set_wptr,	335	.set_wptr = &r100_gfx_set_wptr,
336	};	336	};
337		337
338	static struct radeon_asic r300_asic = {	338	static struct radeon_asic r300_asic = {
339	.init = &r300_init,	339	.init = &r300_init,
340	.fini = &r300_fini,	340	.fini = &r300_fini,
341	.suspend = &r300_suspend,	341	.suspend = &r300_suspend,
342	.resume = &r300_resume,	342	.resume = &r300_resume,
343	.vga_set_state = &r100_vga_set_state,	343	.vga_set_state = &r100_vga_set_state,
344	.asic_reset = &r300_asic_reset,	344	.asic_reset = &r300_asic_reset,
345	.ioctl_wait_idle = NULL,	345	.ioctl_wait_idle = NULL,
346	.gui_idle = &r100_gui_idle,	346	.gui_idle = &r100_gui_idle,
347	.mc_wait_for_idle = &r300_mc_wait_for_idle,	347	.mc_wait_for_idle = &r300_mc_wait_for_idle,
348	.gart = {	348	.gart = {
349	.tlb_flush = &r100_pci_gart_tlb_flush,	349	.tlb_flush = &r100_pci_gart_tlb_flush,
350	.set_page = &r100_pci_gart_set_page,	350	.set_page = &r100_pci_gart_set_page,
351	},	351	},
352	.ring = {	352	.ring = {
353	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	353	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
354	},	354	},
355	.irq = {	355	.irq = {
356	.set = &r100_irq_set,	356	.set = &r100_irq_set,
357	.process = &r100_irq_process,	357	.process = &r100_irq_process,
358	},	358	},
359	.display = {	359	.display = {
360	.bandwidth_update = &r100_bandwidth_update,	360	.bandwidth_update = &r100_bandwidth_update,
361	.get_vblank_counter = &r100_get_vblank_counter,	361	.get_vblank_counter = &r100_get_vblank_counter,
362	.wait_for_vblank = &r100_wait_for_vblank,	362	.wait_for_vblank = &r100_wait_for_vblank,
363	.set_backlight_level = &radeon_legacy_set_backlight_level,	363	.set_backlight_level = &radeon_legacy_set_backlight_level,
364	.get_backlight_level = &radeon_legacy_get_backlight_level,	364	.get_backlight_level = &radeon_legacy_get_backlight_level,
365	},	365	},
366	.copy = {	366	.copy = {
367	.blit = &r100_copy_blit,	367	.blit = &r100_copy_blit,
368	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	368	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369	.dma = &r200_copy_dma,	369	.dma = &r200_copy_dma,
370	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	370	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371	.copy = &r100_copy_blit,	371	.copy = &r100_copy_blit,
372	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	372	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373	},	373	},
374	.surface = {	374	.surface = {
375	.set_reg = r100_set_surface_reg,	375	.set_reg = r100_set_surface_reg,
376	.clear_reg = r100_clear_surface_reg,	376	.clear_reg = r100_clear_surface_reg,
377	},	377	},
378	.hpd = {	378	.hpd = {
379	.init = &r100_hpd_init,	379	.init = &r100_hpd_init,
380	.fini = &r100_hpd_fini,	380	.fini = &r100_hpd_fini,
381	.sense = &r100_hpd_sense,	381	.sense = &r100_hpd_sense,
382	.set_polarity = &r100_hpd_set_polarity,	382	.set_polarity = &r100_hpd_set_polarity,
383	},	383	},
384	.pm = {	384	.pm = {
385	.misc = &r100_pm_misc,	385	.misc = &r100_pm_misc,
386	.prepare = &r100_pm_prepare,	386	.prepare = &r100_pm_prepare,
387	.finish = &r100_pm_finish,	387	.finish = &r100_pm_finish,
388	.init_profile = &r100_pm_init_profile,	388	.init_profile = &r100_pm_init_profile,
389	.get_dynpm_state = &r100_pm_get_dynpm_state,	389	.get_dynpm_state = &r100_pm_get_dynpm_state,
390	.get_engine_clock = &radeon_legacy_get_engine_clock,	390	.get_engine_clock = &radeon_legacy_get_engine_clock,
391	.set_engine_clock = &radeon_legacy_set_engine_clock,	391	.set_engine_clock = &radeon_legacy_set_engine_clock,
392	.get_memory_clock = &radeon_legacy_get_memory_clock,	392	.get_memory_clock = &radeon_legacy_get_memory_clock,
393	.set_memory_clock = NULL,	393	.set_memory_clock = NULL,
394	.get_pcie_lanes = &rv370_get_pcie_lanes,	394	.get_pcie_lanes = &rv370_get_pcie_lanes,
395	.set_pcie_lanes = &rv370_set_pcie_lanes,	395	.set_pcie_lanes = &rv370_set_pcie_lanes,
396	.set_clock_gating = &radeon_legacy_set_clock_gating,	396	.set_clock_gating = &radeon_legacy_set_clock_gating,
397	},	397	},
398	.pflip = {	398	.pflip = {
399	.pre_page_flip = &r100_pre_page_flip,	399	.pre_page_flip = &r100_pre_page_flip,
400	.page_flip = &r100_page_flip,	400	.page_flip = &r100_page_flip,
401	.post_page_flip = &r100_post_page_flip,	401	.post_page_flip = &r100_post_page_flip,
402	},	402	},
403	};	403	};
404		404
405	static struct radeon_asic r300_asic_pcie = {	405	static struct radeon_asic r300_asic_pcie = {
406	.init = &r300_init,	406	.init = &r300_init,
407	.fini = &r300_fini,	407	.fini = &r300_fini,
408	.suspend = &r300_suspend,	408	.suspend = &r300_suspend,
409	.resume = &r300_resume,	409	.resume = &r300_resume,
410	.vga_set_state = &r100_vga_set_state,	410	.vga_set_state = &r100_vga_set_state,
411	.asic_reset = &r300_asic_reset,	411	.asic_reset = &r300_asic_reset,
412	.ioctl_wait_idle = NULL,	412	.ioctl_wait_idle = NULL,
413	.gui_idle = &r100_gui_idle,	413	.gui_idle = &r100_gui_idle,
414	.mc_wait_for_idle = &r300_mc_wait_for_idle,	414	.mc_wait_for_idle = &r300_mc_wait_for_idle,
415	.gart = {	415	.gart = {
416	.tlb_flush = &rv370_pcie_gart_tlb_flush,	416	.tlb_flush = &rv370_pcie_gart_tlb_flush,
417	.set_page = &rv370_pcie_gart_set_page,	417	.set_page = &rv370_pcie_gart_set_page,
418	},	418	},
419	.ring = {	419	.ring = {
420	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	420	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
421	},	421	},
422	.irq = {	422	.irq = {
423	.set = &r100_irq_set,	423	.set = &r100_irq_set,
424	.process = &r100_irq_process,	424	.process = &r100_irq_process,
425	},	425	},
426	.display = {	426	.display = {
427	.bandwidth_update = &r100_bandwidth_update,	427	.bandwidth_update = &r100_bandwidth_update,
428	.get_vblank_counter = &r100_get_vblank_counter,	428	.get_vblank_counter = &r100_get_vblank_counter,
429	.wait_for_vblank = &r100_wait_for_vblank,	429	.wait_for_vblank = &r100_wait_for_vblank,
430	.set_backlight_level = &radeon_legacy_set_backlight_level,	430	.set_backlight_level = &radeon_legacy_set_backlight_level,
431	.get_backlight_level = &radeon_legacy_get_backlight_level,	431	.get_backlight_level = &radeon_legacy_get_backlight_level,
432	},	432	},
433	.copy = {	433	.copy = {
434	.blit = &r100_copy_blit,	434	.blit = &r100_copy_blit,
435	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	435	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436	.dma = &r200_copy_dma,	436	.dma = &r200_copy_dma,
437	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	437	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438	.copy = &r100_copy_blit,	438	.copy = &r100_copy_blit,
439	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	439	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
440	},	440	},
441	.surface = {	441	.surface = {
442	.set_reg = r100_set_surface_reg,	442	.set_reg = r100_set_surface_reg,
443	.clear_reg = r100_clear_surface_reg,	443	.clear_reg = r100_clear_surface_reg,
444	},	444	},
445	.hpd = {	445	.hpd = {
446	.init = &r100_hpd_init,	446	.init = &r100_hpd_init,
447	.fini = &r100_hpd_fini,	447	.fini = &r100_hpd_fini,
448	.sense = &r100_hpd_sense,	448	.sense = &r100_hpd_sense,
449	.set_polarity = &r100_hpd_set_polarity,	449	.set_polarity = &r100_hpd_set_polarity,
450	},	450	},
451	.pm = {	451	.pm = {
452	.misc = &r100_pm_misc,	452	.misc = &r100_pm_misc,
453	.prepare = &r100_pm_prepare,	453	.prepare = &r100_pm_prepare,
454	.finish = &r100_pm_finish,	454	.finish = &r100_pm_finish,
455	.init_profile = &r100_pm_init_profile,	455	.init_profile = &r100_pm_init_profile,
456	.get_dynpm_state = &r100_pm_get_dynpm_state,	456	.get_dynpm_state = &r100_pm_get_dynpm_state,
457	.get_engine_clock = &radeon_legacy_get_engine_clock,	457	.get_engine_clock = &radeon_legacy_get_engine_clock,
458	.set_engine_clock = &radeon_legacy_set_engine_clock,	458	.set_engine_clock = &radeon_legacy_set_engine_clock,
459	.get_memory_clock = &radeon_legacy_get_memory_clock,	459	.get_memory_clock = &radeon_legacy_get_memory_clock,
460	.set_memory_clock = NULL,	460	.set_memory_clock = NULL,
461	.get_pcie_lanes = &rv370_get_pcie_lanes,	461	.get_pcie_lanes = &rv370_get_pcie_lanes,
462	.set_pcie_lanes = &rv370_set_pcie_lanes,	462	.set_pcie_lanes = &rv370_set_pcie_lanes,
463	.set_clock_gating = &radeon_legacy_set_clock_gating,	463	.set_clock_gating = &radeon_legacy_set_clock_gating,
464	},	464	},
465	.pflip = {	465	.pflip = {
466	.pre_page_flip = &r100_pre_page_flip,	466	.pre_page_flip = &r100_pre_page_flip,
467	.page_flip = &r100_page_flip,	467	.page_flip = &r100_page_flip,
468	.post_page_flip = &r100_post_page_flip,	468	.post_page_flip = &r100_post_page_flip,
469	},	469	},
470	};	470	};
471		471
472	static struct radeon_asic r420_asic = {	472	static struct radeon_asic r420_asic = {
473	.init = &r420_init,	473	.init = &r420_init,
474	.fini = &r420_fini,	474	.fini = &r420_fini,
475	.suspend = &r420_suspend,	475	.suspend = &r420_suspend,
476	.resume = &r420_resume,	476	.resume = &r420_resume,
477	.vga_set_state = &r100_vga_set_state,	477	.vga_set_state = &r100_vga_set_state,
478	.asic_reset = &r300_asic_reset,	478	.asic_reset = &r300_asic_reset,
479	.ioctl_wait_idle = NULL,	479	.ioctl_wait_idle = NULL,
480	.gui_idle = &r100_gui_idle,	480	.gui_idle = &r100_gui_idle,
481	.mc_wait_for_idle = &r300_mc_wait_for_idle,	481	.mc_wait_for_idle = &r300_mc_wait_for_idle,
482	.gart = {	482	.gart = {
483	.tlb_flush = &rv370_pcie_gart_tlb_flush,	483	.tlb_flush = &rv370_pcie_gart_tlb_flush,
484	.set_page = &rv370_pcie_gart_set_page,	484	.set_page = &rv370_pcie_gart_set_page,
485	},	485	},
486	.ring = {	486	.ring = {
487	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	487	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
488	},	488	},
489	.irq = {	489	.irq = {
490	.set = &r100_irq_set,	490	.set = &r100_irq_set,
491	.process = &r100_irq_process,	491	.process = &r100_irq_process,
492	},	492	},
493	.display = {	493	.display = {
494	.bandwidth_update = &r100_bandwidth_update,	494	.bandwidth_update = &r100_bandwidth_update,
495	.get_vblank_counter = &r100_get_vblank_counter,	495	.get_vblank_counter = &r100_get_vblank_counter,
496	.wait_for_vblank = &r100_wait_for_vblank,	496	.wait_for_vblank = &r100_wait_for_vblank,
497	.set_backlight_level = &atombios_set_backlight_level,	497	.set_backlight_level = &atombios_set_backlight_level,
498	.get_backlight_level = &atombios_get_backlight_level,	498	.get_backlight_level = &atombios_get_backlight_level,
499	},	499	},
500	.copy = {	500	.copy = {
501	.blit = &r100_copy_blit,	501	.blit = &r100_copy_blit,
502	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	502	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503	.dma = &r200_copy_dma,	503	.dma = &r200_copy_dma,
504	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	504	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505	.copy = &r100_copy_blit,	505	.copy = &r100_copy_blit,
506	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	506	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
507	},	507	},
508	.surface = {	508	.surface = {
509	.set_reg = r100_set_surface_reg,	509	.set_reg = r100_set_surface_reg,
510	.clear_reg = r100_clear_surface_reg,	510	.clear_reg = r100_clear_surface_reg,
511	},	511	},
512	.hpd = {	512	.hpd = {
513	.init = &r100_hpd_init,	513	.init = &r100_hpd_init,
514	.fini = &r100_hpd_fini,	514	.fini = &r100_hpd_fini,
515	.sense = &r100_hpd_sense,	515	.sense = &r100_hpd_sense,
516	.set_polarity = &r100_hpd_set_polarity,	516	.set_polarity = &r100_hpd_set_polarity,
517	},	517	},
518	.pm = {	518	.pm = {
519	.misc = &r100_pm_misc,	519	.misc = &r100_pm_misc,
520	.prepare = &r100_pm_prepare,	520	.prepare = &r100_pm_prepare,
521	.finish = &r100_pm_finish,	521	.finish = &r100_pm_finish,
522	.init_profile = &r420_pm_init_profile,	522	.init_profile = &r420_pm_init_profile,
523	.get_dynpm_state = &r100_pm_get_dynpm_state,	523	.get_dynpm_state = &r100_pm_get_dynpm_state,
524	.get_engine_clock = &radeon_atom_get_engine_clock,	524	.get_engine_clock = &radeon_atom_get_engine_clock,
525	.set_engine_clock = &radeon_atom_set_engine_clock,	525	.set_engine_clock = &radeon_atom_set_engine_clock,
526	.get_memory_clock = &radeon_atom_get_memory_clock,	526	.get_memory_clock = &radeon_atom_get_memory_clock,
527	.set_memory_clock = &radeon_atom_set_memory_clock,	527	.set_memory_clock = &radeon_atom_set_memory_clock,
528	.get_pcie_lanes = &rv370_get_pcie_lanes,	528	.get_pcie_lanes = &rv370_get_pcie_lanes,
529	.set_pcie_lanes = &rv370_set_pcie_lanes,	529	.set_pcie_lanes = &rv370_set_pcie_lanes,
530	.set_clock_gating = &radeon_atom_set_clock_gating,	530	.set_clock_gating = &radeon_atom_set_clock_gating,
531	},	531	},
532	.pflip = {	532	.pflip = {
533	.pre_page_flip = &r100_pre_page_flip,	533	.pre_page_flip = &r100_pre_page_flip,
534	.page_flip = &r100_page_flip,	534	.page_flip = &r100_page_flip,
535	.post_page_flip = &r100_post_page_flip,	535	.post_page_flip = &r100_post_page_flip,
536	},	536	},
537	};	537	};
538		538
539	static struct radeon_asic rs400_asic = {	539	static struct radeon_asic rs400_asic = {
540	.init = &rs400_init,	540	.init = &rs400_init,
541	.fini = &rs400_fini,	541	.fini = &rs400_fini,
542	.suspend = &rs400_suspend,	542	.suspend = &rs400_suspend,
543	.resume = &rs400_resume,	543	.resume = &rs400_resume,
544	.vga_set_state = &r100_vga_set_state,	544	.vga_set_state = &r100_vga_set_state,
545	.asic_reset = &r300_asic_reset,	545	.asic_reset = &r300_asic_reset,
546	.ioctl_wait_idle = NULL,	546	.ioctl_wait_idle = NULL,
547	.gui_idle = &r100_gui_idle,	547	.gui_idle = &r100_gui_idle,
548	.mc_wait_for_idle = &rs400_mc_wait_for_idle,	548	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
549	.gart = {	549	.gart = {
550	.tlb_flush = &rs400_gart_tlb_flush,	550	.tlb_flush = &rs400_gart_tlb_flush,
551	.set_page = &rs400_gart_set_page,	551	.set_page = &rs400_gart_set_page,
552	},	552	},
553	.ring = {	553	.ring = {
554	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	554	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
555	},	555	},
556	.irq = {	556	.irq = {
557	.set = &r100_irq_set,	557	.set = &r100_irq_set,
558	.process = &r100_irq_process,	558	.process = &r100_irq_process,
559	},	559	},
560	.display = {	560	.display = {
561	.bandwidth_update = &r100_bandwidth_update,	561	.bandwidth_update = &r100_bandwidth_update,
562	.get_vblank_counter = &r100_get_vblank_counter,	562	.get_vblank_counter = &r100_get_vblank_counter,
563	.wait_for_vblank = &r100_wait_for_vblank,	563	.wait_for_vblank = &r100_wait_for_vblank,
564	.set_backlight_level = &radeon_legacy_set_backlight_level,	564	.set_backlight_level = &radeon_legacy_set_backlight_level,
565	.get_backlight_level = &radeon_legacy_get_backlight_level,	565	.get_backlight_level = &radeon_legacy_get_backlight_level,
566	},	566	},
567	.copy = {	567	.copy = {
568	.blit = &r100_copy_blit,	568	.blit = &r100_copy_blit,
569	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	569	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570	.dma = &r200_copy_dma,	570	.dma = &r200_copy_dma,
571	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	571	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572	.copy = &r100_copy_blit,	572	.copy = &r100_copy_blit,
573	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	573	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
574	},	574	},
575	.surface = {	575	.surface = {
576	.set_reg = r100_set_surface_reg,	576	.set_reg = r100_set_surface_reg,
577	.clear_reg = r100_clear_surface_reg,	577	.clear_reg = r100_clear_surface_reg,
578	},	578	},
579	.hpd = {	579	.hpd = {
580	.init = &r100_hpd_init,	580	.init = &r100_hpd_init,
581	.fini = &r100_hpd_fini,	581	.fini = &r100_hpd_fini,
582	.sense = &r100_hpd_sense,	582	.sense = &r100_hpd_sense,
583	.set_polarity = &r100_hpd_set_polarity,	583	.set_polarity = &r100_hpd_set_polarity,
584	},	584	},
585	.pm = {	585	.pm = {
586	.misc = &r100_pm_misc,	586	.misc = &r100_pm_misc,
587	.prepare = &r100_pm_prepare,	587	.prepare = &r100_pm_prepare,
588	.finish = &r100_pm_finish,	588	.finish = &r100_pm_finish,
589	.init_profile = &r100_pm_init_profile,	589	.init_profile = &r100_pm_init_profile,
590	.get_dynpm_state = &r100_pm_get_dynpm_state,	590	.get_dynpm_state = &r100_pm_get_dynpm_state,
591	.get_engine_clock = &radeon_legacy_get_engine_clock,	591	.get_engine_clock = &radeon_legacy_get_engine_clock,
592	.set_engine_clock = &radeon_legacy_set_engine_clock,	592	.set_engine_clock = &radeon_legacy_set_engine_clock,
593	.get_memory_clock = &radeon_legacy_get_memory_clock,	593	.get_memory_clock = &radeon_legacy_get_memory_clock,
594	.set_memory_clock = NULL,	594	.set_memory_clock = NULL,
595	.get_pcie_lanes = NULL,	595	.get_pcie_lanes = NULL,
596	.set_pcie_lanes = NULL,	596	.set_pcie_lanes = NULL,
597	.set_clock_gating = &radeon_legacy_set_clock_gating,	597	.set_clock_gating = &radeon_legacy_set_clock_gating,
598	},	598	},
599	.pflip = {	599	.pflip = {
600	.pre_page_flip = &r100_pre_page_flip,	600	.pre_page_flip = &r100_pre_page_flip,
601	.page_flip = &r100_page_flip,	601	.page_flip = &r100_page_flip,
602	.post_page_flip = &r100_post_page_flip,	602	.post_page_flip = &r100_post_page_flip,
603	},	603	},
604	};	604	};
605		605
606	static struct radeon_asic rs600_asic = {	606	static struct radeon_asic rs600_asic = {
607	.init = &rs600_init,	607	.init = &rs600_init,
608	.fini = &rs600_fini,	608	.fini = &rs600_fini,
609	.suspend = &rs600_suspend,	609	.suspend = &rs600_suspend,
610	.resume = &rs600_resume,	610	.resume = &rs600_resume,
611	.vga_set_state = &r100_vga_set_state,	611	.vga_set_state = &r100_vga_set_state,
612	.asic_reset = &rs600_asic_reset,	612	.asic_reset = &rs600_asic_reset,
613	.ioctl_wait_idle = NULL,	613	.ioctl_wait_idle = NULL,
614	.gui_idle = &r100_gui_idle,	614	.gui_idle = &r100_gui_idle,
615	.mc_wait_for_idle = &rs600_mc_wait_for_idle,	615	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
616	.gart = {	616	.gart = {
617	.tlb_flush = &rs600_gart_tlb_flush,	617	.tlb_flush = &rs600_gart_tlb_flush,
618	.set_page = &rs600_gart_set_page,	618	.set_page = &rs600_gart_set_page,
619	},	619	},
620	.ring = {	620	.ring = {
621	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	621	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
622	},	622	},
623	.irq = {	623	.irq = {
624	.set = &rs600_irq_set,	624	.set = &rs600_irq_set,
625	.process = &rs600_irq_process,	625	.process = &rs600_irq_process,
626	},	626	},
627	.display = {	627	.display = {
628	.bandwidth_update = &rs600_bandwidth_update,	628	.bandwidth_update = &rs600_bandwidth_update,
629	.get_vblank_counter = &rs600_get_vblank_counter,	629	.get_vblank_counter = &rs600_get_vblank_counter,
630	.wait_for_vblank = &avivo_wait_for_vblank,	630	.wait_for_vblank = &avivo_wait_for_vblank,
631	.set_backlight_level = &atombios_set_backlight_level,	631	.set_backlight_level = &atombios_set_backlight_level,
632	.get_backlight_level = &atombios_get_backlight_level,	632	.get_backlight_level = &atombios_get_backlight_level,
633	.hdmi_enable = &r600_hdmi_enable,	633	.hdmi_enable = &r600_hdmi_enable,
634	.hdmi_setmode = &r600_hdmi_setmode,	634	.hdmi_setmode = &r600_hdmi_setmode,
635	},	635	},
636	.copy = {	636	.copy = {
637	.blit = &r100_copy_blit,	637	.blit = &r100_copy_blit,
638	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	638	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639	.dma = &r200_copy_dma,	639	.dma = &r200_copy_dma,
640	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	640	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641	.copy = &r100_copy_blit,	641	.copy = &r100_copy_blit,
642	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	642	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
643	},	643	},
644	.surface = {	644	.surface = {
645	.set_reg = r100_set_surface_reg,	645	.set_reg = r100_set_surface_reg,
646	.clear_reg = r100_clear_surface_reg,	646	.clear_reg = r100_clear_surface_reg,
647	},	647	},
648	.hpd = {	648	.hpd = {
649	.init = &rs600_hpd_init,	649	.init = &rs600_hpd_init,
650	.fini = &rs600_hpd_fini,	650	.fini = &rs600_hpd_fini,
651	.sense = &rs600_hpd_sense,	651	.sense = &rs600_hpd_sense,
652	.set_polarity = &rs600_hpd_set_polarity,	652	.set_polarity = &rs600_hpd_set_polarity,
653	},	653	},
654	.pm = {	654	.pm = {
655	.misc = &rs600_pm_misc,	655	.misc = &rs600_pm_misc,
656	.prepare = &rs600_pm_prepare,	656	.prepare = &rs600_pm_prepare,
657	.finish = &rs600_pm_finish,	657	.finish = &rs600_pm_finish,
658	.init_profile = &r420_pm_init_profile,	658	.init_profile = &r420_pm_init_profile,
659	.get_dynpm_state = &r100_pm_get_dynpm_state,	659	.get_dynpm_state = &r100_pm_get_dynpm_state,
660	.get_engine_clock = &radeon_atom_get_engine_clock,	660	.get_engine_clock = &radeon_atom_get_engine_clock,
661	.set_engine_clock = &radeon_atom_set_engine_clock,	661	.set_engine_clock = &radeon_atom_set_engine_clock,
662	.get_memory_clock = &radeon_atom_get_memory_clock,	662	.get_memory_clock = &radeon_atom_get_memory_clock,
663	.set_memory_clock = &radeon_atom_set_memory_clock,	663	.set_memory_clock = &radeon_atom_set_memory_clock,
664	.get_pcie_lanes = NULL,	664	.get_pcie_lanes = NULL,
665	.set_pcie_lanes = NULL,	665	.set_pcie_lanes = NULL,
666	.set_clock_gating = &radeon_atom_set_clock_gating,	666	.set_clock_gating = &radeon_atom_set_clock_gating,
667	},	667	},
668	.pflip = {	668	.pflip = {
669	.pre_page_flip = &rs600_pre_page_flip,	669	.pre_page_flip = &rs600_pre_page_flip,
670	.page_flip = &rs600_page_flip,	670	.page_flip = &rs600_page_flip,
671	.post_page_flip = &rs600_post_page_flip,	671	.post_page_flip = &rs600_post_page_flip,
672	},	672	},
673	};	673	};
674		674
675	static struct radeon_asic rs690_asic = {	675	static struct radeon_asic rs690_asic = {
676	.init = &rs690_init,	676	.init = &rs690_init,
677	.fini = &rs690_fini,	677	.fini = &rs690_fini,
678	.suspend = &rs690_suspend,	678	.suspend = &rs690_suspend,
679	.resume = &rs690_resume,	679	.resume = &rs690_resume,
680	.vga_set_state = &r100_vga_set_state,	680	.vga_set_state = &r100_vga_set_state,
681	.asic_reset = &rs600_asic_reset,	681	.asic_reset = &rs600_asic_reset,
682	.ioctl_wait_idle = NULL,	682	.ioctl_wait_idle = NULL,
683	.gui_idle = &r100_gui_idle,	683	.gui_idle = &r100_gui_idle,
684	.mc_wait_for_idle = &rs690_mc_wait_for_idle,	684	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
685	.gart = {	685	.gart = {
686	.tlb_flush = &rs400_gart_tlb_flush,	686	.tlb_flush = &rs400_gart_tlb_flush,
687	.set_page = &rs400_gart_set_page,	687	.set_page = &rs400_gart_set_page,
688	},	688	},
689	.ring = {	689	.ring = {
690	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	690	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
691	},	691	},
692	.irq = {	692	.irq = {
693	.set = &rs600_irq_set,	693	.set = &rs600_irq_set,
694	.process = &rs600_irq_process,	694	.process = &rs600_irq_process,
695	},	695	},
696	.display = {	696	.display = {
697	.get_vblank_counter = &rs600_get_vblank_counter,	697	.get_vblank_counter = &rs600_get_vblank_counter,
698	.bandwidth_update = &rs690_bandwidth_update,	698	.bandwidth_update = &rs690_bandwidth_update,
699	.wait_for_vblank = &avivo_wait_for_vblank,	699	.wait_for_vblank = &avivo_wait_for_vblank,
700	.set_backlight_level = &atombios_set_backlight_level,	700	.set_backlight_level = &atombios_set_backlight_level,
701	.get_backlight_level = &atombios_get_backlight_level,	701	.get_backlight_level = &atombios_get_backlight_level,
702	.hdmi_enable = &r600_hdmi_enable,	702	.hdmi_enable = &r600_hdmi_enable,
703	.hdmi_setmode = &r600_hdmi_setmode,	703	.hdmi_setmode = &r600_hdmi_setmode,
704	},	704	},
705	.copy = {	705	.copy = {
706	.blit = &r100_copy_blit,	706	.blit = &r100_copy_blit,
707	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	707	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708	.dma = &r200_copy_dma,	708	.dma = &r200_copy_dma,
709	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	709	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710	.copy = &r200_copy_dma,	710	.copy = &r200_copy_dma,
711	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	711	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
712	},	712	},
713	.surface = {	713	.surface = {
714	.set_reg = r100_set_surface_reg,	714	.set_reg = r100_set_surface_reg,
715	.clear_reg = r100_clear_surface_reg,	715	.clear_reg = r100_clear_surface_reg,
716	},	716	},
717	.hpd = {	717	.hpd = {
718	.init = &rs600_hpd_init,	718	.init = &rs600_hpd_init,
719	.fini = &rs600_hpd_fini,	719	.fini = &rs600_hpd_fini,
720	.sense = &rs600_hpd_sense,	720	.sense = &rs600_hpd_sense,
721	.set_polarity = &rs600_hpd_set_polarity,	721	.set_polarity = &rs600_hpd_set_polarity,
722	},	722	},
723	.pm = {	723	.pm = {
724	.misc = &rs600_pm_misc,	724	.misc = &rs600_pm_misc,
725	.prepare = &rs600_pm_prepare,	725	.prepare = &rs600_pm_prepare,
726	.finish = &rs600_pm_finish,	726	.finish = &rs600_pm_finish,
727	.init_profile = &r420_pm_init_profile,	727	.init_profile = &r420_pm_init_profile,
728	.get_dynpm_state = &r100_pm_get_dynpm_state,	728	.get_dynpm_state = &r100_pm_get_dynpm_state,
729	.get_engine_clock = &radeon_atom_get_engine_clock,	729	.get_engine_clock = &radeon_atom_get_engine_clock,
730	.set_engine_clock = &radeon_atom_set_engine_clock,	730	.set_engine_clock = &radeon_atom_set_engine_clock,
731	.get_memory_clock = &radeon_atom_get_memory_clock,	731	.get_memory_clock = &radeon_atom_get_memory_clock,
732	.set_memory_clock = &radeon_atom_set_memory_clock,	732	.set_memory_clock = &radeon_atom_set_memory_clock,
733	.get_pcie_lanes = NULL,	733	.get_pcie_lanes = NULL,
734	.set_pcie_lanes = NULL,	734	.set_pcie_lanes = NULL,
735	.set_clock_gating = &radeon_atom_set_clock_gating,	735	.set_clock_gating = &radeon_atom_set_clock_gating,
736	},	736	},
737	.pflip = {	737	.pflip = {
738	.pre_page_flip = &rs600_pre_page_flip,	738	.pre_page_flip = &rs600_pre_page_flip,
739	.page_flip = &rs600_page_flip,	739	.page_flip = &rs600_page_flip,
740	.post_page_flip = &rs600_post_page_flip,	740	.post_page_flip = &rs600_post_page_flip,
741	},	741	},
742	};	742	};
743		743
744	static struct radeon_asic rv515_asic = {	744	static struct radeon_asic rv515_asic = {
745	.init = &rv515_init,	745	.init = &rv515_init,
746	.fini = &rv515_fini,	746	.fini = &rv515_fini,
747	.suspend = &rv515_suspend,	747	.suspend = &rv515_suspend,
748	.resume = &rv515_resume,	748	.resume = &rv515_resume,
749	.vga_set_state = &r100_vga_set_state,	749	.vga_set_state = &r100_vga_set_state,
750	.asic_reset = &rs600_asic_reset,	750	.asic_reset = &rs600_asic_reset,
751	.ioctl_wait_idle = NULL,	751	.ioctl_wait_idle = NULL,
752	.gui_idle = &r100_gui_idle,	752	.gui_idle = &r100_gui_idle,
753	.mc_wait_for_idle = &rv515_mc_wait_for_idle,	753	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
754	.gart = {	754	.gart = {
755	.tlb_flush = &rv370_pcie_gart_tlb_flush,	755	.tlb_flush = &rv370_pcie_gart_tlb_flush,
756	.set_page = &rv370_pcie_gart_set_page,	756	.set_page = &rv370_pcie_gart_set_page,
757	},	757	},
758	.ring = {	758	.ring = {
759	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	759	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
760	},	760	},
761	.irq = {	761	.irq = {
762	.set = &rs600_irq_set,	762	.set = &rs600_irq_set,
763	.process = &rs600_irq_process,	763	.process = &rs600_irq_process,
764	},	764	},
765	.display = {	765	.display = {
766	.get_vblank_counter = &rs600_get_vblank_counter,	766	.get_vblank_counter = &rs600_get_vblank_counter,
767	.bandwidth_update = &rv515_bandwidth_update,	767	.bandwidth_update = &rv515_bandwidth_update,
768	.wait_for_vblank = &avivo_wait_for_vblank,	768	.wait_for_vblank = &avivo_wait_for_vblank,
769	.set_backlight_level = &atombios_set_backlight_level,	769	.set_backlight_level = &atombios_set_backlight_level,
770	.get_backlight_level = &atombios_get_backlight_level,	770	.get_backlight_level = &atombios_get_backlight_level,
771	},	771	},
772	.copy = {	772	.copy = {
773	.blit = &r100_copy_blit,	773	.blit = &r100_copy_blit,
774	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	774	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775	.dma = &r200_copy_dma,	775	.dma = &r200_copy_dma,
776	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	776	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777	.copy = &r100_copy_blit,	777	.copy = &r100_copy_blit,
778	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	778	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779	},	779	},
780	.surface = {	780	.surface = {
781	.set_reg = r100_set_surface_reg,	781	.set_reg = r100_set_surface_reg,
782	.clear_reg = r100_clear_surface_reg,	782	.clear_reg = r100_clear_surface_reg,
783	},	783	},
784	.hpd = {	784	.hpd = {
785	.init = &rs600_hpd_init,	785	.init = &rs600_hpd_init,
786	.fini = &rs600_hpd_fini,	786	.fini = &rs600_hpd_fini,
787	.sense = &rs600_hpd_sense,	787	.sense = &rs600_hpd_sense,
788	.set_polarity = &rs600_hpd_set_polarity,	788	.set_polarity = &rs600_hpd_set_polarity,
789	},	789	},
790	.pm = {	790	.pm = {
791	.misc = &rs600_pm_misc,	791	.misc = &rs600_pm_misc,
792	.prepare = &rs600_pm_prepare,	792	.prepare = &rs600_pm_prepare,
793	.finish = &rs600_pm_finish,	793	.finish = &rs600_pm_finish,
794	.init_profile = &r420_pm_init_profile,	794	.init_profile = &r420_pm_init_profile,
795	.get_dynpm_state = &r100_pm_get_dynpm_state,	795	.get_dynpm_state = &r100_pm_get_dynpm_state,
796	.get_engine_clock = &radeon_atom_get_engine_clock,	796	.get_engine_clock = &radeon_atom_get_engine_clock,
797	.set_engine_clock = &radeon_atom_set_engine_clock,	797	.set_engine_clock = &radeon_atom_set_engine_clock,
798	.get_memory_clock = &radeon_atom_get_memory_clock,	798	.get_memory_clock = &radeon_atom_get_memory_clock,
799	.set_memory_clock = &radeon_atom_set_memory_clock,	799	.set_memory_clock = &radeon_atom_set_memory_clock,
800	.get_pcie_lanes = &rv370_get_pcie_lanes,	800	.get_pcie_lanes = &rv370_get_pcie_lanes,
801	.set_pcie_lanes = &rv370_set_pcie_lanes,	801	.set_pcie_lanes = &rv370_set_pcie_lanes,
802	.set_clock_gating = &radeon_atom_set_clock_gating,	802	.set_clock_gating = &radeon_atom_set_clock_gating,
803	},	803	},
804	.pflip = {	804	.pflip = {
805	.pre_page_flip = &rs600_pre_page_flip,	805	.pre_page_flip = &rs600_pre_page_flip,
806	.page_flip = &rs600_page_flip,	806	.page_flip = &rs600_page_flip,
807	.post_page_flip = &rs600_post_page_flip,	807	.post_page_flip = &rs600_post_page_flip,
808	},	808	},
809	};	809	};
810		810
811	static struct radeon_asic r520_asic = {	811	static struct radeon_asic r520_asic = {
812	.init = &r520_init,	812	.init = &r520_init,
813	.fini = &rv515_fini,	813	.fini = &rv515_fini,
814	.suspend = &rv515_suspend,	814	.suspend = &rv515_suspend,
815	.resume = &r520_resume,	815	.resume = &r520_resume,
816	.vga_set_state = &r100_vga_set_state,	816	.vga_set_state = &r100_vga_set_state,
817	.asic_reset = &rs600_asic_reset,	817	.asic_reset = &rs600_asic_reset,
818	.ioctl_wait_idle = NULL,	818	.ioctl_wait_idle = NULL,
819	.gui_idle = &r100_gui_idle,	819	.gui_idle = &r100_gui_idle,
820	.mc_wait_for_idle = &r520_mc_wait_for_idle,	820	.mc_wait_for_idle = &r520_mc_wait_for_idle,
821	.gart = {	821	.gart = {
822	.tlb_flush = &rv370_pcie_gart_tlb_flush,	822	.tlb_flush = &rv370_pcie_gart_tlb_flush,
823	.set_page = &rv370_pcie_gart_set_page,	823	.set_page = &rv370_pcie_gart_set_page,
824	},	824	},
825	.ring = {	825	.ring = {
826	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	826	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
827	},	827	},
828	.irq = {	828	.irq = {
829	.set = &rs600_irq_set,	829	.set = &rs600_irq_set,
830	.process = &rs600_irq_process,	830	.process = &rs600_irq_process,
831	},	831	},
832	.display = {	832	.display = {
833	.bandwidth_update = &rv515_bandwidth_update,	833	.bandwidth_update = &rv515_bandwidth_update,
834	.get_vblank_counter = &rs600_get_vblank_counter,	834	.get_vblank_counter = &rs600_get_vblank_counter,
835	.wait_for_vblank = &avivo_wait_for_vblank,	835	.wait_for_vblank = &avivo_wait_for_vblank,
836	.set_backlight_level = &atombios_set_backlight_level,	836	.set_backlight_level = &atombios_set_backlight_level,
837	.get_backlight_level = &atombios_get_backlight_level,	837	.get_backlight_level = &atombios_get_backlight_level,
838	},	838	},
839	.copy = {	839	.copy = {
840	.blit = &r100_copy_blit,	840	.blit = &r100_copy_blit,
841	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	841	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842	.dma = &r200_copy_dma,	842	.dma = &r200_copy_dma,
843	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	843	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844	.copy = &r100_copy_blit,	844	.copy = &r100_copy_blit,
845	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	845	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
846	},	846	},
847	.surface = {	847	.surface = {
848	.set_reg = r100_set_surface_reg,	848	.set_reg = r100_set_surface_reg,
849	.clear_reg = r100_clear_surface_reg,	849	.clear_reg = r100_clear_surface_reg,
850	},	850	},
851	.hpd = {	851	.hpd = {
852	.init = &rs600_hpd_init,	852	.init = &rs600_hpd_init,
853	.fini = &rs600_hpd_fini,	853	.fini = &rs600_hpd_fini,
854	.sense = &rs600_hpd_sense,	854	.sense = &rs600_hpd_sense,
855	.set_polarity = &rs600_hpd_set_polarity,	855	.set_polarity = &rs600_hpd_set_polarity,
856	},	856	},
857	.pm = {	857	.pm = {
858	.misc = &rs600_pm_misc,	858	.misc = &rs600_pm_misc,
859	.prepare = &rs600_pm_prepare,	859	.prepare = &rs600_pm_prepare,
860	.finish = &rs600_pm_finish,	860	.finish = &rs600_pm_finish,
861	.init_profile = &r420_pm_init_profile,	861	.init_profile = &r420_pm_init_profile,
862	.get_dynpm_state = &r100_pm_get_dynpm_state,	862	.get_dynpm_state = &r100_pm_get_dynpm_state,
863	.get_engine_clock = &radeon_atom_get_engine_clock,	863	.get_engine_clock = &radeon_atom_get_engine_clock,
864	.set_engine_clock = &radeon_atom_set_engine_clock,	864	.set_engine_clock = &radeon_atom_set_engine_clock,
865	.get_memory_clock = &radeon_atom_get_memory_clock,	865	.get_memory_clock = &radeon_atom_get_memory_clock,
866	.set_memory_clock = &radeon_atom_set_memory_clock,	866	.set_memory_clock = &radeon_atom_set_memory_clock,
867	.get_pcie_lanes = &rv370_get_pcie_lanes,	867	.get_pcie_lanes = &rv370_get_pcie_lanes,
868	.set_pcie_lanes = &rv370_set_pcie_lanes,	868	.set_pcie_lanes = &rv370_set_pcie_lanes,
869	.set_clock_gating = &radeon_atom_set_clock_gating,	869	.set_clock_gating = &radeon_atom_set_clock_gating,
870	},	870	},
871	.pflip = {	871	.pflip = {
872	.pre_page_flip = &rs600_pre_page_flip,	872	.pre_page_flip = &rs600_pre_page_flip,
873	.page_flip = &rs600_page_flip,	873	.page_flip = &rs600_page_flip,
874	.post_page_flip = &rs600_post_page_flip,	874	.post_page_flip = &rs600_post_page_flip,
875	},	875	},
876	};	876	};
877		877
878	static struct radeon_asic_ring r600_gfx_ring = {	878	static struct radeon_asic_ring r600_gfx_ring = {
879	.ib_execute = &r600_ring_ib_execute,	879	.ib_execute = &r600_ring_ib_execute,
880	.emit_fence = &r600_fence_ring_emit,	880	.emit_fence = &r600_fence_ring_emit,
881	.emit_semaphore = &r600_semaphore_ring_emit,	881	.emit_semaphore = &r600_semaphore_ring_emit,
882	.cs_parse = &r600_cs_parse,	882	.cs_parse = &r600_cs_parse,
883	.ring_test = &r600_ring_test,	883	.ring_test = &r600_ring_test,
884	.ib_test = &r600_ib_test,	884	.ib_test = &r600_ib_test,
885	.is_lockup = &r600_gfx_is_lockup,	885	.is_lockup = &r600_gfx_is_lockup,
886	.get_rptr = &r600_gfx_get_rptr,	886	.get_rptr = &r600_gfx_get_rptr,
887	.get_wptr = &r600_gfx_get_wptr,	887	.get_wptr = &r600_gfx_get_wptr,
888	.set_wptr = &r600_gfx_set_wptr,	888	.set_wptr = &r600_gfx_set_wptr,
889	};	889	};
890		890
891	static struct radeon_asic_ring r600_dma_ring = {	891	static struct radeon_asic_ring r600_dma_ring = {
892	.ib_execute = &r600_dma_ring_ib_execute,	892	.ib_execute = &r600_dma_ring_ib_execute,
893	.emit_fence = &r600_dma_fence_ring_emit,	893	.emit_fence = &r600_dma_fence_ring_emit,
894	.emit_semaphore = &r600_dma_semaphore_ring_emit,	894	.emit_semaphore = &r600_dma_semaphore_ring_emit,
895	.cs_parse = &r600_dma_cs_parse,	895	.cs_parse = &r600_dma_cs_parse,
896	.ring_test = &r600_dma_ring_test,	896	.ring_test = &r600_dma_ring_test,
897	.ib_test = &r600_dma_ib_test,	897	.ib_test = &r600_dma_ib_test,
898	.is_lockup = &r600_dma_is_lockup,	898	.is_lockup = &r600_dma_is_lockup,
899	.get_rptr = &r600_dma_get_rptr,	899	.get_rptr = &r600_dma_get_rptr,
900	.get_wptr = &r600_dma_get_wptr,	900	.get_wptr = &r600_dma_get_wptr,
901	.set_wptr = &r600_dma_set_wptr,	901	.set_wptr = &r600_dma_set_wptr,
902	};	902	};
903		903
904	static struct radeon_asic r600_asic = {	904	static struct radeon_asic r600_asic = {
905	.init = &r600_init,	905	.init = &r600_init,
906	.fini = &r600_fini,	906	.fini = &r600_fini,
907	.suspend = &r600_suspend,	907	.suspend = &r600_suspend,
908	.resume = &r600_resume,	908	.resume = &r600_resume,
909	.vga_set_state = &r600_vga_set_state,	909	.vga_set_state = &r600_vga_set_state,
910	.asic_reset = &r600_asic_reset,	910	.asic_reset = &r600_asic_reset,
911	.ioctl_wait_idle = r600_ioctl_wait_idle,	911	.ioctl_wait_idle = r600_ioctl_wait_idle,
912	.gui_idle = &r600_gui_idle,	912	.gui_idle = &r600_gui_idle,
913	.mc_wait_for_idle = &r600_mc_wait_for_idle,	913	.mc_wait_for_idle = &r600_mc_wait_for_idle,
914	.get_xclk = &r600_get_xclk,	914	.get_xclk = &r600_get_xclk,
915	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	915	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
916	.gart = {	916	.gart = {
917	.tlb_flush = &r600_pcie_gart_tlb_flush,	917	.tlb_flush = &r600_pcie_gart_tlb_flush,
918	.set_page = &rs600_gart_set_page,	918	.set_page = &rs600_gart_set_page,
919	},	919	},
920	.ring = {	920	.ring = {
921	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	921	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	922	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
923	},	923	},
924	.irq = {	924	.irq = {
925	.set = &r600_irq_set,	925	.set = &r600_irq_set,
926	.process = &r600_irq_process,	926	.process = &r600_irq_process,
927	},	927	},
928	.display = {	928	.display = {
929	.bandwidth_update = &rv515_bandwidth_update,	929	.bandwidth_update = &rv515_bandwidth_update,
930	.get_vblank_counter = &rs600_get_vblank_counter,	930	.get_vblank_counter = &rs600_get_vblank_counter,
931	.wait_for_vblank = &avivo_wait_for_vblank,	931	.wait_for_vblank = &avivo_wait_for_vblank,
932	.set_backlight_level = &atombios_set_backlight_level,	932	.set_backlight_level = &atombios_set_backlight_level,
933	.get_backlight_level = &atombios_get_backlight_level,	933	.get_backlight_level = &atombios_get_backlight_level,
934	.hdmi_enable = &r600_hdmi_enable,	934	.hdmi_enable = &r600_hdmi_enable,
935	.hdmi_setmode = &r600_hdmi_setmode,	935	.hdmi_setmode = &r600_hdmi_setmode,
936	},	936	},
937	.copy = {	937	.copy = {
938	.blit = &r600_copy_cpdma,	938	.blit = &r600_copy_cpdma,
939	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	939	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
940	.dma = &r600_copy_dma,	940	.dma = &r600_copy_dma,
941	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	941	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
942	.copy = &r600_copy_cpdma,	942	.copy = &r600_copy_cpdma,
943	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	943	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
944	},	944	},
945	.surface = {	945	.surface = {
946	.set_reg = r600_set_surface_reg,	946	.set_reg = r600_set_surface_reg,
947	.clear_reg = r600_clear_surface_reg,	947	.clear_reg = r600_clear_surface_reg,
948	},	948	},
949	.hpd = {	949	.hpd = {
950	.init = &r600_hpd_init,	950	.init = &r600_hpd_init,
951	.fini = &r600_hpd_fini,	951	.fini = &r600_hpd_fini,
952	.sense = &r600_hpd_sense,	952	.sense = &r600_hpd_sense,
953	.set_polarity = &r600_hpd_set_polarity,	953	.set_polarity = &r600_hpd_set_polarity,
954	},	954	},
955	.pm = {	955	.pm = {
956	.misc = &r600_pm_misc,	956	.misc = &r600_pm_misc,
957	.prepare = &rs600_pm_prepare,	957	.prepare = &rs600_pm_prepare,
958	.finish = &rs600_pm_finish,	958	.finish = &rs600_pm_finish,
959	.init_profile = &r600_pm_init_profile,	959	.init_profile = &r600_pm_init_profile,
960	.get_dynpm_state = &r600_pm_get_dynpm_state,	960	.get_dynpm_state = &r600_pm_get_dynpm_state,
961	.get_engine_clock = &radeon_atom_get_engine_clock,	961	.get_engine_clock = &radeon_atom_get_engine_clock,
962	.set_engine_clock = &radeon_atom_set_engine_clock,	962	.set_engine_clock = &radeon_atom_set_engine_clock,
963	.get_memory_clock = &radeon_atom_get_memory_clock,	963	.get_memory_clock = &radeon_atom_get_memory_clock,
964	.set_memory_clock = &radeon_atom_set_memory_clock,	964	.set_memory_clock = &radeon_atom_set_memory_clock,
965	.get_pcie_lanes = &r600_get_pcie_lanes,	965	.get_pcie_lanes = &r600_get_pcie_lanes,
966	.set_pcie_lanes = &r600_set_pcie_lanes,	966	.set_pcie_lanes = &r600_set_pcie_lanes,
967	.set_clock_gating = NULL,	967	.set_clock_gating = NULL,
968	.get_temperature = &rv6xx_get_temp,	968	.get_temperature = &rv6xx_get_temp,
969	},	969	},
970	.pflip = {	970	.pflip = {
971	.pre_page_flip = &rs600_pre_page_flip,	971	.pre_page_flip = &rs600_pre_page_flip,
972	.page_flip = &rs600_page_flip,	972	.page_flip = &rs600_page_flip,
973	.post_page_flip = &rs600_post_page_flip,	973	.post_page_flip = &rs600_post_page_flip,
974	},	974	},
975	};	975	};
976		976
977	static struct radeon_asic rv6xx_asic = {	977	static struct radeon_asic rv6xx_asic = {
978	.init = &r600_init,	978	.init = &r600_init,
979	.fini = &r600_fini,	979	.fini = &r600_fini,
980	.suspend = &r600_suspend,	980	.suspend = &r600_suspend,
981	.resume = &r600_resume,	981	.resume = &r600_resume,
982	.vga_set_state = &r600_vga_set_state,	982	.vga_set_state = &r600_vga_set_state,
983	.asic_reset = &r600_asic_reset,	983	.asic_reset = &r600_asic_reset,
984	.ioctl_wait_idle = r600_ioctl_wait_idle,	984	.ioctl_wait_idle = r600_ioctl_wait_idle,
985	.gui_idle = &r600_gui_idle,	985	.gui_idle = &r600_gui_idle,
986	.mc_wait_for_idle = &r600_mc_wait_for_idle,	986	.mc_wait_for_idle = &r600_mc_wait_for_idle,
987	.get_xclk = &r600_get_xclk,	987	.get_xclk = &r600_get_xclk,
988	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	988	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
989	.gart = {	989	.gart = {
990	.tlb_flush = &r600_pcie_gart_tlb_flush,	990	.tlb_flush = &r600_pcie_gart_tlb_flush,
991	.set_page = &rs600_gart_set_page,	991	.set_page = &rs600_gart_set_page,
992	},	992	},
993	.ring = {	993	.ring = {
994	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	994	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	995	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
996	},	996	},
997	.irq = {	997	.irq = {
998	.set = &r600_irq_set,	998	.set = &r600_irq_set,
999	.process = &r600_irq_process,	999	.process = &r600_irq_process,
1000	},	1000	},
1001	.display = {	1001	.display = {
1002	.bandwidth_update = &rv515_bandwidth_update,	1002	.bandwidth_update = &rv515_bandwidth_update,
1003	.get_vblank_counter = &rs600_get_vblank_counter,	1003	.get_vblank_counter = &rs600_get_vblank_counter,
1004	.wait_for_vblank = &avivo_wait_for_vblank,	1004	.wait_for_vblank = &avivo_wait_for_vblank,
1005	.set_backlight_level = &atombios_set_backlight_level,	1005	.set_backlight_level = &atombios_set_backlight_level,
1006	.get_backlight_level = &atombios_get_backlight_level,	1006	.get_backlight_level = &atombios_get_backlight_level,
1007	.hdmi_enable = &r600_hdmi_enable,	1007	.hdmi_enable = &r600_hdmi_enable,
1008	.hdmi_setmode = &r600_hdmi_setmode,	1008	.hdmi_setmode = &r600_hdmi_setmode,
1009	},	1009	},
1010	.copy = {	1010	.copy = {
1011	.blit = &r600_copy_cpdma,	1011	.blit = &r600_copy_cpdma,
1012	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1012	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013	.dma = &r600_copy_dma,	1013	.dma = &r600_copy_dma,
1014	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1014	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1015	.copy = &r600_copy_cpdma,	1015	.copy = &r600_copy_cpdma,
1016	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1016	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1017	},	1017	},
1018	.surface = {	1018	.surface = {
1019	.set_reg = r600_set_surface_reg,	1019	.set_reg = r600_set_surface_reg,
1020	.clear_reg = r600_clear_surface_reg,	1020	.clear_reg = r600_clear_surface_reg,
1021	},	1021	},
1022	.hpd = {	1022	.hpd = {
1023	.init = &r600_hpd_init,	1023	.init = &r600_hpd_init,
1024	.fini = &r600_hpd_fini,	1024	.fini = &r600_hpd_fini,
1025	.sense = &r600_hpd_sense,	1025	.sense = &r600_hpd_sense,
1026	.set_polarity = &r600_hpd_set_polarity,	1026	.set_polarity = &r600_hpd_set_polarity,
1027	},	1027	},
1028	.pm = {	1028	.pm = {
1029	.misc = &r600_pm_misc,	1029	.misc = &r600_pm_misc,
1030	.prepare = &rs600_pm_prepare,	1030	.prepare = &rs600_pm_prepare,
1031	.finish = &rs600_pm_finish,	1031	.finish = &rs600_pm_finish,
1032	.init_profile = &r600_pm_init_profile,	1032	.init_profile = &r600_pm_init_profile,
1033	.get_dynpm_state = &r600_pm_get_dynpm_state,	1033	.get_dynpm_state = &r600_pm_get_dynpm_state,
1034	.get_engine_clock = &radeon_atom_get_engine_clock,	1034	.get_engine_clock = &radeon_atom_get_engine_clock,
1035	.set_engine_clock = &radeon_atom_set_engine_clock,	1035	.set_engine_clock = &radeon_atom_set_engine_clock,
1036	.get_memory_clock = &radeon_atom_get_memory_clock,	1036	.get_memory_clock = &radeon_atom_get_memory_clock,
1037	.set_memory_clock = &radeon_atom_set_memory_clock,	1037	.set_memory_clock = &radeon_atom_set_memory_clock,
1038	.get_pcie_lanes = &r600_get_pcie_lanes,	1038	.get_pcie_lanes = &r600_get_pcie_lanes,
1039	.set_pcie_lanes = &r600_set_pcie_lanes,	1039	.set_pcie_lanes = &r600_set_pcie_lanes,
1040	.set_clock_gating = NULL,	1040	.set_clock_gating = NULL,
1041	.get_temperature = &rv6xx_get_temp,	1041	.get_temperature = &rv6xx_get_temp,
1042	.set_uvd_clocks = &r600_set_uvd_clocks,	1042	.set_uvd_clocks = &r600_set_uvd_clocks,
1043	},	1043	},
1044	.dpm = {	1044	.dpm = {
1045	.init = &rv6xx_dpm_init,	1045	.init = &rv6xx_dpm_init,
1046	.setup_asic = &rv6xx_setup_asic,	1046	.setup_asic = &rv6xx_setup_asic,
1047	.enable = &rv6xx_dpm_enable,	1047	.enable = &rv6xx_dpm_enable,
1048	.late_enable = &r600_dpm_late_enable,	1048	.late_enable = &r600_dpm_late_enable,
1049	.disable = &rv6xx_dpm_disable,	1049	.disable = &rv6xx_dpm_disable,
1050	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1050	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1051	.set_power_state = &rv6xx_dpm_set_power_state,	1051	.set_power_state = &rv6xx_dpm_set_power_state,
1052	.post_set_power_state = &r600_dpm_post_set_power_state,	1052	.post_set_power_state = &r600_dpm_post_set_power_state,
1053	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,	1053	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1054	.fini = &rv6xx_dpm_fini,	1054	.fini = &rv6xx_dpm_fini,
1055	.get_sclk = &rv6xx_dpm_get_sclk,	1055	.get_sclk = &rv6xx_dpm_get_sclk,
1056	.get_mclk = &rv6xx_dpm_get_mclk,	1056	.get_mclk = &rv6xx_dpm_get_mclk,
1057	.print_power_state = &rv6xx_dpm_print_power_state,	1057	.print_power_state = &rv6xx_dpm_print_power_state,
1058	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,	1058	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1059	.force_performance_level = &rv6xx_dpm_force_performance_level,	1059	.force_performance_level = &rv6xx_dpm_force_performance_level,
1060	},	1060	},
1061	.pflip = {	1061	.pflip = {
1062	.pre_page_flip = &rs600_pre_page_flip,	1062	.pre_page_flip = &rs600_pre_page_flip,
1063	.page_flip = &rs600_page_flip,	1063	.page_flip = &rs600_page_flip,
1064	.post_page_flip = &rs600_post_page_flip,	1064	.post_page_flip = &rs600_post_page_flip,
1065	},	1065	},
1066	};	1066	};
1067		1067
1068	static struct radeon_asic rs780_asic = {	1068	static struct radeon_asic rs780_asic = {
1069	.init = &r600_init,	1069	.init = &r600_init,
1070	.fini = &r600_fini,	1070	.fini = &r600_fini,
1071	.suspend = &r600_suspend,	1071	.suspend = &r600_suspend,
1072	.resume = &r600_resume,	1072	.resume = &r600_resume,
1073	.vga_set_state = &r600_vga_set_state,	1073	.vga_set_state = &r600_vga_set_state,
1074	.asic_reset = &r600_asic_reset,	1074	.asic_reset = &r600_asic_reset,
1075	.ioctl_wait_idle = r600_ioctl_wait_idle,	1075	.ioctl_wait_idle = r600_ioctl_wait_idle,
1076	.gui_idle = &r600_gui_idle,	1076	.gui_idle = &r600_gui_idle,
1077	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1077	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1078	.get_xclk = &r600_get_xclk,	1078	.get_xclk = &r600_get_xclk,
1079	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1079	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1080	.gart = {	1080	.gart = {
1081	.tlb_flush = &r600_pcie_gart_tlb_flush,	1081	.tlb_flush = &r600_pcie_gart_tlb_flush,
1082	.set_page = &rs600_gart_set_page,	1082	.set_page = &rs600_gart_set_page,
1083	},	1083	},
1084	.ring = {	1084	.ring = {
1085	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1085	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1086	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1086	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1087	},	1087	},
1088	.irq = {	1088	.irq = {
1089	.set = &r600_irq_set,	1089	.set = &r600_irq_set,
1090	.process = &r600_irq_process,	1090	.process = &r600_irq_process,
1091	},	1091	},
1092	.display = {	1092	.display = {
1093	.bandwidth_update = &rs690_bandwidth_update,	1093	.bandwidth_update = &rs690_bandwidth_update,
1094	.get_vblank_counter = &rs600_get_vblank_counter,	1094	.get_vblank_counter = &rs600_get_vblank_counter,
1095	.wait_for_vblank = &avivo_wait_for_vblank,	1095	.wait_for_vblank = &avivo_wait_for_vblank,
1096	.set_backlight_level = &atombios_set_backlight_level,	1096	.set_backlight_level = &atombios_set_backlight_level,
1097	.get_backlight_level = &atombios_get_backlight_level,	1097	.get_backlight_level = &atombios_get_backlight_level,
1098	.hdmi_enable = &r600_hdmi_enable,	1098	.hdmi_enable = &r600_hdmi_enable,
1099	.hdmi_setmode = &r600_hdmi_setmode,	1099	.hdmi_setmode = &r600_hdmi_setmode,
1100	},	1100	},
1101	.copy = {	1101	.copy = {
1102	.blit = &r600_copy_cpdma,	1102	.blit = &r600_copy_cpdma,
1103	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1103	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1104	.dma = &r600_copy_dma,	1104	.dma = &r600_copy_dma,
1105	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1105	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1106	.copy = &r600_copy_cpdma,	1106	.copy = &r600_copy_cpdma,
1107	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1107	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1108	},	1108	},
1109	.surface = {	1109	.surface = {
1110	.set_reg = r600_set_surface_reg,	1110	.set_reg = r600_set_surface_reg,
1111	.clear_reg = r600_clear_surface_reg,	1111	.clear_reg = r600_clear_surface_reg,
1112	},	1112	},
1113	.hpd = {	1113	.hpd = {
1114	.init = &r600_hpd_init,	1114	.init = &r600_hpd_init,
1115	.fini = &r600_hpd_fini,	1115	.fini = &r600_hpd_fini,
1116	.sense = &r600_hpd_sense,	1116	.sense = &r600_hpd_sense,
1117	.set_polarity = &r600_hpd_set_polarity,	1117	.set_polarity = &r600_hpd_set_polarity,
1118	},	1118	},
1119	.pm = {	1119	.pm = {
1120	.misc = &r600_pm_misc,	1120	.misc = &r600_pm_misc,
1121	.prepare = &rs600_pm_prepare,	1121	.prepare = &rs600_pm_prepare,
1122	.finish = &rs600_pm_finish,	1122	.finish = &rs600_pm_finish,
1123	.init_profile = &rs780_pm_init_profile,	1123	.init_profile = &rs780_pm_init_profile,
1124	.get_dynpm_state = &r600_pm_get_dynpm_state,	1124	.get_dynpm_state = &r600_pm_get_dynpm_state,
1125	.get_engine_clock = &radeon_atom_get_engine_clock,	1125	.get_engine_clock = &radeon_atom_get_engine_clock,
1126	.set_engine_clock = &radeon_atom_set_engine_clock,	1126	.set_engine_clock = &radeon_atom_set_engine_clock,
1127	.get_memory_clock = NULL,	1127	.get_memory_clock = NULL,
1128	.set_memory_clock = NULL,	1128	.set_memory_clock = NULL,
1129	.get_pcie_lanes = NULL,	1129	.get_pcie_lanes = NULL,
1130	.set_pcie_lanes = NULL,	1130	.set_pcie_lanes = NULL,
1131	.set_clock_gating = NULL,	1131	.set_clock_gating = NULL,
1132	.get_temperature = &rv6xx_get_temp,	1132	.get_temperature = &rv6xx_get_temp,
1133	.set_uvd_clocks = &r600_set_uvd_clocks,	1133	.set_uvd_clocks = &r600_set_uvd_clocks,
1134	},	1134	},
1135	.dpm = {	1135	.dpm = {
1136	.init = &rs780_dpm_init,	1136	.init = &rs780_dpm_init,
1137	.setup_asic = &rs780_dpm_setup_asic,	1137	.setup_asic = &rs780_dpm_setup_asic,
1138	.enable = &rs780_dpm_enable,	1138	.enable = &rs780_dpm_enable,
1139	.late_enable = &r600_dpm_late_enable,	1139	.late_enable = &r600_dpm_late_enable,
1140	.disable = &rs780_dpm_disable,	1140	.disable = &rs780_dpm_disable,
1141	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1141	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1142	.set_power_state = &rs780_dpm_set_power_state,	1142	.set_power_state = &rs780_dpm_set_power_state,
1143	.post_set_power_state = &r600_dpm_post_set_power_state,	1143	.post_set_power_state = &r600_dpm_post_set_power_state,
1144	.display_configuration_changed = &rs780_dpm_display_configuration_changed,	1144	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
1145	.fini = &rs780_dpm_fini,	1145	.fini = &rs780_dpm_fini,
1146	.get_sclk = &rs780_dpm_get_sclk,	1146	.get_sclk = &rs780_dpm_get_sclk,
1147	.get_mclk = &rs780_dpm_get_mclk,	1147	.get_mclk = &rs780_dpm_get_mclk,
1148	.print_power_state = &rs780_dpm_print_power_state,	1148	.print_power_state = &rs780_dpm_print_power_state,
1149	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,	1149	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1150	.force_performance_level = &rs780_dpm_force_performance_level,	1150	.force_performance_level = &rs780_dpm_force_performance_level,
1151	},	1151	},
1152	.pflip = {	1152	.pflip = {
1153	.pre_page_flip = &rs600_pre_page_flip,	1153	.pre_page_flip = &rs600_pre_page_flip,
1154	.page_flip = &rs600_page_flip,	1154	.page_flip = &rs600_page_flip,
1155	.post_page_flip = &rs600_post_page_flip,	1155	.post_page_flip = &rs600_post_page_flip,
1156	},	1156	},
1157	};	1157	};
1158		1158
1159	static struct radeon_asic_ring rv770_uvd_ring = {	1159	static struct radeon_asic_ring rv770_uvd_ring = {
1160	.ib_execute = &uvd_v1_0_ib_execute,	1160	.ib_execute = &uvd_v1_0_ib_execute,
1161	.emit_fence = &uvd_v2_2_fence_emit,	1161	.emit_fence = &uvd_v2_2_fence_emit,
1162	.emit_semaphore = &uvd_v1_0_semaphore_emit,	1162	.emit_semaphore = &uvd_v1_0_semaphore_emit,
1163	.cs_parse = &radeon_uvd_cs_parse,	1163	.cs_parse = &radeon_uvd_cs_parse,
1164	.ring_test = &uvd_v1_0_ring_test,	1164	.ring_test = &uvd_v1_0_ring_test,
1165	.ib_test = &uvd_v1_0_ib_test,	1165	.ib_test = &uvd_v1_0_ib_test,
1166	.is_lockup = &radeon_ring_test_lockup,	1166	.is_lockup = &radeon_ring_test_lockup,
1167	.get_rptr = &uvd_v1_0_get_rptr,	1167	.get_rptr = &uvd_v1_0_get_rptr,
1168	.get_wptr = &uvd_v1_0_get_wptr,	1168	.get_wptr = &uvd_v1_0_get_wptr,
1169	.set_wptr = &uvd_v1_0_set_wptr,	1169	.set_wptr = &uvd_v1_0_set_wptr,
1170	};	1170	};
1171		1171
1172	static struct radeon_asic rv770_asic = {	1172	static struct radeon_asic rv770_asic = {
1173	.init = &rv770_init,	1173	.init = &rv770_init,
1174	.fini = &rv770_fini,	1174	.fini = &rv770_fini,
1175	.suspend = &rv770_suspend,	1175	.suspend = &rv770_suspend,
1176	.resume = &rv770_resume,	1176	.resume = &rv770_resume,
1177	.asic_reset = &r600_asic_reset,	1177	.asic_reset = &r600_asic_reset,
1178	.vga_set_state = &r600_vga_set_state,	1178	.vga_set_state = &r600_vga_set_state,
1179	.ioctl_wait_idle = r600_ioctl_wait_idle,	1179	.ioctl_wait_idle = r600_ioctl_wait_idle,
1180	.gui_idle = &r600_gui_idle,	1180	.gui_idle = &r600_gui_idle,
1181	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1181	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1182	.get_xclk = &rv770_get_xclk,	1182	.get_xclk = &rv770_get_xclk,
1183	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1183	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1184	.gart = {	1184	.gart = {
1185	.tlb_flush = &r600_pcie_gart_tlb_flush,	1185	.tlb_flush = &r600_pcie_gart_tlb_flush,
1186	.set_page = &rs600_gart_set_page,	1186	.set_page = &rs600_gart_set_page,
1187	},	1187	},
1188	.ring = {	1188	.ring = {
1189	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1189	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1190	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1190	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1191	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1191	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1192	},	1192	},
1193	.irq = {	1193	.irq = {
1194	.set = &r600_irq_set,	1194	.set = &r600_irq_set,
1195	.process = &r600_irq_process,	1195	.process = &r600_irq_process,
1196	},	1196	},
1197	.display = {	1197	.display = {
1198	.bandwidth_update = &rv515_bandwidth_update,	1198	.bandwidth_update = &rv515_bandwidth_update,
1199	.get_vblank_counter = &rs600_get_vblank_counter,	1199	.get_vblank_counter = &rs600_get_vblank_counter,
1200	.wait_for_vblank = &avivo_wait_for_vblank,	1200	.wait_for_vblank = &avivo_wait_for_vblank,
1201	.set_backlight_level = &atombios_set_backlight_level,	1201	.set_backlight_level = &atombios_set_backlight_level,
1202	.get_backlight_level = &atombios_get_backlight_level,	1202	.get_backlight_level = &atombios_get_backlight_level,
1203	.hdmi_enable = &r600_hdmi_enable,	1203	.hdmi_enable = &r600_hdmi_enable,
1204	.hdmi_setmode = &r600_hdmi_setmode,	1204	.hdmi_setmode = &r600_hdmi_setmode,
1205	},	1205	},
1206	.copy = {	1206	.copy = {
1207	.blit = &r600_copy_cpdma,	1207	.blit = &r600_copy_cpdma,
1208	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1208	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1209	.dma = &rv770_copy_dma,	1209	.dma = &rv770_copy_dma,
1210	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1210	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1211	.copy = &rv770_copy_dma,	1211	.copy = &rv770_copy_dma,
1212	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1212	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1213	},	1213	},
1214	.surface = {	1214	.surface = {
1215	.set_reg = r600_set_surface_reg,	1215	.set_reg = r600_set_surface_reg,
1216	.clear_reg = r600_clear_surface_reg,	1216	.clear_reg = r600_clear_surface_reg,
1217	},	1217	},
1218	.hpd = {	1218	.hpd = {
1219	.init = &r600_hpd_init,	1219	.init = &r600_hpd_init,
1220	.fini = &r600_hpd_fini,	1220	.fini = &r600_hpd_fini,
1221	.sense = &r600_hpd_sense,	1221	.sense = &r600_hpd_sense,
1222	.set_polarity = &r600_hpd_set_polarity,	1222	.set_polarity = &r600_hpd_set_polarity,
1223	},	1223	},
1224	.pm = {	1224	.pm = {
1225	.misc = &rv770_pm_misc,	1225	.misc = &rv770_pm_misc,
1226	.prepare = &rs600_pm_prepare,	1226	.prepare = &rs600_pm_prepare,
1227	.finish = &rs600_pm_finish,	1227	.finish = &rs600_pm_finish,
1228	.init_profile = &r600_pm_init_profile,	1228	.init_profile = &r600_pm_init_profile,
1229	.get_dynpm_state = &r600_pm_get_dynpm_state,	1229	.get_dynpm_state = &r600_pm_get_dynpm_state,
1230	.get_engine_clock = &radeon_atom_get_engine_clock,	1230	.get_engine_clock = &radeon_atom_get_engine_clock,
1231	.set_engine_clock = &radeon_atom_set_engine_clock,	1231	.set_engine_clock = &radeon_atom_set_engine_clock,
1232	.get_memory_clock = &radeon_atom_get_memory_clock,	1232	.get_memory_clock = &radeon_atom_get_memory_clock,
1233	.set_memory_clock = &radeon_atom_set_memory_clock,	1233	.set_memory_clock = &radeon_atom_set_memory_clock,
1234	.get_pcie_lanes = &r600_get_pcie_lanes,	1234	.get_pcie_lanes = &r600_get_pcie_lanes,
1235	.set_pcie_lanes = &r600_set_pcie_lanes,	1235	.set_pcie_lanes = &r600_set_pcie_lanes,
1236	.set_clock_gating = &radeon_atom_set_clock_gating,	1236	.set_clock_gating = &radeon_atom_set_clock_gating,
1237	.set_uvd_clocks = &rv770_set_uvd_clocks,	1237	.set_uvd_clocks = &rv770_set_uvd_clocks,
1238	.get_temperature = &rv770_get_temp,	1238	.get_temperature = &rv770_get_temp,
1239	},	1239	},
1240	.dpm = {	1240	.dpm = {
1241	.init = &rv770_dpm_init,	1241	.init = &rv770_dpm_init,
1242	.setup_asic = &rv770_dpm_setup_asic,	1242	.setup_asic = &rv770_dpm_setup_asic,
1243	.enable = &rv770_dpm_enable,	1243	.enable = &rv770_dpm_enable,
1244	.late_enable = &rv770_dpm_late_enable,	1244	.late_enable = &rv770_dpm_late_enable,
1245	.disable = &rv770_dpm_disable,	1245	.disable = &rv770_dpm_disable,
1246	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1246	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1247	.set_power_state = &rv770_dpm_set_power_state,	1247	.set_power_state = &rv770_dpm_set_power_state,
1248	.post_set_power_state = &r600_dpm_post_set_power_state,	1248	.post_set_power_state = &r600_dpm_post_set_power_state,
1249	.display_configuration_changed = &rv770_dpm_display_configuration_changed,	1249	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
1250	.fini = &rv770_dpm_fini,	1250	.fini = &rv770_dpm_fini,
1251	.get_sclk = &rv770_dpm_get_sclk,	1251	.get_sclk = &rv770_dpm_get_sclk,
1252	.get_mclk = &rv770_dpm_get_mclk,	1252	.get_mclk = &rv770_dpm_get_mclk,
1253	.print_power_state = &rv770_dpm_print_power_state,	1253	.print_power_state = &rv770_dpm_print_power_state,
1254	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,	1254	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1255	.force_performance_level = &rv770_dpm_force_performance_level,	1255	.force_performance_level = &rv770_dpm_force_performance_level,
1256	.vblank_too_short = &rv770_dpm_vblank_too_short,	1256	.vblank_too_short = &rv770_dpm_vblank_too_short,
1257	},	1257	},
1258	.pflip = {	1258	.pflip = {
1259	.pre_page_flip = &rs600_pre_page_flip,	1259	.pre_page_flip = &rs600_pre_page_flip,
1260	.page_flip = &rv770_page_flip,	1260	.page_flip = &rv770_page_flip,
1261	.post_page_flip = &rs600_post_page_flip,	1261	.post_page_flip = &rs600_post_page_flip,
1262	},	1262	},
1263	};	1263	};
1264		1264
1265	static struct radeon_asic_ring evergreen_gfx_ring = {	1265	static struct radeon_asic_ring evergreen_gfx_ring = {
1266	.ib_execute = &evergreen_ring_ib_execute,	1266	.ib_execute = &evergreen_ring_ib_execute,
1267	.emit_fence = &r600_fence_ring_emit,	1267	.emit_fence = &r600_fence_ring_emit,
1268	.emit_semaphore = &r600_semaphore_ring_emit,	1268	.emit_semaphore = &r600_semaphore_ring_emit,
1269	.cs_parse = &evergreen_cs_parse,	1269	.cs_parse = &evergreen_cs_parse,
1270	.ring_test = &r600_ring_test,	1270	.ring_test = &r600_ring_test,
1271	.ib_test = &r600_ib_test,	1271	.ib_test = &r600_ib_test,
1272	.is_lockup = &evergreen_gfx_is_lockup,	1272	.is_lockup = &evergreen_gfx_is_lockup,
1273	.get_rptr = &r600_gfx_get_rptr,	1273	.get_rptr = &r600_gfx_get_rptr,
1274	.get_wptr = &r600_gfx_get_wptr,	1274	.get_wptr = &r600_gfx_get_wptr,
1275	.set_wptr = &r600_gfx_set_wptr,	1275	.set_wptr = &r600_gfx_set_wptr,
1276	};	1276	};
1277		1277
1278	static struct radeon_asic_ring evergreen_dma_ring = {	1278	static struct radeon_asic_ring evergreen_dma_ring = {
1279	.ib_execute = &evergreen_dma_ring_ib_execute,	1279	.ib_execute = &evergreen_dma_ring_ib_execute,
1280	.emit_fence = &evergreen_dma_fence_ring_emit,	1280	.emit_fence = &evergreen_dma_fence_ring_emit,
1281	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1281	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1282	.cs_parse = &evergreen_dma_cs_parse,	1282	.cs_parse = &evergreen_dma_cs_parse,
1283	.ring_test = &r600_dma_ring_test,	1283	.ring_test = &r600_dma_ring_test,
1284	.ib_test = &r600_dma_ib_test,	1284	.ib_test = &r600_dma_ib_test,
1285	.is_lockup = &evergreen_dma_is_lockup,	1285	.is_lockup = &evergreen_dma_is_lockup,
1286	.get_rptr = &r600_dma_get_rptr,	1286	.get_rptr = &r600_dma_get_rptr,
1287	.get_wptr = &r600_dma_get_wptr,	1287	.get_wptr = &r600_dma_get_wptr,
1288	.set_wptr = &r600_dma_set_wptr,	1288	.set_wptr = &r600_dma_set_wptr,
1289	};	1289	};
1290		1290
1291	static struct radeon_asic evergreen_asic = {	1291	static struct radeon_asic evergreen_asic = {
1292	.init = &evergreen_init,	1292	.init = &evergreen_init,
1293	.fini = &evergreen_fini,	1293	.fini = &evergreen_fini,
1294	.suspend = &evergreen_suspend,	1294	.suspend = &evergreen_suspend,
1295	.resume = &evergreen_resume,	1295	.resume = &evergreen_resume,
1296	.asic_reset = &evergreen_asic_reset,	1296	.asic_reset = &evergreen_asic_reset,
1297	.vga_set_state = &r600_vga_set_state,	1297	.vga_set_state = &r600_vga_set_state,
1298	.ioctl_wait_idle = r600_ioctl_wait_idle,	1298	.ioctl_wait_idle = r600_ioctl_wait_idle,
1299	.gui_idle = &r600_gui_idle,	1299	.gui_idle = &r600_gui_idle,
1300	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1300	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1301	.get_xclk = &rv770_get_xclk,	1301	.get_xclk = &rv770_get_xclk,
1302	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1302	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1303	.gart = {	1303	.gart = {
1304	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1304	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1305	.set_page = &rs600_gart_set_page,	1305	.set_page = &rs600_gart_set_page,
1306	},	1306	},
1307	.ring = {	1307	.ring = {
1308	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1308	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1309	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1309	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1310	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1310	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1311	},	1311	},
1312	.irq = {	1312	.irq = {
1313	.set = &evergreen_irq_set,	1313	.set = &evergreen_irq_set,
1314	.process = &evergreen_irq_process,	1314	.process = &evergreen_irq_process,
1315	},	1315	},
1316	.display = {	1316	.display = {
1317	.bandwidth_update = &evergreen_bandwidth_update,	1317	.bandwidth_update = &evergreen_bandwidth_update,
1318	.get_vblank_counter = &evergreen_get_vblank_counter,	1318	.get_vblank_counter = &evergreen_get_vblank_counter,
1319	.wait_for_vblank = &dce4_wait_for_vblank,	1319	.wait_for_vblank = &dce4_wait_for_vblank,
1320	.set_backlight_level = &atombios_set_backlight_level,	1320	.set_backlight_level = &atombios_set_backlight_level,
1321	.get_backlight_level = &atombios_get_backlight_level,	1321	.get_backlight_level = &atombios_get_backlight_level,
1322	.hdmi_enable = &evergreen_hdmi_enable,	1322	.hdmi_enable = &evergreen_hdmi_enable,
1323	.hdmi_setmode = &evergreen_hdmi_setmode,	1323	.hdmi_setmode = &evergreen_hdmi_setmode,
1324	},	1324	},
1325	.copy = {	1325	.copy = {
1326	.blit = &r600_copy_cpdma,	1326	.blit = &r600_copy_cpdma,
1327	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1327	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1328	.dma = &evergreen_copy_dma,	1328	.dma = &evergreen_copy_dma,
1329	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1329	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1330	.copy = &evergreen_copy_dma,	1330	.copy = &evergreen_copy_dma,
1331	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1331	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1332	},	1332	},
1333	.surface = {	1333	.surface = {
1334	.set_reg = r600_set_surface_reg,	1334	.set_reg = r600_set_surface_reg,
1335	.clear_reg = r600_clear_surface_reg,	1335	.clear_reg = r600_clear_surface_reg,
1336	},	1336	},
1337	.hpd = {	1337	.hpd = {
1338	.init = &evergreen_hpd_init,	1338	.init = &evergreen_hpd_init,
1339	.fini = &evergreen_hpd_fini,	1339	.fini = &evergreen_hpd_fini,
1340	.sense = &evergreen_hpd_sense,	1340	.sense = &evergreen_hpd_sense,
1341	.set_polarity = &evergreen_hpd_set_polarity,	1341	.set_polarity = &evergreen_hpd_set_polarity,
1342	},	1342	},
1343	.pm = {	1343	.pm = {
1344	.misc = &evergreen_pm_misc,	1344	.misc = &evergreen_pm_misc,
1345	.prepare = &evergreen_pm_prepare,	1345	.prepare = &evergreen_pm_prepare,
1346	.finish = &evergreen_pm_finish,	1346	.finish = &evergreen_pm_finish,
1347	.init_profile = &r600_pm_init_profile,	1347	.init_profile = &r600_pm_init_profile,
1348	.get_dynpm_state = &r600_pm_get_dynpm_state,	1348	.get_dynpm_state = &r600_pm_get_dynpm_state,
1349	.get_engine_clock = &radeon_atom_get_engine_clock,	1349	.get_engine_clock = &radeon_atom_get_engine_clock,
1350	.set_engine_clock = &radeon_atom_set_engine_clock,	1350	.set_engine_clock = &radeon_atom_set_engine_clock,
1351	.get_memory_clock = &radeon_atom_get_memory_clock,	1351	.get_memory_clock = &radeon_atom_get_memory_clock,
1352	.set_memory_clock = &radeon_atom_set_memory_clock,	1352	.set_memory_clock = &radeon_atom_set_memory_clock,
1353	.get_pcie_lanes = &r600_get_pcie_lanes,	1353	.get_pcie_lanes = &r600_get_pcie_lanes,
1354	.set_pcie_lanes = &r600_set_pcie_lanes,	1354	.set_pcie_lanes = &r600_set_pcie_lanes,
1355	.set_clock_gating = NULL,	1355	.set_clock_gating = NULL,
1356	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1356	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1357	.get_temperature = &evergreen_get_temp,	1357	.get_temperature = &evergreen_get_temp,
1358	},	1358	},
1359	.dpm = {	1359	.dpm = {
1360	.init = &cypress_dpm_init,	1360	.init = &cypress_dpm_init,
1361	.setup_asic = &cypress_dpm_setup_asic,	1361	.setup_asic = &cypress_dpm_setup_asic,
1362	.enable = &cypress_dpm_enable,	1362	.enable = &cypress_dpm_enable,
1363	.late_enable = &rv770_dpm_late_enable,	1363	.late_enable = &rv770_dpm_late_enable,
1364	.disable = &cypress_dpm_disable,	1364	.disable = &cypress_dpm_disable,
1365	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1365	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1366	.set_power_state = &cypress_dpm_set_power_state,	1366	.set_power_state = &cypress_dpm_set_power_state,
1367	.post_set_power_state = &r600_dpm_post_set_power_state,	1367	.post_set_power_state = &r600_dpm_post_set_power_state,
1368	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1368	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1369	.fini = &cypress_dpm_fini,	1369	.fini = &cypress_dpm_fini,
1370	.get_sclk = &rv770_dpm_get_sclk,	1370	.get_sclk = &rv770_dpm_get_sclk,
1371	.get_mclk = &rv770_dpm_get_mclk,	1371	.get_mclk = &rv770_dpm_get_mclk,
1372	.print_power_state = &rv770_dpm_print_power_state,	1372	.print_power_state = &rv770_dpm_print_power_state,
1373	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,	1373	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1374	.force_performance_level = &rv770_dpm_force_performance_level,	1374	.force_performance_level = &rv770_dpm_force_performance_level,
1375	.vblank_too_short = &cypress_dpm_vblank_too_short,	1375	.vblank_too_short = &cypress_dpm_vblank_too_short,
1376	},	1376	},
1377	.pflip = {	1377	.pflip = {
1378	.pre_page_flip = &evergreen_pre_page_flip,	1378	.pre_page_flip = &evergreen_pre_page_flip,
1379	.page_flip = &evergreen_page_flip,	1379	.page_flip = &evergreen_page_flip,
1380	.post_page_flip = &evergreen_post_page_flip,	1380	.post_page_flip = &evergreen_post_page_flip,
1381	},	1381	},
1382	};	1382	};
1383		1383
1384	static struct radeon_asic sumo_asic = {	1384	static struct radeon_asic sumo_asic = {
1385	.init = &evergreen_init,	1385	.init = &evergreen_init,
1386	.fini = &evergreen_fini,	1386	.fini = &evergreen_fini,
1387	.suspend = &evergreen_suspend,	1387	.suspend = &evergreen_suspend,
1388	.resume = &evergreen_resume,	1388	.resume = &evergreen_resume,
1389	.asic_reset = &evergreen_asic_reset,	1389	.asic_reset = &evergreen_asic_reset,
1390	.vga_set_state = &r600_vga_set_state,	1390	.vga_set_state = &r600_vga_set_state,
1391	.ioctl_wait_idle = r600_ioctl_wait_idle,	1391	.ioctl_wait_idle = r600_ioctl_wait_idle,
1392	.gui_idle = &r600_gui_idle,	1392	.gui_idle = &r600_gui_idle,
1393	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1393	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394	.get_xclk = &r600_get_xclk,	1394	.get_xclk = &r600_get_xclk,
1395	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1395	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1396	.gart = {	1396	.gart = {
1397	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1397	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398	.set_page = &rs600_gart_set_page,	1398	.set_page = &rs600_gart_set_page,
1399	},	1399	},
1400	.ring = {	1400	.ring = {
1401	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1401	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1402	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1403	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1404	},	1404	},
1405	.irq = {	1405	.irq = {
1406	.set = &evergreen_irq_set,	1406	.set = &evergreen_irq_set,
1407	.process = &evergreen_irq_process,	1407	.process = &evergreen_irq_process,
1408	},	1408	},
1409	.display = {	1409	.display = {
1410	.bandwidth_update = &evergreen_bandwidth_update,	1410	.bandwidth_update = &evergreen_bandwidth_update,
1411	.get_vblank_counter = &evergreen_get_vblank_counter,	1411	.get_vblank_counter = &evergreen_get_vblank_counter,
1412	.wait_for_vblank = &dce4_wait_for_vblank,	1412	.wait_for_vblank = &dce4_wait_for_vblank,
1413	.set_backlight_level = &atombios_set_backlight_level,	1413	.set_backlight_level = &atombios_set_backlight_level,
1414	.get_backlight_level = &atombios_get_backlight_level,	1414	.get_backlight_level = &atombios_get_backlight_level,
1415	.hdmi_enable = &evergreen_hdmi_enable,	1415	.hdmi_enable = &evergreen_hdmi_enable,
1416	.hdmi_setmode = &evergreen_hdmi_setmode,	1416	.hdmi_setmode = &evergreen_hdmi_setmode,
1417	},	1417	},
1418	.copy = {	1418	.copy = {
1419	.blit = &r600_copy_cpdma,	1419	.blit = &r600_copy_cpdma,
1420	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1420	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1421	.dma = &evergreen_copy_dma,	1421	.dma = &evergreen_copy_dma,
1422	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1422	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1423	.copy = &evergreen_copy_dma,	1423	.copy = &evergreen_copy_dma,
1424	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1424	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1425	},	1425	},
1426	.surface = {	1426	.surface = {
1427	.set_reg = r600_set_surface_reg,	1427	.set_reg = r600_set_surface_reg,
1428	.clear_reg = r600_clear_surface_reg,	1428	.clear_reg = r600_clear_surface_reg,
1429	},	1429	},
1430	.hpd = {	1430	.hpd = {
1431	.init = &evergreen_hpd_init,	1431	.init = &evergreen_hpd_init,
1432	.fini = &evergreen_hpd_fini,	1432	.fini = &evergreen_hpd_fini,
1433	.sense = &evergreen_hpd_sense,	1433	.sense = &evergreen_hpd_sense,
1434	.set_polarity = &evergreen_hpd_set_polarity,	1434	.set_polarity = &evergreen_hpd_set_polarity,
1435	},	1435	},
1436	.pm = {	1436	.pm = {
1437	.misc = &evergreen_pm_misc,	1437	.misc = &evergreen_pm_misc,
1438	.prepare = &evergreen_pm_prepare,	1438	.prepare = &evergreen_pm_prepare,
1439	.finish = &evergreen_pm_finish,	1439	.finish = &evergreen_pm_finish,
1440	.init_profile = &sumo_pm_init_profile,	1440	.init_profile = &sumo_pm_init_profile,
1441	.get_dynpm_state = &r600_pm_get_dynpm_state,	1441	.get_dynpm_state = &r600_pm_get_dynpm_state,
1442	.get_engine_clock = &radeon_atom_get_engine_clock,	1442	.get_engine_clock = &radeon_atom_get_engine_clock,
1443	.set_engine_clock = &radeon_atom_set_engine_clock,	1443	.set_engine_clock = &radeon_atom_set_engine_clock,
1444	.get_memory_clock = NULL,	1444	.get_memory_clock = NULL,
1445	.set_memory_clock = NULL,	1445	.set_memory_clock = NULL,
1446	.get_pcie_lanes = NULL,	1446	.get_pcie_lanes = NULL,
1447	.set_pcie_lanes = NULL,	1447	.set_pcie_lanes = NULL,
1448	.set_clock_gating = NULL,	1448	.set_clock_gating = NULL,
1449	.set_uvd_clocks = &sumo_set_uvd_clocks,	1449	.set_uvd_clocks = &sumo_set_uvd_clocks,
1450	.get_temperature = &sumo_get_temp,	1450	.get_temperature = &sumo_get_temp,
1451	},	1451	},
1452	.dpm = {	1452	.dpm = {
1453	.init = &sumo_dpm_init,	1453	.init = &sumo_dpm_init,
1454	.setup_asic = &sumo_dpm_setup_asic,	1454	.setup_asic = &sumo_dpm_setup_asic,
1455	.enable = &sumo_dpm_enable,	1455	.enable = &sumo_dpm_enable,
1456	.late_enable = &sumo_dpm_late_enable,	1456	.late_enable = &sumo_dpm_late_enable,
1457	.disable = &sumo_dpm_disable,	1457	.disable = &sumo_dpm_disable,
1458	.pre_set_power_state = &sumo_dpm_pre_set_power_state,	1458	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
1459	.set_power_state = &sumo_dpm_set_power_state,	1459	.set_power_state = &sumo_dpm_set_power_state,
1460	.post_set_power_state = &sumo_dpm_post_set_power_state,	1460	.post_set_power_state = &sumo_dpm_post_set_power_state,
1461	.display_configuration_changed = &sumo_dpm_display_configuration_changed,	1461	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
1462	.fini = &sumo_dpm_fini,	1462	.fini = &sumo_dpm_fini,
1463	.get_sclk = &sumo_dpm_get_sclk,	1463	.get_sclk = &sumo_dpm_get_sclk,
1464	.get_mclk = &sumo_dpm_get_mclk,	1464	.get_mclk = &sumo_dpm_get_mclk,
1465	.print_power_state = &sumo_dpm_print_power_state,	1465	.print_power_state = &sumo_dpm_print_power_state,
1466	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,	1466	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1467	.force_performance_level = &sumo_dpm_force_performance_level,	1467	.force_performance_level = &sumo_dpm_force_performance_level,
1468	},	1468	},
1469	.pflip = {	1469	.pflip = {
1470	.pre_page_flip = &evergreen_pre_page_flip,	1470	.pre_page_flip = &evergreen_pre_page_flip,
1471	.page_flip = &evergreen_page_flip,	1471	.page_flip = &evergreen_page_flip,
1472	.post_page_flip = &evergreen_post_page_flip,	1472	.post_page_flip = &evergreen_post_page_flip,
1473	},	1473	},
1474	};	1474	};
1475		1475
1476	static struct radeon_asic btc_asic = {	1476	static struct radeon_asic btc_asic = {
1477	.init = &evergreen_init,	1477	.init = &evergreen_init,
1478	.fini = &evergreen_fini,	1478	.fini = &evergreen_fini,
1479	.suspend = &evergreen_suspend,	1479	.suspend = &evergreen_suspend,
1480	.resume = &evergreen_resume,	1480	.resume = &evergreen_resume,
1481	.asic_reset = &evergreen_asic_reset,	1481	.asic_reset = &evergreen_asic_reset,
1482	.vga_set_state = &r600_vga_set_state,	1482	.vga_set_state = &r600_vga_set_state,
1483	.ioctl_wait_idle = r600_ioctl_wait_idle,	1483	.ioctl_wait_idle = r600_ioctl_wait_idle,
1484	.gui_idle = &r600_gui_idle,	1484	.gui_idle = &r600_gui_idle,
1485	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1485	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1486	.get_xclk = &rv770_get_xclk,	1486	.get_xclk = &rv770_get_xclk,
1487	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1487	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1488	.gart = {	1488	.gart = {
1489	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1489	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1490	.set_page = &rs600_gart_set_page,	1490	.set_page = &rs600_gart_set_page,
1491	},	1491	},
1492	.ring = {	1492	.ring = {
1493	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1493	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1494	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1494	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1495	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1495	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1496	},	1496	},
1497	.irq = {	1497	.irq = {
1498	.set = &evergreen_irq_set,	1498	.set = &evergreen_irq_set,
1499	.process = &evergreen_irq_process,	1499	.process = &evergreen_irq_process,
1500	},	1500	},
1501	.display = {	1501	.display = {
1502	.bandwidth_update = &evergreen_bandwidth_update,	1502	.bandwidth_update = &evergreen_bandwidth_update,
1503	.get_vblank_counter = &evergreen_get_vblank_counter,	1503	.get_vblank_counter = &evergreen_get_vblank_counter,
1504	.wait_for_vblank = &dce4_wait_for_vblank,	1504	.wait_for_vblank = &dce4_wait_for_vblank,
1505	.set_backlight_level = &atombios_set_backlight_level,	1505	.set_backlight_level = &atombios_set_backlight_level,
1506	.get_backlight_level = &atombios_get_backlight_level,	1506	.get_backlight_level = &atombios_get_backlight_level,
1507	.hdmi_enable = &evergreen_hdmi_enable,	1507	.hdmi_enable = &evergreen_hdmi_enable,
1508	.hdmi_setmode = &evergreen_hdmi_setmode,	1508	.hdmi_setmode = &evergreen_hdmi_setmode,
1509	},	1509	},
1510	.copy = {	1510	.copy = {
1511	.blit = &r600_copy_cpdma,	1511	.blit = &r600_copy_cpdma,
1512	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1512	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1513	.dma = &evergreen_copy_dma,	1513	.dma = &evergreen_copy_dma,
1514	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1514	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1515	.copy = &evergreen_copy_dma,	1515	.copy = &evergreen_copy_dma,
1516	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1516	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1517	},	1517	},
1518	.surface = {	1518	.surface = {
1519	.set_reg = r600_set_surface_reg,	1519	.set_reg = r600_set_surface_reg,
1520	.clear_reg = r600_clear_surface_reg,	1520	.clear_reg = r600_clear_surface_reg,
1521	},	1521	},
1522	.hpd = {	1522	.hpd = {
1523	.init = &evergreen_hpd_init,	1523	.init = &evergreen_hpd_init,
1524	.fini = &evergreen_hpd_fini,	1524	.fini = &evergreen_hpd_fini,
1525	.sense = &evergreen_hpd_sense,	1525	.sense = &evergreen_hpd_sense,
1526	.set_polarity = &evergreen_hpd_set_polarity,	1526	.set_polarity = &evergreen_hpd_set_polarity,
1527	},	1527	},
1528	.pm = {	1528	.pm = {
1529	.misc = &evergreen_pm_misc,	1529	.misc = &evergreen_pm_misc,
1530	.prepare = &evergreen_pm_prepare,	1530	.prepare = &evergreen_pm_prepare,
1531	.finish = &evergreen_pm_finish,	1531	.finish = &evergreen_pm_finish,
1532	.init_profile = &btc_pm_init_profile,	1532	.init_profile = &btc_pm_init_profile,
1533	.get_dynpm_state = &r600_pm_get_dynpm_state,	1533	.get_dynpm_state = &r600_pm_get_dynpm_state,
1534	.get_engine_clock = &radeon_atom_get_engine_clock,	1534	.get_engine_clock = &radeon_atom_get_engine_clock,
1535	.set_engine_clock = &radeon_atom_set_engine_clock,	1535	.set_engine_clock = &radeon_atom_set_engine_clock,
1536	.get_memory_clock = &radeon_atom_get_memory_clock,	1536	.get_memory_clock = &radeon_atom_get_memory_clock,
1537	.set_memory_clock = &radeon_atom_set_memory_clock,	1537	.set_memory_clock = &radeon_atom_set_memory_clock,
1538	.get_pcie_lanes = &r600_get_pcie_lanes,	1538	.get_pcie_lanes = &r600_get_pcie_lanes,
1539	.set_pcie_lanes = &r600_set_pcie_lanes,	1539	.set_pcie_lanes = &r600_set_pcie_lanes,
1540	.set_clock_gating = NULL,	1540	.set_clock_gating = NULL,
1541	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1541	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1542	.get_temperature = &evergreen_get_temp,	1542	.get_temperature = &evergreen_get_temp,
1543	},	1543	},
1544	.dpm = {	1544	.dpm = {
1545	.init = &btc_dpm_init,	1545	.init = &btc_dpm_init,
1546	.setup_asic = &btc_dpm_setup_asic,	1546	.setup_asic = &btc_dpm_setup_asic,
1547	.enable = &btc_dpm_enable,	1547	.enable = &btc_dpm_enable,
1548	.late_enable = &rv770_dpm_late_enable,	1548	.late_enable = &rv770_dpm_late_enable,
1549	.disable = &btc_dpm_disable,	1549	.disable = &btc_dpm_disable,
1550	.pre_set_power_state = &btc_dpm_pre_set_power_state,	1550	.pre_set_power_state = &btc_dpm_pre_set_power_state,
1551	.set_power_state = &btc_dpm_set_power_state,	1551	.set_power_state = &btc_dpm_set_power_state,
1552	.post_set_power_state = &btc_dpm_post_set_power_state,	1552	.post_set_power_state = &btc_dpm_post_set_power_state,
1553	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1553	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1554	.fini = &btc_dpm_fini,	1554	.fini = &btc_dpm_fini,
1555	.get_sclk = &btc_dpm_get_sclk,	1555	.get_sclk = &btc_dpm_get_sclk,
1556	.get_mclk = &btc_dpm_get_mclk,	1556	.get_mclk = &btc_dpm_get_mclk,
1557	.print_power_state = &rv770_dpm_print_power_state,	1557	.print_power_state = &rv770_dpm_print_power_state,
1558	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,	1558	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1559	.force_performance_level = &rv770_dpm_force_performance_level,	1559	.force_performance_level = &rv770_dpm_force_performance_level,
1560	.vblank_too_short = &btc_dpm_vblank_too_short,	1560	.vblank_too_short = &btc_dpm_vblank_too_short,
1561	},	1561	},
1562	.pflip = {	1562	.pflip = {
1563	.pre_page_flip = &evergreen_pre_page_flip,	1563	.pre_page_flip = &evergreen_pre_page_flip,
1564	.page_flip = &evergreen_page_flip,	1564	.page_flip = &evergreen_page_flip,
1565	.post_page_flip = &evergreen_post_page_flip,	1565	.post_page_flip = &evergreen_post_page_flip,
1566	},	1566	},
1567	};	1567	};
1568		1568
1569	static struct radeon_asic_ring cayman_gfx_ring = {	1569	static struct radeon_asic_ring cayman_gfx_ring = {
1570	.ib_execute = &cayman_ring_ib_execute,	1570	.ib_execute = &cayman_ring_ib_execute,
1571	.ib_parse = &evergreen_ib_parse,	1571	.ib_parse = &evergreen_ib_parse,
1572	.emit_fence = &cayman_fence_ring_emit,	1572	.emit_fence = &cayman_fence_ring_emit,
1573	.emit_semaphore = &r600_semaphore_ring_emit,	1573	.emit_semaphore = &r600_semaphore_ring_emit,
1574	.cs_parse = &evergreen_cs_parse,	1574	.cs_parse = &evergreen_cs_parse,
1575	.ring_test = &r600_ring_test,	1575	.ring_test = &r600_ring_test,
1576	.ib_test = &r600_ib_test,	1576	.ib_test = &r600_ib_test,
1577	.is_lockup = &cayman_gfx_is_lockup,	1577	.is_lockup = &cayman_gfx_is_lockup,
1578	.vm_flush = &cayman_vm_flush,	1578	.vm_flush = &cayman_vm_flush,
1579	.get_rptr = &cayman_gfx_get_rptr,	1579	.get_rptr = &cayman_gfx_get_rptr,
1580	.get_wptr = &cayman_gfx_get_wptr,	1580	.get_wptr = &cayman_gfx_get_wptr,
1581	.set_wptr = &cayman_gfx_set_wptr,	1581	.set_wptr = &cayman_gfx_set_wptr,
1582	};	1582	};
1583		1583
1584	static struct radeon_asic_ring cayman_dma_ring = {	1584	static struct radeon_asic_ring cayman_dma_ring = {
1585	.ib_execute = &cayman_dma_ring_ib_execute,	1585	.ib_execute = &cayman_dma_ring_ib_execute,
1586	.ib_parse = &evergreen_dma_ib_parse,	1586	.ib_parse = &evergreen_dma_ib_parse,
1587	.emit_fence = &evergreen_dma_fence_ring_emit,	1587	.emit_fence = &evergreen_dma_fence_ring_emit,
1588	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1588	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1589	.cs_parse = &evergreen_dma_cs_parse,	1589	.cs_parse = &evergreen_dma_cs_parse,
1590	.ring_test = &r600_dma_ring_test,	1590	.ring_test = &r600_dma_ring_test,
1591	.ib_test = &r600_dma_ib_test,	1591	.ib_test = &r600_dma_ib_test,
1592	.is_lockup = &cayman_dma_is_lockup,	1592	.is_lockup = &cayman_dma_is_lockup,
1593	.vm_flush = &cayman_dma_vm_flush,	1593	.vm_flush = &cayman_dma_vm_flush,
1594	.get_rptr = &cayman_dma_get_rptr,	1594	.get_rptr = &cayman_dma_get_rptr,
1595	.get_wptr = &cayman_dma_get_wptr,	1595	.get_wptr = &cayman_dma_get_wptr,
1596	.set_wptr = &cayman_dma_set_wptr	1596	.set_wptr = &cayman_dma_set_wptr
1597	};	1597	};
1598		1598
1599	static struct radeon_asic_ring cayman_uvd_ring = {	1599	static struct radeon_asic_ring cayman_uvd_ring = {
1600	.ib_execute = &uvd_v1_0_ib_execute,	1600	.ib_execute = &uvd_v1_0_ib_execute,
1601	.emit_fence = &uvd_v2_2_fence_emit,	1601	.emit_fence = &uvd_v2_2_fence_emit,
1602	.emit_semaphore = &uvd_v3_1_semaphore_emit,	1602	.emit_semaphore = &uvd_v3_1_semaphore_emit,
1603	.cs_parse = &radeon_uvd_cs_parse,	1603	.cs_parse = &radeon_uvd_cs_parse,
1604	.ring_test = &uvd_v1_0_ring_test,	1604	.ring_test = &uvd_v1_0_ring_test,
1605	.ib_test = &uvd_v1_0_ib_test,	1605	.ib_test = &uvd_v1_0_ib_test,
1606	.is_lockup = &radeon_ring_test_lockup,	1606	.is_lockup = &radeon_ring_test_lockup,
1607	.get_rptr = &uvd_v1_0_get_rptr,	1607	.get_rptr = &uvd_v1_0_get_rptr,
1608	.get_wptr = &uvd_v1_0_get_wptr,	1608	.get_wptr = &uvd_v1_0_get_wptr,
1609	.set_wptr = &uvd_v1_0_set_wptr,	1609	.set_wptr = &uvd_v1_0_set_wptr,
1610	};	1610	};
1611		1611
1612	static struct radeon_asic cayman_asic = {	1612	static struct radeon_asic cayman_asic = {
1613	.init = &cayman_init,	1613	.init = &cayman_init,
1614	.fini = &cayman_fini,	1614	.fini = &cayman_fini,
1615	.suspend = &cayman_suspend,	1615	.suspend = &cayman_suspend,
1616	.resume = &cayman_resume,	1616	.resume = &cayman_resume,
1617	.asic_reset = &cayman_asic_reset,	1617	.asic_reset = &cayman_asic_reset,
1618	.vga_set_state = &r600_vga_set_state,	1618	.vga_set_state = &r600_vga_set_state,
1619	.ioctl_wait_idle = r600_ioctl_wait_idle,	1619	.ioctl_wait_idle = r600_ioctl_wait_idle,
1620	.gui_idle = &r600_gui_idle,	1620	.gui_idle = &r600_gui_idle,
1621	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1621	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1622	.get_xclk = &rv770_get_xclk,	1622	.get_xclk = &rv770_get_xclk,
1623	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1623	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1624	.gart = {	1624	.gart = {
1625	.tlb_flush = &cayman_pcie_gart_tlb_flush,	1625	.tlb_flush = &cayman_pcie_gart_tlb_flush,
1626	.set_page = &rs600_gart_set_page,	1626	.set_page = &rs600_gart_set_page,
1627	},	1627	},
1628	.vm = {	1628	.vm = {
1629	.init = &cayman_vm_init,	1629	.init = &cayman_vm_init,
1630	.fini = &cayman_vm_fini,	1630	.fini = &cayman_vm_fini,
1631	.set_page = &cayman_dma_vm_set_page,	1631	.set_page = &cayman_dma_vm_set_page,
1632	},	1632	},
1633	.ring = {	1633	.ring = {
1634	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,	1634	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1635	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,	1635	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1636	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,	1636	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1637	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,	1637	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1638	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,	1638	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1639	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1639	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1640	},	1640	},
1641	.irq = {	1641	.irq = {
1642	.set = &evergreen_irq_set,	1642	.set = &evergreen_irq_set,
1643	.process = &evergreen_irq_process,	1643	.process = &evergreen_irq_process,
1644	},	1644	},
1645	.display = {	1645	.display = {
1646	.bandwidth_update = &evergreen_bandwidth_update,	1646	.bandwidth_update = &evergreen_bandwidth_update,
1647	.get_vblank_counter = &evergreen_get_vblank_counter,	1647	.get_vblank_counter = &evergreen_get_vblank_counter,
1648	.wait_for_vblank = &dce4_wait_for_vblank,	1648	.wait_for_vblank = &dce4_wait_for_vblank,
1649	.set_backlight_level = &atombios_set_backlight_level,	1649	.set_backlight_level = &atombios_set_backlight_level,
1650	.get_backlight_level = &atombios_get_backlight_level,	1650	.get_backlight_level = &atombios_get_backlight_level,
1651	.hdmi_enable = &evergreen_hdmi_enable,	1651	.hdmi_enable = &evergreen_hdmi_enable,
1652	.hdmi_setmode = &evergreen_hdmi_setmode,	1652	.hdmi_setmode = &evergreen_hdmi_setmode,
1653	},	1653	},
1654	.copy = {	1654	.copy = {
1655	.blit = &r600_copy_cpdma,	1655	.blit = &r600_copy_cpdma,
1656	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1656	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1657	.dma = &evergreen_copy_dma,	1657	.dma = &evergreen_copy_dma,
1658	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1658	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1659	.copy = &evergreen_copy_dma,	1659	.copy = &evergreen_copy_dma,
1660	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1660	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1661	},	1661	},
1662	.surface = {	1662	.surface = {
1663	.set_reg = r600_set_surface_reg,	1663	.set_reg = r600_set_surface_reg,
1664	.clear_reg = r600_clear_surface_reg,	1664	.clear_reg = r600_clear_surface_reg,
1665	},	1665	},
1666	.hpd = {	1666	.hpd = {
1667	.init = &evergreen_hpd_init,	1667	.init = &evergreen_hpd_init,
1668	.fini = &evergreen_hpd_fini,	1668	.fini = &evergreen_hpd_fini,
1669	.sense = &evergreen_hpd_sense,	1669	.sense = &evergreen_hpd_sense,
1670	.set_polarity = &evergreen_hpd_set_polarity,	1670	.set_polarity = &evergreen_hpd_set_polarity,
1671	},	1671	},
1672	.pm = {	1672	.pm = {
1673	.misc = &evergreen_pm_misc,	1673	.misc = &evergreen_pm_misc,
1674	.prepare = &evergreen_pm_prepare,	1674	.prepare = &evergreen_pm_prepare,
1675	.finish = &evergreen_pm_finish,	1675	.finish = &evergreen_pm_finish,
1676	.init_profile = &btc_pm_init_profile,	1676	.init_profile = &btc_pm_init_profile,
1677	.get_dynpm_state = &r600_pm_get_dynpm_state,	1677	.get_dynpm_state = &r600_pm_get_dynpm_state,
1678	.get_engine_clock = &radeon_atom_get_engine_clock,	1678	.get_engine_clock = &radeon_atom_get_engine_clock,
1679	.set_engine_clock = &radeon_atom_set_engine_clock,	1679	.set_engine_clock = &radeon_atom_set_engine_clock,
1680	.get_memory_clock = &radeon_atom_get_memory_clock,	1680	.get_memory_clock = &radeon_atom_get_memory_clock,
1681	.set_memory_clock = &radeon_atom_set_memory_clock,	1681	.set_memory_clock = &radeon_atom_set_memory_clock,
1682	.get_pcie_lanes = &r600_get_pcie_lanes,	1682	.get_pcie_lanes = &r600_get_pcie_lanes,
1683	.set_pcie_lanes = &r600_set_pcie_lanes,	1683	.set_pcie_lanes = &r600_set_pcie_lanes,
1684	.set_clock_gating = NULL,	1684	.set_clock_gating = NULL,
1685	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1685	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1686	.get_temperature = &evergreen_get_temp,	1686	.get_temperature = &evergreen_get_temp,
1687	},	1687	},
1688	.dpm = {	1688	.dpm = {
1689	.init = &ni_dpm_init,	1689	.init = &ni_dpm_init,
1690	.setup_asic = &ni_dpm_setup_asic,	1690	.setup_asic = &ni_dpm_setup_asic,
1691	.enable = &ni_dpm_enable,	1691	.enable = &ni_dpm_enable,
1692	.late_enable = &rv770_dpm_late_enable,	1692	.late_enable = &rv770_dpm_late_enable,
1693	.disable = &ni_dpm_disable,	1693	.disable = &ni_dpm_disable,
1694	.pre_set_power_state = &ni_dpm_pre_set_power_state,	1694	.pre_set_power_state = &ni_dpm_pre_set_power_state,
1695	.set_power_state = &ni_dpm_set_power_state,	1695	.set_power_state = &ni_dpm_set_power_state,
1696	.post_set_power_state = &ni_dpm_post_set_power_state,	1696	.post_set_power_state = &ni_dpm_post_set_power_state,
1697	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1697	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1698	.fini = &ni_dpm_fini,	1698	.fini = &ni_dpm_fini,
1699	.get_sclk = &ni_dpm_get_sclk,	1699	.get_sclk = &ni_dpm_get_sclk,
1700	.get_mclk = &ni_dpm_get_mclk,	1700	.get_mclk = &ni_dpm_get_mclk,
1701	.print_power_state = &ni_dpm_print_power_state,	1701	.print_power_state = &ni_dpm_print_power_state,
1702	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,	1702	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1703	.force_performance_level = &ni_dpm_force_performance_level,	1703	.force_performance_level = &ni_dpm_force_performance_level,
1704	.vblank_too_short = &ni_dpm_vblank_too_short,	1704	.vblank_too_short = &ni_dpm_vblank_too_short,
1705	},	1705	},
1706	.pflip = {	1706	.pflip = {
1707	.pre_page_flip = &evergreen_pre_page_flip,	1707	.pre_page_flip = &evergreen_pre_page_flip,
1708	.page_flip = &evergreen_page_flip,	1708	.page_flip = &evergreen_page_flip,
1709	.post_page_flip = &evergreen_post_page_flip,	1709	.post_page_flip = &evergreen_post_page_flip,
1710	},	1710	},
1711	};	1711	};
1712		1712
1713	static struct radeon_asic trinity_asic = {	1713	static struct radeon_asic trinity_asic = {
1714	.init = &cayman_init,	1714	.init = &cayman_init,
1715	.fini = &cayman_fini,	1715	.fini = &cayman_fini,
1716	.suspend = &cayman_suspend,	1716	.suspend = &cayman_suspend,
1717	.resume = &cayman_resume,	1717	.resume = &cayman_resume,
1718	.asic_reset = &cayman_asic_reset,	1718	.asic_reset = &cayman_asic_reset,
1719	.vga_set_state = &r600_vga_set_state,	1719	.vga_set_state = &r600_vga_set_state,
1720	.ioctl_wait_idle = r600_ioctl_wait_idle,	1720	.ioctl_wait_idle = r600_ioctl_wait_idle,
1721	.gui_idle = &r600_gui_idle,	1721	.gui_idle = &r600_gui_idle,
1722	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1722	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1723	.get_xclk = &r600_get_xclk,	1723	.get_xclk = &r600_get_xclk,
1724	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1724	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1725	.gart = {	1725	.gart = {
1726	.tlb_flush = &cayman_pcie_gart_tlb_flush,	1726	.tlb_flush = &cayman_pcie_gart_tlb_flush,
1727	.set_page = &rs600_gart_set_page,	1727	.set_page = &rs600_gart_set_page,
1728	},	1728	},
1729	.vm = {	1729	.vm = {
1730	.init = &cayman_vm_init,	1730	.init = &cayman_vm_init,
1731	.fini = &cayman_vm_fini,	1731	.fini = &cayman_vm_fini,
1732	.set_page = &cayman_dma_vm_set_page,	1732	.set_page = &cayman_dma_vm_set_page,
1733	},	1733	},
1734	.ring = {	1734	.ring = {
1735	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,	1735	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1736	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,	1736	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1737	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,	1737	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1738	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,	1738	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1739	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,	1739	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1740	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1740	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1741	},	1741	},
1742	.irq = {	1742	.irq = {
1743	.set = &evergreen_irq_set,	1743	.set = &evergreen_irq_set,
1744	.process = &evergreen_irq_process,	1744	.process = &evergreen_irq_process,
1745	},	1745	},
1746	.display = {	1746	.display = {
1747	.bandwidth_update = &dce6_bandwidth_update,	1747	.bandwidth_update = &dce6_bandwidth_update,
1748	.get_vblank_counter = &evergreen_get_vblank_counter,	1748	.get_vblank_counter = &evergreen_get_vblank_counter,
1749	.wait_for_vblank = &dce4_wait_for_vblank,	1749	.wait_for_vblank = &dce4_wait_for_vblank,
1750	.set_backlight_level = &atombios_set_backlight_level,	1750	.set_backlight_level = &atombios_set_backlight_level,
1751	.get_backlight_level = &atombios_get_backlight_level,	1751	.get_backlight_level = &atombios_get_backlight_level,
1752	.hdmi_enable = &evergreen_hdmi_enable,	1752	.hdmi_enable = &evergreen_hdmi_enable,
1753	.hdmi_setmode = &evergreen_hdmi_setmode,	1753	.hdmi_setmode = &evergreen_hdmi_setmode,
1754	},	1754	},
1755	.copy = {	1755	.copy = {
1756	.blit = &r600_copy_cpdma,	1756	.blit = &r600_copy_cpdma,
1757	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1757	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1758	.dma = &evergreen_copy_dma,	1758	.dma = &evergreen_copy_dma,
1759	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1759	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1760	.copy = &evergreen_copy_dma,	1760	.copy = &evergreen_copy_dma,
1761	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1761	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1762	},	1762	},
1763	.surface = {	1763	.surface = {
1764	.set_reg = r600_set_surface_reg,	1764	.set_reg = r600_set_surface_reg,
1765	.clear_reg = r600_clear_surface_reg,	1765	.clear_reg = r600_clear_surface_reg,
1766	},	1766	},
1767	.hpd = {	1767	.hpd = {
1768	.init = &evergreen_hpd_init,	1768	.init = &evergreen_hpd_init,
1769	.fini = &evergreen_hpd_fini,	1769	.fini = &evergreen_hpd_fini,
1770	.sense = &evergreen_hpd_sense,	1770	.sense = &evergreen_hpd_sense,
1771	.set_polarity = &evergreen_hpd_set_polarity,	1771	.set_polarity = &evergreen_hpd_set_polarity,
1772	},	1772	},
1773	.pm = {	1773	.pm = {
1774	.misc = &evergreen_pm_misc,	1774	.misc = &evergreen_pm_misc,
1775	.prepare = &evergreen_pm_prepare,	1775	.prepare = &evergreen_pm_prepare,
1776	.finish = &evergreen_pm_finish,	1776	.finish = &evergreen_pm_finish,
1777	.init_profile = &sumo_pm_init_profile,	1777	.init_profile = &sumo_pm_init_profile,
1778	.get_dynpm_state = &r600_pm_get_dynpm_state,	1778	.get_dynpm_state = &r600_pm_get_dynpm_state,
1779	.get_engine_clock = &radeon_atom_get_engine_clock,	1779	.get_engine_clock = &radeon_atom_get_engine_clock,
1780	.set_engine_clock = &radeon_atom_set_engine_clock,	1780	.set_engine_clock = &radeon_atom_set_engine_clock,
1781	.get_memory_clock = NULL,	1781	.get_memory_clock = NULL,
1782	.set_memory_clock = NULL,	1782	.set_memory_clock = NULL,
1783	.get_pcie_lanes = NULL,	1783	.get_pcie_lanes = NULL,
1784	.set_pcie_lanes = NULL,	1784	.set_pcie_lanes = NULL,
1785	.set_clock_gating = NULL,	1785	.set_clock_gating = NULL,
1786	.set_uvd_clocks = &sumo_set_uvd_clocks,	1786	.set_uvd_clocks = &sumo_set_uvd_clocks,
1787	.get_temperature = &tn_get_temp,	1787	.get_temperature = &tn_get_temp,
1788	},	1788	},
1789	.dpm = {	1789	.dpm = {
1790	.init = &trinity_dpm_init,	1790	.init = &trinity_dpm_init,
1791	.setup_asic = &trinity_dpm_setup_asic,	1791	.setup_asic = &trinity_dpm_setup_asic,
1792	.enable = &trinity_dpm_enable,	1792	.enable = &trinity_dpm_enable,
1793	.late_enable = &trinity_dpm_late_enable,	1793	.late_enable = &trinity_dpm_late_enable,
1794	.disable = &trinity_dpm_disable,	1794	.disable = &trinity_dpm_disable,
1795	.pre_set_power_state = &trinity_dpm_pre_set_power_state,	1795	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
1796	.set_power_state = &trinity_dpm_set_power_state,	1796	.set_power_state = &trinity_dpm_set_power_state,
1797	.post_set_power_state = &trinity_dpm_post_set_power_state,	1797	.post_set_power_state = &trinity_dpm_post_set_power_state,
1798	.display_configuration_changed = &trinity_dpm_display_configuration_changed,	1798	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
1799	.fini = &trinity_dpm_fini,	1799	.fini = &trinity_dpm_fini,
1800	.get_sclk = &trinity_dpm_get_sclk,	1800	.get_sclk = &trinity_dpm_get_sclk,
1801	.get_mclk = &trinity_dpm_get_mclk,	1801	.get_mclk = &trinity_dpm_get_mclk,
1802	.print_power_state = &trinity_dpm_print_power_state,	1802	.print_power_state = &trinity_dpm_print_power_state,
1803	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,	1803	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1804	.force_performance_level = &trinity_dpm_force_performance_level,	1804	.force_performance_level = &trinity_dpm_force_performance_level,
1805	.enable_bapm = &trinity_dpm_enable_bapm,	1805	.enable_bapm = &trinity_dpm_enable_bapm,
1806	},	1806	},
1807	.pflip = {	1807	.pflip = {
1808	.pre_page_flip = &evergreen_pre_page_flip,	1808	.pre_page_flip = &evergreen_pre_page_flip,
1809	.page_flip = &evergreen_page_flip,	1809	.page_flip = &evergreen_page_flip,
1810	.post_page_flip = &evergreen_post_page_flip,	1810	.post_page_flip = &evergreen_post_page_flip,
1811	},	1811	},
1812	};	1812	};
1813		1813
1814	static struct radeon_asic_ring si_gfx_ring = {	1814	static struct radeon_asic_ring si_gfx_ring = {
1815	.ib_execute = &si_ring_ib_execute,	1815	.ib_execute = &si_ring_ib_execute,
1816	.ib_parse = &si_ib_parse,	1816	.ib_parse = &si_ib_parse,
1817	.emit_fence = &si_fence_ring_emit,	1817	.emit_fence = &si_fence_ring_emit,
1818	.emit_semaphore = &r600_semaphore_ring_emit,	1818	.emit_semaphore = &r600_semaphore_ring_emit,
1819	.cs_parse = NULL,	1819	.cs_parse = NULL,
1820	.ring_test = &r600_ring_test,	1820	.ring_test = &r600_ring_test,
1821	.ib_test = &r600_ib_test,	1821	.ib_test = &r600_ib_test,
1822	.is_lockup = &si_gfx_is_lockup,	1822	.is_lockup = &si_gfx_is_lockup,
1823	.vm_flush = &si_vm_flush,	1823	.vm_flush = &si_vm_flush,
1824	.get_rptr = &cayman_gfx_get_rptr,	1824	.get_rptr = &cayman_gfx_get_rptr,
1825	.get_wptr = &cayman_gfx_get_wptr,	1825	.get_wptr = &cayman_gfx_get_wptr,
1826	.set_wptr = &cayman_gfx_set_wptr,	1826	.set_wptr = &cayman_gfx_set_wptr,
1827	};	1827	};
1828		1828
1829	static struct radeon_asic_ring si_dma_ring = {	1829	static struct radeon_asic_ring si_dma_ring = {
1830	.ib_execute = &cayman_dma_ring_ib_execute,	1830	.ib_execute = &cayman_dma_ring_ib_execute,
1831	.ib_parse = &evergreen_dma_ib_parse,	1831	.ib_parse = &evergreen_dma_ib_parse,
1832	.emit_fence = &evergreen_dma_fence_ring_emit,	1832	.emit_fence = &evergreen_dma_fence_ring_emit,
1833	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1833	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1834	.cs_parse = NULL,	1834	.cs_parse = NULL,
1835	.ring_test = &r600_dma_ring_test,	1835	.ring_test = &r600_dma_ring_test,
1836	.ib_test = &r600_dma_ib_test,	1836	.ib_test = &r600_dma_ib_test,
1837	.is_lockup = &si_dma_is_lockup,	1837	.is_lockup = &si_dma_is_lockup,
1838	.vm_flush = &si_dma_vm_flush,	1838	.vm_flush = &si_dma_vm_flush,
1839	.get_rptr = &cayman_dma_get_rptr,	1839	.get_rptr = &cayman_dma_get_rptr,
1840	.get_wptr = &cayman_dma_get_wptr,	1840	.get_wptr = &cayman_dma_get_wptr,
1841	.set_wptr = &cayman_dma_set_wptr,	1841	.set_wptr = &cayman_dma_set_wptr,
1842	};	1842	};
1843		1843
1844	static struct radeon_asic si_asic = {	1844	static struct radeon_asic si_asic = {
1845	.init = &si_init,	1845	.init = &si_init,
1846	.fini = &si_fini,	1846	.fini = &si_fini,
1847	.suspend = &si_suspend,	1847	.suspend = &si_suspend,
1848	.resume = &si_resume,	1848	.resume = &si_resume,
1849	.asic_reset = &si_asic_reset,	1849	.asic_reset = &si_asic_reset,
1850	.vga_set_state = &r600_vga_set_state,	1850	.vga_set_state = &r600_vga_set_state,
1851	.ioctl_wait_idle = r600_ioctl_wait_idle,	1851	.ioctl_wait_idle = r600_ioctl_wait_idle,
1852	.gui_idle = &r600_gui_idle,	1852	.gui_idle = &r600_gui_idle,
1853	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1853	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1854	.get_xclk = &si_get_xclk,	1854	.get_xclk = &si_get_xclk,
1855	.get_gpu_clock_counter = &si_get_gpu_clock_counter,	1855	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
1856	.gart = {	1856	.gart = {
1857	.tlb_flush = &si_pcie_gart_tlb_flush,	1857	.tlb_flush = &si_pcie_gart_tlb_flush,
1858	.set_page = &rs600_gart_set_page,	1858	.set_page = &rs600_gart_set_page,
1859	},	1859	},
1860	.vm = {	1860	.vm = {
1861	.init = &si_vm_init,	1861	.init = &si_vm_init,
1862	.fini = &si_vm_fini,	1862	.fini = &si_vm_fini,
1863	.set_page = &si_dma_vm_set_page,	1863	.set_page = &si_dma_vm_set_page,
1864	},	1864	},
1865	.ring = {	1865	.ring = {
1866	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,	1866	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1867	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,	1867	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1868	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,	1868	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1869	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,	1869	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1870	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,	1870	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1871	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1871	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1872	},	1872	},
1873	.irq = {	1873	.irq = {
1874	.set = &si_irq_set,	1874	.set = &si_irq_set,
1875	.process = &si_irq_process,	1875	.process = &si_irq_process,
1876	},	1876	},
1877	.display = {	1877	.display = {
1878	.bandwidth_update = &dce6_bandwidth_update,	1878	.bandwidth_update = &dce6_bandwidth_update,
1879	.get_vblank_counter = &evergreen_get_vblank_counter,	1879	.get_vblank_counter = &evergreen_get_vblank_counter,
1880	.wait_for_vblank = &dce4_wait_for_vblank,	1880	.wait_for_vblank = &dce4_wait_for_vblank,
1881	.set_backlight_level = &atombios_set_backlight_level,	1881	.set_backlight_level = &atombios_set_backlight_level,
1882	.get_backlight_level = &atombios_get_backlight_level,	1882	.get_backlight_level = &atombios_get_backlight_level,
1883	.hdmi_enable = &evergreen_hdmi_enable,	1883	.hdmi_enable = &evergreen_hdmi_enable,
1884	.hdmi_setmode = &evergreen_hdmi_setmode,	1884	.hdmi_setmode = &evergreen_hdmi_setmode,
1885	},	1885	},
1886	.copy = {	1886	.copy = {
1887	.blit = &r600_copy_cpdma,	1887	.blit = &r600_copy_cpdma,
1888	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1888	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1889	.dma = &si_copy_dma,	1889	.dma = &si_copy_dma,
1890	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1890	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1891	.copy = &si_copy_dma,	1891	.copy = &si_copy_dma,
1892	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1892	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1893	},	1893	},
1894	.surface = {	1894	.surface = {
1895	.set_reg = r600_set_surface_reg,	1895	.set_reg = r600_set_surface_reg,
1896	.clear_reg = r600_clear_surface_reg,	1896	.clear_reg = r600_clear_surface_reg,
1897	},	1897	},
1898	.hpd = {	1898	.hpd = {
1899	.init = &evergreen_hpd_init,	1899	.init = &evergreen_hpd_init,
1900	.fini = &evergreen_hpd_fini,	1900	.fini = &evergreen_hpd_fini,
1901	.sense = &evergreen_hpd_sense,	1901	.sense = &evergreen_hpd_sense,
1902	.set_polarity = &evergreen_hpd_set_polarity,	1902	.set_polarity = &evergreen_hpd_set_polarity,
1903	},	1903	},
1904	.pm = {	1904	.pm = {
1905	.misc = &evergreen_pm_misc,	1905	.misc = &evergreen_pm_misc,
1906	.prepare = &evergreen_pm_prepare,	1906	.prepare = &evergreen_pm_prepare,
1907	.finish = &evergreen_pm_finish,	1907	.finish = &evergreen_pm_finish,
1908	.init_profile = &sumo_pm_init_profile,	1908	.init_profile = &sumo_pm_init_profile,
1909	.get_dynpm_state = &r600_pm_get_dynpm_state,	1909	.get_dynpm_state = &r600_pm_get_dynpm_state,
1910	.get_engine_clock = &radeon_atom_get_engine_clock,	1910	.get_engine_clock = &radeon_atom_get_engine_clock,
1911	.set_engine_clock = &radeon_atom_set_engine_clock,	1911	.set_engine_clock = &radeon_atom_set_engine_clock,
1912	.get_memory_clock = &radeon_atom_get_memory_clock,	1912	.get_memory_clock = &radeon_atom_get_memory_clock,
1913	.set_memory_clock = &radeon_atom_set_memory_clock,	1913	.set_memory_clock = &radeon_atom_set_memory_clock,
1914	.get_pcie_lanes = &r600_get_pcie_lanes,	1914	.get_pcie_lanes = &r600_get_pcie_lanes,
1915	.set_pcie_lanes = &r600_set_pcie_lanes,	1915	.set_pcie_lanes = &r600_set_pcie_lanes,
1916	.set_clock_gating = NULL,	1916	.set_clock_gating = NULL,
1917	.set_uvd_clocks = &si_set_uvd_clocks,	1917	.set_uvd_clocks = &si_set_uvd_clocks,
1918	.get_temperature = &si_get_temp,	1918	.get_temperature = &si_get_temp,
1919	},	1919	},
1920	.dpm = {	1920	.dpm = {
1921	.init = &si_dpm_init,	1921	.init = &si_dpm_init,
1922	.setup_asic = &si_dpm_setup_asic,	1922	.setup_asic = &si_dpm_setup_asic,
1923	.enable = &si_dpm_enable,	1923	.enable = &si_dpm_enable,
1924	.late_enable = &si_dpm_late_enable,	1924	.late_enable = &si_dpm_late_enable,
1925	.disable = &si_dpm_disable,	1925	.disable = &si_dpm_disable,
1926	.pre_set_power_state = &si_dpm_pre_set_power_state,	1926	.pre_set_power_state = &si_dpm_pre_set_power_state,
1927	.set_power_state = &si_dpm_set_power_state,	1927	.set_power_state = &si_dpm_set_power_state,
1928	.post_set_power_state = &si_dpm_post_set_power_state,	1928	.post_set_power_state = &si_dpm_post_set_power_state,
1929	.display_configuration_changed = &si_dpm_display_configuration_changed,	1929	.display_configuration_changed = &si_dpm_display_configuration_changed,
1930	.fini = &si_dpm_fini,	1930	.fini = &si_dpm_fini,
1931	.get_sclk = &ni_dpm_get_sclk,	1931	.get_sclk = &ni_dpm_get_sclk,
1932	.get_mclk = &ni_dpm_get_mclk,	1932	.get_mclk = &ni_dpm_get_mclk,
1933	.print_power_state = &ni_dpm_print_power_state,	1933	.print_power_state = &ni_dpm_print_power_state,
1934	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,	1934	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1935	.force_performance_level = &si_dpm_force_performance_level,	1935	.force_performance_level = &si_dpm_force_performance_level,
1936	.vblank_too_short = &ni_dpm_vblank_too_short,	1936	.vblank_too_short = &ni_dpm_vblank_too_short,
1937	},	1937	},
1938	.pflip = {	1938	.pflip = {
1939	.pre_page_flip = &evergreen_pre_page_flip,	1939	.pre_page_flip = &evergreen_pre_page_flip,
1940	.page_flip = &evergreen_page_flip,	1940	.page_flip = &evergreen_page_flip,
1941	.post_page_flip = &evergreen_post_page_flip,	1941	.post_page_flip = &evergreen_post_page_flip,
1942	},	1942	},
1943	};	1943	};
1944		1944
1945	static struct radeon_asic_ring ci_gfx_ring = {	1945	static struct radeon_asic_ring ci_gfx_ring = {
1946	.ib_execute = &cik_ring_ib_execute,	1946	.ib_execute = &cik_ring_ib_execute,
1947	.ib_parse = &cik_ib_parse,	1947	.ib_parse = &cik_ib_parse,
1948	.emit_fence = &cik_fence_gfx_ring_emit,	1948	.emit_fence = &cik_fence_gfx_ring_emit,
1949	.emit_semaphore = &cik_semaphore_ring_emit,	1949	.emit_semaphore = &cik_semaphore_ring_emit,
1950	.cs_parse = NULL,	1950	.cs_parse = NULL,
1951	.ring_test = &cik_ring_test,	1951	.ring_test = &cik_ring_test,
1952	.ib_test = &cik_ib_test,	1952	.ib_test = &cik_ib_test,
1953	.is_lockup = &cik_gfx_is_lockup,	1953	.is_lockup = &cik_gfx_is_lockup,
1954	.vm_flush = &cik_vm_flush,	1954	.vm_flush = &cik_vm_flush,
1955	.get_rptr = &cik_gfx_get_rptr,	1955	.get_rptr = &cik_gfx_get_rptr,
1956	.get_wptr = &cik_gfx_get_wptr,	1956	.get_wptr = &cik_gfx_get_wptr,
1957	.set_wptr = &cik_gfx_set_wptr,	1957	.set_wptr = &cik_gfx_set_wptr,
1958	};	1958	};
1959		1959
1960	static struct radeon_asic_ring ci_cp_ring = {	1960	static struct radeon_asic_ring ci_cp_ring = {
1961	.ib_execute = &cik_ring_ib_execute,	1961	.ib_execute = &cik_ring_ib_execute,
1962	.ib_parse = &cik_ib_parse,	1962	.ib_parse = &cik_ib_parse,
1963	.emit_fence = &cik_fence_compute_ring_emit,	1963	.emit_fence = &cik_fence_compute_ring_emit,
1964	.emit_semaphore = &cik_semaphore_ring_emit,	1964	.emit_semaphore = &cik_semaphore_ring_emit,
1965	.cs_parse = NULL,	1965	.cs_parse = NULL,
1966	.ring_test = &cik_ring_test,	1966	.ring_test = &cik_ring_test,
1967	.ib_test = &cik_ib_test,	1967	.ib_test = &cik_ib_test,
1968	.is_lockup = &cik_gfx_is_lockup,	1968	.is_lockup = &cik_gfx_is_lockup,
1969	.vm_flush = &cik_vm_flush,	1969	.vm_flush = &cik_vm_flush,
1970	.get_rptr = &cik_compute_get_rptr,	1970	.get_rptr = &cik_compute_get_rptr,
1971	.get_wptr = &cik_compute_get_wptr,	1971	.get_wptr = &cik_compute_get_wptr,
1972	.set_wptr = &cik_compute_set_wptr,	1972	.set_wptr = &cik_compute_set_wptr,
1973	};	1973	};
1974		1974
1975	static struct radeon_asic_ring ci_dma_ring = {	1975	static struct radeon_asic_ring ci_dma_ring = {
1976	.ib_execute = &cik_sdma_ring_ib_execute,	1976	.ib_execute = &cik_sdma_ring_ib_execute,
1977	.ib_parse = &cik_ib_parse,	1977	.ib_parse = &cik_ib_parse,
1978	.emit_fence = &cik_sdma_fence_ring_emit,	1978	.emit_fence = &cik_sdma_fence_ring_emit,
1979	.emit_semaphore = &cik_sdma_semaphore_ring_emit,	1979	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
1980	.cs_parse = NULL,	1980	.cs_parse = NULL,
1981	.ring_test = &cik_sdma_ring_test,	1981	.ring_test = &cik_sdma_ring_test,
1982	.ib_test = &cik_sdma_ib_test,	1982	.ib_test = &cik_sdma_ib_test,
1983	.is_lockup = &cik_sdma_is_lockup,	1983	.is_lockup = &cik_sdma_is_lockup,
1984	.vm_flush = &cik_dma_vm_flush,	1984	.vm_flush = &cik_dma_vm_flush,
1985	.get_rptr = &cik_sdma_get_rptr,	1985	.get_rptr = &cik_sdma_get_rptr,
1986	.get_wptr = &cik_sdma_get_wptr,	1986	.get_wptr = &cik_sdma_get_wptr,
1987	.set_wptr = &cik_sdma_set_wptr,	1987	.set_wptr = &cik_sdma_set_wptr,
1988	};	1988	};
1989		1989
1990	static struct radeon_asic_ring ci_vce_ring = {	1990	static struct radeon_asic_ring ci_vce_ring = {
1991	.ib_execute = &radeon_vce_ib_execute,	1991	.ib_execute = &radeon_vce_ib_execute,
1992	.emit_fence = &radeon_vce_fence_emit,	1992	.emit_fence = &radeon_vce_fence_emit,
1993	.emit_semaphore = &radeon_vce_semaphore_emit,	1993	.emit_semaphore = &radeon_vce_semaphore_emit,
1994	.cs_parse = &radeon_vce_cs_parse,	1994	.cs_parse = &radeon_vce_cs_parse,
1995	.ring_test = &radeon_vce_ring_test,	1995	.ring_test = &radeon_vce_ring_test,
1996	.ib_test = &radeon_vce_ib_test,	1996	.ib_test = &radeon_vce_ib_test,
1997	.is_lockup = &radeon_ring_test_lockup,	1997	.is_lockup = &radeon_ring_test_lockup,
1998	.get_rptr = &vce_v1_0_get_rptr,	1998	.get_rptr = &vce_v1_0_get_rptr,
1999	.get_wptr = &vce_v1_0_get_wptr,	1999	.get_wptr = &vce_v1_0_get_wptr,
2000	.set_wptr = &vce_v1_0_set_wptr,	2000	.set_wptr = &vce_v1_0_set_wptr,
2001	};	2001	};
2002		2002
2003	static struct radeon_asic ci_asic = {	2003	static struct radeon_asic ci_asic = {
2004	.init = &cik_init,	2004	.init = &cik_init,
2005	.fini = &cik_fini,	2005	.fini = &cik_fini,
2006	.suspend = &cik_suspend,	2006	.suspend = &cik_suspend,
2007	.resume = &cik_resume,	2007	.resume = &cik_resume,
2008	.asic_reset = &cik_asic_reset,	2008	.asic_reset = &cik_asic_reset,
2009	.vga_set_state = &r600_vga_set_state,	2009	.vga_set_state = &r600_vga_set_state,
2010	.ioctl_wait_idle = NULL,	2010	.ioctl_wait_idle = NULL,
2011	.gui_idle = &r600_gui_idle,	2011	.gui_idle = &r600_gui_idle,
2012	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	2012	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2013	.get_xclk = &cik_get_xclk,	2013	.get_xclk = &cik_get_xclk,
2014	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,	2014	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2015	.gart = {	2015	.gart = {
2016	.tlb_flush = &cik_pcie_gart_tlb_flush,	2016	.tlb_flush = &cik_pcie_gart_tlb_flush,
2017	.set_page = &rs600_gart_set_page,	2017	.set_page = &rs600_gart_set_page,
2018	},	2018	},
2019	.vm = {	2019	.vm = {
2020	.init = &cik_vm_init,	2020	.init = &cik_vm_init,
2021	.fini = &cik_vm_fini,	2021	.fini = &cik_vm_fini,
2022	.set_page = &cik_sdma_vm_set_page,	2022	.set_page = &cik_sdma_vm_set_page,
2023	},	2023	},
2024	.ring = {	2024	.ring = {
2025	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,	2025	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2026	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,	2026	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2027	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,	2027	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2028	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,	2028	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2029	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,	2029	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2030	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	2030	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2031	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,	2031	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2032	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,	2032	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2033	},	2033	},
2034	.irq = {	2034	.irq = {
2035	.set = &cik_irq_set,	2035	.set = &cik_irq_set,
2036	.process = &cik_irq_process,	2036	.process = &cik_irq_process,
2037	},	2037	},
2038	.display = {	2038	.display = {
2039	.bandwidth_update = &dce8_bandwidth_update,	2039	.bandwidth_update = &dce8_bandwidth_update,
2040	.get_vblank_counter = &evergreen_get_vblank_counter,	2040	.get_vblank_counter = &evergreen_get_vblank_counter,
2041	.wait_for_vblank = &dce4_wait_for_vblank,	2041	.wait_for_vblank = &dce4_wait_for_vblank,
2042	.set_backlight_level = &atombios_set_backlight_level,	2042	.set_backlight_level = &atombios_set_backlight_level,
2043	.get_backlight_level = &atombios_get_backlight_level,	2043	.get_backlight_level = &atombios_get_backlight_level,
2044	.hdmi_enable = &evergreen_hdmi_enable,	2044	.hdmi_enable = &evergreen_hdmi_enable,
2045	.hdmi_setmode = &evergreen_hdmi_setmode,	2045	.hdmi_setmode = &evergreen_hdmi_setmode,
2046	},	2046	},
2047	.copy = {	2047	.copy = {
2048	.blit = &cik_copy_cpdma,	2048	.blit = &cik_copy_cpdma,
2049	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	2049	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2050	.dma = &cik_copy_dma,	2050	.dma = &cik_copy_dma,
2051	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	2051	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2052	.copy = &cik_copy_dma,	2052	.copy = &cik_copy_cpdma,
2053	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	2053	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2054	},	2054	},
2055	.surface = {	2055	.surface = {
2056	.set_reg = r600_set_surface_reg,	2056	.set_reg = r600_set_surface_reg,
2057	.clear_reg = r600_clear_surface_reg,	2057	.clear_reg = r600_clear_surface_reg,
2058	},	2058	},
2059	.hpd = {	2059	.hpd = {
2060	.init = &evergreen_hpd_init,	2060	.init = &evergreen_hpd_init,
2061	.fini = &evergreen_hpd_fini,	2061	.fini = &evergreen_hpd_fini,
2062	.sense = &evergreen_hpd_sense,	2062	.sense = &evergreen_hpd_sense,
2063	.set_polarity = &evergreen_hpd_set_polarity,	2063	.set_polarity = &evergreen_hpd_set_polarity,
2064	},	2064	},
2065	.pm = {	2065	.pm = {
2066	.misc = &evergreen_pm_misc,	2066	.misc = &evergreen_pm_misc,
2067	.prepare = &evergreen_pm_prepare,	2067	.prepare = &evergreen_pm_prepare,
2068	.finish = &evergreen_pm_finish,	2068	.finish = &evergreen_pm_finish,
2069	.init_profile = &sumo_pm_init_profile,	2069	.init_profile = &sumo_pm_init_profile,
2070	.get_dynpm_state = &r600_pm_get_dynpm_state,	2070	.get_dynpm_state = &r600_pm_get_dynpm_state,
2071	.get_engine_clock = &radeon_atom_get_engine_clock,	2071	.get_engine_clock = &radeon_atom_get_engine_clock,
2072	.set_engine_clock = &radeon_atom_set_engine_clock,	2072	.set_engine_clock = &radeon_atom_set_engine_clock,
2073	.get_memory_clock = &radeon_atom_get_memory_clock,	2073	.get_memory_clock = &radeon_atom_get_memory_clock,
2074	.set_memory_clock = &radeon_atom_set_memory_clock,	2074	.set_memory_clock = &radeon_atom_set_memory_clock,
2075	.get_pcie_lanes = NULL,	2075	.get_pcie_lanes = NULL,
2076	.set_pcie_lanes = NULL,	2076	.set_pcie_lanes = NULL,
2077	.set_clock_gating = NULL,	2077	.set_clock_gating = NULL,
2078	.set_uvd_clocks = &cik_set_uvd_clocks,	2078	.set_uvd_clocks = &cik_set_uvd_clocks,
2079	.set_vce_clocks = &cik_set_vce_clocks,	2079	.set_vce_clocks = &cik_set_vce_clocks,
2080	.get_temperature = &ci_get_temp,	2080	.get_temperature = &ci_get_temp,
2081	},	2081	},
2082	.dpm = {	2082	.dpm = {
2083	.init = &ci_dpm_init,	2083	.init = &ci_dpm_init,
2084	.setup_asic = &ci_dpm_setup_asic,	2084	.setup_asic = &ci_dpm_setup_asic,
2085	.enable = &ci_dpm_enable,	2085	.enable = &ci_dpm_enable,
2086	.late_enable = &ci_dpm_late_enable,	2086	.late_enable = &ci_dpm_late_enable,
2087	.disable = &ci_dpm_disable,	2087	.disable = &ci_dpm_disable,
2088	.pre_set_power_state = &ci_dpm_pre_set_power_state,	2088	.pre_set_power_state = &ci_dpm_pre_set_power_state,
2089	.set_power_state = &ci_dpm_set_power_state,	2089	.set_power_state = &ci_dpm_set_power_state,
2090	.post_set_power_state = &ci_dpm_post_set_power_state,	2090	.post_set_power_state = &ci_dpm_post_set_power_state,
2091	.display_configuration_changed = &ci_dpm_display_configuration_changed,	2091	.display_configuration_changed = &ci_dpm_display_configuration_changed,
2092	.fini = &ci_dpm_fini,	2092	.fini = &ci_dpm_fini,
2093	.get_sclk = &ci_dpm_get_sclk,	2093	.get_sclk = &ci_dpm_get_sclk,
2094	.get_mclk = &ci_dpm_get_mclk,	2094	.get_mclk = &ci_dpm_get_mclk,
2095	.print_power_state = &ci_dpm_print_power_state,	2095	.print_power_state = &ci_dpm_print_power_state,
2096	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,	2096	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2097	.force_performance_level = &ci_dpm_force_performance_level,	2097	.force_performance_level = &ci_dpm_force_performance_level,
2098	.vblank_too_short = &ci_dpm_vblank_too_short,	2098	.vblank_too_short = &ci_dpm_vblank_too_short,
2099	.powergate_uvd = &ci_dpm_powergate_uvd,	2099	.powergate_uvd = &ci_dpm_powergate_uvd,
2100	},	2100	},
2101	.pflip = {	2101	.pflip = {
2102	.pre_page_flip = &evergreen_pre_page_flip,	2102	.pre_page_flip = &evergreen_pre_page_flip,
2103	.page_flip = &evergreen_page_flip,	2103	.page_flip = &evergreen_page_flip,
2104	.post_page_flip = &evergreen_post_page_flip,	2104	.post_page_flip = &evergreen_post_page_flip,
2105	},	2105	},
2106	};	2106	};
2107		2107
2108	static struct radeon_asic kv_asic = {	2108	static struct radeon_asic kv_asic = {
2109	.init = &cik_init,	2109	.init = &cik_init,
2110	.fini = &cik_fini,	2110	.fini = &cik_fini,
2111	.suspend = &cik_suspend,	2111	.suspend = &cik_suspend,
2112	.resume = &cik_resume,	2112	.resume = &cik_resume,
2113	.asic_reset = &cik_asic_reset,	2113	.asic_reset = &cik_asic_reset,
2114	.vga_set_state = &r600_vga_set_state,	2114	.vga_set_state = &r600_vga_set_state,
2115	.ioctl_wait_idle = NULL,	2115	.ioctl_wait_idle = NULL,
2116	.gui_idle = &r600_gui_idle,	2116	.gui_idle = &r600_gui_idle,
2117	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	2117	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2118	.get_xclk = &cik_get_xclk,	2118	.get_xclk = &cik_get_xclk,
2119	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,	2119	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2120	.gart = {	2120	.gart = {
2121	.tlb_flush = &cik_pcie_gart_tlb_flush,	2121	.tlb_flush = &cik_pcie_gart_tlb_flush,
2122	.set_page = &rs600_gart_set_page,	2122	.set_page = &rs600_gart_set_page,
2123	},	2123	},
2124	.vm = {	2124	.vm = {
2125	.init = &cik_vm_init,	2125	.init = &cik_vm_init,
2126	.fini = &cik_vm_fini,	2126	.fini = &cik_vm_fini,
2127	.set_page = &cik_sdma_vm_set_page,	2127	.set_page = &cik_sdma_vm_set_page,
2128	},	2128	},
2129	.ring = {	2129	.ring = {
2130	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,	2130	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2131	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,	2131	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2132	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,	2132	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2133	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,	2133	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2134	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,	2134	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2135	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	2135	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2136	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,	2136	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2137	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,	2137	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2138	},	2138	},
2139	.irq = {	2139	.irq = {
2140	.set = &cik_irq_set,	2140	.set = &cik_irq_set,
2141	.process = &cik_irq_process,	2141	.process = &cik_irq_process,
2142	},	2142	},
2143	.display = {	2143	.display = {
2144	.bandwidth_update = &dce8_bandwidth_update,	2144	.bandwidth_update = &dce8_bandwidth_update,
2145	.get_vblank_counter = &evergreen_get_vblank_counter,	2145	.get_vblank_counter = &evergreen_get_vblank_counter,
2146	.wait_for_vblank = &dce4_wait_for_vblank,	2146	.wait_for_vblank = &dce4_wait_for_vblank,
2147	.set_backlight_level = &atombios_set_backlight_level,	2147	.set_backlight_level = &atombios_set_backlight_level,
2148	.get_backlight_level = &atombios_get_backlight_level,	2148	.get_backlight_level = &atombios_get_backlight_level,
2149	.hdmi_enable = &evergreen_hdmi_enable,	2149	.hdmi_enable = &evergreen_hdmi_enable,
2150	.hdmi_setmode = &evergreen_hdmi_setmode,	2150	.hdmi_setmode = &evergreen_hdmi_setmode,
2151	},	2151	},
2152	.copy = {	2152	.copy = {
2153	.blit = &cik_copy_cpdma,	2153	.blit = &cik_copy_cpdma,
2154	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	2154	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2155	.dma = &cik_copy_dma,	2155	.dma = &cik_copy_dma,
2156	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	2156	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2157	.copy = &cik_copy_dma,	2157	.copy = &cik_copy_dma,
2158	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	2158	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2159	},	2159	},
2160	.surface = {	2160	.surface = {
2161	.set_reg = r600_set_surface_reg,	2161	.set_reg = r600_set_surface_reg,
2162	.clear_reg = r600_clear_surface_reg,	2162	.clear_reg = r600_clear_surface_reg,
2163	},	2163	},
2164	.hpd = {	2164	.hpd = {
2165	.init = &evergreen_hpd_init,	2165	.init = &evergreen_hpd_init,
2166	.fini = &evergreen_hpd_fini,	2166	.fini = &evergreen_hpd_fini,
2167	.sense = &evergreen_hpd_sense,	2167	.sense = &evergreen_hpd_sense,
2168	.set_polarity = &evergreen_hpd_set_polarity,	2168	.set_polarity = &evergreen_hpd_set_polarity,
2169	},	2169	},
2170	.pm = {	2170	.pm = {
2171	.misc = &evergreen_pm_misc,	2171	.misc = &evergreen_pm_misc,
2172	.prepare = &evergreen_pm_prepare,	2172	.prepare = &evergreen_pm_prepare,
2173	.finish = &evergreen_pm_finish,	2173	.finish = &evergreen_pm_finish,
2174	.init_profile = &sumo_pm_init_profile,	2174	.init_profile = &sumo_pm_init_profile,
2175	.get_dynpm_state = &r600_pm_get_dynpm_state,	2175	.get_dynpm_state = &r600_pm_get_dynpm_state,
2176	.get_engine_clock = &radeon_atom_get_engine_clock,	2176	.get_engine_clock = &radeon_atom_get_engine_clock,
2177	.set_engine_clock = &radeon_atom_set_engine_clock,	2177	.set_engine_clock = &radeon_atom_set_engine_clock,
2178	.get_memory_clock = &radeon_atom_get_memory_clock,	2178	.get_memory_clock = &radeon_atom_get_memory_clock,
2179	.set_memory_clock = &radeon_atom_set_memory_clock,	2179	.set_memory_clock = &radeon_atom_set_memory_clock,
2180	.get_pcie_lanes = NULL,	2180	.get_pcie_lanes = NULL,
2181	.set_pcie_lanes = NULL,	2181	.set_pcie_lanes = NULL,
2182	.set_clock_gating = NULL,	2182	.set_clock_gating = NULL,
2183	.set_uvd_clocks = &cik_set_uvd_clocks,	2183	.set_uvd_clocks = &cik_set_uvd_clocks,
2184	.set_vce_clocks = &cik_set_vce_clocks,	2184	.set_vce_clocks = &cik_set_vce_clocks,
2185	.get_temperature = &kv_get_temp,	2185	.get_temperature = &kv_get_temp,
2186	},	2186	},
2187	.dpm = {	2187	.dpm = {
2188	.init = &kv_dpm_init,	2188	.init = &kv_dpm_init,
2189	.setup_asic = &kv_dpm_setup_asic,	2189	.setup_asic = &kv_dpm_setup_asic,
2190	.enable = &kv_dpm_enable,	2190	.enable = &kv_dpm_enable,
2191	.late_enable = &kv_dpm_late_enable,	2191	.late_enable = &kv_dpm_late_enable,
2192	.disable = &kv_dpm_disable,	2192	.disable = &kv_dpm_disable,
2193	.pre_set_power_state = &kv_dpm_pre_set_power_state,	2193	.pre_set_power_state = &kv_dpm_pre_set_power_state,
2194	.set_power_state = &kv_dpm_set_power_state,	2194	.set_power_state = &kv_dpm_set_power_state,
2195	.post_set_power_state = &kv_dpm_post_set_power_state,	2195	.post_set_power_state = &kv_dpm_post_set_power_state,
2196	.display_configuration_changed = &kv_dpm_display_configuration_changed,	2196	.display_configuration_changed = &kv_dpm_display_configuration_changed,
2197	.fini = &kv_dpm_fini,	2197	.fini = &kv_dpm_fini,
2198	.get_sclk = &kv_dpm_get_sclk,	2198	.get_sclk = &kv_dpm_get_sclk,
2199	.get_mclk = &kv_dpm_get_mclk,	2199	.get_mclk = &kv_dpm_get_mclk,
2200	.print_power_state = &kv_dpm_print_power_state,	2200	.print_power_state = &kv_dpm_print_power_state,
2201	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,	2201	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2202	.force_performance_level = &kv_dpm_force_performance_level,	2202	.force_performance_level = &kv_dpm_force_performance_level,
2203	.powergate_uvd = &kv_dpm_powergate_uvd,	2203	.powergate_uvd = &kv_dpm_powergate_uvd,
2204	.enable_bapm = &kv_dpm_enable_bapm,	2204	.enable_bapm = &kv_dpm_enable_bapm,
2205	},	2205	},
2206	.pflip = {	2206	.pflip = {
2207	.pre_page_flip = &evergreen_pre_page_flip,	2207	.pre_page_flip = &evergreen_pre_page_flip,
2208	.page_flip = &evergreen_page_flip,	2208	.page_flip = &evergreen_page_flip,
2209	.post_page_flip = &evergreen_post_page_flip,	2209	.post_page_flip = &evergreen_post_page_flip,
2210	},	2210	},
2211	};	2211	};
2212		2212
2213	/**	2213	/**
2214	* radeon_asic_init - register asic specific callbacks	2214	* radeon_asic_init - register asic specific callbacks
2215	*	2215	*
2216	* @rdev: radeon device pointer	2216	* @rdev: radeon device pointer
2217	*	2217	*
2218	* Registers the appropriate asic specific callbacks for each	2218	* Registers the appropriate asic specific callbacks for each
2219	* chip family. Also sets other asics specific info like the number	2219	* chip family. Also sets other asics specific info like the number
2220	* of crtcs and the register aperture accessors (all asics).	2220	* of crtcs and the register aperture accessors (all asics).
2221	* Returns 0 for success.	2221	* Returns 0 for success.
2222	*/	2222	*/
2223	int radeon_asic_init(struct radeon_device *rdev)	2223	int radeon_asic_init(struct radeon_device *rdev)
2224	{	2224	{
2225	radeon_register_accessor_init(rdev);	2225	radeon_register_accessor_init(rdev);
2226		2226
2227	/* set the number of crtcs */	2227	/* set the number of crtcs */
2228	if (rdev->flags & RADEON_SINGLE_CRTC)	2228	if (rdev->flags & RADEON_SINGLE_CRTC)
2229	rdev->num_crtc = 1;	2229	rdev->num_crtc = 1;
2230	else	2230	else
2231	rdev->num_crtc = 2;	2231	rdev->num_crtc = 2;
2232		2232
2233	rdev->has_uvd = false;	2233	rdev->has_uvd = false;
2234		2234
2235	switch (rdev->family) {	2235	switch (rdev->family) {
2236	case CHIP_R100:	2236	case CHIP_R100:
2237	case CHIP_RV100:	2237	case CHIP_RV100:
2238	case CHIP_RS100:	2238	case CHIP_RS100:
2239	case CHIP_RV200:	2239	case CHIP_RV200:
2240	case CHIP_RS200:	2240	case CHIP_RS200:
2241	rdev->asic = &r100_asic;	2241	rdev->asic = &r100_asic;
2242	break;	2242	break;
2243	case CHIP_R200:	2243	case CHIP_R200:
2244	case CHIP_RV250:	2244	case CHIP_RV250:
2245	case CHIP_RS300:	2245	case CHIP_RS300:
2246	case CHIP_RV280:	2246	case CHIP_RV280:
2247	rdev->asic = &r200_asic;	2247	rdev->asic = &r200_asic;
2248	break;	2248	break;
2249	case CHIP_R300:	2249	case CHIP_R300:
2250	case CHIP_R350:	2250	case CHIP_R350:
2251	case CHIP_RV350:	2251	case CHIP_RV350:
2252	case CHIP_RV380:	2252	case CHIP_RV380:
2253	if (rdev->flags & RADEON_IS_PCIE)	2253	if (rdev->flags & RADEON_IS_PCIE)
2254	rdev->asic = &r300_asic_pcie;	2254	rdev->asic = &r300_asic_pcie;
2255	else	2255	else
2256	rdev->asic = &r300_asic;	2256	rdev->asic = &r300_asic;
2257	break;	2257	break;
2258	case CHIP_R420:	2258	case CHIP_R420:
2259	case CHIP_R423:	2259	case CHIP_R423:
2260	case CHIP_RV410:	2260	case CHIP_RV410:
2261	rdev->asic = &r420_asic;	2261	rdev->asic = &r420_asic;
2262	/* handle macs */	2262	/* handle macs */
2263	if (rdev->bios == NULL) {	2263	if (rdev->bios == NULL) {
2264	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;	2264	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2265	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;	2265	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2266	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;	2266	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2267	rdev->asic->pm.set_memory_clock = NULL;	2267	rdev->asic->pm.set_memory_clock = NULL;
2268	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;	2268	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2269	}	2269	}
2270	break;	2270	break;
2271	case CHIP_RS400:	2271	case CHIP_RS400:
2272	case CHIP_RS480:	2272	case CHIP_RS480:
2273	rdev->asic = &rs400_asic;	2273	rdev->asic = &rs400_asic;
2274	break;	2274	break;
2275	case CHIP_RS600:	2275	case CHIP_RS600:
2276	rdev->asic = &rs600_asic;	2276	rdev->asic = &rs600_asic;
2277	break;	2277	break;
2278	case CHIP_RS690:	2278	case CHIP_RS690:
2279	case CHIP_RS740:	2279	case CHIP_RS740:
2280	rdev->asic = &rs690_asic;	2280	rdev->asic = &rs690_asic;
2281	break;	2281	break;
2282	case CHIP_RV515:	2282	case CHIP_RV515:
2283	rdev->asic = &rv515_asic;	2283	rdev->asic = &rv515_asic;
2284	break;	2284	break;
2285	case CHIP_R520:	2285	case CHIP_R520:
2286	case CHIP_RV530:	2286	case CHIP_RV530:
2287	case CHIP_RV560:	2287	case CHIP_RV560:
2288	case CHIP_RV570:	2288	case CHIP_RV570:
2289	case CHIP_R580:	2289	case CHIP_R580:
2290	rdev->asic = &r520_asic;	2290	rdev->asic = &r520_asic;
2291	break;	2291	break;
2292	case CHIP_R600:	2292	case CHIP_R600:
2293	rdev->asic = &r600_asic;	2293	rdev->asic = &r600_asic;
2294	break;	2294	break;
2295	case CHIP_RV610:	2295	case CHIP_RV610:
2296	case CHIP_RV630:	2296	case CHIP_RV630:
2297	case CHIP_RV620:	2297	case CHIP_RV620:
2298	case CHIP_RV635:	2298	case CHIP_RV635:
2299	case CHIP_RV670:	2299	case CHIP_RV670:
2300	rdev->asic = &rv6xx_asic;	2300	rdev->asic = &rv6xx_asic;
2301	rdev->has_uvd = true;	2301	rdev->has_uvd = true;
2302	break;	2302	break;
2303	case CHIP_RS780:	2303	case CHIP_RS780:
2304	case CHIP_RS880:	2304	case CHIP_RS880:
2305	rdev->asic = &rs780_asic;	2305	rdev->asic = &rs780_asic;
2306	rdev->has_uvd = true;	2306	rdev->has_uvd = true;
2307	break;	2307	break;
2308	case CHIP_RV770:	2308	case CHIP_RV770:
2309	case CHIP_RV730:	2309	case CHIP_RV730:
2310	case CHIP_RV710:	2310	case CHIP_RV710:
2311	case CHIP_RV740:	2311	case CHIP_RV740:
2312	rdev->asic = &rv770_asic;	2312	rdev->asic = &rv770_asic;
2313	rdev->has_uvd = true;	2313	rdev->has_uvd = true;
2314	break;	2314	break;
2315	case CHIP_CEDAR:	2315	case CHIP_CEDAR:
2316	case CHIP_REDWOOD:	2316	case CHIP_REDWOOD:
2317	case CHIP_JUNIPER:	2317	case CHIP_JUNIPER:
2318	case CHIP_CYPRESS:	2318	case CHIP_CYPRESS:
2319	case CHIP_HEMLOCK:	2319	case CHIP_HEMLOCK:
2320	/* set num crtcs */	2320	/* set num crtcs */
2321	if (rdev->family == CHIP_CEDAR)	2321	if (rdev->family == CHIP_CEDAR)
2322	rdev->num_crtc = 4;	2322	rdev->num_crtc = 4;
2323	else	2323	else
2324	rdev->num_crtc = 6;	2324	rdev->num_crtc = 6;
2325	rdev->asic = &evergreen_asic;	2325	rdev->asic = &evergreen_asic;
2326	rdev->has_uvd = true;	2326	rdev->has_uvd = true;
2327	break;	2327	break;
2328	case CHIP_PALM:	2328	case CHIP_PALM:
2329	case CHIP_SUMO:	2329	case CHIP_SUMO:
2330	case CHIP_SUMO2:	2330	case CHIP_SUMO2:
2331	rdev->asic = &sumo_asic;	2331	rdev->asic = &sumo_asic;
2332	rdev->has_uvd = true;	2332	rdev->has_uvd = true;
2333	break;	2333	break;
2334	case CHIP_BARTS:	2334	case CHIP_BARTS:
2335	case CHIP_TURKS:	2335	case CHIP_TURKS:
2336	case CHIP_CAICOS:	2336	case CHIP_CAICOS:
2337	/* set num crtcs */	2337	/* set num crtcs */
2338	if (rdev->family == CHIP_CAICOS)	2338	if (rdev->family == CHIP_CAICOS)
2339	rdev->num_crtc = 4;	2339	rdev->num_crtc = 4;
2340	else	2340	else
2341	rdev->num_crtc = 6;	2341	rdev->num_crtc = 6;
2342	rdev->asic = &btc_asic;	2342	rdev->asic = &btc_asic;
2343	rdev->has_uvd = true;	2343	rdev->has_uvd = true;
2344	break;	2344	break;
2345	case CHIP_CAYMAN:	2345	case CHIP_CAYMAN:
2346	rdev->asic = &cayman_asic;	2346	rdev->asic = &cayman_asic;
2347	/* set num crtcs */	2347	/* set num crtcs */
2348	rdev->num_crtc = 6;	2348	rdev->num_crtc = 6;
2349	rdev->has_uvd = true;	2349	rdev->has_uvd = true;
2350	break;	2350	break;
2351	case CHIP_ARUBA:	2351	case CHIP_ARUBA:
2352	rdev->asic = &trinity_asic;	2352	rdev->asic = &trinity_asic;
2353	/* set num crtcs */	2353	/* set num crtcs */
2354	rdev->num_crtc = 4;	2354	rdev->num_crtc = 4;
2355	rdev->has_uvd = true;	2355	rdev->has_uvd = true;
2356	break;	2356	break;
2357	case CHIP_TAHITI:	2357	case CHIP_TAHITI:
2358	case CHIP_PITCAIRN:	2358	case CHIP_PITCAIRN:
2359	case CHIP_VERDE:	2359	case CHIP_VERDE:
2360	case CHIP_OLAND:	2360	case CHIP_OLAND:
2361	case CHIP_HAINAN:	2361	case CHIP_HAINAN:
2362	rdev->asic = &si_asic;	2362	rdev->asic = &si_asic;
2363	/* set num crtcs */	2363	/* set num crtcs */
2364	if (rdev->family == CHIP_HAINAN)	2364	if (rdev->family == CHIP_HAINAN)
2365	rdev->num_crtc = 0;	2365	rdev->num_crtc = 0;
2366	else if (rdev->family == CHIP_OLAND)	2366	else if (rdev->family == CHIP_OLAND)
2367	rdev->num_crtc = 2;	2367	rdev->num_crtc = 2;
2368	else	2368	else
2369	rdev->num_crtc = 6;	2369	rdev->num_crtc = 6;
2370	if (rdev->family == CHIP_HAINAN)	2370	if (rdev->family == CHIP_HAINAN)
2371	rdev->has_uvd = false;	2371	rdev->has_uvd = false;
2372	else	2372	else
2373	rdev->has_uvd = true;	2373	rdev->has_uvd = true;
2374	switch (rdev->family) {	2374	switch (rdev->family) {
2375	case CHIP_TAHITI:	2375	case CHIP_TAHITI:
2376	rdev->cg_flags =	2376	rdev->cg_flags =
2377	RADEON_CG_SUPPORT_GFX_MGCG \|	2377	RADEON_CG_SUPPORT_GFX_MGCG \|
2378	RADEON_CG_SUPPORT_GFX_MGLS \|	2378	RADEON_CG_SUPPORT_GFX_MGLS \|
2379	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2379	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2380	RADEON_CG_SUPPORT_GFX_CGLS \|	2380	RADEON_CG_SUPPORT_GFX_CGLS \|
2381	RADEON_CG_SUPPORT_GFX_CGTS \|	2381	RADEON_CG_SUPPORT_GFX_CGTS \|
2382	RADEON_CG_SUPPORT_GFX_CP_LS \|	2382	RADEON_CG_SUPPORT_GFX_CP_LS \|
2383	RADEON_CG_SUPPORT_MC_MGCG \|	2383	RADEON_CG_SUPPORT_MC_MGCG \|
2384	RADEON_CG_SUPPORT_SDMA_MGCG \|	2384	RADEON_CG_SUPPORT_SDMA_MGCG \|
2385	RADEON_CG_SUPPORT_BIF_LS \|	2385	RADEON_CG_SUPPORT_BIF_LS \|
2386	RADEON_CG_SUPPORT_VCE_MGCG \|	2386	RADEON_CG_SUPPORT_VCE_MGCG \|
2387	RADEON_CG_SUPPORT_UVD_MGCG \|	2387	RADEON_CG_SUPPORT_UVD_MGCG \|
2388	RADEON_CG_SUPPORT_HDP_LS \|	2388	RADEON_CG_SUPPORT_HDP_LS \|
2389	RADEON_CG_SUPPORT_HDP_MGCG;	2389	RADEON_CG_SUPPORT_HDP_MGCG;
2390	rdev->pg_flags = 0;	2390	rdev->pg_flags = 0;
2391	break;	2391	break;
2392	case CHIP_PITCAIRN:	2392	case CHIP_PITCAIRN:
2393	rdev->cg_flags =	2393	rdev->cg_flags =
2394	RADEON_CG_SUPPORT_GFX_MGCG \|	2394	RADEON_CG_SUPPORT_GFX_MGCG \|
2395	RADEON_CG_SUPPORT_GFX_MGLS \|	2395	RADEON_CG_SUPPORT_GFX_MGLS \|
2396	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2396	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2397	RADEON_CG_SUPPORT_GFX_CGLS \|	2397	RADEON_CG_SUPPORT_GFX_CGLS \|
2398	RADEON_CG_SUPPORT_GFX_CGTS \|	2398	RADEON_CG_SUPPORT_GFX_CGTS \|
2399	RADEON_CG_SUPPORT_GFX_CP_LS \|	2399	RADEON_CG_SUPPORT_GFX_CP_LS \|
2400	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2400	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2401	RADEON_CG_SUPPORT_MC_LS \|	2401	RADEON_CG_SUPPORT_MC_LS \|
2402	RADEON_CG_SUPPORT_MC_MGCG \|	2402	RADEON_CG_SUPPORT_MC_MGCG \|
2403	RADEON_CG_SUPPORT_SDMA_MGCG \|	2403	RADEON_CG_SUPPORT_SDMA_MGCG \|
2404	RADEON_CG_SUPPORT_BIF_LS \|	2404	RADEON_CG_SUPPORT_BIF_LS \|
2405	RADEON_CG_SUPPORT_VCE_MGCG \|	2405	RADEON_CG_SUPPORT_VCE_MGCG \|
2406	RADEON_CG_SUPPORT_UVD_MGCG \|	2406	RADEON_CG_SUPPORT_UVD_MGCG \|
2407	RADEON_CG_SUPPORT_HDP_LS \|	2407	RADEON_CG_SUPPORT_HDP_LS \|
2408	RADEON_CG_SUPPORT_HDP_MGCG;	2408	RADEON_CG_SUPPORT_HDP_MGCG;
2409	rdev->pg_flags = 0;	2409	rdev->pg_flags = 0;
2410	break;	2410	break;
2411	case CHIP_VERDE:	2411	case CHIP_VERDE:
2412	rdev->cg_flags =	2412	rdev->cg_flags =
2413	RADEON_CG_SUPPORT_GFX_MGCG \|	2413	RADEON_CG_SUPPORT_GFX_MGCG \|
2414	RADEON_CG_SUPPORT_GFX_MGLS \|	2414	RADEON_CG_SUPPORT_GFX_MGLS \|
2415	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2415	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2416	RADEON_CG_SUPPORT_GFX_CGLS \|	2416	RADEON_CG_SUPPORT_GFX_CGLS \|
2417	RADEON_CG_SUPPORT_GFX_CGTS \|	2417	RADEON_CG_SUPPORT_GFX_CGTS \|
2418	RADEON_CG_SUPPORT_GFX_CP_LS \|	2418	RADEON_CG_SUPPORT_GFX_CP_LS \|
2419	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2419	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2420	RADEON_CG_SUPPORT_MC_LS \|	2420	RADEON_CG_SUPPORT_MC_LS \|
2421	RADEON_CG_SUPPORT_MC_MGCG \|	2421	RADEON_CG_SUPPORT_MC_MGCG \|
2422	RADEON_CG_SUPPORT_SDMA_MGCG \|	2422	RADEON_CG_SUPPORT_SDMA_MGCG \|
2423	RADEON_CG_SUPPORT_BIF_LS \|	2423	RADEON_CG_SUPPORT_BIF_LS \|
2424	RADEON_CG_SUPPORT_VCE_MGCG \|	2424	RADEON_CG_SUPPORT_VCE_MGCG \|
2425	RADEON_CG_SUPPORT_UVD_MGCG \|	2425	RADEON_CG_SUPPORT_UVD_MGCG \|
2426	RADEON_CG_SUPPORT_HDP_LS \|	2426	RADEON_CG_SUPPORT_HDP_LS \|
2427	RADEON_CG_SUPPORT_HDP_MGCG;	2427	RADEON_CG_SUPPORT_HDP_MGCG;
2428	rdev->pg_flags = 0 \|	2428	rdev->pg_flags = 0 \|
2429	/RADEON_PG_SUPPORT_GFX_PG \| /	2429	/RADEON_PG_SUPPORT_GFX_PG \| /
2430	RADEON_PG_SUPPORT_SDMA;	2430	RADEON_PG_SUPPORT_SDMA;
2431	break;	2431	break;
2432	case CHIP_OLAND:	2432	case CHIP_OLAND:
2433	rdev->cg_flags =	2433	rdev->cg_flags =
2434	RADEON_CG_SUPPORT_GFX_MGCG \|	2434	RADEON_CG_SUPPORT_GFX_MGCG \|
2435	RADEON_CG_SUPPORT_GFX_MGLS \|	2435	RADEON_CG_SUPPORT_GFX_MGLS \|
2436	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2436	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2437	RADEON_CG_SUPPORT_GFX_CGLS \|	2437	RADEON_CG_SUPPORT_GFX_CGLS \|
2438	RADEON_CG_SUPPORT_GFX_CGTS \|	2438	RADEON_CG_SUPPORT_GFX_CGTS \|
2439	RADEON_CG_SUPPORT_GFX_CP_LS \|	2439	RADEON_CG_SUPPORT_GFX_CP_LS \|
2440	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2440	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2441	RADEON_CG_SUPPORT_MC_LS \|	2441	RADEON_CG_SUPPORT_MC_LS \|
2442	RADEON_CG_SUPPORT_MC_MGCG \|	2442	RADEON_CG_SUPPORT_MC_MGCG \|
2443	RADEON_CG_SUPPORT_SDMA_MGCG \|	2443	RADEON_CG_SUPPORT_SDMA_MGCG \|
2444	RADEON_CG_SUPPORT_BIF_LS \|	2444	RADEON_CG_SUPPORT_BIF_LS \|
2445	RADEON_CG_SUPPORT_UVD_MGCG \|	2445	RADEON_CG_SUPPORT_UVD_MGCG \|
2446	RADEON_CG_SUPPORT_HDP_LS \|	2446	RADEON_CG_SUPPORT_HDP_LS \|
2447	RADEON_CG_SUPPORT_HDP_MGCG;	2447	RADEON_CG_SUPPORT_HDP_MGCG;
2448	rdev->pg_flags = 0;	2448	rdev->pg_flags = 0;
2449	break;	2449	break;
2450	case CHIP_HAINAN:	2450	case CHIP_HAINAN:
2451	rdev->cg_flags =	2451	rdev->cg_flags =
2452	RADEON_CG_SUPPORT_GFX_MGCG \|	2452	RADEON_CG_SUPPORT_GFX_MGCG \|
2453	RADEON_CG_SUPPORT_GFX_MGLS \|	2453	RADEON_CG_SUPPORT_GFX_MGLS \|
2454	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2454	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2455	RADEON_CG_SUPPORT_GFX_CGLS \|	2455	RADEON_CG_SUPPORT_GFX_CGLS \|
2456	RADEON_CG_SUPPORT_GFX_CGTS \|	2456	RADEON_CG_SUPPORT_GFX_CGTS \|
2457	RADEON_CG_SUPPORT_GFX_CP_LS \|	2457	RADEON_CG_SUPPORT_GFX_CP_LS \|
2458	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2458	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2459	RADEON_CG_SUPPORT_MC_LS \|	2459	RADEON_CG_SUPPORT_MC_LS \|
2460	RADEON_CG_SUPPORT_MC_MGCG \|	2460	RADEON_CG_SUPPORT_MC_MGCG \|
2461	RADEON_CG_SUPPORT_SDMA_MGCG \|	2461	RADEON_CG_SUPPORT_SDMA_MGCG \|
2462	RADEON_CG_SUPPORT_BIF_LS \|	2462	RADEON_CG_SUPPORT_BIF_LS \|
2463	RADEON_CG_SUPPORT_HDP_LS \|	2463	RADEON_CG_SUPPORT_HDP_LS \|
2464	RADEON_CG_SUPPORT_HDP_MGCG;	2464	RADEON_CG_SUPPORT_HDP_MGCG;
2465	rdev->pg_flags = 0;	2465	rdev->pg_flags = 0;
2466	break;	2466	break;
2467	default:	2467	default:
2468	rdev->cg_flags = 0;	2468	rdev->cg_flags = 0;
2469	rdev->pg_flags = 0;	2469	rdev->pg_flags = 0;
2470	break;	2470	break;
2471	}	2471	}
2472	break;	2472	break;
2473	case CHIP_BONAIRE:	2473	case CHIP_BONAIRE:
2474	case CHIP_HAWAII:	2474	case CHIP_HAWAII:
2475	rdev->asic = &ci_asic;	2475	rdev->asic = &ci_asic;
2476	rdev->num_crtc = 6;	2476	rdev->num_crtc = 6;
2477	rdev->has_uvd = true;	2477	rdev->has_uvd = true;
2478	if (rdev->family == CHIP_BONAIRE) {	2478	if (rdev->family == CHIP_BONAIRE) {
2479	rdev->cg_flags =	2479	rdev->cg_flags =
2480	RADEON_CG_SUPPORT_GFX_MGCG \|	2480	RADEON_CG_SUPPORT_GFX_MGCG \|
2481	RADEON_CG_SUPPORT_GFX_MGLS \|	2481	RADEON_CG_SUPPORT_GFX_MGLS \|
2482	RADEON_CG_SUPPORT_GFX_CGCG \|	2482	RADEON_CG_SUPPORT_GFX_CGCG \|
2483	RADEON_CG_SUPPORT_GFX_CGLS \|	2483	RADEON_CG_SUPPORT_GFX_CGLS \|
2484	RADEON_CG_SUPPORT_GFX_CGTS \|	2484	RADEON_CG_SUPPORT_GFX_CGTS \|
2485	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2485	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2486	RADEON_CG_SUPPORT_GFX_CP_LS \|	2486	RADEON_CG_SUPPORT_GFX_CP_LS \|
2487	RADEON_CG_SUPPORT_MC_LS \|	2487	RADEON_CG_SUPPORT_MC_LS \|
2488	RADEON_CG_SUPPORT_MC_MGCG \|	2488	RADEON_CG_SUPPORT_MC_MGCG \|
2489	RADEON_CG_SUPPORT_SDMA_MGCG \|	2489	RADEON_CG_SUPPORT_SDMA_MGCG \|
2490	RADEON_CG_SUPPORT_SDMA_LS \|	2490	RADEON_CG_SUPPORT_SDMA_LS \|
2491	RADEON_CG_SUPPORT_BIF_LS \|	2491	RADEON_CG_SUPPORT_BIF_LS \|
2492	RADEON_CG_SUPPORT_VCE_MGCG \|	2492	RADEON_CG_SUPPORT_VCE_MGCG \|
2493	RADEON_CG_SUPPORT_UVD_MGCG \|	2493	RADEON_CG_SUPPORT_UVD_MGCG \|
2494	RADEON_CG_SUPPORT_HDP_LS \|	2494	RADEON_CG_SUPPORT_HDP_LS \|
2495	RADEON_CG_SUPPORT_HDP_MGCG;	2495	RADEON_CG_SUPPORT_HDP_MGCG;
2496	rdev->pg_flags = 0;	2496	rdev->pg_flags = 0;
2497	} else {	2497	} else {
2498	rdev->cg_flags =	2498	rdev->cg_flags =
2499	RADEON_CG_SUPPORT_GFX_MGCG \|	2499	RADEON_CG_SUPPORT_GFX_MGCG \|
2500	RADEON_CG_SUPPORT_GFX_MGLS \|	2500	RADEON_CG_SUPPORT_GFX_MGLS \|
2501	RADEON_CG_SUPPORT_GFX_CGCG \|	2501	RADEON_CG_SUPPORT_GFX_CGCG \|
2502	RADEON_CG_SUPPORT_GFX_CGLS \|	2502	RADEON_CG_SUPPORT_GFX_CGLS \|
2503	RADEON_CG_SUPPORT_GFX_CGTS \|	2503	RADEON_CG_SUPPORT_GFX_CGTS \|
2504	RADEON_CG_SUPPORT_GFX_CP_LS \|	2504	RADEON_CG_SUPPORT_GFX_CP_LS \|
2505	RADEON_CG_SUPPORT_MC_LS \|	2505	RADEON_CG_SUPPORT_MC_LS \|
2506	RADEON_CG_SUPPORT_MC_MGCG \|	2506	RADEON_CG_SUPPORT_MC_MGCG \|
2507	RADEON_CG_SUPPORT_SDMA_MGCG \|	2507	RADEON_CG_SUPPORT_SDMA_MGCG \|
2508	RADEON_CG_SUPPORT_SDMA_LS \|	2508	RADEON_CG_SUPPORT_SDMA_LS \|
2509	RADEON_CG_SUPPORT_BIF_LS \|	2509	RADEON_CG_SUPPORT_BIF_LS \|
2510	RADEON_CG_SUPPORT_VCE_MGCG \|	2510	RADEON_CG_SUPPORT_VCE_MGCG \|
2511	RADEON_CG_SUPPORT_UVD_MGCG \|	2511	RADEON_CG_SUPPORT_UVD_MGCG \|
2512	RADEON_CG_SUPPORT_HDP_LS \|	2512	RADEON_CG_SUPPORT_HDP_LS \|
2513	RADEON_CG_SUPPORT_HDP_MGCG;	2513	RADEON_CG_SUPPORT_HDP_MGCG;
2514	rdev->pg_flags = 0;	2514	rdev->pg_flags = 0;
2515	}	2515	}
2516	break;	2516	break;
2517	case CHIP_KAVERI:	2517	case CHIP_KAVERI:
2518	case CHIP_KABINI:	2518	case CHIP_KABINI:
2519	case CHIP_MULLINS:	2519	case CHIP_MULLINS:
2520	rdev->asic = &kv_asic;	2520	rdev->asic = &kv_asic;
2521	/* set num crtcs */	2521	/* set num crtcs */
2522	if (rdev->family == CHIP_KAVERI) {	2522	if (rdev->family == CHIP_KAVERI) {
2523	rdev->num_crtc = 4;	2523	rdev->num_crtc = 4;
2524	rdev->cg_flags =	2524	rdev->cg_flags =
2525	RADEON_CG_SUPPORT_GFX_MGCG \|	2525	RADEON_CG_SUPPORT_GFX_MGCG \|
2526	RADEON_CG_SUPPORT_GFX_MGLS \|	2526	RADEON_CG_SUPPORT_GFX_MGLS \|
2527	RADEON_CG_SUPPORT_GFX_CGCG \|	2527	RADEON_CG_SUPPORT_GFX_CGCG \|
2528	RADEON_CG_SUPPORT_GFX_CGLS \|	2528	RADEON_CG_SUPPORT_GFX_CGLS \|
2529	RADEON_CG_SUPPORT_GFX_CGTS \|	2529	RADEON_CG_SUPPORT_GFX_CGTS \|
2530	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2530	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2531	RADEON_CG_SUPPORT_GFX_CP_LS \|	2531	RADEON_CG_SUPPORT_GFX_CP_LS \|
2532	RADEON_CG_SUPPORT_SDMA_MGCG \|	2532	RADEON_CG_SUPPORT_SDMA_MGCG \|
2533	RADEON_CG_SUPPORT_SDMA_LS \|	2533	RADEON_CG_SUPPORT_SDMA_LS \|
2534	RADEON_CG_SUPPORT_BIF_LS \|	2534	RADEON_CG_SUPPORT_BIF_LS \|
2535	RADEON_CG_SUPPORT_VCE_MGCG \|	2535	RADEON_CG_SUPPORT_VCE_MGCG \|
2536	RADEON_CG_SUPPORT_UVD_MGCG \|	2536	RADEON_CG_SUPPORT_UVD_MGCG \|
2537	RADEON_CG_SUPPORT_HDP_LS \|	2537	RADEON_CG_SUPPORT_HDP_LS \|
2538	RADEON_CG_SUPPORT_HDP_MGCG;	2538	RADEON_CG_SUPPORT_HDP_MGCG;
2539	rdev->pg_flags = 0;	2539	rdev->pg_flags = 0;
2540	/*RADEON_PG_SUPPORT_GFX_PG \|	2540	/*RADEON_PG_SUPPORT_GFX_PG \|
2541	RADEON_PG_SUPPORT_GFX_SMG \|	2541	RADEON_PG_SUPPORT_GFX_SMG \|
2542	RADEON_PG_SUPPORT_GFX_DMG \|	2542	RADEON_PG_SUPPORT_GFX_DMG \|
2543	RADEON_PG_SUPPORT_UVD \|	2543	RADEON_PG_SUPPORT_UVD \|
2544	RADEON_PG_SUPPORT_VCE \|	2544	RADEON_PG_SUPPORT_VCE \|
2545	RADEON_PG_SUPPORT_CP \|	2545	RADEON_PG_SUPPORT_CP \|
2546	RADEON_PG_SUPPORT_GDS \|	2546	RADEON_PG_SUPPORT_GDS \|
2547	RADEON_PG_SUPPORT_RLC_SMU_HS \|	2547	RADEON_PG_SUPPORT_RLC_SMU_HS \|
2548	RADEON_PG_SUPPORT_ACP \|	2548	RADEON_PG_SUPPORT_ACP \|
2549	RADEON_PG_SUPPORT_SAMU;*/	2549	RADEON_PG_SUPPORT_SAMU;*/
2550	} else {	2550	} else {
2551	rdev->num_crtc = 2;	2551	rdev->num_crtc = 2;
2552	rdev->cg_flags =	2552	rdev->cg_flags =
2553	RADEON_CG_SUPPORT_GFX_MGCG \|	2553	RADEON_CG_SUPPORT_GFX_MGCG \|
2554	RADEON_CG_SUPPORT_GFX_MGLS \|	2554	RADEON_CG_SUPPORT_GFX_MGLS \|
2555	RADEON_CG_SUPPORT_GFX_CGCG \|	2555	RADEON_CG_SUPPORT_GFX_CGCG \|
2556	RADEON_CG_SUPPORT_GFX_CGLS \|	2556	RADEON_CG_SUPPORT_GFX_CGLS \|
2557	RADEON_CG_SUPPORT_GFX_CGTS \|	2557	RADEON_CG_SUPPORT_GFX_CGTS \|
2558	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2558	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2559	RADEON_CG_SUPPORT_GFX_CP_LS \|	2559	RADEON_CG_SUPPORT_GFX_CP_LS \|
2560	RADEON_CG_SUPPORT_SDMA_MGCG \|	2560	RADEON_CG_SUPPORT_SDMA_MGCG \|
2561	RADEON_CG_SUPPORT_SDMA_LS \|	2561	RADEON_CG_SUPPORT_SDMA_LS \|
2562	RADEON_CG_SUPPORT_BIF_LS \|	2562	RADEON_CG_SUPPORT_BIF_LS \|
2563	RADEON_CG_SUPPORT_VCE_MGCG \|	2563	RADEON_CG_SUPPORT_VCE_MGCG \|
2564	RADEON_CG_SUPPORT_UVD_MGCG \|	2564	RADEON_CG_SUPPORT_UVD_MGCG \|
2565	RADEON_CG_SUPPORT_HDP_LS \|	2565	RADEON_CG_SUPPORT_HDP_LS \|
2566	RADEON_CG_SUPPORT_HDP_MGCG;	2566	RADEON_CG_SUPPORT_HDP_MGCG;
2567	rdev->pg_flags = 0;	2567	rdev->pg_flags = 0;
2568	/*RADEON_PG_SUPPORT_GFX_PG \|	2568	/*RADEON_PG_SUPPORT_GFX_PG \|
2569	RADEON_PG_SUPPORT_GFX_SMG \|	2569	RADEON_PG_SUPPORT_GFX_SMG \|
2570	RADEON_PG_SUPPORT_UVD \|	2570	RADEON_PG_SUPPORT_UVD \|
2571	RADEON_PG_SUPPORT_VCE \|	2571	RADEON_PG_SUPPORT_VCE \|
2572	RADEON_PG_SUPPORT_CP \|	2572	RADEON_PG_SUPPORT_CP \|
2573	RADEON_PG_SUPPORT_GDS \|	2573	RADEON_PG_SUPPORT_GDS \|
2574	RADEON_PG_SUPPORT_RLC_SMU_HS \|	2574	RADEON_PG_SUPPORT_RLC_SMU_HS \|
2575	RADEON_PG_SUPPORT_SAMU;*/	2575	RADEON_PG_SUPPORT_SAMU;*/
2576	}	2576	}
2577	rdev->has_uvd = true;	2577	rdev->has_uvd = true;
2578	break;	2578	break;
2579	default:	2579	default:
2580	/* FIXME: not supported yet */	2580	/* FIXME: not supported yet */
2581	return -EINVAL;	2581	return -EINVAL;
2582	}	2582	}
2583		2583
2584	if (rdev->flags & RADEON_IS_IGP) {	2584	if (rdev->flags & RADEON_IS_IGP) {
2585	rdev->asic->pm.get_memory_clock = NULL;	2585	rdev->asic->pm.get_memory_clock = NULL;
2586	rdev->asic->pm.set_memory_clock = NULL;	2586	rdev->asic->pm.set_memory_clock = NULL;
2587	}	2587	}
2588		2588
2589	return 0;	2589	return 0;
2590	}	2590	}
2591		2591
2592		2592

drivers/gpu/drm/radeon/radeon_vm.c

Diff comments View file @ 0a4ae72

 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  * Copyright 2009 Jerome Glisse.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
  */
 #include <drm/drmP.h>
 #include <drm/radeon_drm.h>
 #include "radeon.h"
 #include "radeon_trace.h"
 /*
  * GPUVM
  * GPUVM is similar to the legacy gart on older asics, however
  * rather than there being a single global gart table
  * for the entire GPU, there are multiple VM page tables active
  * at any given time.  The VM page tables can contain a mix
  * vram pages and system memory pages and system memory pages
  * can be mapped as snooped (cached system pages) or unsnooped
  * (uncached system pages).
  * Each VM has an ID associated with it and there is a page table
  * associated with each VMID.  When execting a command buffer,
  * the kernel tells the the ring what VMID to use for that command
  * buffer.  VMIDs are allocated dynamically as commands are submitted.
  * The userspace drivers maintain their own address space and the kernel
  * sets up their pages tables accordingly when they submit their
  * command buffers and a VMID is assigned.
  * Cayman/Trinity support up to 8 active VMs at any given time;
  * SI supports 16.
  */
 /**
  * radeon_vm_num_pde - return the number of page directory entries
  *
  * @rdev: radeon_device pointer
  *
  * Calculate the number of page directory entries (cayman+).
  */
 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
 {
 	return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE;
 }
 /**
  * radeon_vm_directory_size - returns the size of the page directory in bytes
  *
  * @rdev: radeon_device pointer
  *
  * Calculate the size of the page directory in bytes (cayman+).
  */
 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
 {
 	return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
 }
 /**
  * radeon_vm_manager_init - init the vm manager
  *
  * @rdev: radeon_device pointer
  *
  * Init the vm manager (cayman+).
  * Returns 0 for success, error for failure.
  */
 int radeon_vm_manager_init(struct radeon_device *rdev)
 {
 	int r;
 	if (!rdev->vm_manager.enabled) {
 		r = radeon_asic_vm_init(rdev);
 		if (r)
 			return r;
 		rdev->vm_manager.enabled = true;
 	}
 	return 0;
 }
 /**
  * radeon_vm_manager_fini - tear down the vm manager
  *
  * @rdev: radeon_device pointer
  *
  * Tear down the VM manager (cayman+).
  */
 void radeon_vm_manager_fini(struct radeon_device *rdev)
 {
 	int i;
 	if (!rdev->vm_manager.enabled)
 		return;
 	for (i = 0; i < RADEON_NUM_VM; ++i)
 		radeon_fence_unref(&rdev->vm_manager.active[i]);
 	radeon_asic_vm_fini(rdev);
 	rdev->vm_manager.enabled = false;
 }
 /**
  * radeon_vm_get_bos - add the vm BOs to a validation list
  *
  * @vm: vm providing the BOs
  * @head: head of validation list
  *
  * Add the page directory to the list of BOs to
  * validate for command submission (cayman+).
  */
 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
 					  struct radeon_vm *vm,
 					  struct list_head *head)
 {
 	struct radeon_cs_reloc *list;
 	unsigned i, idx;
-	list = kmalloc_array(vm->max_pde_used + 1,
+	list = kmalloc_array(vm->max_pde_used + 2,
 			     sizeof(struct radeon_cs_reloc), GFP_KERNEL);
 	if (!list)
 		return NULL;
 	/* add the vm page table to the list */
 	list[0].gobj = NULL;
 	list[0].robj = vm->page_directory;
 	list[0].domain = RADEON_GEM_DOMAIN_VRAM;
 	list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM;
 	list[0].tv.bo = &vm->page_directory->tbo;
 	list[0].tiling_flags = 0;
 	list[0].handle = 0;
 	list_add(&list[0].tv.head, head);
 	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
 		if (!vm->page_tables[i].bo)
 			continue;
 		list[idx].gobj = NULL;
 		list[idx].robj = vm->page_tables[i].bo;
 		list[idx].domain = RADEON_GEM_DOMAIN_VRAM;
 		list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM;
 		list[idx].tv.bo = &list[idx].robj->tbo;
 		list[idx].tiling_flags = 0;
 		list[idx].handle = 0;
 		list_add(&list[idx++].tv.head, head);
 	}
 	return list;
 }
 /**
  * radeon_vm_grab_id - allocate the next free VMID
  *
  * @rdev: radeon_device pointer
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
  *
  * Allocate an id for the vm (cayman+).
  * Returns the fence we need to sync to (if any).
  *
  * Global and local mutex must be locked!
  */
 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
 				       struct radeon_vm *vm, int ring)
 {
 	struct radeon_fence *best[RADEON_NUM_RINGS] = {};
 	unsigned choices[2] = {};
 	unsigned i;
 	/* check if the id is still valid */
 	if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
 		return NULL;
 	/* we definately need to flush */
 	radeon_fence_unref(&vm->last_flush);
 	/* skip over VMID 0, since it is the system VM */
 	for (i = 1; i < rdev->vm_manager.nvm; ++i) {
 		struct radeon_fence *fence = rdev->vm_manager.active[i];
 		if (fence == NULL) {
 			/* found a free one */
 			vm->id = i;
 			trace_radeon_vm_grab_id(vm->id, ring);
 			return NULL;
 		}
 		if (radeon_fence_is_earlier(fence, best[fence->ring])) {
 			best[fence->ring] = fence;
 			choices[fence->ring == ring ? 0 : 1] = i;
 		}
 	}
 	for (i = 0; i < 2; ++i) {
 		if (choices[i]) {
 			vm->id = choices[i];
 			trace_radeon_vm_grab_id(vm->id, ring);
 			return rdev->vm_manager.active[choices[i]];
 		}
 	}
 	/* should never happen */
 	BUG();
 	return NULL;
 }
 /**
  * radeon_vm_flush - hardware flush the vm
  *
  * @rdev: radeon_device pointer
  * @vm: vm we want to flush
  * @ring: ring to use for flush
  *
  * Flush the vm (cayman+).
  *
  * Global and local mutex must be locked!
  */
 void radeon_vm_flush(struct radeon_device *rdev,
 		     struct radeon_vm *vm,
 		     int ring)
 {
 	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
 	/* if we can't remember our last VM flush then flush now! */
 	/* XXX figure out why we have to flush all the time */
 	if (!vm->last_flush || true || pd_addr != vm->pd_gpu_addr) {
 		vm->pd_gpu_addr = pd_addr;
 		radeon_ring_vm_flush(rdev, ring, vm);
 	}
 }
 /**
  * radeon_vm_fence - remember fence for vm
  *
  * @rdev: radeon_device pointer
  * @vm: vm we want to fence
  * @fence: fence to remember
  *
  * Fence the vm (cayman+).
  * Set the fence used to protect page table and id.
  *
  * Global and local mutex must be locked!
  */
 void radeon_vm_fence(struct radeon_device *rdev,
 		     struct radeon_vm *vm,
 		     struct radeon_fence *fence)
 {
 	radeon_fence_unref(&vm->fence);
 	vm->fence = radeon_fence_ref(fence);
 	radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
 	rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
 	radeon_fence_unref(&vm->last_id_use);
 	vm->last_id_use = radeon_fence_ref(fence);
         /* we just flushed the VM, remember that */
         if (!vm->last_flush)
                 vm->last_flush = radeon_fence_ref(fence);
 }
 /**
  * radeon_vm_bo_find - find the bo_va for a specific vm & bo
  *
  * @vm: requested vm
  * @bo: requested buffer object
  *
  * Find @bo inside the requested vm (cayman+).
  * Search inside the @bos vm list for the requested vm
  * Returns the found bo_va or NULL if none is found
  *
  * Object has to be reserved!
  */
 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
 				       struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	list_for_each_entry(bo_va, &bo->va, bo_list) {
 		if (bo_va->vm == vm) {
 			return bo_va;
 		}
 	}
 	return NULL;
 }
 /**
  * radeon_vm_bo_add - add a bo to a specific vm
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  *
  * Add @bo into the requested vm (cayman+).
  * Add @bo to the list of bos associated with the vm
  * Returns newly added bo_va or NULL for failure
  *
  * Object has to be reserved!
  */
 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
 				      struct radeon_vm *vm,
 				      struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
 	if (bo_va == NULL) {
 		return NULL;
 	}
 	bo_va->vm = vm;
 	bo_va->bo = bo;
 	bo_va->soffset = 0;
 	bo_va->eoffset = 0;
 	bo_va->flags = 0;
 	bo_va->valid = false;
 	bo_va->ref_count = 1;
 	INIT_LIST_HEAD(&bo_va->bo_list);
 	INIT_LIST_HEAD(&bo_va->vm_list);
 	mutex_lock(&vm->mutex);
 	list_add(&bo_va->vm_list, &vm->va);
 	list_add_tail(&bo_va->bo_list, &bo->va);
 	mutex_unlock(&vm->mutex);
 	return bo_va;
 }
 /**
  * radeon_vm_clear_bo - initially clear the page dir/table
  *
  * @rdev: radeon_device pointer
  * @bo: bo to clear
  */
 static int radeon_vm_clear_bo(struct radeon_device *rdev,
 			      struct radeon_bo *bo)
 {
         struct ttm_validate_buffer tv;
         struct ww_acquire_ctx ticket;
         struct list_head head;
 	struct radeon_ib ib;
 	unsigned entries;
 	uint64_t addr;
 	int r;
         memset(&tv, 0, sizeof(tv));
         tv.bo = &bo->tbo;
         INIT_LIST_HEAD(&head);
         list_add(&tv.head, &head);
         r = ttm_eu_reserve_buffers(&ticket, &head);
         if (r)
 		return r;
         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
         if (r)
                 goto error;
 	addr = radeon_bo_gpu_offset(bo);
 	entries = radeon_bo_size(bo) / 8;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib,
 			  NULL, entries * 2 + 64);
 	if (r)
                 goto error;
 	ib.length_dw = 0;
 	radeon_asic_vm_set_page(rdev, &ib, addr, 0, entries, 0, 0);
 	r = radeon_ib_schedule(rdev, &ib, NULL);
 	if (r)
                 goto error;
 	ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 	radeon_ib_free(rdev, &ib);
 	return 0;
 error:
 	ttm_eu_backoff_reservation(&ticket, &head);
 	return r;
 }
 /**
  * radeon_vm_bo_set_addr - set bos virtual address inside a vm
  *
  * @rdev: radeon_device pointer
  * @bo_va: bo_va to store the address
  * @soffset: requested offset of the buffer in the VM address space
  * @flags: attributes of pages (read/write/valid/etc.)
  *
  * Set offset of @bo_va (cayman+).
  * Validate and set the offset requested within the vm address space.
  * Returns 0 for success, error for failure.
  *
  * Object has to be reserved!
  */
 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
 			  struct radeon_bo_va *bo_va,
 			  uint64_t soffset,
 			  uint32_t flags)
 {
 	uint64_t size = radeon_bo_size(bo_va->bo);
 	uint64_t eoffset, last_offset = 0;
 	struct radeon_vm *vm = bo_va->vm;
 	struct radeon_bo_va *tmp;
 	struct list_head *head;
 	unsigned last_pfn, pt_idx;
 	int r;
 	if (soffset) {
 		/* make sure object fit at this offset */
 		eoffset = soffset + size;
 		if (soffset >= eoffset) {
 			return -EINVAL;
 		}
 		last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
 		if (last_pfn > rdev->vm_manager.max_pfn) {
 			dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
 				last_pfn, rdev->vm_manager.max_pfn);
 			return -EINVAL;
 		}
 	} else {
 		eoffset = last_pfn = 0;
 	}
 	mutex_lock(&vm->mutex);
 	head = &vm->va;
 	last_offset = 0;
 	list_for_each_entry(tmp, &vm->va, vm_list) {
 		if (bo_va == tmp) {
 			/* skip over currently modified bo */
 			continue;
 		}
 		if (soffset >= last_offset && eoffset <= tmp->soffset) {
 			/* bo can be added before this one */
 			break;
 		}
 		if (eoffset > tmp->soffset && soffset < tmp->eoffset) {
 			/* bo and tmp overlap, invalid offset */
 			dev_err(rdev->dev, "bo %p va 0x%08X conflict with (bo %p 0x%08X 0x%08X)\n",
 				bo_va->bo, (unsigned)bo_va->soffset, tmp->bo,
 				(unsigned)tmp->soffset, (unsigned)tmp->eoffset);
 			mutex_unlock(&vm->mutex);
 			return -EINVAL;
 		}
 		last_offset = tmp->eoffset;
 		head = &tmp->vm_list;
 	}
 	bo_va->soffset = soffset;
 	bo_va->eoffset = eoffset;
 	bo_va->flags = flags;
 	bo_va->valid = false;
 	list_move(&bo_va->vm_list, head);
 	soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
 	eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
 	if (eoffset > vm->max_pde_used)
 		vm->max_pde_used = eoffset;
 	radeon_bo_unreserve(bo_va->bo);
 	/* walk over the address space and allocate the page tables */
 	for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
 		struct radeon_bo *pt;
 		if (vm->page_tables[pt_idx].bo)
 			continue;
 		/* drop mutex to allocate and clear page table */
 		mutex_unlock(&vm->mutex);
 		r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
 				     RADEON_GPU_PAGE_SIZE, false,
 				     RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
 		if (r)
 			return r;
 		r = radeon_vm_clear_bo(rdev, pt);
 		if (r) {
 			radeon_bo_unref(&pt);
 			radeon_bo_reserve(bo_va->bo, false);
 			return r;
 		}
 		/* aquire mutex again */
 		mutex_lock(&vm->mutex);
 		if (vm->page_tables[pt_idx].bo) {
 			/* someone else allocated the pt in the meantime */
 			mutex_unlock(&vm->mutex);
 			radeon_bo_unref(&pt);
 			mutex_lock(&vm->mutex);
 			continue;
 		}
 		vm->page_tables[pt_idx].addr = 0;
 		vm->page_tables[pt_idx].bo = pt;
 	}
 	mutex_unlock(&vm->mutex);
 	return radeon_bo_reserve(bo_va->bo, false);
 }
 /**
  * radeon_vm_map_gart - get the physical address of a gart page
  *
  * @rdev: radeon_device pointer
  * @addr: the unmapped addr
  *
  * Look up the physical address of the page that the pte resolves
  * to (cayman+).
  * Returns the physical address of the page.
  */
 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
 {
 	uint64_t result;
 	/* page table offset */
 	result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
 	/* in case cpu page size != gpu page size*/
 	result |= addr & (~PAGE_MASK);
 	return result;
 }
 /**
  * radeon_vm_page_flags - translate page flags to what the hw uses
  *
  * @flags: flags comming from userspace
  *
  * Translate the flags the userspace ABI uses to hw flags.
  */
 static uint32_t radeon_vm_page_flags(uint32_t flags)
 {
         uint32_t hw_flags = 0;
         hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
         hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
         hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
         if (flags & RADEON_VM_PAGE_SYSTEM) {
                 hw_flags |= R600_PTE_SYSTEM;
                 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
         }
         return hw_flags;
 }
 /**
  * radeon_vm_update_pdes - make sure that page directory is valid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @start: start of GPU address range
  * @end: end of GPU address range
  *
  * Allocates new page tables if necessary
  * and updates the page directory (cayman+).
  * Returns 0 for success, error for failure.
  *
  * Global and local mutex must be locked!
  */
 int radeon_vm_update_page_directory(struct radeon_device *rdev,
 				    struct radeon_vm *vm)
 {
 	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
-	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
+	struct radeon_bo *pd = vm->page_directory;
+	uint64_t pd_addr = radeon_bo_gpu_offset(pd);
 	uint64_t last_pde = ~0, last_pt = ~0;
 	unsigned count = 0, pt_idx, ndw;
 	struct radeon_ib ib;
 	int r;
 	/* padding, etc. */
 	ndw = 64;
 	/* assume the worst case */
 	ndw += vm->max_pde_used * 16;
 	/* update too big for an IB */
 	if (ndw > 0xfffff)
 		return -ENOMEM;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
 	if (r)
 		return r;
 	ib.length_dw = 0;
 	/* walk over the address space and update the page directory */
 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
 		struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
 		uint64_t pde, pt;
 		if (bo == NULL)
 			continue;
 		pt = radeon_bo_gpu_offset(bo);
 		if (vm->page_tables[pt_idx].addr == pt)
 			continue;
 		vm->page_tables[pt_idx].addr = pt;
 		pde = pd_addr + pt_idx * 8;
 		if (((last_pde + 8 * count) != pde) ||
 		    ((last_pt + incr * count) != pt)) {
 			if (count) {
 				radeon_asic_vm_set_page(rdev, &ib, last_pde,
 							last_pt, count, incr,
 							R600_PTE_VALID);
 			}
 			count = 1;
 			last_pde = pde;
 			last_pt = pt;
 		} else {
 			++count;
 		}
 	}
 	if (count)
 		radeon_asic_vm_set_page(rdev, &ib, last_pde, last_pt, count,
 					incr, R600_PTE_VALID);
 	if (ib.length_dw != 0) {
+		radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
 		radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
 		r = radeon_ib_schedule(rdev, &ib, NULL);
 		if (r) {
 			radeon_ib_free(rdev, &ib);
 			return r;
 		}
 		radeon_fence_unref(&vm->fence);
 		vm->fence = radeon_fence_ref(ib.fence);
 		radeon_fence_unref(&vm->last_flush);
 	}
 	radeon_ib_free(rdev, &ib);
 	return 0;
 }
 /**
  * radeon_vm_update_ptes - make sure that page tables are valid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @start: start of GPU address range
  * @end: end of GPU address range
  * @dst: destination address to map to
  * @flags: mapping flags
  *
  * Update the page tables in the range @start - @end (cayman+).
  *
  * Global and local mutex must be locked!
  */
 static void radeon_vm_update_ptes(struct radeon_device *rdev,
 				  struct radeon_vm *vm,
 				  struct radeon_ib *ib,
 				  uint64_t start, uint64_t end,
 				  uint64_t dst, uint32_t flags)
 {
 	static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
 	uint64_t last_pte = ~0, last_dst = ~0;
 	unsigned count = 0;
 	uint64_t addr;
 	start = start / RADEON_GPU_PAGE_SIZE;
 	end = end / RADEON_GPU_PAGE_SIZE;
 	/* walk over the address space and update the page tables */
 	for (addr = start; addr < end; ) {
 		uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
+		struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
 		unsigned nptes;
 		uint64_t pte;
+		radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);
 		if ((addr & ~mask) == (end & ~mask))
 			nptes = end - addr;
 		else
 			nptes = RADEON_VM_PTE_COUNT - (addr & mask);
-		pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo);
+		pte = radeon_bo_gpu_offset(pt);
 		pte += (addr & mask) * 8;
 		if ((last_pte + 8 * count) != pte) {
 			if (count) {
 				radeon_asic_vm_set_page(rdev, ib, last_pte,
 							last_dst, count,
 							RADEON_GPU_PAGE_SIZE,
 							flags);
 			}
 			count = nptes;
 			last_pte = pte;
 			last_dst = dst;
 		} else {
 			count += nptes;
 		}
 		addr += nptes;
 		dst += nptes * RADEON_GPU_PAGE_SIZE;
 	}
 	if (count) {
 		radeon_asic_vm_set_page(rdev, ib, last_pte,
 					last_dst, count,
 					RADEON_GPU_PAGE_SIZE, flags);
 	}
 }
 /**
  * radeon_vm_bo_update - map a bo into the vm page table
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  * @mem: ttm mem
  *
  * Fill in the page table entries for @bo (cayman+).
  * Returns 0 for success, -EINVAL for failure.
  *
  * Object have to be reserved and mutex must be locked!
  */
 int radeon_vm_bo_update(struct radeon_device *rdev,
 			struct radeon_vm *vm,
 			struct radeon_bo *bo,
 			struct ttm_mem_reg *mem)
 {
 	struct radeon_ib ib;
 	struct radeon_bo_va *bo_va;
 	unsigned nptes, ndw;
 	uint64_t addr;
 	int r;
 	bo_va = radeon_vm_bo_find(vm, bo);
 	if (bo_va == NULL) {
 		dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
 		return -EINVAL;
 	}
 	if (!bo_va->soffset) {
 		dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
 			bo, vm);
 		return -EINVAL;
 	}
 	if ((bo_va->valid && mem) || (!bo_va->valid && mem == NULL))
 		return 0;
 	bo_va->flags &= ~RADEON_VM_PAGE_VALID;
 	bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
 	if (mem) {
 		addr = mem->start << PAGE_SHIFT;
 		if (mem->mem_type != TTM_PL_SYSTEM) {
 			bo_va->flags |= RADEON_VM_PAGE_VALID;
 			bo_va->valid = true;
 		}
 		if (mem->mem_type == TTM_PL_TT) {
 			bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
 		} else {
 			addr += rdev->vm_manager.vram_base_offset;
 		}
 	} else {
 		addr = 0;
 		bo_va->valid = false;
 	}
 	trace_radeon_vm_bo_update(bo_va);
 	nptes = radeon_bo_ngpu_pages(bo);
 	/* padding, etc. */
 	ndw = 64;
 	if (RADEON_VM_BLOCK_SIZE > 11)
 		/* reserve space for one header for every 2k dwords */
 		ndw += (nptes >> 11) * 4;
 	else
 		/* reserve space for one header for
 		    every (1 << BLOCK_SIZE) entries */
 		ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4;
 	/* reserve space for pte addresses */
 	ndw += nptes * 2;
 	/* update too big for an IB */
 	if (ndw > 0xfffff)
 		return -ENOMEM;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
 	if (r)
 		return r;
 	ib.length_dw = 0;
 	radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
 			      addr, radeon_vm_page_flags(bo_va->flags));
 	radeon_semaphore_sync_to(ib.semaphore, vm->fence);
 	r = radeon_ib_schedule(rdev, &ib, NULL);
 	if (r) {
 		radeon_ib_free(rdev, &ib);
 		return r;
 	}
 	radeon_fence_unref(&vm->fence);
 	vm->fence = radeon_fence_ref(ib.fence);
 	radeon_ib_free(rdev, &ib);
 	radeon_fence_unref(&vm->last_flush);
 	return 0;
 }
 /**
  * radeon_vm_bo_rmv - remove a bo to a specific vm
  *
  * @rdev: radeon_device pointer
  * @bo_va: requested bo_va
  *
  * Remove @bo_va->bo from the requested vm (cayman+).
  * Remove @bo_va->bo from the list of bos associated with the bo_va->vm and
  * remove the ptes for @bo_va in the page table.
  * Returns 0 for success.
  *
  * Object have to be reserved!
  */
 int radeon_vm_bo_rmv(struct radeon_device *rdev,
 		     struct radeon_bo_va *bo_va)
 {
 	int r = 0;
 	mutex_lock(&bo_va->vm->mutex);
 	if (bo_va->soffset)
 		r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL);
 	list_del(&bo_va->vm_list);
 	mutex_unlock(&bo_va->vm->mutex);
 	list_del(&bo_va->bo_list);
 	kfree(bo_va);
 	return r;
 }
 /**
  * radeon_vm_bo_invalidate - mark the bo as invalid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  *
  * Mark @bo as invalid (cayman+).
  */
 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
 			     struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	list_for_each_entry(bo_va, &bo->va, bo_list) {
 		bo_va->valid = false;
 	}
 }
 /**
  * radeon_vm_init - initialize a vm instance
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  *
  * Init @vm fields (cayman+).
  */
 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
 {
 	unsigned pd_size, pd_entries, pts_size;
 	int r;
 	vm->id = 0;
 	vm->fence = NULL;
 	vm->last_flush = NULL;
 	vm->last_id_use = NULL;
 	mutex_init(&vm->mutex);
 	INIT_LIST_HEAD(&vm->va);
 	pd_size = radeon_vm_directory_size(rdev);
 	pd_entries = radeon_vm_num_pdes(rdev);
 	/* allocate page table array */
 	pts_size = pd_entries * sizeof(struct radeon_vm_pt);
 	vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
 	if (vm->page_tables == NULL) {
 		DRM_ERROR("Cannot allocate memory for page table array\n");
 		return -ENOMEM;
 	}
 	r = radeon_bo_create(rdev, pd_size, RADEON_VM_PTB_ALIGN_SIZE, false,
 			     RADEON_GEM_DOMAIN_VRAM, NULL,
 			     &vm->page_directory);
 	if (r)
 		return r;
 	r = radeon_vm_clear_bo(rdev, vm->page_directory);
 	if (r) {
 		radeon_bo_unref(&vm->page_directory);
 		vm->page_directory = NULL;
 		return r;
 	}
 	return 0;
 }
 /**
  * radeon_vm_fini - tear down a vm instance
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  *
  * Tear down @vm (cayman+).
  * Unbind the VM and remove all bos from the vm bo list
  */
 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
 {
 	struct radeon_bo_va *bo_va, *tmp;
 	int i, r;
 	if (!list_empty(&vm->va)) {
 		dev_err(rdev->dev, "still active bo inside vm\n");
 	}
 	list_for_each_entry_safe(bo_va, tmp, &vm->va, vm_list) {
 		list_del_init(&bo_va->vm_list);
 		r = radeon_bo_reserve(bo_va->bo, false);
 		if (!r) {
 			list_del_init(&bo_va->bo_list);
 			radeon_bo_unreserve(bo_va->bo);
 			kfree(bo_va);
 		}
 	}
 	for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
 		radeon_bo_unref(&vm->page_tables[i].bo);
 	kfree(vm->page_tables);
 	radeon_bo_unref(&vm->page_directory);
 	radeon_fence_unref(&vm->fence);
 	radeon_fence_unref(&vm->last_flush);
 	radeon_fence_unref(&vm->last_id_use);
 	mutex_destroy(&vm->mutex);
 }