Eric Lee / smarc-ti-linux-kernel

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Commit 0dafc3d94596522787e216711d305add1c1dce99

Authored by Jingoo Han
Committed by Felipe Balbi
1 parent 17c128e8c8
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

usb: phy: samsung: Remove unnecessary lines of register bit definitions 

Remove unnecessary lines of register bit definitions in order
to enhance the readability. In this case, there are lines
per register offset definitions. There is no functional change.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Showing 1 changed file with 2 additions and 34 deletions Side-by-side Diff

drivers/usb/phy/phy-samsung-usb.h
Diff comments   View file @ 0dafc3d
... ... @@ -21,7 +21,6 @@
21 21 /* Register definitions */
22 22  
23 23 #define SAMSUNG_PHYPWR (0x00)
24   -
25 24 #define PHYPWR_NORMAL_MASK (0x19 << 0)
26 25 #define PHYPWR_OTG_DISABLE (0x1 << 4)
27 26 #define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
... ... @@ -31,7 +30,6 @@
31 30 #define PHYPWR_SLEEP_PHY0 (0x1 << 5)
32 31  
33 32 #define SAMSUNG_PHYCLK (0x04)
34   -
35 33 #define PHYCLK_MODE_USB11 (0x1 << 6)
36 34 #define PHYCLK_EXT_OSC (0x1 << 5)
37 35 #define PHYCLK_COMMON_ON_N (0x1 << 4)
... ... @@ -42,7 +40,6 @@
42 40 #define PHYCLK_CLKSEL_24M (0x3 << 0)
43 41  
44 42 #define SAMSUNG_RSTCON (0x08)
45   -
46 43 #define RSTCON_PHYLINK_SWRST (0x1 << 2)
47 44 #define RSTCON_HLINK_SWRST (0x1 << 1)
48 45 #define RSTCON_SWRST (0x1 << 0)
49 46  
50 47  
51 48  
52 49  
53 50  
... ... @@ -50,26 +47,20 @@
50 47 /* EXYNOS4X12 */
51 48 #define EXYNOS4X12_PHY_HSIC_CTRL0 (0x04)
52 49 #define EXYNOS4X12_PHY_HSIC_CTRL1 (0x08)
53   -
54 50 #define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
55 51 #define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
56 52 #define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
57   -
58 53 #define RSTCON_HOSTPHY_SWRST (0xf << 3)
59 54  
60 55 /* EXYNOS5 */
61 56 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
62   -
63 57 #define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
64   -
65 58 #define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
66 59 #define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
67 60 #define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
68 61 #define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
69   -
70 62 #define HOST_CTRL0_FSEL_MASK (0x7 << 16)
71 63 #define HOST_CTRL0_FSEL(_x) ((_x) << 16)
72   -
73 64 #define FSEL_CLKSEL_50M (0x7)
74 65 #define FSEL_CLKSEL_24M (0x5)
75 66 #define FSEL_CLKSEL_20M (0x4)
... ... @@ -77,7 +68,6 @@
77 68 #define FSEL_CLKSEL_12M (0x2)
78 69 #define FSEL_CLKSEL_10M (0x1)
79 70 #define FSEL_CLKSEL_9600K (0x0)
80   -
81 71 #define HOST_CTRL0_TESTBURNIN (0x1 << 11)
82 72 #define HOST_CTRL0_RETENABLE (0x1 << 10)
83 73 #define HOST_CTRL0_COMMONON_N (0x1 << 9)
84 74  
... ... @@ -98,10 +88,8 @@
98 88 #define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
99 89  
100 90 #define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
101   -
102 91 #define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
103 92 #define HSIC_CTRL_REFCLKSEL (0x2 << 23)
104   -
105 93 #define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
106 94 #define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
107 95 #define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
... ... @@ -109,7 +97,6 @@
109 97 #define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
110 98 #define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
111 99 #define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
112   -
113 100 #define HSIC_CTRL_SIDDQ (0x1 << 6)
114 101 #define HSIC_CTRL_FORCESLEEP (0x1 << 5)
115 102 #define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
116 103  
117 104  
118 105  
119 106  
120 107  
121 108  
... ... @@ -118,36 +105,29 @@
118 105 #define HSIC_CTRL_PHYSWRST (0x1 << 0)
119 106  
120 107 #define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
121   -
122 108 #define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
123 109 #define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
124 110 #define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
125 111 #define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
126 112  
127 113 #define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
128   -
129 114 #define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
130 115 #define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
131 116 #define HOST_OHCICTRL_CNTSEL (0x1 << 1)
132 117 #define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
133 118  
134 119 #define EXYNOS5_PHY_OTG_SYS (0x38)
135   -
136 120 #define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
137 121 #define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
138 122 #define OTG_SYS_PHY0_SWRST (0x1 << 12)
139   -
140 123 #define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
141 124 #define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
142 125 #define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
143 126 #define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
144   -
145 127 #define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
146 128 #define OTG_SYS_COMMON_ON (0x1 << 7)
147   -
148 129 #define OTG_SYS_FSEL_MASK (0x7 << 4)
149 130 #define OTG_SYS_FSEL(_x) ((_x) << 4)
150   -
151 131 #define OTG_SYS_FORCESLEEP (0x1 << 3)
152 132 #define OTG_SYS_OTGDISABLE (0x1 << 2)
153 133 #define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
154 134  
... ... @@ -157,13 +137,11 @@
157 137  
158 138 /* EXYNOS5: USB 3.0 DRD */
159 139 #define EXYNOS5_DRD_LINKSYSTEM (0x04)
160   -
161 140 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
162 141 #define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
163 142 #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
164 143  
165 144 #define EXYNOS5_DRD_PHYUTMI (0x08)
166   -
167 145 #define PHYUTMI_OTGDISABLE (0x1 << 6)
168 146 #define PHYUTMI_FORCESUSPEND (0x1 << 1)
169 147 #define PHYUTMI_FORCESLEEP (0x1 << 0)
170 148  
171 149  
172 150  
173 151  
174 152  
175 153  
176 154  
177 155  
178 156  
179 157  
180 158  
181 159  
182 160  
... ... @@ -171,68 +149,58 @@
171 149 #define EXYNOS5_DRD_PHYPIPE (0x0c)
172 150  
173 151 #define EXYNOS5_DRD_PHYCLKRST (0x10)
174   -
175 152 #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
176 153 #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
177   -
178 154 #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
179 155 #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
180   -
181 156 #define PHYCLKRST_SSC_EN (0x1 << 20)
182 157 #define PHYCLKRST_REF_SSP_EN (0x1 << 19)
183 158 #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
184   -
185 159 #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
186 160 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
187 161 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
188 162 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
189 163 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
190 164 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
191   -
192 165 #define PHYCLKRST_FSEL_MASK (0x3f << 5)
193 166 #define PHYCLKRST_FSEL(_x) ((_x) << 5)
194 167 #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
195 168 #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
196 169 #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
197 170 #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
198   -
199 171 #define PHYCLKRST_RETENABLEN (0x1 << 4)
200   -
201 172 #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
202 173 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
203 174 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
204   -
205 175 #define PHYCLKRST_PORTRESET (0x1 << 1)
206 176 #define PHYCLKRST_COMMONONN (0x1 << 0)
207 177  
208 178 #define EXYNOS5_DRD_PHYREG0 (0x14)
  179 +
209 180 #define EXYNOS5_DRD_PHYREG1 (0x18)
210 181  
211 182 #define EXYNOS5_DRD_PHYPARAM0 (0x1c)
212   -
213 183 #define PHYPARAM0_REF_USE_PAD (0x1 << 31)
214 184 #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
215 185 #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
216 186  
217 187 #define EXYNOS5_DRD_PHYPARAM1 (0x20)
218   -
219 188 #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
220 189 #define PHYPARAM1_PCS_TXDEEMPH (0x1c)
221 190  
222 191 #define EXYNOS5_DRD_PHYTERM (0x24)
223 192  
224 193 #define EXYNOS5_DRD_PHYTEST (0x28)
225   -
226 194 #define PHYTEST_POWERDOWN_SSP (0x1 << 3)
227 195 #define PHYTEST_POWERDOWN_HSP (0x1 << 2)
228 196  
229 197 #define EXYNOS5_DRD_PHYADP (0x2c)
230 198  
231 199 #define EXYNOS5_DRD_PHYBATCHG (0x30)
232   -
233 200 #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
234 201  
235 202 #define EXYNOS5_DRD_PHYRESUME (0x34)
  203 +
236 204 #define EXYNOS5_DRD_LINKPORT (0x44)
237 205  
238 206 #ifndef MHZ