Eric Lee / smarc-ti-linux-kernel

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Commit 0f37ee50e2b263eb5941d91ef6da7d4ca51f7488

Authored by LCPD Auto Merger
2 parents f0f52afb60 27ab869c5c
Exists in smarct4x-processor-sdk-linux-02.00.01 and in 3 other branches processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-02.00.01, smarct4x-800-processor-sdk-linux-02.00.01

Merge branch 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-lsk-linux-4.1.y 

TI-Feature: ti_linux_base_lsk
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.1.y

* 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
  net: netcp: remove obsolete driver code
  phy: keystone: update header of the file
  phy: keystone: remove comments per vendor recommendation
  ARM: dts: keystone: enable gbe serdes support
  phy: keystone: change function names per vendor recommendation
  phy: keystone: rename data structures based on vendor recommendation
  phy: keystone: reduce one level of nesting in the function call
  phy: keystone: remove hyperlink support
  phy: keystone: update comments per IP vendor recommendation

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

Showing 6 changed files Side-by-side Diff

arch/arm/boot/dts/k2e-evm.dts
Diff comments   View file @ 0f37ee5
... ... @@ -189,4 +189,8 @@
189 189 &dsp0 {
190 190 memory-region = <&dsp_common_cma_pool>;
191 191 };
  192 +
  193 +&gbe_serdes0 {
  194 + status = "okay";
  195 +};
arch/arm/boot/dts/k2hk-evm.dts
Diff comments   View file @ 0f37ee5
... ... @@ -237,4 +237,8 @@
237 237 &dsp7 {
238 238 memory-region = <&dsp_common_cma_pool>;
239 239 };
  240 +
  241 +&gbe_serdes {
  242 + status = "okay";
  243 +};
arch/arm/boot/dts/k2l-evm.dts
Diff comments   View file @ 0f37ee5
... ... @@ -170,4 +170,8 @@
170 170 &dsp3 {
171 171 memory-region = <&dsp_common_cma_pool>;
172 172 };
  173 +
  174 +&gbe_serdes0 {
  175 + status = "okay";
  176 +};
drivers/net/ethernet/ti/Makefile
Diff comments   View file @ 0f37ee5
... ... @@ -18,5 +18,5 @@
18 18 obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o
19 19 keystone_netcp-y := netcp_core.o
20 20 obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o
21   -keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o
  21 +keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o
drivers/net/ethernet/ti/netcp_xgbepcsr.c
View file @ 0f37ee5
1   -/*
2   - * XGE PCSR module initialisation
3   - *
4   - * Copyright (C) 2014 Texas Instruments Incorporated
5   - * Authors: Sandeep Nair <sandeep_n@ti.com>
6   - * WingMan Kwok <w-kwok2@ti.com>
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation version 2.
11   - *
12   - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13   - * kind, whether express or implied; without even the implied warranty
14   - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - */
17   -#include "netcp.h"
18   -
19   -/* XGBE registers */
20   -#define XGBE_CTRL_OFFSET 0x0c
21   -#define XGBE_SGMII_1_OFFSET 0x0114
22   -#define XGBE_SGMII_2_OFFSET 0x0214
23   -
24   -/* PCS-R registers */
25   -#define PCSR_CPU_CTRL_OFFSET 0x1fd0
26   -#define POR_EN BIT(29)
27   -
28   -#define reg_rmw(addr, value, mask) \
29   - writel(((readl(addr) & (~(mask))) | \
30   - (value & (mask))), (addr))
31   -
32   -/* bit mask of width w at offset s */
33   -#define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
34   -
35   -/* shift value v to offset s */
36   -#define VAL_SH(v, s) (v << s)
37   -
38   -#define PHY_A(serdes) 0
39   -
40   -struct serdes_cfg {
41   - u32 ofs;
42   - u32 val;
43   - u32 mask;
44   -};
45   -
46   -static struct serdes_cfg cfg_phyb_1p25g_156p25mhz_cmu0[] = {
47   - {0x0000, 0x00800002, 0x00ff00ff},
48   - {0x0014, 0x00003838, 0x0000ffff},
49   - {0x0060, 0x1c44e438, 0xffffffff},
50   - {0x0064, 0x00c18400, 0x00ffffff},
51   - {0x0068, 0x17078200, 0xffffff00},
52   - {0x006c, 0x00000014, 0x000000ff},
53   - {0x0078, 0x0000c000, 0x0000ff00},
54   - {0x0000, 0x00000003, 0x000000ff},
55   -};
56   -
57   -static struct serdes_cfg cfg_phyb_10p3125g_156p25mhz_cmu1[] = {
58   - {0x0c00, 0x00030002, 0x00ff00ff},
59   - {0x0c14, 0x00005252, 0x0000ffff},
60   - {0x0c28, 0x80000000, 0xff000000},
61   - {0x0c2c, 0x000000f6, 0x000000ff},
62   - {0x0c3c, 0x04000405, 0xff00ffff},
63   - {0x0c40, 0xc0800000, 0xffff0000},
64   - {0x0c44, 0x5a202062, 0xffffffff},
65   - {0x0c48, 0x40040424, 0xffffffff},
66   - {0x0c4c, 0x00004002, 0x0000ffff},
67   - {0x0c50, 0x19001c00, 0xff00ff00},
68   - {0x0c54, 0x00002100, 0x0000ff00},
69   - {0x0c58, 0x00000060, 0x000000ff},
70   - {0x0c60, 0x80131e7c, 0xffffffff},
71   - {0x0c64, 0x8400cb02, 0xff00ffff},
72   - {0x0c68, 0x17078200, 0xffffff00},
73   - {0x0c6c, 0x00000016, 0x000000ff},
74   - {0x0c74, 0x00000400, 0x0000ff00},
75   - {0x0c78, 0x0000c000, 0x0000ff00},
76   - {0x0c00, 0x00000003, 0x000000ff},
77   -};
78   -
79   -static struct serdes_cfg cfg_phyb_10p3125g_16bit_lane[] = {
80   - {0x0204, 0x00000080, 0x000000ff},
81   - {0x0208, 0x0000920d, 0x0000ffff},
82   - {0x0204, 0xfc000000, 0xff000000},
83   - {0x0208, 0x00009104, 0x0000ffff},
84   - {0x0210, 0x1a000000, 0xff000000},
85   - {0x0214, 0x00006b58, 0x00ffffff},
86   - {0x0218, 0x75800084, 0xffff00ff},
87   - {0x022c, 0x00300000, 0x00ff0000},
88   - {0x0230, 0x00003800, 0x0000ff00},
89   - {0x024c, 0x008f0000, 0x00ff0000},
90   - {0x0250, 0x30000000, 0xff000000},
91   - {0x0260, 0x00000002, 0x000000ff},
92   - {0x0264, 0x00000057, 0x000000ff},
93   - {0x0268, 0x00575700, 0x00ffff00},
94   - {0x0278, 0xff000000, 0xff000000},
95   - {0x0280, 0x00500050, 0x00ff00ff},
96   - {0x0284, 0x00001f15, 0x0000ffff},
97   - {0x028c, 0x00006f00, 0x0000ff00},
98   - {0x0294, 0x00000000, 0xffffff00},
99   - {0x0298, 0x00002640, 0xff00ffff},
100   - {0x029c, 0x00000003, 0x000000ff},
101   - {0x02a4, 0x00000f13, 0x0000ffff},
102   - {0x02a8, 0x0001b600, 0x00ffff00},
103   - {0x0380, 0x00000030, 0x000000ff},
104   - {0x03c0, 0x00000200, 0x0000ff00},
105   - {0x03cc, 0x00000018, 0x000000ff},
106   - {0x03cc, 0x00000000, 0x000000ff},
107   -};
108   -
109   -static struct serdes_cfg cfg_phyb_10p3125g_comlane[] = {
110   - {0x0a00, 0x00000800, 0x0000ff00},
111   - {0x0a84, 0x00000000, 0x000000ff},
112   - {0x0a8c, 0x00130000, 0x00ff0000},
113   - {0x0a90, 0x77a00000, 0xffff0000},
114   - {0x0a94, 0x00007777, 0x0000ffff},
115   - {0x0b08, 0x000f0000, 0xffff0000},
116   - {0x0b0c, 0x000f0000, 0x00ffffff},
117   - {0x0b10, 0xbe000000, 0xff000000},
118   - {0x0b14, 0x000000ff, 0x000000ff},
119   - {0x0b18, 0x00000014, 0x000000ff},
120   - {0x0b5c, 0x981b0000, 0xffff0000},
121   - {0x0b64, 0x00001100, 0x0000ff00},
122   - {0x0b78, 0x00000c00, 0x0000ff00},
123   - {0x0abc, 0xff000000, 0xff000000},
124   - {0x0ac0, 0x0000008b, 0x000000ff},
125   -};
126   -
127   -static struct serdes_cfg cfg_cm_c1_c2[] = {
128   - {0x0208, 0x00000000, 0x00000f00},
129   - {0x0208, 0x00000000, 0x0000001f},
130   - {0x0204, 0x00000000, 0x00040000},
131   - {0x0208, 0x000000a0, 0x000000e0},
132   -};
133   -
134   -static void netcp_xgbe_serdes_cmu_init(void __iomem *serdes_regs)
135   -{
136   - int i;
137   -
138   - /* cmu0 setup */
139   - for (i = 0; i < ARRAY_SIZE(cfg_phyb_1p25g_156p25mhz_cmu0); i++) {
140   - reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs,
141   - cfg_phyb_1p25g_156p25mhz_cmu0[i].val,
142   - cfg_phyb_1p25g_156p25mhz_cmu0[i].mask);
143   - }
144   -
145   - /* cmu1 setup */
146   - for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_156p25mhz_cmu1); i++) {
147   - reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs,
148   - cfg_phyb_10p3125g_156p25mhz_cmu1[i].val,
149   - cfg_phyb_10p3125g_156p25mhz_cmu1[i].mask);
150   - }
151   -}
152   -
153   -/* lane is 0 based */
154   -static void netcp_xgbe_serdes_lane_config(
155   - void __iomem *serdes_regs, int lane)
156   -{
157   - int i;
158   -
159   - /* lane setup */
160   - for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_16bit_lane); i++) {
161   - reg_rmw(serdes_regs +
162   - cfg_phyb_10p3125g_16bit_lane[i].ofs +
163   - (0x200 * lane),
164   - cfg_phyb_10p3125g_16bit_lane[i].val,
165   - cfg_phyb_10p3125g_16bit_lane[i].mask);
166   - }
167   -
168   - /* disable auto negotiation*/
169   - reg_rmw(serdes_regs + (0x200 * lane) + 0x0380,
170   - 0x00000000, 0x00000010);
171   -
172   - /* disable link training */
173   - reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0,
174   - 0x00000000, 0x00000200);
175   -}
176   -
177   -static void netcp_xgbe_serdes_com_enable(void __iomem *serdes_regs)
178   -{
179   - int i;
180   -
181   - for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_comlane); i++) {
182   - reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs,
183   - cfg_phyb_10p3125g_comlane[i].val,
184   - cfg_phyb_10p3125g_comlane[i].mask);
185   - }
186   -}
187   -
188   -static void netcp_xgbe_serdes_lane_enable(
189   - void __iomem *serdes_regs, int lane)
190   -{
191   - /* Set Lane Control Rate */
192   - writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane));
193   -}
194   -
195   -static void netcp_xgbe_serdes_phyb_rst_clr(void __iomem *serdes_regs)
196   -{
197   - reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff);
198   -}
199   -
200   -static void netcp_xgbe_serdes_pll_disable(void __iomem *serdes_regs)
201   -{
202   - writel(0x88000000, serdes_regs + 0x1ff4);
203   -}
204   -
205   -static void netcp_xgbe_serdes_pll_enable(void __iomem *serdes_regs)
206   -{
207   - netcp_xgbe_serdes_phyb_rst_clr(serdes_regs);
208   - writel(0xee000000, serdes_regs + 0x1ff4);
209   -}
210   -
211   -static int netcp_xgbe_wait_pll_locked(void __iomem *sw_regs)
212   -{
213   - unsigned long timeout;
214   - int ret = 0;
215   - u32 val_1, val_0;
216   -
217   - timeout = jiffies + msecs_to_jiffies(500);
218   - do {
219   - val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4));
220   - val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4));
221   -
222   - if (val_1 && val_0)
223   - return 0;
224   -
225   - if (time_after(jiffies, timeout)) {
226   - ret = -ETIMEDOUT;
227   - break;
228   - }
229   -
230   - cpu_relax();
231   - } while (true);
232   -
233   - pr_err("XGBE serdes not locked: time out.\n");
234   - return ret;
235   -}
236   -
237   -static void netcp_xgbe_serdes_enable_xgmii_port(void __iomem *sw_regs)
238   -{
239   - writel(0x03, sw_regs + XGBE_CTRL_OFFSET);
240   -}
241   -
242   -static u32 netcp_xgbe_serdes_read_tbus_val(void __iomem *serdes_regs)
243   -{
244   - u32 tmp;
245   -
246   - if (PHY_A(serdes_regs)) {
247   - tmp = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff;
248   - tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00);
249   - } else {
250   - tmp = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff;
251   - }
252   -
253   - return tmp;
254   -}
255   -
256   -static void netcp_xgbe_serdes_write_tbus_addr(void __iomem *serdes_regs,
257   - int select, int ofs)
258   -{
259   - if (PHY_A(serdes_regs)) {
260   - reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24,
261   - ~0x00ffffff);
262   - return;
263   - }
264   -
265   - /* For 2 lane Phy-B, lane0 is actually lane1 */
266   - switch (select) {
267   - case 1:
268   - select = 2;
269   - break;
270   - case 2:
271   - select = 3;
272   - break;
273   - default:
274   - return;
275   - }
276   -
277   - reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff);
278   -}
279   -
280   -static u32 netcp_xgbe_serdes_read_select_tbus(void __iomem *serdes_regs,
281   - int select, int ofs)
282   -{
283   - /* Set tbus address */
284   - netcp_xgbe_serdes_write_tbus_addr(serdes_regs, select, ofs);
285   - /* Get TBUS Value */
286   - return netcp_xgbe_serdes_read_tbus_val(serdes_regs);
287   -}
288   -
289   -static void netcp_xgbe_serdes_reset_cdr(void __iomem *serdes_regs,
290   - void __iomem *sig_detect_reg, int lane)
291   -{
292   - u32 tmp, dlpf, tbus;
293   -
294   - /*Get the DLPF values */
295   - tmp = netcp_xgbe_serdes_read_select_tbus(
296   - serdes_regs, lane + 1, 5);
297   -
298   - dlpf = tmp >> 2;
299   -
300   - if (dlpf < 400 || dlpf > 700) {
301   - reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1));
302   - mdelay(1);
303   - reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1));
304   - } else {
305   - tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane +
306   - 1, 0xe);
307   -
308   - pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n",
309   - tmp >> 2, tmp & 3, (tbus >> 2) & 3);
310   - }
311   -}
312   -
313   -/* Call every 100 ms */
314   -static int netcp_xgbe_check_link_status(void __iomem *serdes_regs,
315   - void __iomem *sw_regs, u32 lanes,
316   - u32 *current_state, u32 *lane_down)
317   -{
318   - void __iomem *pcsr_base = sw_regs + 0x0600;
319   - void __iomem *sig_detect_reg;
320   - u32 pcsr_rx_stat, blk_lock, blk_errs;
321   - int loss, i, status = 1;
322   -
323   - for (i = 0; i < lanes; i++) {
324   - /* Get the Loss bit */
325   - loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1;
326   -
327   - /* Get Block Errors and Block Lock bits */
328   - pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80));
329   - blk_lock = (pcsr_rx_stat >> 30) & 0x1;
330   - blk_errs = (pcsr_rx_stat >> 16) & 0x0ff;
331   -
332   - /* Get Signal Detect Overlay Address */
333   - sig_detect_reg = serdes_regs + (i * 0x200) + 0x200 + 0x04;
334   -
335   - /* If Block errors maxed out, attempt recovery! */
336   - if (blk_errs == 0x0ff)
337   - blk_lock = 0;
338   -
339   - switch (current_state[i]) {
340   - case 0:
341   - /* if good link lock the signal detect ON! */
342   - if (!loss && blk_lock) {
343   - pr_debug("XGBE PCSR Linked Lane: %d\n", i);
344   - reg_rmw(sig_detect_reg, VAL_SH(3, 1),
345   - MASK_WID_SH(2, 1));
346   - current_state[i] = 1;
347   - } else if (!blk_lock) {
348   - /* if no lock, then reset CDR */
349   - pr_debug("XGBE PCSR Recover Lane: %d\n", i);
350   - netcp_xgbe_serdes_reset_cdr(serdes_regs,
351   - sig_detect_reg, i);
352   - }
353   - break;
354   -
355   - case 1:
356   - if (!blk_lock) {
357   - /* Link Lost? */
358   - lane_down[i] = 1;
359   - current_state[i] = 2;
360   - }
361   - break;
362   -
363   - case 2:
364   - if (blk_lock)
365   - /* Nope just noise */
366   - current_state[i] = 1;
367   - else {
368   - /* Lost the block lock, reset CDR if it is
369   - * not centered and go back to sync state
370   - */
371   - netcp_xgbe_serdes_reset_cdr(serdes_regs,
372   - sig_detect_reg, i);
373   - current_state[i] = 0;
374   - }
375   - break;
376   -
377   - default:
378   - pr_err("XGBE: unknown current_state[%d] %d\n",
379   - i, current_state[i]);
380   - break;
381   - }
382   -
383   - if (blk_errs > 0) {
384   - /* Reset the Error counts! */
385   - reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0),
386   - MASK_WID_SH(8, 0));
387   -
388   - reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0),
389   - MASK_WID_SH(8, 0));
390   - }
391   -
392   - status &= (current_state[i] == 1);
393   - }
394   -
395   - return status;
396   -}
397   -
398   -static int netcp_xgbe_serdes_check_lane(void __iomem *serdes_regs,
399   - void __iomem *sw_regs)
400   -{
401   - u32 current_state[2] = {0, 0};
402   - int retries = 0, link_up;
403   - u32 lane_down[2];
404   -
405   - do {
406   - lane_down[0] = 0;
407   - lane_down[1] = 0;
408   -
409   - link_up = netcp_xgbe_check_link_status(serdes_regs, sw_regs, 2,
410   - current_state,
411   - lane_down);
412   -
413   - /* if we did not get link up then wait 100ms before calling
414   - * it again
415   - */
416   - if (link_up)
417   - break;
418   -
419   - if (lane_down[0])
420   - pr_debug("XGBE: detected link down on lane 0\n");
421   -
422   - if (lane_down[1])
423   - pr_debug("XGBE: detected link down on lane 1\n");
424   -
425   - if (++retries > 1) {
426   - pr_debug("XGBE: timeout waiting for serdes link up\n");
427   - return -ETIMEDOUT;
428   - }
429   - mdelay(100);
430   - } while (!link_up);
431   -
432   - pr_debug("XGBE: PCSR link is up\n");
433   - return 0;
434   -}
435   -
436   -static void netcp_xgbe_serdes_setup_cm_c1_c2(void __iomem *serdes_regs,
437   - int lane, int cm, int c1, int c2)
438   -{
439   - int i;
440   -
441   - for (i = 0; i < ARRAY_SIZE(cfg_cm_c1_c2); i++) {
442   - reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane),
443   - cfg_cm_c1_c2[i].val,
444   - cfg_cm_c1_c2[i].mask);
445   - }
446   -}
447   -
448   -static void netcp_xgbe_reset_serdes(void __iomem *serdes_regs)
449   -{
450   - /* Toggle the POR_EN bit in CONFIG.CPU_CTRL */
451   - /* enable POR_EN bit */
452   - reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN);
453   - usleep_range(10, 100);
454   -
455   - /* disable POR_EN bit */
456   - reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN);
457   - usleep_range(10, 100);
458   -}
459   -
460   -static int netcp_xgbe_serdes_config(void __iomem *serdes_regs,
461   - void __iomem *sw_regs)
462   -{
463   - u32 ret, i;
464   -
465   - netcp_xgbe_serdes_pll_disable(serdes_regs);
466   - netcp_xgbe_serdes_cmu_init(serdes_regs);
467   -
468   - for (i = 0; i < 2; i++)
469   - netcp_xgbe_serdes_lane_config(serdes_regs, i);
470   -
471   - netcp_xgbe_serdes_com_enable(serdes_regs);
472   - /* This is EVM + RTM-BOC specific */
473   - for (i = 0; i < 2; i++)
474   - netcp_xgbe_serdes_setup_cm_c1_c2(serdes_regs, i, 0, 0, 5);
475   -
476   - netcp_xgbe_serdes_pll_enable(serdes_regs);
477   - for (i = 0; i < 2; i++)
478   - netcp_xgbe_serdes_lane_enable(serdes_regs, i);
479   -
480   - /* SB PLL Status Poll */
481   - ret = netcp_xgbe_wait_pll_locked(sw_regs);
482   - if (ret)
483   - return ret;
484   -
485   - netcp_xgbe_serdes_enable_xgmii_port(sw_regs);
486   - netcp_xgbe_serdes_check_lane(serdes_regs, sw_regs);
487   - return ret;
488   -}
489   -
490   -int netcp_xgbe_serdes_init(void __iomem *serdes_regs, void __iomem *xgbe_regs)
491   -{
492   - u32 val;
493   -
494   - /* read COMLANE bits 4:0 */
495   - val = readl(serdes_regs + 0xa00);
496   - if (val & 0x1f) {
497   - pr_debug("XGBE: serdes already in operation - reset\n");
498   - netcp_xgbe_reset_serdes(serdes_regs);
499   - }
500   - return netcp_xgbe_serdes_config(serdes_regs, xgbe_regs);
501   -}
drivers/phy/phy-keystone-serdes.c
Diff comments   View file @ 0f37ee5
Changes suppressed. Click to show
... ... @@ -8,17 +8,6 @@
8 8 *
9 9 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
10 10 *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation version 2.
14   - *
15   - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16   - * kind, whether express or implied; without even the implied warranty
17   - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
21   - *
22 11 * Redistribution and use in source and binary forms, with or without
23 12 * modification, are permitted provided that the following conditions
24 13 * are met:
... ... @@ -60,9 +49,6 @@
60 49 #include <linux/phy/phy.h>
61 50 #include <linux/platform_device.h>
62 51  
63   -/*
64   - * Keystone2 SERDES registers
65   - */
66 52 #define KSERDES_SS_OFFSET 0x1fc0
67 53 #define MOD_VER_REG (KSERDES_SS_OFFSET + 0x00)
68 54 #define MEM_ADR_REG (KSERDES_SS_OFFSET + 0x04)
... ... @@ -86,9 +72,6 @@
86 72 #define CMU1_SS_OFFSET 0x0c00
87 73 #define CMU1_REG(x) (CMU1_SS_OFFSET + x)
88 74  
89   -/*
90   - * XGE PCS-R registers
91   - */
92 75 #define PCSR_OFFSET(x) (x * 0x80)
93 76  
94 77 #define PCSR_TX_CTL(x) (PCSR_OFFSET(x) + 0x00)
95 78  
... ... @@ -102,17 +85,9 @@
102 85 #define reg_rmw(addr, value, mask) \
103 86 writel(((readl(addr) & (~(mask))) | (value & (mask))), (addr))
104 87  
105   -/*
106   - * Replaces bit field [msb:lsb] in register located
107   - * at (base + offset) by val
108   - */
109 88 #define FINSR(base, offset, msb, lsb, val) \
110 89 reg_rmw((base) + (offset), ((val) << (lsb)), GENMASK((msb), (lsb)))
111 90  
112   -/*
113   - * This version of FEXTR is NOT safe for msb = 31, lsb = 0
114   - * but then why would we need FEXTR for that case.
115   - */
116 91 #define FEXTR(val, msb, lsb) \
117 92 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
118 93  
119 94  
120 95  
... ... @@ -125,13 +100,11 @@
125 100 ((MOD_VER(serdes) == 0x4eb9) || (MOD_VER(serdes) == 0x4ebd))
126 101  
127 102 #define MAX_COMPARATORS 5
128   -#define DFE_OFFSET_SAMPLES 100
  103 +#define OFFSET_SAMPLES 100
129 104  
130   -/* yes comparator starts from 1 */
131 105 #define for_each_comparator(i) \
132 106 for (i = 1; i < MAX_COMPARATORS; i++)
133 107  
134   -/* CPU CTRL bits */
135 108 #define CPU_EN BIT(31)
136 109 #define CPU_GO BIT(30)
137 110 #define POR_EN BIT(29)
138 111  
... ... @@ -153,12 +126,10 @@
153 126  
154 127 #define SERDES_REG_INDEX 0
155 128  
156   -/* SERDES internal memory */
157 129 #define KSERDES_XFW_MEM_SIZE SZ_64K
158 130 #define KSERDES_XFW_CONFIG_MEM_SIZE SZ_64
159 131 #define KSERDES_XFW_NUM_PARAMS 5
160 132  
161   -/* Last 64B of the 64KB internal mem is for parameters */
162 133 #define KSERDES_XFW_CONFIG_START_ADDR \
163 134 (KSERDES_XFW_MEM_SIZE - KSERDES_XFW_CONFIG_MEM_SIZE)
164 135  
... ... @@ -174,7 +145,6 @@
174 145 static const char * const ks2_xgbe_serdes_firmwares[] = {"ks2_xgbe_serdes.bin"};
175 146 static const char * const ks2_pcie_serdes_firmwares[] = {"ks2_pcie_serdes.bin"};
176 147  
177   -/* SERDES Link Rate Kbps */
178 148 enum kserdes_link_rate {
179 149 KSERDES_LINK_RATE_1P25G = 1250000,
180 150 KSERDES_LINK_RATE_3P125G = 3125000,
... ... @@ -189,7 +159,6 @@
189 159 KSERDES_LINK_RATE_12P5G = 12500000,
190 160 };
191 161  
192   -/* SERDES Lane Control Rate */
193 162 enum kserdes_lane_ctrl_rate {
194 163 KSERDES_FULL_RATE,
195 164 KSERDES_HALF_RATE,
... ... @@ -234,7 +203,7 @@
234 203 u32 lane_seeds;
235 204 u32 fast_train;
236 205 u32 active_lane;
237   - u32 c1, c2, cm, attn, boost, dlpf, cdrcal;
  206 + u32 c1, c2, cm, attn, boost, dlpf, rxcal;
238 207 u32 lane_config[KSERDES_MAX_LANES];
239 208 };
240 209  
241 210  
... ... @@ -245,14 +214,12 @@
245 214 void __iomem *regs;
246 215 struct regmap *peripheral_regmap;
247 216 struct regmap *pcsr_regmap;
248   - /* non-fw specific */
249 217 const char *init_fw;
250 218 struct serdes_cfg *init_cfg;
251 219 int init_cfg_len;
252 220 enum kserdes_link_rate link_rate;
253 221 bool rx_force_enable;
254 222 struct kserdes_lane_config lane[KSERDES_MAX_LANES];
255   - /* fw specific */
256 223 bool firmware;
257 224 struct kserdes_fw_config fw;
258 225 };
... ... @@ -263,7 +230,7 @@
263 230 struct kserdes_config sc;
264 231 };
265 232  
266   -struct kserdes_comparator_tap_ofs {
  233 +struct kserdes_cmp_tap_ofs {
267 234 u32 cmp;
268 235 u32 tap1;
269 236 u32 tap2;
... ... @@ -273,7 +240,7 @@
273 240 };
274 241  
275 242 struct kserdes_lane_offsets {
276   - struct kserdes_comparator_tap_ofs ct_ofs[MAX_COMPARATORS];
  243 + struct kserdes_cmp_tap_ofs ct_ofs[MAX_COMPARATORS];
277 244 };
278 245  
279 246 struct kserdes_offsets {
280 247  
281 248  
... ... @@ -398,13 +365,11 @@
398 365  
399 366 static u32 _kserdes_read_select_tbus(void __iomem *sregs, int select, int ofs)
400 367 {
401   - /* set tbus address */
402 368 _kserdes_write_tbus_addr(sregs, select, ofs);
403   - /* get tbus value */
404 369 return _kserdes_read_tbus_val(sregs);
405 370 }
406 371  
407   -static inline void kserdes_tap1_patch(struct kserdes_config *sc)
  372 +static inline void kserdes_highspeed_cfg1(struct kserdes_config *sc)
408 373 {
409 374 FINSR(sc->regs, CML_REG(0xbc), 28, 24, 0x1e);
410 375 }
411 376  
412 377  
413 378  
414 379  
415 380  
416 381  
417 382  
418 383  
419 384  
420 385  
421 386  
422 387  
423 388  
424 389  
425 390  
426 391  
427 392  
428 393  
429 394  
430 395  
... ... @@ -438,96 +403,56 @@
438 403 FINSR(sc->regs, LANEX_REG(lane, 0x98), 0, 0, 0x1);
439 404 }
440 405  
441   -static void kserdes_phya_lane_patch(struct kserdes_config *sc, u32 lane)
  406 +static void kserdes_phyb_cfg(struct kserdes_config *sc)
442 407 {
443   - /* pma_ln_vreg */
444   - FINSR(sc->regs, LANEX_REG(lane, 0x18), 25, 24, 0x2);
445   - /* pma_ln_vregh */
446   - FINSR(sc->regs, LANEX_REG(lane, 0x18), 27, 26, 0x2);
447   - /* pma_int_step */
448   - FINSR(sc->regs, LANEX_REG(lane, 0x14), 15, 13, 0x1);
449   - /* turn off att_boost */
450   - FINSR(sc->regs, LANEX_REG(lane, 0x4c), 19, 16, 0xf);
451   - /* set dfe_bias to 10 */
452   - FINSR(sc->regs, LANEX_REG(lane, 0x4c), 23, 20, 0xa);
453   - /* Set offset average num of samples to max value */
454   - FINSR(sc->regs, LANEX_REG(lane, 0x78), 30, 24, 0x7f);
455   -}
456   -
457   -static void kserdes_phyb_patch(struct kserdes_config *sc)
458   -{
459 408 int lane;
460 409  
461   - /* Enables the Center DFE */
462 410 for_each_enable_lane(sc, lane)
463 411 kserdes_cdfe_enable(sc, lane);
464 412  
465   - /* setting initial cdfe */
466 413 FINSR(sc->regs, CML_REG(0x108), 23, 16, 0x04);
467 414  
468   - /* setting rx tap */
469 415 FINSR(sc->regs, CML_REG(0xbc), 28, 24, 0x0);
470 416  
471   - /* enable cdfe_ln_force_cal for cdfe */
472 417 for_each_lane(sc, lane)
473 418 kserdes_cdfe_force_calibration_enable(sc, lane);
474 419 }
475 420  
476 421 static inline void kserdes_set_lane_starts(struct kserdes_config *sc, u32 lane)
477 422 {
478   - /* att start -1 for short channel */
479 423 FINSR(sc->regs, LANEX_REG(lane, 0x8c), 11, 8,
480 424 sc->lane[lane].rx_start.att);
481   - /* boost start -3 for short channel */
482 425 FINSR(sc->regs, LANEX_REG(lane, 0x8c), 15, 12,
483 426 sc->lane[lane].rx_start.boost);
484 427 }
485 428  
486   -static void kserdes_phy_patch(struct kserdes_config *sc)
  429 +static void kserdes_highspeed_cfg(struct kserdes_config *sc)
487 430 {
488 431 int lane;
489 432  
490 433 if (sc->phy_type == KSERDES_PHY_XGE) {
491   - kserdes_phyb_patch(sc);
492   - } else if (sc->link_rate >= KSERDES_LINK_RATE_9P8304G) {
493   - for_each_enable_lane(sc, lane)
494   - kserdes_phya_lane_patch(sc, lane);
  434 + kserdes_phyb_cfg(sc);
495 435 }
496 436  
497   - /* Set ATT and BOOST start values for each lane */
498 437 for_each_enable_lane(sc, lane)
499 438 kserdes_set_lane_starts(sc, lane);
500 439 }
501 440  
502   -static inline void _kserdes_set_training_pattern(void __iomem *sregs)
503   -{
504   - FINSR(sregs, CML_REG(0xc8), 5, 0, 0x0f);
505   -}
506   -
507 441 static void kserdes_set_lane_overrides(struct kserdes_config *sc, u32 lane)
508 442 {
509 443 u32 val_0, val_1, val;
510 444  
511   - /* read laneX_ctrl_i/laneX_pd_i */
512 445 val_0 = _kserdes_read_select_tbus(sc->regs, lane + 1, 0);
513 446  
514   - /* read laneX_rate_i */
515 447 val_1 = _kserdes_read_select_tbus(sc->regs, lane + 1, 1);
516 448  
517   - /* set RESET state */
518 449 val = 0;
519   - /* user rate */
520 450 val |= ((val_1 >> 9) & 0x3) << 1;
521   - /* user PD */
522 451 val |= (val_0 & 0x3) << 3;
523   - /* user ctrl_i */
524 452 val |= ((val_0 >> 2) & 0x1ff) << 5;
525   - /* set override */
526 453 val |= (1 << 14);
527   - /* try claer TX Valid bits */
528 454 val &= ~0x60;
529 455  
530   - /* Only modify the reset bit and the overlay bit */
531 456 FINSR(sc->regs, LANEX_REG(lane, 0x028), 29, 15, val);
532 457 }
533 458  
... ... @@ -548,7 +473,6 @@
548 473 cm = sc->lane[lane].tx_coeff.cm;
549 474  
550 475 if (sc->phy_type == KSERDES_PHY_XGE) {
551   - /* TX Control override enable */
552 476 FINSR(sc->regs, LANEX_REG(lane, 0x8), 11, 8, (cm & 0xf));
553 477 FINSR(sc->regs, LANEX_REG(lane, 0x8), 4, 0, (c1 & 0x1f));
554 478 FINSR(sc->regs, LANEX_REG(lane, 0x8), 7, 5, (c2 & 0x7));
555 479  
556 480  
557 481  
... ... @@ -591,14 +515,10 @@
591 515 struct kserdes_tx_coeff *tc = &sc->lane[lane].tx_coeff;
592 516  
593 517 if (sc->phy_type == KSERDES_PHY_XGE) {
594   - /* Tx Swing */
595 518 FINSR(sc->regs, LANEX_REG(lane, 0x004), 29, 26, tc->att);
596   - /* Regulator voltage */
597 519 FINSR(sc->regs, LANEX_REG(lane, 0x0a4), 2, 0, tc->vreg);
598 520 } else {
599   - /* Tx Swing */
600 521 FINSR(sc->regs, LANEX_REG(lane, 0x004), 28, 25, tc->att);
601   - /* Regulator voltage */
602 522 FINSR(sc->regs, LANEX_REG(lane, 0x084), 7, 5, tc->vreg);
603 523 }
604 524  
605 525  
606 526  
607 527  
608 528  
... ... @@ -640,41 +560,24 @@
640 560 u32 ofs = 28;
641 561 u32 ret, i;
642 562  
643   - /*
644   - * assume all enable lanes not-ok (1) and all others
645   - * ok (0) to start
646   - */
647 563 for_each_enable_lane(sc, i)
648 564 lanes_not_ok |= (1 << i);
649 565  
650   - /*
651   - * This is not a mistake. For 2-laner, we
652   - * check bit 29 and 30, NOT 28 and 29.
653   - */
654 566 if (!FOUR_LANE(sc->regs))
655 567 ofs = 29;
656 568  
657 569 do {
658 570 time_check = jiffies;
659 571 for_each_enable_lane(sc, i) {
660   - /*
661   - * no need to check again if this lane's status
662   - * is already good
663   - */
664 572 if (!(lanes_not_ok & (1 << i)))
665 573 continue;
666 574  
667 575 ret = kserdes_readl(sc->regs, CML_REG(0x1f8));
668 576  
669   - /*
670   - * clear corresponding lane_not_ok bit if
671   - * status is good (1)
672   - */
673 577 if (ret & BIT(ofs + i))
674 578 lanes_not_ok &= ~(1 << i);
675 579 }
676 580  
677   - /* get out if all lanes are good to go */
678 581 if (!lanes_not_ok)
679 582 return 0;
680 583  
681 584  
682 585  
683 586  
... ... @@ -692,34 +595,21 @@
692 595 u32 lanes_not_ok = 0;
693 596 u32 ret, i;
694 597  
695   - /*
696   - * assume all enable lanes not-ok (1) and all others
697   - * ok (0) to start
698   - */
699 598 for_each_enable_lane(sc, i)
700 599 lanes_not_ok |= (1 << i);
701 600  
702 601 do {
703 602 time_check = jiffies;
704 603 for_each_enable_lane(sc, i) {
705   - /*
706   - * no need to check again if this lane's status
707   - * is already good
708   - */
709 604 if (!(lanes_not_ok & (1 << i)))
710 605 continue;
711 606  
712 607 ret = _kserdes_read_select_tbus(sc->regs, i + 1, 0x02);
713 608  
714   - /*
715   - * clear corresponding lane_not_ok bit if
716   - * status is good (0)
717   - */
718 609 if (!(ret & BIT(4)))
719 610 lanes_not_ok &= ~(1 << i);
720 611 }
721 612  
722   - /* get out if all lanes are good to go */
723 613 if (!lanes_not_ok)
724 614 return 0;
725 615  
726 616  
... ... @@ -739,10 +629,8 @@
739 629 static inline void kserdes_release_reset(struct kserdes_config *sc, u32 lane)
740 630 {
741 631 if (sc->phy_type == KSERDES_PHY_XGE) {
742   - /* set pma_cmu_sel to 1 */
743 632 FINSR(sc->regs, LANEX_REG(lane, 0x60), 0, 0, 0x1);
744 633 }
745   - /* release reset */
746 634 _kserdes_lane_reset(sc->regs, lane, 0);
747 635 }
748 636  
... ... @@ -756,7 +644,6 @@
756 644 if (!poll)
757 645 goto done;
758 646  
759   - /* Check Lane OK */
760 647 if (sc->phy_type == KSERDES_PHY_PCIE)
761 648 ret = kserdes_deassert_reset_poll_pcie(sc);
762 649 else
... ... @@ -778,7 +665,6 @@
778 665 FINSR(sregs, LANE_CTRL_STS_REG(lane), 15, 13, 0x7);
779 666 }
780 667  
781   -/* Caller should make sure sgmii cannot be fullrate */
782 668 static inline int _kserdes_set_lane_ctrl_rate(void __iomem *sregs, u32 lane,
783 669 enum kserdes_lane_ctrl_rate rate)
784 670 {
785 671  
... ... @@ -798,9 +684,7 @@
798 684 return -EINVAL;
799 685 }
800 686  
801   - /* Tx */
802 687 FINSR(sregs, LANE_CTRL_STS_REG(lane), 28, 26, rate_mode);
803   - /* Rx */
804 688 FINSR(sregs, LANE_CTRL_STS_REG(lane), 12, 10, rate_mode);
805 689 return 0;
806 690 }
807 691  
... ... @@ -828,11 +712,9 @@
828 712 return;
829 713 }
830 714  
831   - /* disable attenuation auto scale */
832 715 FINSR(sc->regs, LANEX_REG(lane, 0x30), 11, 11, 0x1);
833 716 FINSR(sc->regs, LANEX_REG(lane, 0x30), 13, 12, 0x0);
834 717  
835   - /* set NES bit if loopback enabled */
836 718 if (sc->lane[lane].loopback)
837 719 _kserdes_set_lane_loopback(sc->regs, lane, sc->link_rate);
838 720  
839 721  
... ... @@ -903,10 +785,8 @@
903 785 {
904 786 u32 val, i;
905 787  
906   - /* Check PLL OK Status Bit */
907 788 val = _kserdes_get_pll_status(sc->regs);
908 789 if (!val) {
909   - /* pll is not ready */
910 790 goto done;
911 791 }
912 792  
913 793  
... ... @@ -916,15 +796,10 @@
916 796 goto done;
917 797 }
918 798  
919   - /* Check Lane OK Status Bits */
920 799 for_each_enable_lane(sc, i)
921 800 val &= _kserdes_get_lane_status(sc->regs, i, sc->phy_type);
922 801  
923 802 done:
924   - /*
925   - * if any of the status is 0, this is 0
926   - * i.e. serdes status is not good
927   - */
928 803 return val;
929 804 }
930 805  
931 806  
932 807  
933 808  
934 809  
... ... @@ -961,20 +836,16 @@
961 836  
962 837 for_each_lane(sc, i) {
963 838 FINSR(sc->regs, LANEX_REG(i, 0x7c), 31, 24, term);
964   - /* set termination override */
965 839 FINSR(sc->regs, LANEX_REG(i, 0x7c), 20, 20, 0x1);
966 840 }
967 841 }
968 842  
969   -/* lane is 0-based */
970 843 static void
971   -_kserdes_get_cmp_tap_offsets_xge(void __iomem *sregs, u32 lane, u32 cmp,
972   - struct kserdes_comparator_tap_ofs *ofs)
  844 +_kserdes_write_offsets_xge(void __iomem *sregs, u32 lane, u32 cmp,
  845 + struct kserdes_cmp_tap_ofs *ofs)
973 846 {
974   - /* set comparator number */
975 847 FINSR(sregs, CML_REG(0x8c), 23, 21, cmp);
976 848  
977   - /* read offsets */
978 849 FINSR(sregs, CMU0_REG(0xfc), 26, 16, ((lane + 2) << 8) + 0x11);
979 850 ofs->cmp = (_kserdes_read_tbus_val(sregs) & 0x0ff0) >> 4;
980 851  
... ... @@ -998,8 +869,8 @@
998 869 static void kserdes_add_offsets_xge(struct kserdes_config *sc,
999 870 struct kserdes_offsets *sofs)
1000 871 {
1001   - struct kserdes_comparator_tap_ofs *ctofs;
1002   - struct kserdes_comparator_tap_ofs sample;
  872 + struct kserdes_cmp_tap_ofs *ctofs;
  873 + struct kserdes_cmp_tap_ofs sample;
1003 874 struct kserdes_lane_offsets *lofs;
1004 875 u32 lane, cmp;
1005 876  
... ... @@ -1008,7 +879,7 @@
1008 879 for_each_comparator(cmp) {
1009 880 ctofs = &lofs->ct_ofs[cmp];
1010 881  
1011   - _kserdes_get_cmp_tap_offsets_xge(sc->regs, lane,
  882 + _kserdes_write_offsets_xge(sc->regs, lane,
1012 883 cmp, &sample);
1013 884  
1014 885 ctofs->cmp += sample.cmp;
1015 886  
1016 887  
1017 888  
... ... @@ -1021,15 +892,11 @@
1021 892 }
1022 893 }
1023 894  
1024   -/* lane is 0-based */
1025 895 static void
1026 896 kserdes_get_cmp_tap_offsets_non_xge(void __iomem *sregs, u32 lane, u32 cmp,
1027   - struct kserdes_comparator_tap_ofs *ofs)
  897 + struct kserdes_cmp_tap_ofs *ofs)
1028 898 {
1029   - /* set comparator number */
1030 899 FINSR(sregs, CML_REG(0x8c), 23, 21, cmp);
1031   -
1032   - /* read offsets */
1033 900 FINSR(sregs, CMU0_REG(0x8), 31, 24, ((lane + 1) << 5) + 0x12);
1034 901 ofs->cmp = (_kserdes_read_tbus_val(sregs) & 0x0ff0) >> 4;
1035 902 }
... ... @@ -1037,8 +904,8 @@
1037 904 static void kserdes_add_offsets_non_xge(struct kserdes_config *sc,
1038 905 struct kserdes_offsets *sofs)
1039 906 {
1040   - struct kserdes_comparator_tap_ofs *ctofs;
1041   - struct kserdes_comparator_tap_ofs sample;
  907 + struct kserdes_cmp_tap_ofs *ctofs;
  908 + struct kserdes_cmp_tap_ofs sample;
1042 909 struct kserdes_lane_offsets *lofs;
1043 910 u32 lane, cmp;
1044 911  
1045 912  
... ... @@ -1058,14 +925,13 @@
1058 925 static void kserdes_get_average_offsets(struct kserdes_config *sc, u32 samples,
1059 926 struct kserdes_offsets *sofs)
1060 927 {
1061   - struct kserdes_comparator_tap_ofs *ctofs;
  928 + struct kserdes_cmp_tap_ofs *ctofs;
1062 929 struct kserdes_lane_offsets *lofs;
1063 930 u32 i, lane, cmp;
1064 931 int ret;
1065 932  
1066 933 memset(sofs, 0, sizeof(*sofs));
1067 934  
1068   - /* get the total of each offset for specified number of samples */
1069 935 for (i = 0; i < samples; i++) {
1070 936 kserdes_assert_reset(sc);
1071 937 ret = kserdes_deassert_reset(sc, 1);
... ... @@ -1082,7 +948,6 @@
1082 948 kserdes_add_offsets_non_xge(sc, sofs);
1083 949 }
1084 950  
1085   - /* take the average */
1086 951 for_each_lane(sc, lane) {
1087 952 lofs = &sofs->lane_ofs[lane];
1088 953 for_each_comparator(cmp) {
1089 954  
1090 955  
1091 956  
1092 957  
1093 958  
1094 959  
1095 960  
1096 961  
1097 962  
1098 963  
1099 964  
1100 965  
... ... @@ -1103,42 +968,30 @@
1103 968  
1104 969 static void
1105 970 _kserdes_override_cmp_tap_offsets(void __iomem *sregs, u32 lane, u32 cmp,
1106   - struct kserdes_comparator_tap_ofs *ofs)
  971 + struct kserdes_cmp_tap_ofs *ofs)
1107 972 {
1108   - /* set dfe_shadow_lane_sel */
1109 973 FINSR(sregs, CML_REG(0xf0), 27, 26, (lane + 1));
1110 974  
1111   - /* set cmp_offset_ovr_en to 1 */
1112 975 FINSR(sregs, CML_REG(0x98), 24, 24, 0x1);
1113 976  
1114   - /* set rxeq_ovr_en to 0x1 */
1115 977 FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1116 978  
1117   - /* set rxeq_dfe_cmp_sel_ovr to comp_no */
1118 979 FINSR(sregs, LANEX_REG(lane, 0x30), 7, 5, cmp);
1119 980  
1120   - /* set dfe_tap_ovr_en to 1 */
1121 981 FINSR(sregs, LANEX_REG(lane, 0x5c), 31, 31, 0x1);
1122 982  
1123   - /* set cmp offset override */
1124 983 FINSR(sregs, CML_REG(0x9c), 7, 0, ofs->cmp);
1125   - /* set tap offset overrides */
1126 984 FINSR(sregs, LANEX_REG(lane, 0x58), 30, 24, ofs->tap1);
1127 985 FINSR(sregs, LANEX_REG(lane, 0x5c), 5, 0, ofs->tap2);
1128 986 FINSR(sregs, LANEX_REG(lane, 0x5c), 13, 8, ofs->tap3);
1129 987 FINSR(sregs, LANEX_REG(lane, 0x5c), 21, 16, ofs->tap4);
1130 988 FINSR(sregs, LANEX_REG(lane, 0x5c), 29, 24, ofs->tap5);
1131 989  
1132   - /* set rxeq_ovr_latch_o = 0x1 */
1133 990 FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x1);
1134   - /* set rxeq_ovr_latch_o = 0x0 */
1135 991 FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x0);
1136 992  
1137   - /* set cmp_offset_ovr_en to 0 */
1138 993 FINSR(sregs, CML_REG(0x98), 24, 24, 0x0);
1139   - /* set rxeq_ovr_en to 0x0 */
1140 994 FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x0);
1141   - /* set dfe_tap_ovr_en to 0 */
1142 995 FINSR(sregs, LANEX_REG(lane, 0x5c), 31, 31, 0x0);
1143 996 }
1144 997  
1145 998  
1146 999  
1147 1000  
1148 1001  
... ... @@ -1146,18 +999,13 @@
1146 999 _kserdes_override_cmp_offset_cdfe(void __iomem *sregs, u32 lane,
1147 1000 u32 cmp, u32 cmp_offset)
1148 1001 {
1149   - /* enable comparator offset calibrate */
1150 1002 FINSR(sregs, LANEX_REG(lane, 0x58), 18, 18, 0x1);
1151 1003  
1152   - /* set gcfsm sel override to comparator */
1153 1004 FINSR(sregs, LANEX_REG(lane, 0x4c), 5, 2, (0x1 << (cmp - 1)));
1154   - /* set comparator offset */
1155 1005 FINSR(sregs, LANEX_REG(lane, 0x48), 24, 17, cmp_offset);
1156   - /* latch in value */
1157 1006 FINSR(sregs, LANEX_REG(lane, 0x48), 29, 29, 0x1);
1158 1007 FINSR(sregs, LANEX_REG(lane, 0x48), 29, 29, 0x0);
1159 1008  
1160   - /* disable comparator offset calibrate */
1161 1009 FINSR(sregs, LANEX_REG(lane, 0x58), 18, 18, 0x0);
1162 1010 }
1163 1011  
1164 1012  
1165 1013  
1166 1014  
1167 1015  
1168 1016  
1169 1017  
1170 1018  
... ... @@ -1165,36 +1013,29 @@
1165 1013 _kserdes_override_tap_offset_cdfe(void __iomem *sregs, u32 lane,
1166 1014 u32 tap, u32 width, u32 tap_offset)
1167 1015 {
1168   - /* enable tap */
1169 1016 FINSR(sregs, LANEX_REG(lane, 0x58), 23, 19, BIT(tap - 1));
1170   - /* set tap offset */
1171 1017 FINSR(sregs, LANEX_REG(lane, 0x48), 17 + (width - 1), 17, tap_offset);
1172   - /* latch in value */
1173 1018 FINSR(sregs, LANEX_REG(lane, 0x48), 29, 29, 0x1);
1174 1019 FINSR(sregs, LANEX_REG(lane, 0x48), 29, 29, 0x0);
1175 1020 }
1176 1021  
1177 1022 static void
1178 1023 _kserdes_override_cmp_tap_offsets_cdfe(void __iomem *sregs, u32 lane, u32 cmp,
1179   - struct kserdes_comparator_tap_ofs *ofs)
  1024 + struct kserdes_cmp_tap_ofs *ofs)
1180 1025 {
1181   - /* enable overrides */
1182 1026 FINSR(sregs, LANEX_REG(lane, 0x58), 16, 16, 0x1);
1183 1027 FINSR(sregs, LANEX_REG(lane, 0x48), 16, 16, 0x1);
1184 1028  
1185 1029 _kserdes_override_cmp_offset_cdfe(sregs, lane, cmp, ofs->cmp);
1186 1030  
1187   - /* enable tap offset calibrate */
1188 1031 FINSR(sregs, LANEX_REG(lane, 0x58), 17, 17, 0x1);
1189 1032  
1190   - /* set tap offsets */
1191 1033 _kserdes_override_tap_offset_cdfe(sregs, lane, 1, 7, ofs->tap1);
1192 1034 _kserdes_override_tap_offset_cdfe(sregs, lane, 2, 6, ofs->tap2);
1193 1035 _kserdes_override_tap_offset_cdfe(sregs, lane, 3, 6, ofs->tap3);
1194 1036 _kserdes_override_tap_offset_cdfe(sregs, lane, 4, 6, ofs->tap4);
1195 1037 _kserdes_override_tap_offset_cdfe(sregs, lane, 5, 6, ofs->tap5);
1196 1038  
1197   - /* disable overrides */
1198 1039 FINSR(sregs, LANEX_REG(lane, 0x58), 16, 16, 0x0);
1199 1040 FINSR(sregs, LANEX_REG(lane, 0x48), 16, 16, 0x0);
1200 1041 FINSR(sregs, LANEX_REG(lane, 0x58), 18, 18, 0x0);
... ... @@ -1204,7 +1045,7 @@
1204 1045 static void kserdes_set_offsets_xge(struct kserdes_config *sc,
1205 1046 struct kserdes_offsets *sofs)
1206 1047 {
1207   - struct kserdes_comparator_tap_ofs *ctofs;
  1048 + struct kserdes_cmp_tap_ofs *ctofs;
1208 1049 struct kserdes_lane_offsets *lofs;
1209 1050 u32 lane, cmp;
1210 1051  
... ... @@ -1223,7 +1064,7 @@
1223 1064 static void kserdes_set_offsets_non_xge(struct kserdes_config *sc,
1224 1065 struct kserdes_offsets *sofs)
1225 1066 {
1226   - struct kserdes_comparator_tap_ofs *ctofs;
  1067 + struct kserdes_cmp_tap_ofs *ctofs;
1227 1068 struct kserdes_lane_offsets *lofs;
1228 1069 u32 lane, cmp;
1229 1070  
... ... @@ -1246,7 +1087,7 @@
1246 1087 kserdes_set_offsets_non_xge(sc, sofs);
1247 1088 }
1248 1089  
1249   -static void kserdes_dfe_offset_calibration(struct kserdes_config *sc,
  1090 +static void kserdes_phyb_init_cfg(struct kserdes_config *sc,
1250 1091 struct kserdes_offsets *sofs)
1251 1092 {
1252 1093 int lane;
1253 1094  
... ... @@ -1257,13 +1098,11 @@
1257 1098 /* amount of time to sleep is by experiment */
1258 1099 usleep_range(10, 20);
1259 1100  
1260   - /* offset compensation patch */
1261   - kserdes_get_average_offsets(sc, DFE_OFFSET_SAMPLES, sofs);
  1101 + kserdes_get_average_offsets(sc, OFFSET_SAMPLES, sofs);
1262 1102 kserdes_set_offsets(sc, sofs);
1263 1103 /* amount of time to sleep is by experiment */
1264 1104 usleep_range(10, 20);
1265 1105  
1266   - /* re-acquire signal detect */
1267 1106 for_each_lane(sc, lane)
1268 1107 kserdes_force_signal_detect_high(sc, lane);
1269 1108  
... ... @@ -1271,90 +1110,6 @@
1271 1110 usleep_range(10, 20);
1272 1111 }
1273 1112  
1274   -static void kserdes_override_tap_offsets(struct kserdes_config *sc, u32 lane)
1275   -{
1276   - u32 tap1val, tap2val, tap3val, tap4val, tap5val;
1277   - void __iomem *sregs = sc->regs;
1278   - u32 cmp, tap1_ofs;
1279   -
1280   - for_each_comparator(cmp) {
1281   - /*
1282   - * adjust taps only for center comparators of
1283   - * of conparator 1 and 3
1284   - */
1285   - if (!(cmp & 0x1))
1286   - continue;
1287   -
1288   - /* set comparator number */
1289   - FINSR(sregs, CML_REG(0x8c), 23, 21, cmp);
1290   -
1291   - /* read offsets */
1292   - FINSR(sregs, CMU0_REG(0x8), 31, 24, ((lane + 1) << 5) + 0x12);
1293   - tap1_ofs = (_kserdes_read_tbus_val(sregs) & 0x000f) << 3;
1294   -
1295   - FINSR(sregs, CMU0_REG(0x8), 31, 24, ((lane + 1) << 5) + 0x13);
1296   - tap1_ofs |= (_kserdes_read_tbus_val(sregs) & 0x0e00) >> 9;
1297   -
1298   - tap1val = tap1_ofs - 14;
1299   - tap2val = 31;
1300   - tap3val = 31;
1301   - tap4val = 31;
1302   - tap5val = 31;
1303   -
1304   - /* set dfe_shadow_lane_sel */
1305   - FINSR(sregs, CML_REG(0xf0), 27, 26, lane + 1);
1306   - /* Set rxeq_ovr_en to 0x1 */
1307   - FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1308   - /* set rxeq_dfe_cmp_sel_ovr to comp_no */
1309   - FINSR(sregs, LANEX_REG(lane, 0x30), 7, 5, cmp);
1310   - /* set dfe_tap_ovr_en to 1 */
1311   - FINSR(sregs, LANEX_REG(lane, 0x5c), 31, 31, 0x1);
1312   -
1313   - /* set tap overrides */
1314   - FINSR(sregs, LANEX_REG(lane, 0x58), 30, 24, tap1val);
1315   - FINSR(sregs, LANEX_REG(lane, 0x5c), 6, 0, tap2val);
1316   - FINSR(sregs, LANEX_REG(lane, 0x5c), 13, 8, tap3val);
1317   - FINSR(sregs, LANEX_REG(lane, 0x5c), 21, 16, tap4val);
1318   - FINSR(sregs, LANEX_REG(lane, 0x5c), 29, 24, tap5val);
1319   -
1320   - /* set rxeq_ovr_latch_o = 0x1 */
1321   - FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x1);
1322   - /* set rxeq_ovr_latch_o = 0x0 */
1323   - FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x0);
1324   -
1325   - /* set rxeq_ovr_en to 0 */
1326   - FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x0);
1327   - /* set dfe_tap_ovr_en to 0 */
1328   - FINSR(sregs, LANEX_REG(lane, 0x5c), 31, 31, 0x0);
1329   -
1330   - /*
1331   - * This part of code will latch in offsets to
1332   - * tap adaptation logic so that if adaptation
1333   - * occurs, it will pick these offsets
1334   - */
1335   - /* enable overrides */
1336   - FINSR(sregs, LANEX_REG(lane, 0x58), 16, 16, 0x1);
1337   - FINSR(sregs, LANEX_REG(lane, 0x48), 16, 16, 0x1);
1338   -
1339   - /* set gcfsm_cmp_sel to comp_no */
1340   - FINSR(sregs, LANEX_REG(lane, 0x4c), 5, 2, (0x1 << (cmp - 1)));
1341   - /* enable tap offset calibrate */
1342   - FINSR(sregs, LANEX_REG(lane, 0x58), 17, 17, 0x1);
1343   -
1344   - /* enable taps */
1345   - _kserdes_override_tap_offset_cdfe(sregs, lane, 1, 7, tap1val);
1346   - _kserdes_override_tap_offset_cdfe(sregs, lane, 2, 6, tap2val);
1347   - _kserdes_override_tap_offset_cdfe(sregs, lane, 3, 6, tap3val);
1348   - _kserdes_override_tap_offset_cdfe(sregs, lane, 4, 6, tap4val);
1349   - _kserdes_override_tap_offset_cdfe(sregs, lane, 5, 6, tap5val);
1350   -
1351   - /* Disable overrides */
1352   - FINSR(sregs, LANEX_REG(lane, 0x58), 16, 16, 0x0);
1353   - FINSR(sregs, LANEX_REG(lane, 0x48), 16, 16, 0x0);
1354   - FINSR(sregs, LANEX_REG(lane, 0x58), 17, 17, 0x0);
1355   - }
1356   -}
1357   -
1358 1113 static int kserdes_wait_lane_rx_valid(struct kserdes_config *sc, u32 lane)
1359 1114 {
1360 1115 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1361 1116  
1362 1117  
... ... @@ -1375,20 +1130,16 @@
1375 1130 } while (true);
1376 1131 }
1377 1132  
1378   -static int kserdes_att_boost_phya_macro_patch(struct kserdes_config *sc)
  1133 +static int kserdes_att_phya_cfg(struct kserdes_config *sc)
1379 1134 {
1380 1135 u32 i, att_read[KSERDES_MAX_LANES], att_start[KSERDES_MAX_LANES];
1381 1136 int ret;
1382 1137  
1383   - /* First save a copy of initial att start value */
1384 1138 for_each_lane(sc, i) {
1385 1139 att_start[i] = kserdes_readl(sc->regs, LANEX_REG(i, 0x8c));
1386 1140 att_start[i] = (att_start[i] >> 8) & 0xf;
1387 1141 }
1388   - /*
1389   - * Get att and fix this as start value. Turn off att adaptation and
1390   - * do boost readaptation
1391   - */
  1142 +
1392 1143 for_each_lane(sc, i) {
1393 1144 att_read[i] = _kserdes_read_select_tbus(
1394 1145 sc->regs, i + 1,
1395 1146  
1396 1147  
1397 1148  
1398 1149  
1399 1150  
1400 1151  
... ... @@ -1398,24 +1149,16 @@
1398 1149 }
1399 1150  
1400 1151 for_each_lane(sc, i) {
1401   - /* att start */
1402 1152 FINSR(sc->regs, LANEX_REG(i, 0x8c), 11, 8, att_read[i]);
1403 1153 }
1404 1154  
1405   - /* clear att init calibration */
1406 1155 FINSR(sc->regs, CML_REG(0x84), 0, 0, 0x0);
1407   - /* clear att re-calibration */
1408 1156 FINSR(sc->regs, CML_REG(0x8c), 24, 24, 0x0);
1409 1157  
1410   - /* force calibration on all lanes */
1411   - /* set att continuous recal */
1412 1158 FINSR(sc->regs, CML_REG(0x98), 7, 7, 0x1);
1413   - /* clear att continuous recal */
1414 1159 FINSR(sc->regs, CML_REG(0x98), 7, 7, 0x0);
1415   - /* amount of time to sleep is by experiment */
1416 1160 usleep_range(300, 400);
1417 1161  
1418   - /* check rx valid */
1419 1162 for_each_enable_lane(sc, i) {
1420 1163 ret = kserdes_wait_lane_rx_valid(sc, i);
1421 1164 if (ret) {
1422 1165  
1423 1166  
1424 1167  
... ... @@ -1425,24 +1168,21 @@
1425 1168 }
1426 1169 }
1427 1170  
1428   - /* write back initial att start value */
1429 1171 for_each_lane(sc, i)
1430 1172 FINSR(sc->regs, LANEX_REG(i, 0x8c), 11, 8, att_start[i]);
1431 1173  
1432   - /* turn att adaptation back on */
1433 1174 FINSR(sc->regs, CML_REG(0x84), 0, 0, 0x1);
1434 1175 FINSR(sc->regs, CML_REG(0x8c), 24, 24, 0x1);
1435 1176  
1436 1177 return 0;
1437 1178 }
1438 1179  
1439   -static int kserdes_att_boost_phya_lane_patch(struct kserdes_config *sc,
  1180 +static int kserdes_boost_phya_cfg(struct kserdes_config *sc,
1440 1181 u32 lane)
1441 1182 {
1442 1183 u32 boost_read;
1443 1184 int ret;
1444 1185  
1445   - /* check lane rx valid */
1446 1186 ret = kserdes_wait_lane_rx_valid(sc, lane);
1447 1187 if (ret) {
1448 1188 dev_err(sc->dev, "lane %d wait rx valid failed: %d\n",
1449 1189  
1450 1190  
1451 1191  
1452 1192  
1453 1193  
1454 1194  
... ... @@ -1450,25 +1190,18 @@
1450 1190 return ret;
1451 1191 }
1452 1192  
1453   - /* check boost value */
1454 1193 boost_read = _kserdes_read_select_tbus(
1455 1194 sc->regs, lane + 1,
1456 1195 (sc->phy_type == KSERDES_PHY_XGE) ?
1457 1196 0x10 : 0x11);
1458 1197 boost_read = (boost_read >> 8) & 0xf;
1459 1198  
1460   - /* increment boost by 1 if it's 0 */
1461 1199 if (!boost_read) {
1462   - /* Set rxeq_ovr_en to 1 */
1463 1200 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1464   - /* set rxeq_ovr_load_en for boost only */
1465 1201 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 18, 12, 0x2);
1466   - /* set rxeq_ovr_load for a value of 1 */
1467 1202 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 9, 3, 0x1);
1468   - /* latch in new boost value */
1469 1203 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 10, 10, 0x1);
1470 1204 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 10, 10, 0x0);
1471   - /* reset previous registers */
1472 1205 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 2, 2, 0x0);
1473 1206 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 18, 12, 0x0);
1474 1207 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 9, 3, 0x0);
1475 1208  
1476 1209  
1477 1210  
... ... @@ -1476,17 +1209,17 @@
1476 1209 return 0;
1477 1210 }
1478 1211  
1479   -static inline void kserdes_att_boost_phya_patch(struct kserdes_config *sc)
  1212 +static inline void kserdes_rx_att_boost_phya_cfg(struct kserdes_config *sc)
1480 1213 {
1481 1214 int lane;
1482 1215  
1483   - kserdes_att_boost_phya_macro_patch(sc);
  1216 + kserdes_att_phya_cfg(sc);
1484 1217  
1485 1218 for_each_enable_lane(sc, lane)
1486   - kserdes_att_boost_phya_lane_patch(sc, lane);
  1219 + kserdes_boost_phya_cfg(sc, lane);
1487 1220 }
1488 1221  
1489   -static void kserdes_att_boost_phyb_lane_patch(struct kserdes_config *sc,
  1222 +static void kserdes_rx_att_boost_phyb_cfg(struct kserdes_config *sc,
1490 1223 u32 lane)
1491 1224 {
1492 1225 u32 tbus_ofs, rxeq_init_reg_ofs, rxeq_ln_reg_ofs, rxeq_ln_force_bit;
... ... @@ -1494,7 +1227,6 @@
1494 1227 u32 att_start, att_read, boost_read;
1495 1228 int ret;
1496 1229  
1497   - /* some setups */
1498 1230 if (sc->phy_type == KSERDES_PHY_XGE) {
1499 1231 tbus_ofs = 0x10;
1500 1232 rxeq_init_reg_ofs = 0x9c;
1501 1233  
1502 1234  
1503 1235  
1504 1236  
1505 1237  
1506 1238  
... ... @@ -1507,30 +1239,21 @@
1507 1239 rxeq_ln_force_bit = 11;
1508 1240 }
1509 1241  
1510   - /* First save a copy of initial att start value */
1511 1242 att_start = kserdes_readl(sregs, LANEX_REG(lane, 0x8c));
1512 1243 att_start = (att_start >> 8) & 0xf;
1513 1244  
1514   - /* Get att and fix this as start value. Turn off att adaptation and
1515   - * do boost readaptation
1516   - */
1517 1245 att_read = _kserdes_read_select_tbus(sregs, lane + 1, tbus_ofs);
1518 1246 att_read = (att_read >> 4) & 0xf;
1519 1247  
1520   - /* att start */
1521 1248 FINSR(sregs, LANEX_REG(lane, 0x8c), 11, 8, att_read);
1522   - /* clear att init calibration */
1523 1249 FINSR(sregs, LANEX_REG(lane, rxeq_init_reg_ofs), 0, 0, 0x0);
1524   - /* clear att re-calibration */
1525 1250 FINSR(sregs, CML_REG(0x8c), 24, 24, 0x0);
1526 1251  
1527   - /* force calibration */
1528 1252 FINSR(sregs, LANEX_REG(lane, rxeq_ln_reg_ofs),
1529 1253 rxeq_ln_force_bit, rxeq_ln_force_bit, 0x1);
1530 1254 FINSR(sregs, LANEX_REG(lane, rxeq_ln_reg_ofs),
1531 1255 rxeq_ln_force_bit, rxeq_ln_force_bit, 0x0);
1532 1256  
1533   - /* check lane rx valid */
1534 1257 ret = kserdes_wait_lane_rx_valid(sc, lane);
1535 1258 if (ret) {
1536 1259 dev_err(sc->dev, "lane %d wait rx valid failed: %d\n",
1537 1260  
1538 1261  
1539 1262  
1540 1263  
1541 1264  
1542 1265  
1543 1266  
1544 1267  
1545 1268  
1546 1269  
1547 1270  
1548 1271  
... ... @@ -1539,49 +1262,34 @@
1539 1262 /* amount of time to sleep is by experiment */
1540 1263 usleep_range(300, 400);
1541 1264  
1542   - /* check boost value */
1543 1265 boost_read = _kserdes_read_select_tbus(sregs, lane + 1, tbus_ofs);
1544 1266 boost_read = (boost_read >> 8) & 0xf;
1545 1267  
1546   - /* increment boost by 1 if it's 0 */
1547 1268 if (!boost_read) {
1548   - /* Set rxeq_ovr_en to 1 */
1549 1269 FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1550   - /* set rxeq_ovr_load_en for boost only */
1551 1270 FINSR(sregs, LANEX_REG(lane, 0x2c), 18, 12, 0x2);
1552   - /* set rxeq_ovr_load for a value of 1 */
1553 1271 FINSR(sregs, LANEX_REG(lane, 0x2c), 9, 3, 0x1);
1554   - /* latch in new boost value */
1555 1272 FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x1);
1556 1273 FINSR(sregs, LANEX_REG(lane, 0x2c), 10, 10, 0x0);
1557   - /* reset previous registers */
1558 1274 FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x0);
1559 1275 FINSR(sregs, LANEX_REG(lane, 0x2c), 18, 12, 0x0);
1560 1276 FINSR(sregs, LANEX_REG(lane, 0x2c), 9, 3, 0x0);
1561 1277 }
1562 1278  
1563   - /* write back initial att start value */
1564 1279 FINSR(sregs, LANEX_REG(lane, 0x8c), 11, 8, att_start);
1565   - /* turn att adaptation back on */
1566 1280 FINSR(sregs, LANEX_REG(lane, rxeq_init_reg_ofs), 0, 0, 0x1);
1567 1281 FINSR(sregs, CML_REG(0x8c), 24, 24, 0x1);
1568 1282 }
1569 1283  
1570   -static inline void kserdes_att_boost_phyb_patch(struct kserdes_config *sc,
1571   - u32 lane)
  1284 +static void kserdes_rx_att_boost_cfg(struct kserdes_config *sc)
1572 1285 {
1573   - kserdes_att_boost_phyb_lane_patch(sc, lane);
1574   -}
1575   -
1576   -static void kserdes_att_boost_phy_patch(struct kserdes_config *sc)
1577   -{
1578 1286 int lane;
1579 1287  
1580 1288 if (sc->phy_type != KSERDES_PHY_XGE) {
1581   - kserdes_att_boost_phya_patch(sc);
  1289 + kserdes_rx_att_boost_phya_cfg(sc);
1582 1290 } else {
1583 1291 for_each_lane(sc, lane)
1584   - kserdes_att_boost_phyb_patch(sc, lane);
  1292 + kserdes_rx_att_boost_phyb_cfg(sc, lane);
1585 1293 }
1586 1294 }
1587 1295  
1588 1296  
1589 1297  
1590 1298  
1591 1299  
... ... @@ -1593,35 +1301,16 @@
1593 1301 for_each_enable_lane(sc, i)
1594 1302 lanes_enable |= (1 << i);
1595 1303  
1596   - /* configure Tap 1 if PHY-A and link rate greater than 8Gbaud */
1597   - if (sc->link_rate >= KSERDES_LINK_RATE_9P8304G)
1598   - kserdes_tap1_patch(sc);
1599   -
1600   - /*
1601   - * disable transmitter on all lanes to prevent
1602   - * receiver from adapting
1603   - */
1604 1304 for_each_lane(sc, i)
1605 1305 kserdes_set_tx_idle(sc, i);
1606 1306  
1607   - /* apply patch for link rates greater than 8Gbaud */
1608   - kserdes_phy_patch(sc);
  1307 + kserdes_highspeed_cfg(sc);
1609 1308  
1610   - /* write boost training pattern for Hyperlink functional mode */
1611   - if (sc->phy_type == KSERDES_PHY_HYPERLINK)
1612   - _kserdes_set_training_pattern(sc->regs);
1613   -
1614   - /* assert serdes reset */
1615 1309 kserdes_assert_reset(sc);
1616 1310  
1617   - /* apply the TX and RX FIR coefficients to the lanes */
1618 1311 for_each_enable_lane(sc, i)
1619 1312 kserdes_set_tx_rx_fir_coeff(sc, i);
1620 1313  
1621   - /*
1622   - * force Signal Detect Low. This resets the CDR,
1623   - * Attenuation and Boost circuitry
1624   - */
1625 1314 for_each_enable_lane(sc, i)
1626 1315 kserdes_force_signal_detect_low(sc, i);
1627 1316  
... ... @@ -1631,7 +1320,6 @@
1631 1320 return ret;
1632 1321 }
1633 1322  
1634   - /* allow signal detect enable */
1635 1323 for_each_enable_lane(sc, i)
1636 1324 kserdes_set_lane_rate(sc, i);
1637 1325  
1638 1326  
1639 1327  
1640 1328  
1641 1329  
... ... @@ -1643,27 +1331,16 @@
1643 1331 return ret;
1644 1332 }
1645 1333  
1646   - /* get tx termination on lane 0 */
1647 1334 val = _kserdes_get_tx_termination(sc->regs, 0, sc->phy_type);
1648 1335  
1649   - /* apply tx termination to all lanes */
1650 1336 kserdes_set_tx_terminations(sc, val);
1651 1337  
1652   - if (sc->link_rate >= KSERDES_LINK_RATE_9P8304G) {
1653   - /* manually adjust Tap 1 value for phy-a > 8GBaud */
1654   - for_each_enable_lane(sc, i)
1655   - kserdes_override_tap_offsets(sc, i);
1656   - }
1657   -
1658   - /* enable transmitter on all lanes */
1659 1338 for_each_enable_lane(sc, i)
1660 1339 kserdes_clr_tx_idle(sc, i);
1661 1340  
1662   - /* allow Signal Detect Enable */
1663 1341 for_each_enable_lane(sc, i)
1664 1342 kserdes_force_signal_detect_high(sc, i);
1665 1343  
1666   - /* Wait for RX Valid on all lanes */
1667 1344 for_each_enable_lane(sc, i) {
1668 1345 ret = kserdes_wait_lane_rx_valid(sc, i);
1669 1346 if (ret) {
1670 1347  
1671 1348  
... ... @@ -1673,16 +1350,9 @@
1673 1350 }
1674 1351 }
1675 1352  
1676   - /* Apply Attenuation and Boost Patch if rx force flag is set */
1677 1353 if (!sc->rx_force_enable)
1678   - kserdes_att_boost_phy_patch(sc);
  1354 + kserdes_rx_att_boost_cfg(sc);
1679 1355  
1680   - /*
1681   - * If needed, check for errors or see if DLPF is
1682   - * railing and toggle signal detect, i.e. cdr reset
1683   - */
1684   -
1685   - /* Enable MAC RX to allow MAC to take control */
1686 1356 _kserdes_clear_wait_after(sc->regs);
1687 1357  
1688 1358 return lanes_enable;
... ... @@ -1702,7 +1372,6 @@
1702 1372  
1703 1373 static inline void _kserdes_reset(void __iomem *sregs)
1704 1374 {
1705   - /* Toggle POR_EN bit */
1706 1375 FINSR(sregs, CPU_CTRL_REG, 29, 29, 0x1);
1707 1376 /* amount of time to sleep is by experiment */
1708 1377 usleep_range(10, 20);
... ... @@ -1713,7 +1382,6 @@
1713 1382  
1714 1383 static inline void kserdes_xge_pll_enable(struct kserdes_config *sc)
1715 1384 {
1716   - /* phyb reset clear */
1717 1385 if (!sc->firmware)
1718 1386 FINSR(sc->regs, CML_REG(0), 7, 0, 0x1f);
1719 1387  
1720 1388  
... ... @@ -1727,11 +1395,9 @@
1727 1395  
1728 1396 static inline void _kserdes_xge_enable_pcs(void __iomem *sregs, u32 lane)
1729 1397 {
1730   - /* set bus-width to 16 bit mode */
1731 1398 FINSR(sregs, LANE_CTRL_STS_REG(lane), 23, 21, 0x7);
1732 1399 FINSR(sregs, LANE_CTRL_STS_REG(lane), 5, 3, 0x7);
1733 1400  
1734   - /* enable PCS overlay and lane select 10GKR */
1735 1401 FINSR(sregs, LANE_CTRL_STS_REG(lane), 16, 16, 0x1);
1736 1402 FINSR(sregs, LANE_CTRL_STS_REG(lane), 19, 19, 0x1);
1737 1403 }
... ... @@ -1740,7 +1406,6 @@
1740 1406 {
1741 1407 u32 lane_ctrl_rate = sc->lane[lane].ctrl_rate;
1742 1408  
1743   - /* Set Lane Control Rate */
1744 1409 if (sc->link_rate == KSERDES_LINK_RATE_10P3125G)
1745 1410 _kserdes_set_lane_ctrl_rate(sc->regs, lane, lane_ctrl_rate);
1746 1411 else if (sc->link_rate == KSERDES_LINK_RATE_1P25G)
1747 1412  
... ... @@ -1762,9 +1427,8 @@
1762 1427 GENMASK(port, port), BIT(port));
1763 1428 }
1764 1429  
1765   -static inline void _kserdes_reset_cdr(void __iomem *sregs, int lane)
  1430 +static inline void _kserdes_reset_rx(void __iomem *sregs, int lane)
1766 1431 {
1767   - /* toggle signal detect */
1768 1432 _kserdes_force_signal_detect_low(sregs, lane);
1769 1433 /* amount of time to sleep is by experiment */
1770 1434 usleep_range(1000, 2000);
1771 1435  
... ... @@ -1780,10 +1444,8 @@
1780 1444 int ret;
1781 1445  
1782 1446 for_each_enable_lane(sc, i) {
1783   - /* Rx Signal Loss bit in serdes lane control and status reg*/
1784 1447 loss = (kserdes_readl(sc->regs, LANE_CTRL_STS_REG(i))) & 0x01;
1785 1448  
1786   - /* Block Errors and Block Lock bits in PCSR rx status reg */
1787 1449 ret = regmap_read(sc->pcsr_regmap, PCSR_RX_STATUS(i),
1788 1450 &pcsr_rx_stat);
1789 1451  
1790 1452  
1791 1453  
1792 1454  
1793 1455  
1794 1456  
1795 1457  
... ... @@ -1793,48 +1455,36 @@
1793 1455 blk_lock = (pcsr_rx_stat >> 30) & 0x1;
1794 1456 blk_errs = (pcsr_rx_stat >> 16) & 0x0ff;
1795 1457  
1796   - /* If Block error, attempt recovery! */
1797 1458 if (blk_errs)
1798 1459 blk_lock = 0;
1799 1460  
1800 1461 switch (current_state[i]) {
1801 1462 case 0:
1802   - /* if good link lock the signal detect ON! */
1803 1463 if (!loss && blk_lock) {
1804 1464 dev_dbg(sc->dev, "XGE PCSR Linked Lane: %d\n",
1805 1465 i);
1806 1466 FINSR(sc->regs, LANEX_REG(i, 0x04), 2, 1, 0x3);
1807 1467 current_state[i] = 1;
1808 1468 } else {
1809   - /*
1810   - * if no lock, then reset CDR
1811   - * by toggling sig detect
1812   - */
1813 1469 if (!blk_lock) {
1814 1470 dev_dbg(sc->dev,
1815 1471 "XGE PCSR Recover Lane: %d\n",
1816 1472 i);
1817 1473  
1818   - _kserdes_reset_cdr(sc->regs, i);
  1474 + _kserdes_reset_rx(sc->regs, i);
1819 1475 }
1820 1476 }
1821 1477 break;
1822 1478 case 1:
1823 1479 if (!blk_lock) {
1824   - /* Link Lost? */
1825 1480 current_state[i] = 2;
1826 1481 }
1827 1482 break;
1828 1483 case 2:
1829 1484 if (blk_lock) {
1830   - /* Nope just noise */
1831 1485 current_state[i] = 1;
1832 1486 } else {
1833   - /*
1834   - * Lost the block lock, reset CDR if it is
1835   - * not centered and go back to sync state
1836   - */
1837   - _kserdes_reset_cdr(sc->regs, i);
  1487 + _kserdes_reset_rx(sc->regs, i);
1838 1488 current_state[i] = 0;
1839 1489 }
1840 1490 break;
... ... @@ -1845,7 +1495,6 @@
1845 1495 }
1846 1496  
1847 1497 if (blk_errs) {
1848   - /* Reset the Error counts! */
1849 1498 regmap_update_bits(sc->pcsr_regmap, PCSR_RX_CTL(i),
1850 1499 GENMASK(7, 0), 0x19);
1851 1500 regmap_update_bits(sc->pcsr_regmap, PCSR_RX_CTL(i),
1852 1501  
... ... @@ -1910,14 +1559,10 @@
1910 1559 int lanes_up_map = 0;
1911 1560  
1912 1561 if (sc->firmware) {
1913   - /*
1914   - * firmware started in serdes_init and
1915   - * doesn't need lanes enable
1916   - */
1917 1562 return 0;
1918 1563 }
1919 1564  
1920   - kserdes_phy_patch(sc);
  1565 + kserdes_highspeed_cfg(sc);
1921 1566 kserdes_xge_pll_enable(sc);
1922 1567  
1923 1568 for_each_lane(sc, i)
... ... @@ -1930,7 +1575,7 @@
1930 1575 return ret;
1931 1576 }
1932 1577  
1933   - kserdes_dfe_offset_calibration(sc, &sofs);
  1578 + kserdes_phyb_init_cfg(sc, &sofs);
1934 1579  
1935 1580 for_each_lane(sc, i)
1936 1581 _kserdes_enable_xgmii_port(sc->peripheral_regmap, i);
... ... @@ -1950,9 +1595,9 @@
1950 1595 val_0 = kserdes_readl(sc->regs, LANEX_REG(lane, 0x04));
1951 1596 val_1 = kserdes_readl(sc->regs, LANEX_REG(lane, 0x08));
1952 1597  
1953   - tx_ctrl = ((((val_0 >> 18) & 0x1) << 24) | /* TX_CTRL_O_24 */
1954   - (((val_1 >> 0) & 0xffff) << 8) | /* TX_CTRL_O_23_8 */
1955   - (((val_0 >> 24) & 0xff) << 0)); /* TX_CTRL_O_7_0 */
  1598 + tx_ctrl = ((((val_0 >> 18) & 0x1) << 24) |
  1599 + (((val_1 >> 0) & 0xffff) << 8) |
  1600 + (((val_0 >> 24) & 0xff) << 0));
1956 1601  
1957 1602 if (phy_a) {
1958 1603 fw->cm = (val_1 >> 12) & 0xf;
... ... @@ -1974,7 +1619,7 @@
1974 1619 fw->dlpf = (val_0 >> 2) & 0x3ff;
1975 1620  
1976 1621 val_0 = _kserdes_read_select_tbus(sc->regs, lane + 1, 0x6);
1977   - fw->cdrcal = (val_0 >> 3) & 0xff;
  1622 + fw->rxcal = (val_0 >> 3) & 0xff;
1978 1623 }
1979 1624  
1980 1625 static inline void kserdes_xfw_mem_init(struct kserdes_config *sc)
1981 1626  
1982 1627  
... ... @@ -1987,15 +1632,12 @@
1987 1632  
1988 1633 lane_config <<= 8;
1989 1634  
1990   - /* initialize internal parameter area */
1991 1635 kserdes_writel(sc->regs, MEM_ADR_REG, KSERDES_XFW_CONFIG_START_ADDR);
1992 1636  
1993   - /* clean out unused config area */
1994 1637 for (i = KSERDES_XFW_CONFIG_START_ADDR;
1995 1638 i < KSERDES_XFW_PARAM_START_ADDR; i += 4)
1996 1639 kserdes_writel(sc->regs, MEM_DATINC_REG, 0x00000000);
1997 1640  
1998   - /* Flush 64 bytes 10,11,12,13 */
1999 1641 kserdes_writel(sc->regs, MEM_DATINC_REG, XFM_FLUSH_CMD);
2000 1642 kserdes_writel(sc->regs, MEM_DATINC_REG, fw->fast_train);
2001 1643 kserdes_writel(sc->regs, MEM_DATINC_REG, 0x00000000);
... ... @@ -2260,7 +1902,6 @@
2260 1902  
2261 1903 sc->dev = dev;
2262 1904  
2263   - /* Set the defaults base on phy type */
2264 1905 kserdes_set_defaults(sc, sc->phy_type);
2265 1906  
2266 1907 if (sc->phy_type == KSERDES_PHY_XGE) {
... ... @@ -2370,5 +2011,5 @@
2370 2011  
2371 2012 MODULE_AUTHOR("WingMan Kwok <w-kwok2@ti.com>");
2372 2013 MODULE_DESCRIPTION("TI Keystone SerDes driver");
2373   -MODULE_LICENSE("GPL");
  2014 +MODULE_LICENSE("GPL v2");