Commit 1336028b9a1fb33537eab8caec66e812eb8cad63
Committed by
Avi Kivity
1 parent
aaf697e4e0
Exists in
master
and in
20 other branches
KVM: SVM: remove selective CR0 comment
There is not selective cr0 intercept bug. The code in the comment sets the CR0.PG bit. But KVM sets the CR4.PG bit for SVM always to implement the paged real mode. So the 'mov %eax,%cr0' instruction does not change the CR0.PG bit. Selective CR0 intercepts only occur when a bit is actually changed. So its the right behavior that there is no intercept on this instruction. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
Showing 1 changed file with 0 additions and 11 deletions Side-by-side Diff
arch/x86/kvm/svm.c
... | ... | @@ -513,17 +513,6 @@ |
513 | 513 | control->intercept = (1ULL << INTERCEPT_INTR) | |
514 | 514 | (1ULL << INTERCEPT_NMI) | |
515 | 515 | (1ULL << INTERCEPT_SMI) | |
516 | - /* | |
517 | - * selective cr0 intercept bug? | |
518 | - * 0: 0f 22 d8 mov %eax,%cr3 | |
519 | - * 3: 0f 20 c0 mov %cr0,%eax | |
520 | - * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
521 | - * b: 0f 22 c0 mov %eax,%cr0 | |
522 | - * set cr3 ->interception | |
523 | - * get cr0 ->interception | |
524 | - * set cr0 -> no interception | |
525 | - */ | |
526 | - /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
527 | 516 | (1ULL << INTERCEPT_CPUID) | |
528 | 517 | (1ULL << INTERCEPT_INVD) | |
529 | 518 | (1ULL << INTERCEPT_HLT) | |