pm2fb: Permedia 2V initialization fixes

This patch: - initializes correctly the Permedia2V chip if it is not initialized by BIOS - puts back clock frequency for the ELSA WINNER board to 100kHz - fixes returned error values from setcolreg() function - uses more general classes for PCI ids Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

pm2fb: Permedia 2V initialization fixes
This patch: - initializes correctly the Permedia2V chip if it is not initialized by BIOS - puts back clock frequency for the ELSA WINNER board to 100kHz - fixes returned error values from setcolreg() function - uses more general classes for PCI ids Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Krzysztof Helt · Linus Torvalds
1 parent 45f169ec81
Showing 2 changed files with 19 additions and 24 deletions Side-by-side Diff
drivers/video/pm2fb.c
include/video/permedia2.h
@@ -343,7 +343,7 @@
  
 static void reset_config(struct pm2fb_par* p)
 {
-	WAIT_FIFO(p, 52);
+	WAIT_FIFO(p, 53);
 	pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
 			~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
 	pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
@@ -380,6 +380,7 @@
 	pm2_WR(p, PM2R_STATISTICS_MODE, 0);
 	pm2_WR(p, PM2R_SCISSOR_MODE, 0);
 	pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
+	pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
 	switch (p->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
@@ -393,11 +394,6 @@
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
-		pm2v_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
-		pm2v_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
-		pm2v_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
-		pm2v_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
-		pm2v_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
 		break;
 	}
 }
@@ -532,7 +528,7 @@
 	vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
 	vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
  
-	WAIT_FIFO(p, 5);
+	WAIT_FIFO(p, 3);
 	pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
  
 	switch (p->type) {
@@ -551,7 +547,6 @@
 		if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
 			tmp |= 4; /* invert vsync */
 		pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
-		pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
 		break;
 	}
 }
@@ -686,6 +681,7 @@
 	u32 txtmap = 0;
 	u32 pixsize = 0;
 	u32 clrformat = 0;
+	u32 misc = 1; /* 8-bit DAC */
 	u32 xres = (info->var.xres + 31) & ~31;
 	int data64;
  
@@ -767,7 +763,7 @@
 	switch (depth) {
 	case 8:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
-		clrformat = 0x0e;
+		clrformat = 0x2e;
 		break;
 	case 16:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
@@ -775,6 +771,7 @@
 		txtmap = PM2F_TEXTEL_SIZE_16;
 		pixsize = 1;
 		clrformat = 0x70;
+		misc |= 8;
 		break;
 	case 32:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
@@ -782,6 +779,7 @@
 		txtmap = PM2F_TEXTEL_SIZE_32;
 		pixsize = 2;
 		clrformat = 0x20;
+		misc |= 8;
 		break;
 	case 24:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
@@ -789,6 +787,7 @@
 		txtmap = PM2F_TEXTEL_SIZE_24;
 		pixsize = 4;
 		clrformat = 0x20;
+		misc |= 8;
 		break;
 	}
 	pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
@@ -813,7 +812,7 @@
 	pm2_WR(par, PM2R_SCREEN_BASE, base);
 	wmb();
 	set_video(par, video);
-	WAIT_FIFO(par, 6);
+	WAIT_FIFO(par, 10);
 	switch (par->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
  
@@ -821,10 +820,11 @@
 			        (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
+		pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
 		pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
 		pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
-		pm2v_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
-			         (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
+		pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
+		pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
 		break;
 	}
 	set_pixclock(par, pixclock);
@@ -855,7 +855,7 @@
 	struct pm2fb_par *par = info->par;
  
 	if (regno >= info->cmap.len)  /* no. of hw registers */
-		return 1;
+		return -EINVAL;
 	/*
 	 * Program hardware... do anything you want with transp
 	 */
@@ -914,7 +914,7 @@
 		u32 v;
  
 		if (regno >= 16)
-			return 1;
+			return -EINVAL;
  
 		v = (red << info->var.red.offset) |
 			(green << info->var.green.offset) |
@@ -1341,7 +1341,7 @@
 			DPRINTK("We have not been initialized by VGA BIOS "
 				"and are running on an Elsa Winner 2000 Office\n");
 			DPRINTK("Initializing card timings manually...\n");
-			default_par->memclock = 70000;
+			default_par->memclock = 100000;
 		}
 		if (pdev->subsystem_vendor == 0x3d3d &&
 			pdev->subsystem_device == 0x0100) {
  
  
@@ -1491,17 +1491,11 @@
  
 static struct pci_device_id pm2fb_id_table[] = {
 	{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
-	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
-	  0xff0000, 0 },
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
-	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
-	  0xff0000, 0 },
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
-	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
-	  0xff0000, 0 },
-	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
-	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
-	  0xff00, 0 },
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 	{ 0, }
 };
  
@@ -153,6 +153,7 @@
 #define PM2VI_RD_CURSOR_Y_HIGH				0x00A
 #define PM2VI_RD_CURSOR_X_HOT				0x00B
 #define PM2VI_RD_CURSOR_Y_HOT				0x00C
+#define PM2VI_RD_OVERLAY_KEY				0x00D
 #define PM2VI_RD_CLK0_PRESCALE				0x201
 #define PM2VI_RD_CLK0_FEEDBACK				0x202
 #define PM2VI_RD_CLK0_POSTSCALE				0x203
...	...	@@ -343,7 +343,7 @@
343	343
344	344	static void reset_config(struct pm2fb_par* p)
345	345	{
346		- WAIT_FIFO(p, 52);
	346	+ WAIT_FIFO(p, 53);
347	347	pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
348	348	~(PM2F_VGA_ENABLE \| PM2F_VGA_FIXED));
349	349	pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
...	...	@@ -380,6 +380,7 @@
380	380	pm2_WR(p, PM2R_STATISTICS_MODE, 0);
381	381	pm2_WR(p, PM2R_SCISSOR_MODE, 0);
382	382	pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
	383	+ pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
383	384	switch (p->type) {
384	385	case PM2_TYPE_PERMEDIA2:
385	386	pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
...	...	@@ -393,11 +394,6 @@
393	394	break;
394	395	case PM2_TYPE_PERMEDIA2V:
395	396	pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
396		- pm2v_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
397		- pm2v_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
398		- pm2v_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
399		- pm2v_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
400		- pm2v_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
401	397	break;
402	398	}
403	399	}
...	...	@@ -532,7 +528,7 @@
532	528	vsync &= ~(PM2F_HSYNC_MASK \| PM2F_VSYNC_MASK);
533	529	vsync \|= PM2F_HSYNC_ACT_HIGH \| PM2F_VSYNC_ACT_HIGH;
534	530
535		- WAIT_FIFO(p, 5);
	531	+ WAIT_FIFO(p, 3);
536	532	pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
537	533
538	534	switch (p->type) {
...	...	@@ -551,7 +547,6 @@
551	547	if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
552	548	tmp \|= 4; /* invert vsync */
553	549	pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
554		- pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
555	550	break;
556	551	}
557	552	}
...	...	@@ -686,6 +681,7 @@
686	681	u32 txtmap = 0;
687	682	u32 pixsize = 0;
688	683	u32 clrformat = 0;
	684	+ u32 misc = 1; /* 8-bit DAC */
689	685	u32 xres = (info->var.xres + 31) & ~31;
690	686	int data64;
691	687
...	...	@@ -767,7 +763,7 @@
767	763	switch (depth) {
768	764	case 8:
769	765	pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
770		- clrformat = 0x0e;
	766	+ clrformat = 0x2e;
771	767	break;
772	768	case 16:
773	769	pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
...	...	@@ -775,6 +771,7 @@
775	771	txtmap = PM2F_TEXTEL_SIZE_16;
776	772	pixsize = 1;
777	773	clrformat = 0x70;
	774	+ misc \|= 8;
778	775	break;
779	776	case 32:
780	777	pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
...	...	@@ -782,6 +779,7 @@
782	779	txtmap = PM2F_TEXTEL_SIZE_32;
783	780	pixsize = 2;
784	781	clrformat = 0x20;
	782	+ misc \|= 8;
785	783	break;
786	784	case 24:
787	785	pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
...	...	@@ -789,6 +787,7 @@
789	787	txtmap = PM2F_TEXTEL_SIZE_24;
790	788	pixsize = 4;
791	789	clrformat = 0x20;
	790	+ misc \|= 8;
792	791	break;
793	792	}
794	793	pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
...	...	@@ -813,7 +812,7 @@
813	812	pm2_WR(par, PM2R_SCREEN_BASE, base);
814	813	wmb();
815	814	set_video(par, video);
816		- WAIT_FIFO(par, 6);
	815	+ WAIT_FIFO(par, 10);
817	816	switch (par->type) {
818	817	case PM2_TYPE_PERMEDIA2:
819	818	pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
820	819
...	...	@@ -821,10 +820,11 @@
821	820	(depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
822	821	break;
823	822	case PM2_TYPE_PERMEDIA2V:
	823	+ pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
824	824	pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
825	825	pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
826		- pm2v_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
827		- (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
	826	+ pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
	827	+ pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
828	828	break;
829	829	}
830	830	set_pixclock(par, pixclock);
...	...	@@ -855,7 +855,7 @@
855	855	struct pm2fb_par *par = info->par;
856	856
857	857	if (regno >= info->cmap.len) /* no. of hw registers */
858		- return 1;
	858	+ return -EINVAL;
859	859	/*
860	860	* Program hardware... do anything you want with transp
861	861	*/
...	...	@@ -914,7 +914,7 @@
914	914	u32 v;
915	915
916	916	if (regno >= 16)
917		- return 1;
	917	+ return -EINVAL;
918	918
919	919	v = (red << info->var.red.offset) \|
920	920	(green << info->var.green.offset) \|
...	...	@@ -1341,7 +1341,7 @@
1341	1341	DPRINTK("We have not been initialized by VGA BIOS "
1342	1342	"and are running on an Elsa Winner 2000 Office\n");
1343	1343	DPRINTK("Initializing card timings manually...\n");
1344		- default_par->memclock = 70000;
	1344	+ default_par->memclock = 100000;
1345	1345	}
1346	1346	if (pdev->subsystem_vendor == 0x3d3d &&
1347	1347	pdev->subsystem_device == 0x0100) {
1348	1348
1349	1349
...	...	@@ -1491,17 +1491,11 @@
1491	1491
1492	1492	static struct pci_device_id pm2fb_id_table[] = {
1493	1493	{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1494		- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1495		- 0xff0000, 0 },
	1494	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1496	1495	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1497		- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1498		- 0xff0000, 0 },
	1496	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1499	1497	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1500		- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1501		- 0xff0000, 0 },
1502		- { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1503		- PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1504		- 0xff00, 0 },
	1498	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1505	1499	{ 0, }
1506	1500	};
1507	1501
...	...	@@ -153,6 +153,7 @@
153	153	#define PM2VI_RD_CURSOR_Y_HIGH 0x00A
154	154	#define PM2VI_RD_CURSOR_X_HOT 0x00B
155	155	#define PM2VI_RD_CURSOR_Y_HOT 0x00C
	156	+#define PM2VI_RD_OVERLAY_KEY 0x00D
156	157	#define PM2VI_RD_CLK0_PRESCALE 0x201
157	158	#define PM2VI_RD_CLK0_FEEDBACK 0x202
158	159	#define PM2VI_RD_CLK0_POSTSCALE 0x203