siimage: add sil_* I/O ops

Add sil_iowrite{8,16,32}() and sil_ioread{8,16}() helpers, then use them to merge code accessing configuration registers through PCI and MMIO together. [ because of this SATA initialization bits from setup_mmio_siimage() are moved to init_chipset_siimage() ] This also cuts code size a bit: text data bss dec hex filename 4437 164 0 4601 11f9 drivers/ide/pci/siimage.o.before 3979 164 0 4143 102f drivers/ide/pci/siimage.o.after While at it: * Use I/O ops directly instead of using ->IN{B,W} and ->OUT{B,W}. * Fixup CodingStyle in setup_mmio_siimage(). * Rename 'tmpbyte' variable to 'tmp' in init_chipset_siimage(). There should be no functional changes caused by this patch. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>

siimage: add sil_* I/O ops
Add sil_iowrite{8,16,32}() and sil_ioread{8,16}() helpers, then use them to merge code accessing configuration registers through PCI and MMIO together. [ because of this SATA initialization bits from setup_mmio_siimage() are moved to init_chipset_siimage() ] This also cuts code size a bit: text data bss dec hex filename 4437 164 0 4601 11f9 drivers/ide/pci/siimage.o.before 3979 164 0 4143 102f drivers/ide/pci/siimage.o.after While at it: * Use I/O ops directly instead of using ->IN{B,W} and ->OUT{B,W}. * Fixup CodingStyle in setup_mmio_siimage(). * Rename 'tmpbyte' variable to 'tmp' in init_chipset_siimage(). There should be no functional changes caused by this patch. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Bartlomiej Zolnierkiewicz · Eric Lee · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 24a96ae0e3
Showing 1 changed file with 140 additions and 159 deletions Side-by-side Diff
drivers/ide/pci/siimage.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
  * Copyright (C) 2003		Red Hat <alan@redhat.com>
  * Copyright (C) 2007		MontaVista Software, Inc.
- * Copyright (C) 2007		Bartlomiej Zolnierkiewicz
+ * Copyright (C) 2007-2008	Bartlomiej Zolnierkiewicz
  *
  *  May be copied or modified under the terms of the GNU General Public License
  *
@@ -124,6 +124,54 @@
 	return base;
 }
  
+static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
+{
+	u8 tmp = 0;
+
+	if (pci_get_drvdata(dev))
+		tmp = readb((void __iomem *)addr);
+	else
+		pci_read_config_byte(dev, addr, &tmp);
+
+	return tmp;
+}
+
+static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
+{
+	u16 tmp = 0;
+
+	if (pci_get_drvdata(dev))
+		tmp = readw((void __iomem *)addr);
+	else
+		pci_read_config_word(dev, addr, &tmp);
+
+	return tmp;
+}
+
+static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
+{
+	if (pci_get_drvdata(dev))
+		writeb(val, (void __iomem *)addr);
+	else
+		pci_write_config_byte(dev, addr, val);
+}
+
+static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
+{
+	if (pci_get_drvdata(dev))
+		writew(val, (void __iomem *)addr);
+	else
+		pci_write_config_word(dev, addr, val);
+}
+
+static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
+{
+	if (pci_get_drvdata(dev))
+		writel(val, (void __iomem *)addr);
+	else
+		pci_write_config_dword(dev, addr, val);
+}
+
 /**
  *	sil_udma_filter		-	compute UDMA mask
  *	@drive: IDE device
  
@@ -139,12 +187,9 @@
 	ide_hwif_t *hwif = drive->hwif;
 	struct pci_dev *dev = to_pci_dev(hwif->dev);
 	unsigned long base = (unsigned long) hwif->hwif_data;
-	u8 mask = 0, scsc = 0;
+	u8 mask = 0, scsc;
  
-	if (hwif->mmio)
-		scsc = hwif->INB(base + 0x4A);
-	else
-		pci_read_config_byte(dev, 0x8A, &scsc);
+	scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
  
 	if ((scsc & 0x30) == 0x10)	/* 133 */
 		mask = ATA_UDMA6;
@@ -179,6 +224,7 @@
 	const u16 data_speed[]	= { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
  
 	ide_hwif_t *hwif	= HWIF(drive);
+	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 	ide_drive_t *pair	= ide_get_paired_drive(drive);
 	u32 speedt		= 0;
 	u16 speedp		= 0;
  
  
@@ -203,36 +249,20 @@
 	speedp = data_speed[pio];
 	speedt = tf_speed[tf_pio];
  
-	if (hwif->mmio) {
-		hwif->OUTW(speedp, addr);
-		hwif->OUTW(speedt, tfaddr);
-		/* Now set up IORDY */
-		if (pio > 2)
-			hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
-		else
-			hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
+	sil_iowrite16(dev, speedp, addr);
+	sil_iowrite16(dev, speedt, tfaddr);
  
-		mode = hwif->INB(base + addr_mask);
-		mode &= ~(unit ? 0x30 : 0x03);
-		mode |= (unit ? 0x10 : 0x01);
-		hwif->OUTB(mode, base + addr_mask);
-	} else {
-		struct pci_dev *dev = to_pci_dev(hwif->dev);
+	/* now set up IORDY */
+	speedp = sil_ioread16(dev, tfaddr - 2);
+	speedp &= ~0x200;
+	if (pio > 2)
+		speedp |= 0x200;
+	sil_iowrite16(dev, speedp, tfaddr - 2);
  
-		pci_write_config_word(dev, addr, speedp);
-		pci_write_config_word(dev, tfaddr, speedt);
-		pci_read_config_word(dev, tfaddr - 2, &speedp);
-		speedp &= ~0x200;
-		/* Set IORDY for mode 3 or 4 */
-		if (pio > 2)
-			speedp |= 0x200;
-		pci_write_config_word(dev, tfaddr - 2, speedp);
-
-		pci_read_config_byte(dev, addr_mask, &mode);
-		mode &= ~(unit ? 0x30 : 0x03);
-		mode |= (unit ? 0x10 : 0x01);
-		pci_write_config_byte(dev, addr_mask, mode);
-	}
+	mode = sil_ioread8(dev, base + addr_mask);
+	mode &= ~(unit ? 0x30 : 0x03);
+	mode |= (unit ? 0x10 : 0x01);
+	sil_iowrite8(dev, mode, base + addr_mask);
 }
  
 /**
@@ -261,17 +291,10 @@
 	unsigned long ma	= siimage_seldev(drive, 0x08);
 	unsigned long ua	= siimage_seldev(drive, 0x0C);
  
-	if (hwif->mmio) {
-		scsc = hwif->INB(base + 0x4A);
-		mode = hwif->INB(base + addr_mask);
-		multi = hwif->INW(ma);
-		ultra = hwif->INW(ua);
-	} else {
-		pci_read_config_byte(dev, 0x8A, &scsc);
-		pci_read_config_byte(dev, addr_mask, &mode);
-		pci_read_config_word(dev, ma, &multi);
-		pci_read_config_word(dev, ua, &ultra);
-	}
+	scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
+	mode = sil_ioread8(dev, base + addr_mask);
+	multi = sil_ioread16(dev, ma);
+	ultra = sil_ioread16(dev, ua);
  
 	mode &= ~((unit) ? 0x30 : 0x03);
 	ultra &= ~0x3F;
@@ -289,15 +312,9 @@
 		mode |= (unit ? 0x20 : 0x02);
 	}
  
-	if (hwif->mmio) {
-		hwif->OUTB(mode, base + addr_mask);
-		hwif->OUTW(multi, ma);
-		hwif->OUTW(ultra, ua);
-	} else {
-		pci_write_config_byte(dev, addr_mask, mode);
-		pci_write_config_word(dev, ma, multi);
-		pci_write_config_word(dev, ua, ultra);
-	}
+	sil_iowrite8(dev, mode, base + addr_mask);
+	sil_iowrite16(dev, multi, ma);
+	sil_iowrite16(dev, ultra, ua);
 }
  
 /* returns 1 if dma irq issued, 0 otherwise */
  
  
  
  
@@ -460,26 +477,21 @@
 {
 	resource_size_t bar5	= pci_resource_start(dev, 5);
 	unsigned long barsize	= pci_resource_len(dev, 5);
-	u8 tmpbyte	= 0;
 	void __iomem *ioaddr;
-	u32 tmp, irq_mask;
  
 	/*
 	 *	Drop back to PIO if we can't map the mmio. Some
 	 *	systems seem to get terminally confused in the PCI
 	 *	spaces.
 	 */
-	 
-	if(!request_mem_region(bar5, barsize, name))
-	{
+	if (!request_mem_region(bar5, barsize, name)) {
 		printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 		return 0;
 	}
-		
+
 	ioaddr = ioremap(bar5, barsize);
  
-	if (ioaddr == NULL)
-	{
+	if (ioaddr == NULL) {
 		release_mem_region(bar5, barsize);
 		return 0;
 	}
@@ -487,62 +499,6 @@
 	pci_set_master(dev);
 	pci_set_drvdata(dev, (void *) ioaddr);
  
-	if (pdev_is_sata(dev)) {
-		/* make sure IDE0/1 interrupts are not masked */
-		irq_mask = (1 << 22) | (1 << 23);
-		tmp = readl(ioaddr + 0x48);
-		if (tmp & irq_mask) {
-			tmp &= ~irq_mask;
-			writel(tmp, ioaddr + 0x48);
-			readl(ioaddr + 0x48); /* flush */
-		}
-		writel(0, ioaddr + 0x148);
-		writel(0, ioaddr + 0x1C8);
-	}
-
-	writeb(0, ioaddr + 0xB4);
-	writeb(0, ioaddr + 0xF4);
-	tmpbyte = readb(ioaddr + 0x4A);
-
-	switch(tmpbyte & 0x30) {
-		case 0x00:
-			/* In 100 MHz clocking, try and switch to 133 */
-			writeb(tmpbyte|0x10, ioaddr + 0x4A);
-			break;
-		case 0x10:
-			/* On 133Mhz clocking */
-			break;
-		case 0x20:
-			/* On PCIx2 clocking */
-			break;
-		case 0x30:
-			/* Clocking is disabled */
-			/* 133 clock attempt to force it on */
-			writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
-			break;
-	}
-
-	tmpbyte = readb(ioaddr + 0x4A);
-
-	writeb(      0x72, ioaddr + 0xA1);
-	writew(    0x328A, ioaddr + 0xA2);
-	writel(0x62DD62DD, ioaddr + 0xA4);
-	writel(0x43924392, ioaddr + 0xA8);
-	writel(0x40094009, ioaddr + 0xAC);
-	writeb(      0x72, ioaddr + 0xE1);
-	writew(    0x328A, ioaddr + 0xE2);
-	writel(0x62DD62DD, ioaddr + 0xE4);
-	writel(0x43924392, ioaddr + 0xE8);
-	writel(0x40094009, ioaddr + 0xEC);
-
-	if (pdev_is_sata(dev)) {
-		writel(0xFFFF0000, ioaddr + 0x108);
-		writel(0xFFFF0000, ioaddr + 0x188);
-		writel(0x00680000, ioaddr + 0x148);
-		writel(0x00680000, ioaddr + 0x1C8);
-	}
-
-	proc_reports_siimage(dev, (tmpbyte>>4), name);
 	return 1;
 }
  
  
  
  
  
  
  
@@ -557,50 +513,80 @@
  
 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 {
-	u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
+	unsigned long base, scsc_addr;
+	void __iomem *ioaddr = NULL;
+	u8 rev = dev->revision, tmp = 0, BA5_EN = 0;
  
 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
  
 	pci_read_config_byte(dev, 0x8A, &BA5_EN);
-	if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
-		if (setup_mmio_siimage(dev, name)) {
-			return 0;
+
+	if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) {
+		if (setup_mmio_siimage(dev, name))
+			ioaddr = pci_get_drvdata(dev);
+	}
+
+	base = (unsigned long)ioaddr;
+
+	if (ioaddr && pdev_is_sata(dev)) {
+		u32 tmp32, irq_mask;
+
+		/* make sure IDE0/1 interrupts are not masked */
+		irq_mask = (1 << 22) | (1 << 23);
+		tmp32 = readl(ioaddr + 0x48);
+		if (tmp32 & irq_mask) {
+			tmp32 &= ~irq_mask;
+			writel(tmp32, ioaddr + 0x48);
+			readl(ioaddr + 0x48); /* flush */
 		}
+		writel(0, ioaddr + 0x148);
+		writel(0, ioaddr + 0x1C8);
 	}
  
-	pci_write_config_byte(dev, 0x80, 0x00);
-	pci_write_config_byte(dev, 0x84, 0x00);
-	pci_read_config_byte(dev, 0x8A, &tmpbyte);
-	switch(tmpbyte & 0x30) {
-		case 0x00:
-			/* 133 clock attempt to force it on */
-			pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
-		case 0x30:
-			/* if clocking is disabled */
-			/* 133 clock attempt to force it on */
-			pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
-		case 0x10:
-			/* 133 already */
-			break;
-		case 0x20:
-			/* BIOS set PCI x2 clocking */
-			break;
+	sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
+	sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
+
+	scsc_addr = base ? (base + 0x4A) : 0x8A;
+	tmp = sil_ioread8(dev, scsc_addr);
+
+	switch (tmp & 0x30) {
+	case 0x00:
+		/* On 100MHz clocking, try and switch to 133MHz */
+		sil_iowrite8(dev, tmp | 0x10, scsc_addr);
+		break;
+	case 0x30:
+		/* Clocking is disabled, attempt to force 133MHz clocking. */
+		sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
+	case 0x10:
+		/* On 133Mhz clocking. */
+		break;
+	case 0x20:
+		/* On PCIx2 clocking. */
+		break;
 	}
  
-	pci_read_config_byte(dev,   0x8A, &tmpbyte);
+	tmp = sil_ioread8(dev, scsc_addr);
  
-	pci_write_config_byte(dev,  0xA1, 0x72);
-	pci_write_config_word(dev,  0xA2, 0x328A);
-	pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
-	pci_write_config_dword(dev, 0xA8, 0x43924392);
-	pci_write_config_dword(dev, 0xAC, 0x40094009);
-	pci_write_config_byte(dev,  0xB1, 0x72);
-	pci_write_config_word(dev,  0xB2, 0x328A);
-	pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
-	pci_write_config_dword(dev, 0xB8, 0x43924392);
-	pci_write_config_dword(dev, 0xBC, 0x40094009);
+	sil_iowrite8(dev,        0x72, base + 0xA1);
+	sil_iowrite16(dev,     0x328A, base + 0xA2);
+	sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
+	sil_iowrite32(dev, 0x43924392, base + 0xA8);
+	sil_iowrite32(dev, 0x40094009, base + 0xAC);
+	sil_iowrite8(dev,        0x72, base ? (base + 0xE1) : 0xB1);
+	sil_iowrite16(dev,     0x328A, base ? (base + 0xE2) : 0xB2);
+	sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
+	sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
+	sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
  
-	proc_reports_siimage(dev, (tmpbyte>>4), name);
+	if (base && pdev_is_sata(dev)) {
+		writel(0xFFFF0000, ioaddr + 0x108);
+		writel(0xFFFF0000, ioaddr + 0x188);
+		writel(0x00680000, ioaddr + 0x148);
+		writel(0x00680000, ioaddr + 0x1C8);
+	}
+
+	proc_reports_siimage(dev, tmp >> 4, name);
+
 	return 0;
 }
  
@@ -752,12 +738,7 @@
 {
 	struct pci_dev *dev = to_pci_dev(hwif->dev);
 	unsigned long addr = siimage_selreg(hwif, 0);
-	u8 ata66 = 0;
-
-	if (pci_get_drvdata(dev) == NULL)
-		pci_read_config_byte(dev, addr, &ata66);
-	else
-		ata66 = hwif->INB(addr);
+	u8 ata66 = sil_ioread8(dev, addr);
  
 	return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 }
...	...	@@ -2,7 +2,7 @@
2	2	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3	3	* Copyright (C) 2003 Red Hat <alan@redhat.com>
4	4	* Copyright (C) 2007 MontaVista Software, Inc.
5		- * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
	5	+ * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
6	6	*
7	7	* May be copied or modified under the terms of the GNU General Public License
8	8	*
...	...	@@ -124,6 +124,54 @@
124	124	return base;
125	125	}
126	126
	127	+static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
	128	+{
	129	+ u8 tmp = 0;
	130	+
	131	+ if (pci_get_drvdata(dev))
	132	+ tmp = readb((void __iomem *)addr);
	133	+ else
	134	+ pci_read_config_byte(dev, addr, &tmp);
	135	+
	136	+ return tmp;
	137	+}
	138	+
	139	+static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
	140	+{
	141	+ u16 tmp = 0;
	142	+
	143	+ if (pci_get_drvdata(dev))
	144	+ tmp = readw((void __iomem *)addr);
	145	+ else
	146	+ pci_read_config_word(dev, addr, &tmp);
	147	+
	148	+ return tmp;
	149	+}
	150	+
	151	+static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
	152	+{
	153	+ if (pci_get_drvdata(dev))
	154	+ writeb(val, (void __iomem *)addr);
	155	+ else
	156	+ pci_write_config_byte(dev, addr, val);
	157	+}
	158	+
	159	+static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
	160	+{
	161	+ if (pci_get_drvdata(dev))
	162	+ writew(val, (void __iomem *)addr);
	163	+ else
	164	+ pci_write_config_word(dev, addr, val);
	165	+}
	166	+
	167	+static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
	168	+{
	169	+ if (pci_get_drvdata(dev))
	170	+ writel(val, (void __iomem *)addr);
	171	+ else
	172	+ pci_write_config_dword(dev, addr, val);
	173	+}
	174	+
127	175	/**
128	176	* sil_udma_filter - compute UDMA mask
129	177	* @drive: IDE device
130	178
...	...	@@ -139,12 +187,9 @@
139	187	ide_hwif_t *hwif = drive->hwif;
140	188	struct pci_dev *dev = to_pci_dev(hwif->dev);
141	189	unsigned long base = (unsigned long) hwif->hwif_data;
142		- u8 mask = 0, scsc = 0;
	190	+ u8 mask = 0, scsc;
143	191
144		- if (hwif->mmio)
145		- scsc = hwif->INB(base + 0x4A);
146		- else
147		- pci_read_config_byte(dev, 0x8A, &scsc);
	192	+ scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
148	193
149	194	if ((scsc & 0x30) == 0x10) /* 133 */
150	195	mask = ATA_UDMA6;
...	...	@@ -179,6 +224,7 @@
179	224	const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
180	225
181	226	ide_hwif_t *hwif = HWIF(drive);
	227	+ struct pci_dev *dev = to_pci_dev(hwif->dev);
182	228	ide_drive_t *pair = ide_get_paired_drive(drive);
183	229	u32 speedt = 0;
184	230	u16 speedp = 0;
185	231
186	232
...	...	@@ -203,36 +249,20 @@
203	249	speedp = data_speed[pio];
204	250	speedt = tf_speed[tf_pio];
205	251
206		- if (hwif->mmio) {
207		- hwif->OUTW(speedp, addr);
208		- hwif->OUTW(speedt, tfaddr);
209		- /* Now set up IORDY */
210		- if (pio > 2)
211		- hwif->OUTW(hwif->INW(tfaddr-2)\|0x200, tfaddr-2);
212		- else
213		- hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
	252	+ sil_iowrite16(dev, speedp, addr);
	253	+ sil_iowrite16(dev, speedt, tfaddr);
214	254
215		- mode = hwif->INB(base + addr_mask);
216		- mode &= ~(unit ? 0x30 : 0x03);
217		- mode \|= (unit ? 0x10 : 0x01);
218		- hwif->OUTB(mode, base + addr_mask);
219		- } else {
220		- struct pci_dev *dev = to_pci_dev(hwif->dev);
	255	+ /* now set up IORDY */
	256	+ speedp = sil_ioread16(dev, tfaddr - 2);
	257	+ speedp &= ~0x200;
	258	+ if (pio > 2)
	259	+ speedp \|= 0x200;
	260	+ sil_iowrite16(dev, speedp, tfaddr - 2);
221	261
222		- pci_write_config_word(dev, addr, speedp);
223		- pci_write_config_word(dev, tfaddr, speedt);
224		- pci_read_config_word(dev, tfaddr - 2, &speedp);
225		- speedp &= ~0x200;
226		- /* Set IORDY for mode 3 or 4 */
227		- if (pio > 2)
228		- speedp \|= 0x200;
229		- pci_write_config_word(dev, tfaddr - 2, speedp);
230		-
231		- pci_read_config_byte(dev, addr_mask, &mode);
232		- mode &= ~(unit ? 0x30 : 0x03);
233		- mode \|= (unit ? 0x10 : 0x01);
234		- pci_write_config_byte(dev, addr_mask, mode);
235		- }
	262	+ mode = sil_ioread8(dev, base + addr_mask);
	263	+ mode &= ~(unit ? 0x30 : 0x03);
	264	+ mode \|= (unit ? 0x10 : 0x01);
	265	+ sil_iowrite8(dev, mode, base + addr_mask);
236	266	}
237	267
238	268	/**
...	...	@@ -261,17 +291,10 @@
261	291	unsigned long ma = siimage_seldev(drive, 0x08);
262	292	unsigned long ua = siimage_seldev(drive, 0x0C);
263	293
264		- if (hwif->mmio) {
265		- scsc = hwif->INB(base + 0x4A);
266		- mode = hwif->INB(base + addr_mask);
267		- multi = hwif->INW(ma);
268		- ultra = hwif->INW(ua);
269		- } else {
270		- pci_read_config_byte(dev, 0x8A, &scsc);
271		- pci_read_config_byte(dev, addr_mask, &mode);
272		- pci_read_config_word(dev, ma, &multi);
273		- pci_read_config_word(dev, ua, &ultra);
274		- }
	294	+ scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
	295	+ mode = sil_ioread8(dev, base + addr_mask);
	296	+ multi = sil_ioread16(dev, ma);
	297	+ ultra = sil_ioread16(dev, ua);
275	298
276	299	mode &= ~((unit) ? 0x30 : 0x03);
277	300	ultra &= ~0x3F;
...	...	@@ -289,15 +312,9 @@
289	312	mode \|= (unit ? 0x20 : 0x02);
290	313	}
291	314
292		- if (hwif->mmio) {
293		- hwif->OUTB(mode, base + addr_mask);
294		- hwif->OUTW(multi, ma);
295		- hwif->OUTW(ultra, ua);
296		- } else {
297		- pci_write_config_byte(dev, addr_mask, mode);
298		- pci_write_config_word(dev, ma, multi);
299		- pci_write_config_word(dev, ua, ultra);
300		- }
	315	+ sil_iowrite8(dev, mode, base + addr_mask);
	316	+ sil_iowrite16(dev, multi, ma);
	317	+ sil_iowrite16(dev, ultra, ua);
301	318	}
302	319
303	320	/* returns 1 if dma irq issued, 0 otherwise */
304	321
305	322
306	323
307	324
...	...	@@ -460,26 +477,21 @@
460	477	{
461	478	resource_size_t bar5 = pci_resource_start(dev, 5);
462	479	unsigned long barsize = pci_resource_len(dev, 5);
463		- u8 tmpbyte = 0;
464	480	void __iomem *ioaddr;
465		- u32 tmp, irq_mask;
466	481
467	482	/*
468	483	* Drop back to PIO if we can't map the mmio. Some
469	484	* systems seem to get terminally confused in the PCI
470	485	* spaces.
471	486	*/
472		-
473		- if(!request_mem_region(bar5, barsize, name))
474		- {
	487	+ if (!request_mem_region(bar5, barsize, name)) {
475	488	printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
476	489	return 0;
477	490	}
478		-
	491	+
479	492	ioaddr = ioremap(bar5, barsize);
480	493
481		- if (ioaddr == NULL)
482		- {
	494	+ if (ioaddr == NULL) {
483	495	release_mem_region(bar5, barsize);
484	496	return 0;
485	497	}
...	...	@@ -487,62 +499,6 @@
487	499	pci_set_master(dev);
488	500	pci_set_drvdata(dev, (void *) ioaddr);
489	501
490		- if (pdev_is_sata(dev)) {
491		- /* make sure IDE0/1 interrupts are not masked */
492		- irq_mask = (1 << 22) \| (1 << 23);
493		- tmp = readl(ioaddr + 0x48);
494		- if (tmp & irq_mask) {
495		- tmp &= ~irq_mask;
496		- writel(tmp, ioaddr + 0x48);
497		- readl(ioaddr + 0x48); /* flush */
498		- }
499		- writel(0, ioaddr + 0x148);
500		- writel(0, ioaddr + 0x1C8);
501		- }
502		-
503		- writeb(0, ioaddr + 0xB4);
504		- writeb(0, ioaddr + 0xF4);
505		- tmpbyte = readb(ioaddr + 0x4A);
506		-
507		- switch(tmpbyte & 0x30) {
508		- case 0x00:
509		- /* In 100 MHz clocking, try and switch to 133 */
510		- writeb(tmpbyte\|0x10, ioaddr + 0x4A);
511		- break;
512		- case 0x10:
513		- /* On 133Mhz clocking */
514		- break;
515		- case 0x20:
516		- /* On PCIx2 clocking */
517		- break;
518		- case 0x30:
519		- /* Clocking is disabled */
520		- /* 133 clock attempt to force it on */
521		- writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
522		- break;
523		- }
524		-
525		- tmpbyte = readb(ioaddr + 0x4A);
526		-
527		- writeb( 0x72, ioaddr + 0xA1);
528		- writew( 0x328A, ioaddr + 0xA2);
529		- writel(0x62DD62DD, ioaddr + 0xA4);
530		- writel(0x43924392, ioaddr + 0xA8);
531		- writel(0x40094009, ioaddr + 0xAC);
532		- writeb( 0x72, ioaddr + 0xE1);
533		- writew( 0x328A, ioaddr + 0xE2);
534		- writel(0x62DD62DD, ioaddr + 0xE4);
535		- writel(0x43924392, ioaddr + 0xE8);
536		- writel(0x40094009, ioaddr + 0xEC);
537		-
538		- if (pdev_is_sata(dev)) {
539		- writel(0xFFFF0000, ioaddr + 0x108);
540		- writel(0xFFFF0000, ioaddr + 0x188);
541		- writel(0x00680000, ioaddr + 0x148);
542		- writel(0x00680000, ioaddr + 0x1C8);
543		- }
544		-
545		- proc_reports_siimage(dev, (tmpbyte>>4), name);
546	502	return 1;
547	503	}
548	504
549	505
550	506
551	507
552	508
553	509
554	510
...	...	@@ -557,50 +513,80 @@
557	513
558	514	static unsigned int __devinit init_chipset_siimage(struct pci_dev dev, const char name)
559	515	{
560		- u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
	516	+ unsigned long base, scsc_addr;
	517	+ void __iomem *ioaddr = NULL;
	518	+ u8 rev = dev->revision, tmp = 0, BA5_EN = 0;
561	519
562	520	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
563	521
564	522	pci_read_config_byte(dev, 0x8A, &BA5_EN);
565		- if ((BA5_EN & 0x01) \|\| (pci_resource_start(dev, 5))) {
566		- if (setup_mmio_siimage(dev, name)) {
567		- return 0;
	523	+
	524	+ if ((BA5_EN & 0x01) \|\| pci_resource_start(dev, 5)) {
	525	+ if (setup_mmio_siimage(dev, name))
	526	+ ioaddr = pci_get_drvdata(dev);
	527	+ }
	528	+
	529	+ base = (unsigned long)ioaddr;
	530	+
	531	+ if (ioaddr && pdev_is_sata(dev)) {
	532	+ u32 tmp32, irq_mask;
	533	+
	534	+ /* make sure IDE0/1 interrupts are not masked */
	535	+ irq_mask = (1 << 22) \| (1 << 23);
	536	+ tmp32 = readl(ioaddr + 0x48);
	537	+ if (tmp32 & irq_mask) {
	538	+ tmp32 &= ~irq_mask;
	539	+ writel(tmp32, ioaddr + 0x48);
	540	+ readl(ioaddr + 0x48); /* flush */
568	541	}
	542	+ writel(0, ioaddr + 0x148);
	543	+ writel(0, ioaddr + 0x1C8);
569	544	}
570	545
571		- pci_write_config_byte(dev, 0x80, 0x00);
572		- pci_write_config_byte(dev, 0x84, 0x00);
573		- pci_read_config_byte(dev, 0x8A, &tmpbyte);
574		- switch(tmpbyte & 0x30) {
575		- case 0x00:
576		- /* 133 clock attempt to force it on */
577		- pci_write_config_byte(dev, 0x8A, tmpbyte\|0x10);
578		- case 0x30:
579		- /* if clocking is disabled */
580		- /* 133 clock attempt to force it on */
581		- pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
582		- case 0x10:
583		- /* 133 already */
584		- break;
585		- case 0x20:
586		- /* BIOS set PCI x2 clocking */
587		- break;
	546	+ sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
	547	+ sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
	548	+
	549	+ scsc_addr = base ? (base + 0x4A) : 0x8A;
	550	+ tmp = sil_ioread8(dev, scsc_addr);
	551	+
	552	+ switch (tmp & 0x30) {
	553	+ case 0x00:
	554	+ /* On 100MHz clocking, try and switch to 133MHz */
	555	+ sil_iowrite8(dev, tmp \| 0x10, scsc_addr);
	556	+ break;
	557	+ case 0x30:
	558	+ /* Clocking is disabled, attempt to force 133MHz clocking. */
	559	+ sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
	560	+ case 0x10:
	561	+ /* On 133Mhz clocking. */
	562	+ break;
	563	+ case 0x20:
	564	+ /* On PCIx2 clocking. */
	565	+ break;
588	566	}
589	567
590		- pci_read_config_byte(dev, 0x8A, &tmpbyte);
	568	+ tmp = sil_ioread8(dev, scsc_addr);
591	569
592		- pci_write_config_byte(dev, 0xA1, 0x72);
593		- pci_write_config_word(dev, 0xA2, 0x328A);
594		- pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
595		- pci_write_config_dword(dev, 0xA8, 0x43924392);
596		- pci_write_config_dword(dev, 0xAC, 0x40094009);
597		- pci_write_config_byte(dev, 0xB1, 0x72);
598		- pci_write_config_word(dev, 0xB2, 0x328A);
599		- pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
600		- pci_write_config_dword(dev, 0xB8, 0x43924392);
601		- pci_write_config_dword(dev, 0xBC, 0x40094009);
	570	+ sil_iowrite8(dev, 0x72, base + 0xA1);
	571	+ sil_iowrite16(dev, 0x328A, base + 0xA2);
	572	+ sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
	573	+ sil_iowrite32(dev, 0x43924392, base + 0xA8);
	574	+ sil_iowrite32(dev, 0x40094009, base + 0xAC);
	575	+ sil_iowrite8(dev, 0x72, base ? (base + 0xE1) : 0xB1);
	576	+ sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
	577	+ sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
	578	+ sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
	579	+ sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
602	580
603		- proc_reports_siimage(dev, (tmpbyte>>4), name);
	581	+ if (base && pdev_is_sata(dev)) {
	582	+ writel(0xFFFF0000, ioaddr + 0x108);
	583	+ writel(0xFFFF0000, ioaddr + 0x188);
	584	+ writel(0x00680000, ioaddr + 0x148);
	585	+ writel(0x00680000, ioaddr + 0x1C8);
	586	+ }
	587	+
	588	+ proc_reports_siimage(dev, tmp >> 4, name);
	589	+
604	590	return 0;
605	591	}
606	592
...	...	@@ -752,12 +738,7 @@
752	738	{
753	739	struct pci_dev *dev = to_pci_dev(hwif->dev);
754	740	unsigned long addr = siimage_selreg(hwif, 0);
755		- u8 ata66 = 0;
756		-
757		- if (pci_get_drvdata(dev) == NULL)
758		- pci_read_config_byte(dev, addr, &ata66);
759		- else
760		- ata66 = hwif->INB(addr);
	741	+ u8 ata66 = sil_ioread8(dev, addr);
761	742
762	743	return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
763	744	}