cirrusfb: Laguna chipset 8bpp fix

Fix 8bpp mode by adding handling of the Laguna chipsets to various places and stop trashing a HDR register which probably does not exist on the Laguna. Fix compilation warnings about uninitialized variables also. Finally, all 8bpp, 16bpp and 32bpp modes work on the Laguna chipset. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

cirrusfb: Laguna chipset 8bpp fix
Fix 8bpp mode by adding handling of the Laguna chipsets to various places and stop trashing a HDR register which probably does not exist on the Laguna. Fix compilation warnings about uninitialized variables also. Finally, all 8bpp, 16bpp and 32bpp modes work on the Laguna chipset. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Krzysztof Helt · Linus Torvalds
1 parent 48c329e906
Showing 2 changed files with 21 additions and 14 deletions Side-by-side Diff
drivers/video/cirrusfb.c
include/video/cirrus.h
@@ -660,7 +660,7 @@
 	int yres, vdispend, vsyncstart, vsyncend, vtotal;
 	long freq;
 	int nom, den, div;
-	unsigned int control, format, threshold;
+	unsigned int control = 0, format = 0, threshold = 0;
  
 	dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
 	       var->xres, var->yres, var->bits_per_pixel);
@@ -842,8 +842,7 @@
 		threshold = fb_readw(cinfo->laguna_mmio + 0xea);
 		control &= ~0x6800;
 		format = 0;
-		threshold &= 0xffe0;
-		threshold &= 0x3fbf;
+		threshold &= 0xffe0 & 0x3fbf;
 	}
 	if (nom) {
 		tmp = den << 1;
@@ -893,6 +892,8 @@
 		tmp |= 0x40;
 	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 		tmp |= 0x80;
+	if (cinfo->btype == BT_LAGUNA)
+		tmp |= 0xc;
 	WGen(cinfo, VGA_MIS_W, tmp);
  
 	/* Screen A Preset Row-Scan register */
@@ -1228,9 +1229,7 @@
 	if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
 		vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
  
-	if (cinfo->btype == BT_LAGUNA ||
-	    cinfo->btype == BT_GD5480) {
-
+	if (cinfo->btype == BT_LAGUNA) {
 		tmp = 0;
 		if ((htotal + 5) & 256)
 			tmp |= 128;
@@ -1360,7 +1359,8 @@
 		xpix = (unsigned char) ((xoffset % 4) * 2);
 	}
  
-	cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
+	if (cinfo->btype != BT_LAGUNA)
+		cirrusfb_WaitBLT(cinfo->regbase);
  
 	/* lower 8 + 8 bits of screen start address */
 	vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
@@ -1394,7 +1394,8 @@
 	if (info->var.bits_per_pixel == 1)
 		vga_wattr(cinfo->regbase, CL_AR33, xpix);
  
-	cirrusfb_WaitBLT(cinfo->regbase);
+	if (cinfo->btype != BT_LAGUNA)
+		cirrusfb_WaitBLT(cinfo->regbase);
  
 	return 0;
 }
@@ -1513,6 +1514,7 @@
 		vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
 		break;
  
+	case BT_LAGUNA:
 	case BT_ALPINE:
 		/* Nothing to do to reset the board. */
 		break;
@@ -1538,7 +1540,7 @@
 			WGen(cinfo, CL_VSSM2, 0x01);
  
 		/* reset sequencer logic */
-		vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
+		vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
  
 		/* FullBandwidth (video off) and 8/9 dot clock */
 		vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
@@ -1560,6 +1562,7 @@
 			vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
 			break;
 		case BT_ALPINE:
+		case BT_LAGUNA:
 			break;
 		case BT_SD64:
 			vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
@@ -1648,7 +1651,8 @@
 	vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
 	/* Bit Mask: no mask at all */
 	vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
-	if (cinfo->btype == BT_ALPINE)
+
+	if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_LAGUNA)
 		/* (5434 can't have bit 3 set for bitblt) */
 		vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
 	else
@@ -1845,7 +1849,8 @@
 {
 	struct cirrusfb_info *cinfo = info->par;
  
-	cirrusfb_WaitBLT(cinfo->regbase);
+	if (cinfo->btype != BT_LAGUNA)
+		cirrusfb_WaitBLT(cinfo->regbase);
 	cfb_imageblit(info, image);
 }
  
@@ -1992,7 +1997,7 @@
 		    | FBINFO_HWACCEL_YPAN
 		    | FBINFO_HWACCEL_FILLRECT
 		    | FBINFO_HWACCEL_COPYAREA;
-	if (noaccel)
+	if (noaccel || cinfo->btype == BT_LAGUNA)
 		info->flags |= FBINFO_HWACCEL_DISABLED;
 	info->fbops = &cirrusfb_ops;
 	if (cinfo->btype == BT_GD5480) {
@@ -2481,6 +2486,8 @@
 {
 	unsigned char dummy;
  
+	if (cinfo->btype == BT_LAGUNA)
+		return;
 	if (cinfo->btype == BT_PICASSO) {
 		/* Klaus' hint for correct access to HDR on some boards */
 		/* first write 0 to pixel mask (3c6) */
@@ -2548,7 +2555,8 @@
 	vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
  
 	if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
-	    cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
+	    cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
+	    cinfo->btype == BT_LAGUNA) {
 		/* but DAC data register IS, at least for Picasso II */
 		if (cinfo->btype == BT_PICASSO)
 			data += 0xfff;
@@ -32,7 +32,6 @@
 #define CL_VSSM2	0x3c3	/* Motherboard Sleep */
  
 /*** VGA Sequencer Registers ***/
-#define CL_SEQR0	0x0	/* Reset */
 /* the following are from the "extension registers" group */
 #define CL_SEQR6	0x6	/* Unlock ALL Extensions */
 #define CL_SEQR7	0x7	/* Extended Sequencer Mode */
...	...	@@ -660,7 +660,7 @@
660	660	int yres, vdispend, vsyncstart, vsyncend, vtotal;
661	661	long freq;
662	662	int nom, den, div;
663		- unsigned int control, format, threshold;
	663	+ unsigned int control = 0, format = 0, threshold = 0;
664	664
665	665	dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
666	666	var->xres, var->yres, var->bits_per_pixel);
...	...	@@ -842,8 +842,7 @@
842	842	threshold = fb_readw(cinfo->laguna_mmio + 0xea);
843	843	control &= ~0x6800;
844	844	format = 0;
845		- threshold &= 0xffe0;
846		- threshold &= 0x3fbf;
	845	+ threshold &= 0xffe0 & 0x3fbf;
847	846	}
848	847	if (nom) {
849	848	tmp = den << 1;
...	...	@@ -893,6 +892,8 @@
893	892	tmp \|= 0x40;
894	893	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
895	894	tmp \|= 0x80;
	895	+ if (cinfo->btype == BT_LAGUNA)
	896	+ tmp \|= 0xc;
896	897	WGen(cinfo, VGA_MIS_W, tmp);
897	898
898	899	/* Screen A Preset Row-Scan register */
...	...	@@ -1228,9 +1229,7 @@
1228	1229	if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1229	1230	vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1230	1231
1231		- if (cinfo->btype == BT_LAGUNA \|\|
1232		- cinfo->btype == BT_GD5480) {
1233		-
	1232	+ if (cinfo->btype == BT_LAGUNA) {
1234	1233	tmp = 0;
1235	1234	if ((htotal + 5) & 256)
1236	1235	tmp \|= 128;
...	...	@@ -1360,7 +1359,8 @@
1360	1359	xpix = (unsigned char) ((xoffset % 4) * 2);
1361	1360	}
1362	1361
1363		- cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
	1362	+ if (cinfo->btype != BT_LAGUNA)
	1363	+ cirrusfb_WaitBLT(cinfo->regbase);
1364	1364
1365	1365	/* lower 8 + 8 bits of screen start address */
1366	1366	vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
...	...	@@ -1394,7 +1394,8 @@
1394	1394	if (info->var.bits_per_pixel == 1)
1395	1395	vga_wattr(cinfo->regbase, CL_AR33, xpix);
1396	1396
1397		- cirrusfb_WaitBLT(cinfo->regbase);
	1397	+ if (cinfo->btype != BT_LAGUNA)
	1398	+ cirrusfb_WaitBLT(cinfo->regbase);
1398	1399
1399	1400	return 0;
1400	1401	}
...	...	@@ -1513,6 +1514,7 @@
1513	1514	vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1514	1515	break;
1515	1516
	1517	+ case BT_LAGUNA:
1516	1518	case BT_ALPINE:
1517	1519	/* Nothing to do to reset the board. */
1518	1520	break;
...	...	@@ -1538,7 +1540,7 @@
1538	1540	WGen(cinfo, CL_VSSM2, 0x01);
1539	1541
1540	1542	/* reset sequencer logic */
1541		- vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
	1543	+ vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1542	1544
1543	1545	/* FullBandwidth (video off) and 8/9 dot clock */
1544	1546	vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
...	...	@@ -1560,6 +1562,7 @@
1560	1562	vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1561	1563	break;
1562	1564	case BT_ALPINE:
	1565	+ case BT_LAGUNA:
1563	1566	break;
1564	1567	case BT_SD64:
1565	1568	vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
...	...	@@ -1648,7 +1651,8 @@
1648	1651	vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1649	1652	/* Bit Mask: no mask at all */
1650	1653	vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1651		- if (cinfo->btype == BT_ALPINE)
	1654	+
	1655	+ if (cinfo->btype == BT_ALPINE \|\| cinfo->btype == BT_LAGUNA)
1652	1656	/* (5434 can't have bit 3 set for bitblt) */
1653	1657	vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1654	1658	else
...	...	@@ -1845,7 +1849,8 @@
1845	1849	{
1846	1850	struct cirrusfb_info *cinfo = info->par;
1847	1851
1848		- cirrusfb_WaitBLT(cinfo->regbase);
	1852	+ if (cinfo->btype != BT_LAGUNA)
	1853	+ cirrusfb_WaitBLT(cinfo->regbase);
1849	1854	cfb_imageblit(info, image);
1850	1855	}
1851	1856
...	...	@@ -1992,7 +1997,7 @@
1992	1997	\| FBINFO_HWACCEL_YPAN
1993	1998	\| FBINFO_HWACCEL_FILLRECT
1994	1999	\| FBINFO_HWACCEL_COPYAREA;
1995		- if (noaccel)
	2000	+ if (noaccel \|\| cinfo->btype == BT_LAGUNA)
1996	2001	info->flags \|= FBINFO_HWACCEL_DISABLED;
1997	2002	info->fbops = &cirrusfb_ops;
1998	2003	if (cinfo->btype == BT_GD5480) {
...	...	@@ -2481,6 +2486,8 @@
2481	2486	{
2482	2487	unsigned char dummy;
2483	2488
	2489	+ if (cinfo->btype == BT_LAGUNA)
	2490	+ return;
2484	2491	if (cinfo->btype == BT_PICASSO) {
2485	2492	/* Klaus' hint for correct access to HDR on some boards */
2486	2493	/* first write 0 to pixel mask (3c6) */
...	...	@@ -2548,7 +2555,8 @@
2548	2555	vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2549	2556
2550	2557	if (cinfo->btype == BT_PICASSO \|\| cinfo->btype == BT_PICASSO4 \|\|
2551		- cinfo->btype == BT_ALPINE \|\| cinfo->btype == BT_GD5480) {
	2558	+ cinfo->btype == BT_ALPINE \|\| cinfo->btype == BT_GD5480 \|\|
	2559	+ cinfo->btype == BT_LAGUNA) {
2552	2560	/* but DAC data register IS, at least for Picasso II */
2553	2561	if (cinfo->btype == BT_PICASSO)
2554	2562	data += 0xfff;
...	...	@@ -32,7 +32,6 @@
32	32	#define CL_VSSM2 0x3c3 /* Motherboard Sleep */
33	33
34	34	/* VGA Sequencer Registers */
35		-#define CL_SEQR0 0x0 /* Reset */
36	35	/* the following are from the "extension registers" group */
37	36	#define CL_SEQR6 0x6 /* Unlock ALL Extensions */
38	37	#define CL_SEQR7 0x7 /* Extended Sequencer Mode */