Commit 1f28da4920c2ba8db4541e6d65dadec0c373bacb
Committed by
Sekhar Nori
Sekhar Nori
1 parent
70c8ba53dd
Exists in
ti-linux-3.14.y
and in
2 other branches
usb: dwc3: dwc3-omap: Fix disable IRQ
In the wrapper the IRQ disable should be done by writing 1's to the IRQ*_CLR register. Existing code is broken because it instead writes zeros to IRQ*_SET register. Fix this by adding functions dwc3_omap_write_irqmisc_clr() and dwc3_omap_write_irq0_clr() which do the right thing. Signed-off-by: George Cherian <george.cherian@ti.com> [nsekhar@ti.com: minor tweaks to patch description] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Showing 1 changed file with 28 additions and 2 deletions Side-by-side Diff
drivers/usb/dwc3/dwc3-omap.c
| ... | ... | @@ -206,6 +206,18 @@ |
| 206 | 206 | omap->irq0_offset, value); |
| 207 | 207 | } |
| 208 | 208 | |
| 209 | +static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) | |
| 210 | +{ | |
| 211 | + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + | |
| 212 | + omap->irqmisc_offset, value); | |
| 213 | +} | |
| 214 | + | |
| 215 | +static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) | |
| 216 | +{ | |
| 217 | + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - | |
| 218 | + omap->irq0_offset, value); | |
| 219 | +} | |
| 220 | + | |
| 209 | 221 | static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, |
| 210 | 222 | enum omap_dwc3_vbus_id_status status) |
| 211 | 223 | { |
| 212 | 224 | |
| ... | ... | @@ -346,9 +358,23 @@ |
| 346 | 358 | |
| 347 | 359 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) |
| 348 | 360 | { |
| 361 | + u32 reg; | |
| 362 | + | |
| 349 | 363 | /* disable all IRQs */ |
| 350 | - dwc3_omap_write_irqmisc_set(omap, 0x00); | |
| 351 | - dwc3_omap_write_irq0_set(omap, 0x00); | |
| 364 | + reg = USBOTGSS_IRQO_COREIRQ_ST; | |
| 365 | + dwc3_omap_write_irq0_clr(omap, reg); | |
| 366 | + | |
| 367 | + reg = (USBOTGSS_IRQMISC_OEVT | | |
| 368 | + USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
| 369 | + USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
| 370 | + USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
| 371 | + USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
| 372 | + USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
| 373 | + USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
| 374 | + USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
| 375 | + USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
| 376 | + | |
| 377 | + dwc3_omap_write_irqmisc_clr(omap, reg); | |
| 352 | 378 | } |
| 353 | 379 | |
| 354 | 380 | static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); |