Commit 22b8bf17c6c1db887e3e9adb0778d6f03e621e66
Committed by
Daniel Vetter
1 parent
9ed9809fbe
Exists in
master
and in
20 other branches
drm/i915: use HAS_DDI on intel_hdmi.c and intel_display.c
Since basically every code called on these places comes from intel_ddi.c Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Showing 2 changed files with 7 additions and 7 deletions Side-by-side Diff
drivers/gpu/drm/i915/intel_dp.c
... | ... | @@ -332,7 +332,7 @@ |
332 | 332 | uint32_t status; |
333 | 333 | bool done; |
334 | 334 | |
335 | - if (IS_HASWELL(dev)) { | |
335 | + if (HAS_DDI(dev)) { | |
336 | 336 | switch (intel_dig_port->port) { |
337 | 337 | case PORT_A: |
338 | 338 | ch_ctl = DPA_AUX_CH_CTL; |
... | ... | @@ -387,7 +387,7 @@ |
387 | 387 | */ |
388 | 388 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
389 | 389 | |
390 | - if (IS_HASWELL(dev)) { | |
390 | + if (HAS_DDI(dev)) { | |
391 | 391 | switch (intel_dig_port->port) { |
392 | 392 | case PORT_A: |
393 | 393 | ch_ctl = DPA_AUX_CH_CTL; |
... | ... | @@ -842,7 +842,7 @@ |
842 | 842 | intel_link_compute_m_n(intel_crtc->bpp, lane_count, |
843 | 843 | mode->clock, adjusted_mode->clock, &m_n); |
844 | 844 | |
845 | - if (IS_HASWELL(dev)) { | |
845 | + if (HAS_DDI(dev)) { | |
846 | 846 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
847 | 847 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
848 | 848 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
... | ... | @@ -1537,7 +1537,7 @@ |
1537 | 1537 | { |
1538 | 1538 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1539 | 1539 | |
1540 | - if (IS_HASWELL(dev)) { | |
1540 | + if (HAS_DDI(dev)) { | |
1541 | 1541 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1542 | 1542 | case DP_TRAIN_VOLTAGE_SWING_400: |
1543 | 1543 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
... | ... | @@ -1745,7 +1745,7 @@ |
1745 | 1745 | uint32_t signal_levels, mask; |
1746 | 1746 | uint8_t train_set = intel_dp->train_set[0]; |
1747 | 1747 | |
1748 | - if (IS_HASWELL(dev)) { | |
1748 | + if (HAS_DDI(dev)) { | |
1749 | 1749 | signal_levels = intel_hsw_signal_levels(train_set); |
1750 | 1750 | mask = DDI_BUF_EMP_MASK; |
1751 | 1751 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
... | ... | @@ -1776,7 +1776,7 @@ |
1776 | 1776 | int ret; |
1777 | 1777 | uint32_t temp; |
1778 | 1778 | |
1779 | - if (IS_HASWELL(dev)) { | |
1779 | + if (HAS_DDI(dev)) { | |
1780 | 1780 | temp = I915_READ(DP_TP_CTL(port)); |
1781 | 1781 | |
1782 | 1782 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
drivers/gpu/drm/i915/intel_hdmi.c
... | ... | @@ -1044,7 +1044,7 @@ |
1044 | 1044 | } else if (IS_VALLEYVIEW(dev)) { |
1045 | 1045 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
1046 | 1046 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
1047 | - } else if (IS_HASWELL(dev)) { | |
1047 | + } else if (HAS_DDI(dev)) { | |
1048 | 1048 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
1049 | 1049 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
1050 | 1050 | } else if (HAS_PCH_IBX(dev)) { |