powerpc/eeh: Sync OPAL API with firmware

The patch synchronizes OPAL APIs between kernel and firmware. Also, we starts to replace opal_pci_get_phb_diag_data() with the similar opal_pci_get_phb_diag_data2() and the former OPAL API would return OPAL_UNSUPPORTED from now on. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

powerpc/eeh: Sync OPAL API with firmware
The patch synchronizes OPAL APIs between kernel and firmware. Also, we starts to replace opal_pci_get_phb_diag_data() with the similar opal_pci_get_phb_diag_data2() and the former OPAL API would return OPAL_UNSUPPORTED from now on. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Gavin Shan · Benjamin Herrenschmidt
1 parent 8a6b1bc70d
Showing 3 changed files with 119 additions and 22 deletions Side-by-side Diff
arch/powerpc/include/asm/opal.h
arch/powerpc/platforms/powernv/opal-wrappers.S
arch/powerpc/platforms/powernv/pci.c
@@ -117,7 +117,13 @@
 #define OPAL_SET_SLOT_LED_STATUS		55
 #define OPAL_GET_EPOW_STATUS			56
 #define OPAL_SET_SYSTEM_ATTENTION_LED		57
+#define OPAL_RESERVED1				58
+#define OPAL_RESERVED2				59
+#define OPAL_PCI_NEXT_ERROR			60
+#define OPAL_PCI_EEH_FREEZE_STATUS2		61
+#define OPAL_PCI_POLL				62
 #define OPAL_PCI_MSI_EOI			63
+#define OPAL_PCI_GET_PHB_DIAG_DATA2		64
  
 #ifndef __ASSEMBLY__
  
@@ -125,6 +131,7 @@
 enum OpalVendorApiTokens {
 	OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 };
+
 enum OpalFreezeState {
 	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
  
  
  
  
  
  
  
  
  
@@ -134,55 +141,69 @@
 	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 };
+
 enum OpalEehFreezeActionToken {
 	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 };
+
 enum OpalPciStatusToken {
-	OPAL_EEH_PHB_NO_ERROR = 0,
-	OPAL_EEH_PHB_FATAL = 1,
-	OPAL_EEH_PHB_RECOVERABLE = 2,
-	OPAL_EEH_PHB_BUS_ERROR = 3,
-	OPAL_EEH_PCI_NO_DEVSEL = 4,
-	OPAL_EEH_PCI_TA = 5,
-	OPAL_EEH_PCIEX_UR = 6,
-	OPAL_EEH_PCIEX_CA = 7,
-	OPAL_EEH_PCI_MMIO_ERROR = 8,
-	OPAL_EEH_PCI_DMA_ERROR = 9
+	OPAL_EEH_NO_ERROR	= 0,
+	OPAL_EEH_IOC_ERROR	= 1,
+	OPAL_EEH_PHB_ERROR	= 2,
+	OPAL_EEH_PE_ERROR	= 3,
+	OPAL_EEH_PE_MMIO_ERROR	= 4,
+	OPAL_EEH_PE_DMA_ERROR	= 5
 };
+
+enum OpalPciErrorSeverity {
+	OPAL_EEH_SEV_NO_ERROR	= 0,
+	OPAL_EEH_SEV_IOC_DEAD	= 1,
+	OPAL_EEH_SEV_PHB_DEAD	= 2,
+	OPAL_EEH_SEV_PHB_FENCED	= 3,
+	OPAL_EEH_SEV_PE_ER	= 4,
+	OPAL_EEH_SEV_INF	= 5
+};
+
 enum OpalShpcAction {
 	OPAL_SHPC_GET_LINK_STATE = 0,
 	OPAL_SHPC_GET_SLOT_STATE = 1
 };
+
 enum OpalShpcLinkState {
 	OPAL_SHPC_LINK_DOWN = 0,
 	OPAL_SHPC_LINK_UP = 1
 };
+
 enum OpalMmioWindowType {
 	OPAL_M32_WINDOW_TYPE = 1,
 	OPAL_M64_WINDOW_TYPE = 2,
 	OPAL_IO_WINDOW_TYPE = 3
 };
+
 enum OpalShpcSlotState {
 	OPAL_SHPC_DEV_NOT_PRESENT = 0,
 	OPAL_SHPC_DEV_PRESENT = 1
 };
+
 enum OpalExceptionHandler {
 	OPAL_MACHINE_CHECK_HANDLER = 1,
 	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 	OPAL_SOFTPATCH_HANDLER = 3
 };
+
 enum OpalPendingState {
-	OPAL_EVENT_OPAL_INTERNAL = 0x1,
-	OPAL_EVENT_NVRAM = 0x2,
-	OPAL_EVENT_RTC = 0x4,
-	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-	OPAL_EVENT_CONSOLE_INPUT = 0x10,
-	OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
-	OPAL_EVENT_ERROR_LOG = 0x40,
-	OPAL_EVENT_EPOW = 0x80,
-	OPAL_EVENT_LED_STATUS = 0x100
+	OPAL_EVENT_OPAL_INTERNAL	= 0x1,
+	OPAL_EVENT_NVRAM		= 0x2,
+	OPAL_EVENT_RTC			= 0x4,
+	OPAL_EVENT_CONSOLE_OUTPUT	= 0x8,
+	OPAL_EVENT_CONSOLE_INPUT	= 0x10,
+	OPAL_EVENT_ERROR_LOG_AVAIL	= 0x20,
+	OPAL_EVENT_ERROR_LOG		= 0x40,
+	OPAL_EVENT_EPOW			= 0x80,
+	OPAL_EVENT_LED_STATUS		= 0x100,
+	OPAL_EVENT_PCI_ERROR		= 0x200
 };
  
 /* Machine check related definitions */
  
  
  
@@ -364,15 +385,80 @@
 	} u;
 };
  
+enum {
+	OPAL_P7IOC_DIAG_TYPE_NONE	= 0,
+	OPAL_P7IOC_DIAG_TYPE_RGC	= 1,
+	OPAL_P7IOC_DIAG_TYPE_BI		= 2,
+	OPAL_P7IOC_DIAG_TYPE_CI		= 3,
+	OPAL_P7IOC_DIAG_TYPE_MISC	= 4,
+	OPAL_P7IOC_DIAG_TYPE_I2C	= 5,
+	OPAL_P7IOC_DIAG_TYPE_LAST	= 6
+};
+
+struct OpalIoP7IOCErrorData {
+	uint16_t type;
+
+	/* GEM */
+	uint64_t gemXfir;
+	uint64_t gemRfir;
+	uint64_t gemRirqfir;
+	uint64_t gemMask;
+	uint64_t gemRwof;
+
+	/* LEM */
+	uint64_t lemFir;
+	uint64_t lemErrMask;
+	uint64_t lemAction0;
+	uint64_t lemAction1;
+	uint64_t lemWof;
+
+	union {
+		struct OpalIoP7IOCRgcErrorData {
+			uint64_t rgcStatus;		/* 3E1C10 */
+			uint64_t rgcLdcp;		/* 3E1C18 */
+		}rgc;
+		struct OpalIoP7IOCBiErrorData {
+			uint64_t biLdcp0;		/* 3C0100, 3C0118 */
+			uint64_t biLdcp1;		/* 3C0108, 3C0120 */
+			uint64_t biLdcp2;		/* 3C0110, 3C0128 */
+			uint64_t biFenceStatus;		/* 3C0130, 3C0130 */
+
+			uint8_t  biDownbound;		/* BI Downbound or Upbound */
+		}bi;
+		struct OpalIoP7IOCCiErrorData {
+			uint64_t ciPortStatus;		/* 3Dn008 */
+			uint64_t ciPortLdcp;		/* 3Dn010 */
+
+			uint8_t	 ciPort;		/* Index of CI port: 0/1 */
+		}ci;
+	};
+};
+
 /**
  * This structure defines the overlay which will be used to store PHB error
  * data upon request.
  */
 enum {
+	OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
+};
+
+enum {
+	OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
+};
+
+enum {
 	OPAL_P7IOC_NUM_PEST_REGS = 128,
 };
  
+struct OpalIoPhbErrorCommon {
+	uint32_t version;
+	uint32_t ioType;
+	uint32_t len;
+};
+
 struct OpalIoP7IOCPhbErrorData {
+	struct OpalIoPhbErrorCommon common;
+
 	uint32_t brdgCtl;
  
 	// P7IOC utl regs
  
@@ -530,14 +616,21 @@
 					uint64_t pci_mem_size);
 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
  
-int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
-int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
+				   uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
+				   uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
+				    uint64_t diag_buffer_len);
 int64_t opal_pci_fence_phb(uint64_t phb_id);
 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 int64_t opal_get_epow_status(uint64_t *status);
 int64_t opal_set_system_attention_led(uint8_t led_action);
+int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
+			    uint16_t *pci_error_type, uint16_t *severity);
+int64_t opal_pci_poll(uint64_t phb_id);
  
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
@@ -107,5 +107,8 @@
 OPAL_CALL(opal_set_slot_led_status,		OPAL_SET_SLOT_LED_STATUS);
 OPAL_CALL(opal_get_epow_status,			OPAL_GET_EPOW_STATUS);
 OPAL_CALL(opal_set_system_attention_led,	OPAL_SET_SYSTEM_ATTENTION_LED);
+OPAL_CALL(opal_pci_next_error,			OPAL_PCI_NEXT_ERROR);
+OPAL_CALL(opal_pci_poll,			OPAL_PCI_POLL);
 OPAL_CALL(opal_pci_msi_eoi,			OPAL_PCI_MSI_EOI);
+OPAL_CALL(opal_pci_get_phb_diag_data2,		OPAL_PCI_GET_PHB_DIAG_DATA2);
@@ -203,7 +203,8 @@
  
 	spin_lock_irqsave(&phb->lock, flags);
  
-	rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
+	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
+					 PNV_PCI_DIAG_BUF_SIZE);
 	has_diag = (rc == OPAL_SUCCESS);
  
 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
...	...	@@ -117,7 +117,13 @@
117	117	#define OPAL_SET_SLOT_LED_STATUS 55
118	118	#define OPAL_GET_EPOW_STATUS 56
119	119	#define OPAL_SET_SYSTEM_ATTENTION_LED 57
	120	+#define OPAL_RESERVED1 58
	121	+#define OPAL_RESERVED2 59
	122	+#define OPAL_PCI_NEXT_ERROR 60
	123	+#define OPAL_PCI_EEH_FREEZE_STATUS2 61
	124	+#define OPAL_PCI_POLL 62
120	125	#define OPAL_PCI_MSI_EOI 63
	126	+#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
121	127
122	128	#ifndef __ASSEMBLY__
123	129
...	...	@@ -125,6 +131,7 @@
125	131	enum OpalVendorApiTokens {
126	132	OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
127	133	};
	134	+
128	135	enum OpalFreezeState {
129	136	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
130	137	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
131	138
132	139
133	140
134	141
135	142
136	143
137	144
138	145
139	146
...	...	@@ -134,55 +141,69 @@
134	141	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
135	142	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
136	143	};
	144	+
137	145	enum OpalEehFreezeActionToken {
138	146	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
139	147	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
140	148	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
141	149	};
	150	+
142	151	enum OpalPciStatusToken {
143		- OPAL_EEH_PHB_NO_ERROR = 0,
144		- OPAL_EEH_PHB_FATAL = 1,
145		- OPAL_EEH_PHB_RECOVERABLE = 2,
146		- OPAL_EEH_PHB_BUS_ERROR = 3,
147		- OPAL_EEH_PCI_NO_DEVSEL = 4,
148		- OPAL_EEH_PCI_TA = 5,
149		- OPAL_EEH_PCIEX_UR = 6,
150		- OPAL_EEH_PCIEX_CA = 7,
151		- OPAL_EEH_PCI_MMIO_ERROR = 8,
152		- OPAL_EEH_PCI_DMA_ERROR = 9
	152	+ OPAL_EEH_NO_ERROR = 0,
	153	+ OPAL_EEH_IOC_ERROR = 1,
	154	+ OPAL_EEH_PHB_ERROR = 2,
	155	+ OPAL_EEH_PE_ERROR = 3,
	156	+ OPAL_EEH_PE_MMIO_ERROR = 4,
	157	+ OPAL_EEH_PE_DMA_ERROR = 5
153	158	};
	159	+
	160	+enum OpalPciErrorSeverity {
	161	+ OPAL_EEH_SEV_NO_ERROR = 0,
	162	+ OPAL_EEH_SEV_IOC_DEAD = 1,
	163	+ OPAL_EEH_SEV_PHB_DEAD = 2,
	164	+ OPAL_EEH_SEV_PHB_FENCED = 3,
	165	+ OPAL_EEH_SEV_PE_ER = 4,
	166	+ OPAL_EEH_SEV_INF = 5
	167	+};
	168	+
154	169	enum OpalShpcAction {
155	170	OPAL_SHPC_GET_LINK_STATE = 0,
156	171	OPAL_SHPC_GET_SLOT_STATE = 1
157	172	};
	173	+
158	174	enum OpalShpcLinkState {
159	175	OPAL_SHPC_LINK_DOWN = 0,
160	176	OPAL_SHPC_LINK_UP = 1
161	177	};
	178	+
162	179	enum OpalMmioWindowType {
163	180	OPAL_M32_WINDOW_TYPE = 1,
164	181	OPAL_M64_WINDOW_TYPE = 2,
165	182	OPAL_IO_WINDOW_TYPE = 3
166	183	};
	184	+
167	185	enum OpalShpcSlotState {
168	186	OPAL_SHPC_DEV_NOT_PRESENT = 0,
169	187	OPAL_SHPC_DEV_PRESENT = 1
170	188	};
	189	+
171	190	enum OpalExceptionHandler {
172	191	OPAL_MACHINE_CHECK_HANDLER = 1,
173	192	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
174	193	OPAL_SOFTPATCH_HANDLER = 3
175	194	};
	195	+
176	196	enum OpalPendingState {
177		- OPAL_EVENT_OPAL_INTERNAL = 0x1,
178		- OPAL_EVENT_NVRAM = 0x2,
179		- OPAL_EVENT_RTC = 0x4,
180		- OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
181		- OPAL_EVENT_CONSOLE_INPUT = 0x10,
182		- OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
183		- OPAL_EVENT_ERROR_LOG = 0x40,
184		- OPAL_EVENT_EPOW = 0x80,
185		- OPAL_EVENT_LED_STATUS = 0x100
	197	+ OPAL_EVENT_OPAL_INTERNAL = 0x1,
	198	+ OPAL_EVENT_NVRAM = 0x2,
	199	+ OPAL_EVENT_RTC = 0x4,
	200	+ OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
	201	+ OPAL_EVENT_CONSOLE_INPUT = 0x10,
	202	+ OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
	203	+ OPAL_EVENT_ERROR_LOG = 0x40,
	204	+ OPAL_EVENT_EPOW = 0x80,
	205	+ OPAL_EVENT_LED_STATUS = 0x100,
	206	+ OPAL_EVENT_PCI_ERROR = 0x200
186	207	};
187	208
188	209	/* Machine check related definitions */
189	210
190	211
191	212
...	...	@@ -364,15 +385,80 @@
364	385	} u;
365	386	};
366	387
	388	+enum {
	389	+ OPAL_P7IOC_DIAG_TYPE_NONE = 0,
	390	+ OPAL_P7IOC_DIAG_TYPE_RGC = 1,
	391	+ OPAL_P7IOC_DIAG_TYPE_BI = 2,
	392	+ OPAL_P7IOC_DIAG_TYPE_CI = 3,
	393	+ OPAL_P7IOC_DIAG_TYPE_MISC = 4,
	394	+ OPAL_P7IOC_DIAG_TYPE_I2C = 5,
	395	+ OPAL_P7IOC_DIAG_TYPE_LAST = 6
	396	+};
	397	+
	398	+struct OpalIoP7IOCErrorData {
	399	+ uint16_t type;
	400	+
	401	+ /* GEM */
	402	+ uint64_t gemXfir;
	403	+ uint64_t gemRfir;
	404	+ uint64_t gemRirqfir;
	405	+ uint64_t gemMask;
	406	+ uint64_t gemRwof;
	407	+
	408	+ /* LEM */
	409	+ uint64_t lemFir;
	410	+ uint64_t lemErrMask;
	411	+ uint64_t lemAction0;
	412	+ uint64_t lemAction1;
	413	+ uint64_t lemWof;
	414	+
	415	+ union {
	416	+ struct OpalIoP7IOCRgcErrorData {
	417	+ uint64_t rgcStatus; /* 3E1C10 */
	418	+ uint64_t rgcLdcp; /* 3E1C18 */
	419	+ }rgc;
	420	+ struct OpalIoP7IOCBiErrorData {
	421	+ uint64_t biLdcp0; /* 3C0100, 3C0118 */
	422	+ uint64_t biLdcp1; /* 3C0108, 3C0120 */
	423	+ uint64_t biLdcp2; /* 3C0110, 3C0128 */
	424	+ uint64_t biFenceStatus; /* 3C0130, 3C0130 */
	425	+
	426	+ uint8_t biDownbound; /* BI Downbound or Upbound */
	427	+ }bi;
	428	+ struct OpalIoP7IOCCiErrorData {
	429	+ uint64_t ciPortStatus; /* 3Dn008 */
	430	+ uint64_t ciPortLdcp; /* 3Dn010 */
	431	+
	432	+ uint8_t ciPort; /* Index of CI port: 0/1 */
	433	+ }ci;
	434	+ };
	435	+};
	436	+
367	437	/**
368	438	* This structure defines the overlay which will be used to store PHB error
369	439	* data upon request.
370	440	*/
371	441	enum {
	442	+ OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
	443	+};
	444	+
	445	+enum {
	446	+ OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
	447	+};
	448	+
	449	+enum {
372	450	OPAL_P7IOC_NUM_PEST_REGS = 128,
373	451	};
374	452
	453	+struct OpalIoPhbErrorCommon {
	454	+ uint32_t version;
	455	+ uint32_t ioType;
	456	+ uint32_t len;
	457	+};
	458	+
375	459	struct OpalIoP7IOCPhbErrorData {
	460	+ struct OpalIoPhbErrorCommon common;
	461	+
376	462	uint32_t brdgCtl;
377	463
378	464	// P7IOC utl regs
379	465
...	...	@@ -530,14 +616,21 @@
530	616	uint64_t pci_mem_size);
531	617	int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
532	618
533		-int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
534		-int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
	619	+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
	620	+ uint64_t diag_buffer_len);
	621	+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
	622	+ uint64_t diag_buffer_len);
	623	+int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
	624	+ uint64_t diag_buffer_len);
535	625	int64_t opal_pci_fence_phb(uint64_t phb_id);
536	626	int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
537	627	int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
538	628	int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
539	629	int64_t opal_get_epow_status(uint64_t *status);
540	630	int64_t opal_set_system_attention_led(uint8_t led_action);
	631	+int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
	632	+ uint16_t pci_error_type, uint16_t severity);
	633	+int64_t opal_pci_poll(uint64_t phb_id);
541	634
542	635	/* Internal functions */
543	636	extern int early_init_dt_scan_opal(unsigned long node, const char uname, int depth, void data);
...	...	@@ -107,5 +107,8 @@
107	107	OPAL_CALL(opal_set_slot_led_status, OPAL_SET_SLOT_LED_STATUS);
108	108	OPAL_CALL(opal_get_epow_status, OPAL_GET_EPOW_STATUS);
109	109	OPAL_CALL(opal_set_system_attention_led, OPAL_SET_SYSTEM_ATTENTION_LED);
	110	+OPAL_CALL(opal_pci_next_error, OPAL_PCI_NEXT_ERROR);
	111	+OPAL_CALL(opal_pci_poll, OPAL_PCI_POLL);
110	112	OPAL_CALL(opal_pci_msi_eoi, OPAL_PCI_MSI_EOI);
	113	+OPAL_CALL(opal_pci_get_phb_diag_data2, OPAL_PCI_GET_PHB_DIAG_DATA2);
...	...	@@ -203,7 +203,8 @@
203	203
204	204	spin_lock_irqsave(&phb->lock, flags);
205	205
206		- rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
	206	+ rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
	207	+ PNV_PCI_DIAG_BUF_SIZE);
207	208	has_diag = (rc == OPAL_SUCCESS);
208	209
209	210	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,