x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB

The file names are somehow misleading as the code is not specific to AMD K8 CPUs anymore. The files accomodate code for other AMD CPU northbridges as well. Same is true for the config option which is valid for AMD CPU northbridges in general and not specific to K8. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160343.GD4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB
The file names are somehow misleading as the code is not specific to AMD K8 CPUs anymore. The files accomodate code for other AMD CPU northbridges as well. Same is true for the config option which is valid for AMD CPU northbridges in general and not specific to K8. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160343.GD4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Andreas Herrmann · H. Peter Anvin
1 parent 900f9ac9f1
Showing 16 changed files with 201 additions and 201 deletions Side-by-side Diff
arch/x86/Kconfig
arch/x86/include/asm/amd_nb.h
arch/x86/include/asm/k8.h
arch/x86/kernel/Makefile
arch/x86/kernel/amd_nb.c
arch/x86/kernel/aperture_64.c
arch/x86/kernel/cpu/intel_cacheinfo.c
arch/x86/kernel/k8.c
arch/x86/kernel/pci-gart_64.c
arch/x86/kernel/setup.c
arch/x86/mm/k8topology_64.c
arch/x86/mm/numa_64.c
drivers/char/agp/Kconfig
drivers/char/agp/amd64-agp.c
drivers/edac/Kconfig
drivers/edac/amd64_edac.c
@@ -670,7 +670,7 @@
 	bool "GART IOMMU support" if EMBEDDED
 	default y
 	select SWIOTLB
-	depends on X86_64 && PCI && K8_NB
+	depends on X86_64 && PCI && AMD_NB
 	---help---
 	  Support for full DMA access of devices with 32bit memory access only
 	  on systems with more than 3GB. This is usually needed for USB,
@@ -2076,7 +2076,7 @@
  
 endif # X86_32
  
-config K8_NB
+config AMD_NB
 	def_bool y
 	depends on CPU_SUP_AMD && PCI
  
+#ifndef _ASM_X86_AMD_NB_H
+#define _ASM_X86_AMD_NB_H
+
+#include <linux/pci.h>
+
+extern struct pci_device_id k8_nb_ids[];
+struct bootnode;
+
+extern int early_is_k8_nb(u32 value);
+extern int cache_k8_northbridges(void);
+extern void k8_flush_garts(void);
+extern int k8_get_nodes(struct bootnode *nodes);
+extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
+extern int k8_scan_nodes(void);
+
+struct k8_northbridge_info {
+	u16 num;
+	u8 gart_supported;
+	struct pci_dev **nb_misc;
+};
+extern struct k8_northbridge_info k8_northbridges;
+
+#ifdef CONFIG_AMD_NB
+
+static inline struct pci_dev *node_to_k8_nb_misc(int node)
+{
+	return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
+}
+
+#else
+
+static inline struct pci_dev *node_to_k8_nb_misc(int node)
+{
+	return NULL;
+}
+#endif
+
+
+#endif /* _ASM_X86_AMD_NB_H */
-#ifndef _ASM_X86_K8_H
-#define _ASM_X86_K8_H
-
-#include <linux/pci.h>
-
-extern struct pci_device_id k8_nb_ids[];
-struct bootnode;
-
-extern int early_is_k8_nb(u32 value);
-extern int cache_k8_northbridges(void);
-extern void k8_flush_garts(void);
-extern int k8_get_nodes(struct bootnode *nodes);
-extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
-extern int k8_scan_nodes(void);
-
-struct k8_northbridge_info {
-	u16 num;
-	u8 gart_supported;
-	struct pci_dev **nb_misc;
-};
-extern struct k8_northbridge_info k8_northbridges;
-
-#ifdef CONFIG_K8_NB
-
-static inline struct pci_dev *node_to_k8_nb_misc(int node)
-{
-	return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
-}
-
-#else
-
-static inline struct pci_dev *node_to_k8_nb_misc(int node)
-{
-	return NULL;
-}
-#endif
-
-
-#endif /* _ASM_X86_K8_H */
@@ -87,7 +87,7 @@
 obj-$(CONFIG_HPET_TIMER) 	+= hpet.o
 obj-$(CONFIG_APB_TIMER)		+= apb_timer.o
  
-obj-$(CONFIG_K8_NB)		+= k8.o
+obj-$(CONFIG_AMD_NB)		+= amd_nb.o
 obj-$(CONFIG_DEBUG_RODATA_TEST)	+= test_rodata.o
 obj-$(CONFIG_DEBUG_NX_TEST)	+= test_nx.o
  
+/*
+ * Shared support code for AMD K8 northbridges and derivates.
+ * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
+ */
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/amd_nb.h>
+
+static u32 *flush_words;
+
+struct pci_device_id k8_nb_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
+	{}
+};
+EXPORT_SYMBOL(k8_nb_ids);
+
+struct k8_northbridge_info k8_northbridges;
+EXPORT_SYMBOL(k8_northbridges);
+
+static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
+{
+	do {
+		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
+		if (!dev)
+			break;
+	} while (!pci_match_id(&k8_nb_ids[0], dev));
+	return dev;
+}
+
+int cache_k8_northbridges(void)
+{
+	int i;
+	struct pci_dev *dev;
+
+	if (k8_northbridges.num)
+		return 0;
+
+	dev = NULL;
+	while ((dev = next_k8_northbridge(dev)) != NULL)
+		k8_northbridges.num++;
+
+	/* some CPU families (e.g. family 0x11) do not support GART */
+	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
+		k8_northbridges.gart_supported = 1;
+
+	k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
+					  sizeof(void *), GFP_KERNEL);
+	if (!k8_northbridges.nb_misc)
+		return -ENOMEM;
+
+	if (!k8_northbridges.num) {
+		k8_northbridges.nb_misc[0] = NULL;
+		return 0;
+	}
+
+	if (k8_northbridges.gart_supported) {
+		flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
+				      GFP_KERNEL);
+		if (!flush_words) {
+			kfree(k8_northbridges.nb_misc);
+			return -ENOMEM;
+		}
+	}
+
+	dev = NULL;
+	i = 0;
+	while ((dev = next_k8_northbridge(dev)) != NULL) {
+		k8_northbridges.nb_misc[i] = dev;
+		if (k8_northbridges.gart_supported)
+			pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
+	}
+	k8_northbridges.nb_misc[i] = NULL;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cache_k8_northbridges);
+
+/* Ignores subdevice/subvendor but as far as I can figure out
+   they're useless anyways */
+int __init early_is_k8_nb(u32 device)
+{
+	struct pci_device_id *id;
+	u32 vendor = device & 0xffff;
+	device >>= 16;
+	for (id = k8_nb_ids; id->vendor; id++)
+		if (vendor == id->vendor && device == id->device)
+			return 1;
+	return 0;
+}
+
+void k8_flush_garts(void)
+{
+	int flushed, i;
+	unsigned long flags;
+	static DEFINE_SPINLOCK(gart_lock);
+
+	if (!k8_northbridges.gart_supported)
+		return;
+
+	/* Avoid races between AGP and IOMMU. In theory it's not needed
+	   but I'm not sure if the hardware won't lose flush requests
+	   when another is pending. This whole thing is so expensive anyways
+	   that it doesn't matter to serialize more. -AK */
+	spin_lock_irqsave(&gart_lock, flags);
+	flushed = 0;
+	for (i = 0; i < k8_northbridges.num; i++) {
+		pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
+				       flush_words[i]|1);
+		flushed++;
+	}
+	for (i = 0; i < k8_northbridges.num; i++) {
+		u32 w;
+		/* Make sure the hardware actually executed the flush*/
+		for (;;) {
+			pci_read_config_dword(k8_northbridges.nb_misc[i],
+					      0x9c, &w);
+			if (!(w & 1))
+				break;
+			cpu_relax();
+		}
+	}
+	spin_unlock_irqrestore(&gart_lock, flags);
+	if (!flushed)
+		printk("nothing to flush?\n");
+}
+EXPORT_SYMBOL_GPL(k8_flush_garts);
+
+static __init int init_k8_nbs(void)
+{
+	int err = 0;
+
+	err = cache_k8_northbridges();
+
+	if (err < 0)
+		printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
+
+	return err;
+}
+
+/* This has to go after the PCI subsystem */
+fs_initcall(init_k8_nbs);
@@ -27,7 +27,7 @@
 #include <asm/gart.h>
 #include <asm/pci-direct.h>
 #include <asm/dma.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/x86_init.h>
  
 int gart_iommu_aperture;
@@ -17,7 +17,7 @@
  
 #include <asm/processor.h>
 #include <linux/smp.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/smp.h>
  
 #define LVL_1_INST	1
@@ -306,7 +306,7 @@
 	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
 };
  
-#ifdef CONFIG_K8_NB
+#ifdef CONFIG_AMD_NB
  
 /*
  * L3 cache descriptors
  
@@ -556,12 +556,12 @@
 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
 		show_cache_disable_1, store_cache_disable_1);
  
-#else	/* CONFIG_K8_NB */
+#else	/* CONFIG_AMD_NB */
 static void __cpuinit
 amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
 {
 };
-#endif /* CONFIG_K8_NB */
+#endif /* CONFIG_AMD_NB */
  
 static int
 __cpuinit cpuid4_cache_lookup_regs(int index,
@@ -1000,7 +1000,7 @@
  
 static struct attribute *default_l3_attrs[] = {
 	DEFAULT_SYSFS_CACHE_ATTRS,
-#ifdef CONFIG_K8_NB
+#ifdef CONFIG_AMD_NB
 	&cache_disable_0.attr,
 	&cache_disable_1.attr,
 #endif
-/*
- * Shared support code for AMD K8 northbridges and derivates.
- * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
- */
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <asm/k8.h>
-
-static u32 *flush_words;
-
-struct pci_device_id k8_nb_ids[] = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
-	{}
-};
-EXPORT_SYMBOL(k8_nb_ids);
-
-struct k8_northbridge_info k8_northbridges;
-EXPORT_SYMBOL(k8_northbridges);
-
-static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
-{
-	do {
-		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
-		if (!dev)
-			break;
-	} while (!pci_match_id(&k8_nb_ids[0], dev));
-	return dev;
-}
-
-int cache_k8_northbridges(void)
-{
-	int i;
-	struct pci_dev *dev;
-
-	if (k8_northbridges.num)
-		return 0;
-
-	dev = NULL;
-	while ((dev = next_k8_northbridge(dev)) != NULL)
-		k8_northbridges.num++;
-
-	/* some CPU families (e.g. family 0x11) do not support GART */
-	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
-		k8_northbridges.gart_supported = 1;
-
-	k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
-					  sizeof(void *), GFP_KERNEL);
-	if (!k8_northbridges.nb_misc)
-		return -ENOMEM;
-
-	if (!k8_northbridges.num) {
-		k8_northbridges.nb_misc[0] = NULL;
-		return 0;
-	}
-
-	if (k8_northbridges.gart_supported) {
-		flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
-				      GFP_KERNEL);
-		if (!flush_words) {
-			kfree(k8_northbridges.nb_misc);
-			return -ENOMEM;
-		}
-	}
-
-	dev = NULL;
-	i = 0;
-	while ((dev = next_k8_northbridge(dev)) != NULL) {
-		k8_northbridges.nb_misc[i] = dev;
-		if (k8_northbridges.gart_supported)
-			pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
-	}
-	k8_northbridges.nb_misc[i] = NULL;
-	return 0;
-}
-EXPORT_SYMBOL_GPL(cache_k8_northbridges);
-
-/* Ignores subdevice/subvendor but as far as I can figure out
-   they're useless anyways */
-int __init early_is_k8_nb(u32 device)
-{
-	struct pci_device_id *id;
-	u32 vendor = device & 0xffff;
-	device >>= 16;
-	for (id = k8_nb_ids; id->vendor; id++)
-		if (vendor == id->vendor && device == id->device)
-			return 1;
-	return 0;
-}
-
-void k8_flush_garts(void)
-{
-	int flushed, i;
-	unsigned long flags;
-	static DEFINE_SPINLOCK(gart_lock);
-
-	if (!k8_northbridges.gart_supported)
-		return;
-
-	/* Avoid races between AGP and IOMMU. In theory it's not needed
-	   but I'm not sure if the hardware won't lose flush requests
-	   when another is pending. This whole thing is so expensive anyways
-	   that it doesn't matter to serialize more. -AK */
-	spin_lock_irqsave(&gart_lock, flags);
-	flushed = 0;
-	for (i = 0; i < k8_northbridges.num; i++) {
-		pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
-				       flush_words[i]|1);
-		flushed++;
-	}
-	for (i = 0; i < k8_northbridges.num; i++) {
-		u32 w;
-		/* Make sure the hardware actually executed the flush*/
-		for (;;) {
-			pci_read_config_dword(k8_northbridges.nb_misc[i],
-					      0x9c, &w);
-			if (!(w & 1))
-				break;
-			cpu_relax();
-		}
-	}
-	spin_unlock_irqrestore(&gart_lock, flags);
-	if (!flushed)
-		printk("nothing to flush?\n");
-}
-EXPORT_SYMBOL_GPL(k8_flush_garts);
-
-static __init int init_k8_nbs(void)
-{
-	int err = 0;
-
-	err = cache_k8_northbridges();
-
-	if (err < 0)
-		printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
-
-	return err;
-}
-
-/* This has to go after the PCI subsystem */
-fs_initcall(init_k8_nbs);
@@ -39,7 +39,7 @@
 #include <asm/cacheflush.h>
 #include <asm/swiotlb.h>
 #include <asm/dma.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/x86_init.h>
  
 static unsigned long iommu_bus_base;	/* GART remapping area (physical) */
@@ -107,7 +107,7 @@
 #include <asm/percpu.h>
 #include <asm/topology.h>
 #include <asm/apicdef.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #ifdef CONFIG_X86_64
 #include <asm/numa_64.h>
 #endif
@@ -22,7 +22,7 @@
 #include <asm/numa.h>
 #include <asm/mpspec.h>
 #include <asm/apic.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
  
 static struct bootnode __initdata nodes[8];
 static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE;
@@ -18,7 +18,7 @@
 #include <asm/dma.h>
 #include <asm/numa.h>
 #include <asm/acpi.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
  
 struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
 EXPORT_SYMBOL(node_data);
@@ -57,7 +57,7 @@
  
 config AGP_AMD64
 	tristate "AMD Opteron/Athlon64 on-CPU GART support"
-	depends on AGP && X86 && K8_NB
+	depends on AGP && X86 && AMD_NB
 	help
 	  This option gives you AGP support for the GLX component of
 	  X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
@@ -15,7 +15,7 @@
 #include <linux/mmzone.h>
 #include <asm/page.h>		/* PAGE_SIZE */
 #include <asm/e820.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/gart.h>
 #include "agp.h"
  
@@ -66,7 +66,7 @@
  
 config EDAC_AMD64
 	tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
-	depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
+	depends on EDAC_MM_EDAC && AMD_NB && X86_64 && PCI && EDAC_DECODE_MCE
 	help
 	  Support for error detection and correction on the AMD 64
 	  Families of Memory Controllers (K8, F10h and F11h)
 #include "amd64_edac.h"
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
  
 static struct edac_pci_ctl_info *amd64_ctl_pci;
...	...	@@ -670,7 +670,7 @@
670	670	bool "GART IOMMU support" if EMBEDDED
671	671	default y
672	672	select SWIOTLB
673		- depends on X86_64 && PCI && K8_NB
	673	+ depends on X86_64 && PCI && AMD_NB
674	674	---help---
675	675	Support for full DMA access of devices with 32bit memory access only
676	676	on systems with more than 3GB. This is usually needed for USB,
...	...	@@ -2076,7 +2076,7 @@
2076	2076
2077	2077	endif # X86_32
2078	2078
2079		-config K8_NB
	2079	+config AMD_NB
2080	2080	def_bool y
2081	2081	depends on CPU_SUP_AMD && PCI
2082	2082
	1	+#ifndef _ASM_X86_AMD_NB_H
	2	+#define _ASM_X86_AMD_NB_H
	3	+
	4	+#include <linux/pci.h>
	5	+
	6	+extern struct pci_device_id k8_nb_ids[];
	7	+struct bootnode;
	8	+
	9	+extern int early_is_k8_nb(u32 value);
	10	+extern int cache_k8_northbridges(void);
	11	+extern void k8_flush_garts(void);
	12	+extern int k8_get_nodes(struct bootnode *nodes);
	13	+extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
	14	+extern int k8_scan_nodes(void);
	15	+
	16	+struct k8_northbridge_info {
	17	+ u16 num;
	18	+ u8 gart_supported;
	19	+ struct pci_dev **nb_misc;
	20	+};
	21	+extern struct k8_northbridge_info k8_northbridges;
	22	+
	23	+#ifdef CONFIG_AMD_NB
	24	+
	25	+static inline struct pci_dev *node_to_k8_nb_misc(int node)
	26	+{
	27	+ return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
	28	+}
	29	+
	30	+#else
	31	+
	32	+static inline struct pci_dev *node_to_k8_nb_misc(int node)
	33	+{
	34	+ return NULL;
	35	+}
	36	+#endif
	37	+
	38	+
	39	+#endif /* _ASM_X86_AMD_NB_H */
1		-#ifndef _ASM_X86_K8_H
2		-#define _ASM_X86_K8_H
3		-
4		-#include <linux/pci.h>
5		-
6		-extern struct pci_device_id k8_nb_ids[];
7		-struct bootnode;
8		-
9		-extern int early_is_k8_nb(u32 value);
10		-extern int cache_k8_northbridges(void);
11		-extern void k8_flush_garts(void);
12		-extern int k8_get_nodes(struct bootnode *nodes);
13		-extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
14		-extern int k8_scan_nodes(void);
15		-
16		-struct k8_northbridge_info {
17		- u16 num;
18		- u8 gart_supported;
19		- struct pci_dev **nb_misc;
20		-};
21		-extern struct k8_northbridge_info k8_northbridges;
22		-
23		-#ifdef CONFIG_K8_NB
24		-
25		-static inline struct pci_dev *node_to_k8_nb_misc(int node)
26		-{
27		- return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
28		-}
29		-
30		-#else
31		-
32		-static inline struct pci_dev *node_to_k8_nb_misc(int node)
33		-{
34		- return NULL;
35		-}
36		-#endif
37		-
38		-
39		-#endif /* _ASM_X86_K8_H */
...	...	@@ -87,7 +87,7 @@
87	87	obj-$(CONFIG_HPET_TIMER) += hpet.o
88	88	obj-$(CONFIG_APB_TIMER) += apb_timer.o
89	89
90		-obj-$(CONFIG_K8_NB) += k8.o
	90	+obj-$(CONFIG_AMD_NB) += amd_nb.o
91	91	obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
92	92	obj-$(CONFIG_DEBUG_NX_TEST) += test_nx.o
93	93
	1	+/*
	2	+ * Shared support code for AMD K8 northbridges and derivates.
	3	+ * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
	4	+ */
	5	+#include <linux/types.h>
	6	+#include <linux/slab.h>
	7	+#include <linux/init.h>
	8	+#include <linux/errno.h>
	9	+#include <linux/module.h>
	10	+#include <linux/spinlock.h>
	11	+#include <asm/amd_nb.h>
	12	+
	13	+static u32 *flush_words;
	14	+
	15	+struct pci_device_id k8_nb_ids[] = {
	16	+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
	17	+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	18	+ {}
	19	+};
	20	+EXPORT_SYMBOL(k8_nb_ids);
	21	+
	22	+struct k8_northbridge_info k8_northbridges;
	23	+EXPORT_SYMBOL(k8_northbridges);
	24	+
	25	+static struct pci_dev next_k8_northbridge(struct pci_dev dev)
	26	+{
	27	+ do {
	28	+ dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	29	+ if (!dev)
	30	+ break;
	31	+ } while (!pci_match_id(&k8_nb_ids[0], dev));
	32	+ return dev;
	33	+}
	34	+
	35	+int cache_k8_northbridges(void)
	36	+{
	37	+ int i;
	38	+ struct pci_dev *dev;
	39	+
	40	+ if (k8_northbridges.num)
	41	+ return 0;
	42	+
	43	+ dev = NULL;
	44	+ while ((dev = next_k8_northbridge(dev)) != NULL)
	45	+ k8_northbridges.num++;
	46	+
	47	+ /* some CPU families (e.g. family 0x11) do not support GART */
	48	+ if (boot_cpu_data.x86 == 0xf \|\| boot_cpu_data.x86 == 0x10)
	49	+ k8_northbridges.gart_supported = 1;
	50	+
	51	+ k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
	52	+ sizeof(void *), GFP_KERNEL);
	53	+ if (!k8_northbridges.nb_misc)
	54	+ return -ENOMEM;
	55	+
	56	+ if (!k8_northbridges.num) {
	57	+ k8_northbridges.nb_misc[0] = NULL;
	58	+ return 0;
	59	+ }
	60	+
	61	+ if (k8_northbridges.gart_supported) {
	62	+ flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
	63	+ GFP_KERNEL);
	64	+ if (!flush_words) {
	65	+ kfree(k8_northbridges.nb_misc);
	66	+ return -ENOMEM;
	67	+ }
	68	+ }
	69	+
	70	+ dev = NULL;
	71	+ i = 0;
	72	+ while ((dev = next_k8_northbridge(dev)) != NULL) {
	73	+ k8_northbridges.nb_misc[i] = dev;
	74	+ if (k8_northbridges.gart_supported)
	75	+ pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
	76	+ }
	77	+ k8_northbridges.nb_misc[i] = NULL;
	78	+ return 0;
	79	+}
	80	+EXPORT_SYMBOL_GPL(cache_k8_northbridges);
	81	+
	82	+/* Ignores subdevice/subvendor but as far as I can figure out
	83	+ they're useless anyways */
	84	+int __init early_is_k8_nb(u32 device)
	85	+{
	86	+ struct pci_device_id *id;
	87	+ u32 vendor = device & 0xffff;
	88	+ device >>= 16;
	89	+ for (id = k8_nb_ids; id->vendor; id++)
	90	+ if (vendor == id->vendor && device == id->device)
	91	+ return 1;
	92	+ return 0;
	93	+}
	94	+
	95	+void k8_flush_garts(void)
	96	+{
	97	+ int flushed, i;
	98	+ unsigned long flags;
	99	+ static DEFINE_SPINLOCK(gart_lock);
	100	+
	101	+ if (!k8_northbridges.gart_supported)
	102	+ return;
	103	+
	104	+ /* Avoid races between AGP and IOMMU. In theory it's not needed
	105	+ but I'm not sure if the hardware won't lose flush requests
	106	+ when another is pending. This whole thing is so expensive anyways
	107	+ that it doesn't matter to serialize more. -AK */
	108	+ spin_lock_irqsave(&gart_lock, flags);
	109	+ flushed = 0;
	110	+ for (i = 0; i < k8_northbridges.num; i++) {
	111	+ pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
	112	+ flush_words[i]\|1);
	113	+ flushed++;
	114	+ }
	115	+ for (i = 0; i < k8_northbridges.num; i++) {
	116	+ u32 w;
	117	+ /* Make sure the hardware actually executed the flush*/
	118	+ for (;;) {
	119	+ pci_read_config_dword(k8_northbridges.nb_misc[i],
	120	+ 0x9c, &w);
	121	+ if (!(w & 1))
	122	+ break;
	123	+ cpu_relax();
	124	+ }
	125	+ }
	126	+ spin_unlock_irqrestore(&gart_lock, flags);
	127	+ if (!flushed)
	128	+ printk("nothing to flush?\n");
	129	+}
	130	+EXPORT_SYMBOL_GPL(k8_flush_garts);
	131	+
	132	+static __init int init_k8_nbs(void)
	133	+{
	134	+ int err = 0;
	135	+
	136	+ err = cache_k8_northbridges();
	137	+
	138	+ if (err < 0)
	139	+ printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
	140	+
	141	+ return err;
	142	+}
	143	+
	144	+/* This has to go after the PCI subsystem */
	145	+fs_initcall(init_k8_nbs);
...	...	@@ -27,7 +27,7 @@
27	27	#include <asm/gart.h>
28	28	#include <asm/pci-direct.h>
29	29	#include <asm/dma.h>
30		-#include <asm/k8.h>
	30	+#include <asm/amd_nb.h>
31	31	#include <asm/x86_init.h>
32	32
33	33	int gart_iommu_aperture;
...	...	@@ -17,7 +17,7 @@
17	17
18	18	#include <asm/processor.h>
19	19	#include <linux/smp.h>
20		-#include <asm/k8.h>
	20	+#include <asm/amd_nb.h>
21	21	#include <asm/smp.h>
22	22
23	23	#define LVL_1_INST 1
...	...	@@ -306,7 +306,7 @@
306	306	ssize_t (store)(struct _cpuid4_info , const char *, size_t count);
307	307	};
308	308
309		-#ifdef CONFIG_K8_NB
	309	+#ifdef CONFIG_AMD_NB
310	310
311	311	/*
312	312	* L3 cache descriptors
313	313
...	...	@@ -556,12 +556,12 @@
556	556	static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
557	557	show_cache_disable_1, store_cache_disable_1);
558	558
559		-#else /* CONFIG_K8_NB */
	559	+#else /* CONFIG_AMD_NB */
560	560	static void __cpuinit
561	561	amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
562	562	{
563	563	};
564		-#endif /* CONFIG_K8_NB */
	564	+#endif /* CONFIG_AMD_NB */
565	565
566	566	static int
567	567	__cpuinit cpuid4_cache_lookup_regs(int index,
...	...	@@ -1000,7 +1000,7 @@
1000	1000
1001	1001	static struct attribute *default_l3_attrs[] = {
1002	1002	DEFAULT_SYSFS_CACHE_ATTRS,
1003		-#ifdef CONFIG_K8_NB
	1003	+#ifdef CONFIG_AMD_NB
1004	1004	&cache_disable_0.attr,
1005	1005	&cache_disable_1.attr,
1006	1006	#endif
1		-/*
2		- * Shared support code for AMD K8 northbridges and derivates.
3		- * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
4		- */
5		-#include <linux/types.h>
6		-#include <linux/slab.h>
7		-#include <linux/init.h>
8		-#include <linux/errno.h>
9		-#include <linux/module.h>
10		-#include <linux/spinlock.h>
11		-#include <asm/k8.h>
12		-
13		-static u32 *flush_words;
14		-
15		-struct pci_device_id k8_nb_ids[] = {
16		- { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
17		- { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
18		- {}
19		-};
20		-EXPORT_SYMBOL(k8_nb_ids);
21		-
22		-struct k8_northbridge_info k8_northbridges;
23		-EXPORT_SYMBOL(k8_northbridges);
24		-
25		-static struct pci_dev next_k8_northbridge(struct pci_dev dev)
26		-{
27		- do {
28		- dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
29		- if (!dev)
30		- break;
31		- } while (!pci_match_id(&k8_nb_ids[0], dev));
32		- return dev;
33		-}
34		-
35		-int cache_k8_northbridges(void)
36		-{
37		- int i;
38		- struct pci_dev *dev;
39		-
40		- if (k8_northbridges.num)
41		- return 0;
42		-
43		- dev = NULL;
44		- while ((dev = next_k8_northbridge(dev)) != NULL)
45		- k8_northbridges.num++;
46		-
47		- /* some CPU families (e.g. family 0x11) do not support GART */
48		- if (boot_cpu_data.x86 == 0xf \|\| boot_cpu_data.x86 == 0x10)
49		- k8_northbridges.gart_supported = 1;
50		-
51		- k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
52		- sizeof(void *), GFP_KERNEL);
53		- if (!k8_northbridges.nb_misc)
54		- return -ENOMEM;
55		-
56		- if (!k8_northbridges.num) {
57		- k8_northbridges.nb_misc[0] = NULL;
58		- return 0;
59		- }
60		-
61		- if (k8_northbridges.gart_supported) {
62		- flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
63		- GFP_KERNEL);
64		- if (!flush_words) {
65		- kfree(k8_northbridges.nb_misc);
66		- return -ENOMEM;
67		- }
68		- }
69		-
70		- dev = NULL;
71		- i = 0;
72		- while ((dev = next_k8_northbridge(dev)) != NULL) {
73		- k8_northbridges.nb_misc[i] = dev;
74		- if (k8_northbridges.gart_supported)
75		- pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
76		- }
77		- k8_northbridges.nb_misc[i] = NULL;
78		- return 0;
79		-}
80		-EXPORT_SYMBOL_GPL(cache_k8_northbridges);
81		-
82		-/* Ignores subdevice/subvendor but as far as I can figure out
83		- they're useless anyways */
84		-int __init early_is_k8_nb(u32 device)
85		-{
86		- struct pci_device_id *id;
87		- u32 vendor = device & 0xffff;
88		- device >>= 16;
89		- for (id = k8_nb_ids; id->vendor; id++)
90		- if (vendor == id->vendor && device == id->device)
91		- return 1;
92		- return 0;
93		-}
94		-
95		-void k8_flush_garts(void)
96		-{
97		- int flushed, i;
98		- unsigned long flags;
99		- static DEFINE_SPINLOCK(gart_lock);
100		-
101		- if (!k8_northbridges.gart_supported)
102		- return;
103		-
104		- /* Avoid races between AGP and IOMMU. In theory it's not needed
105		- but I'm not sure if the hardware won't lose flush requests
106		- when another is pending. This whole thing is so expensive anyways
107		- that it doesn't matter to serialize more. -AK */
108		- spin_lock_irqsave(&gart_lock, flags);
109		- flushed = 0;
110		- for (i = 0; i < k8_northbridges.num; i++) {
111		- pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
112		- flush_words[i]\|1);
113		- flushed++;
114		- }
115		- for (i = 0; i < k8_northbridges.num; i++) {
116		- u32 w;
117		- /* Make sure the hardware actually executed the flush*/
118		- for (;;) {
119		- pci_read_config_dword(k8_northbridges.nb_misc[i],
120		- 0x9c, &w);
121		- if (!(w & 1))
122		- break;
123		- cpu_relax();
124		- }
125		- }
126		- spin_unlock_irqrestore(&gart_lock, flags);
127		- if (!flushed)
128		- printk("nothing to flush?\n");
129		-}
130		-EXPORT_SYMBOL_GPL(k8_flush_garts);
131		-
132		-static __init int init_k8_nbs(void)
133		-{
134		- int err = 0;
135		-
136		- err = cache_k8_northbridges();
137		-
138		- if (err < 0)
139		- printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
140		-
141		- return err;
142		-}
143		-
144		-/* This has to go after the PCI subsystem */
145		-fs_initcall(init_k8_nbs);
...	...	@@ -39,7 +39,7 @@
39	39	#include <asm/cacheflush.h>
40	40	#include <asm/swiotlb.h>
41	41	#include <asm/dma.h>
42		-#include <asm/k8.h>
	42	+#include <asm/amd_nb.h>
43	43	#include <asm/x86_init.h>
44	44
45	45	static unsigned long iommu_bus_base; /* GART remapping area (physical) */
...	...	@@ -107,7 +107,7 @@
107	107	#include <asm/percpu.h>
108	108	#include <asm/topology.h>
109	109	#include <asm/apicdef.h>
110		-#include <asm/k8.h>
	110	+#include <asm/amd_nb.h>
111	111	#ifdef CONFIG_X86_64
112	112	#include <asm/numa_64.h>
113	113	#endif