clk: clk-mux: Setup default clock parent during mux setup

In an effort to not have to hard code parent clock names for system timers, this patch introduces a DT property "clock-default" to mux-clocks which allows one to specify the default mux clock in DT by referring to the clock phandle. Doing so would allow us to eliminate the clk_set_parent code from mach-omap2/timer.c and also we wouldn't have to hardcode clock parent names in the OMAP_SYS_32K_TIMER_INIT and OMAP_SYS_GP_TIMER_INIT macros. Tested on AM335x beaglebone with timer1 clock. Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com>

clk: clk-mux: Setup default clock parent during mux setup
In an effort to not have to hard code parent clock names for system timers, this patch introduces a DT property "clock-default" to mux-clocks which allows one to specify the default mux clock in DT by referring to the clock phandle. Doing so would allow us to eliminate the clk_set_parent code from mach-omap2/timer.c and also we wouldn't have to hardcode clock parent names in the OMAP_SYS_32K_TIMER_INIT and OMAP_SYS_GP_TIMER_INIT macros. Tested on AM335x beaglebone with timer1 clock. Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com>
Joel Fernandes · Rajendra Nayak
1 parent e29ff85515
Showing 1 changed file with 22 additions and 2 deletions Side-by-side Diff
drivers/clk/clk-mux.c
@@ -186,10 +186,12 @@
  */
 void of_mux_clk_setup(struct device_node *node)
 {
-	struct clk *clk;
+	struct clk *clk, *parent;
+	struct device_node *parent_node;
+	struct of_phandle_args clkspec;
 	const char *clk_name = node->name;
 	void __iomem *reg;
-	int num_parents;
+	int num_parents, parent_idx;
 	const char **parent_names;
 	int i;
 	u8 clk_mux_flags = 0;
@@ -243,6 +245,24 @@
  
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	parent_node = of_parse_phandle(node, "clock-default", 0);
+
+	if (parent_node) {
+		parent_idx = of_count_phandle_with_args(node, "clocks",
+							"#clock-cells");
+		while (parent_idx--) {
+			if (parent_node == of_parse_phandle(node, "clocks",
+							    parent_idx)) {
+				clkspec.np = parent_node;
+				parent = of_clk_get_from_provider(&clkspec);
+				if (parent)
+					clk_set_parent(clk, parent);
+				break;
+			}
+		}
+		of_node_put(parent_node);
+	}
 }
 EXPORT_SYMBOL_GPL(of_mux_clk_setup);
 CLK_OF_DECLARE(mux_clk, "mux-clock", of_mux_clk_setup);
...	...	@@ -186,10 +186,12 @@
186	186	*/
187	187	void of_mux_clk_setup(struct device_node *node)
188	188	{
189		- struct clk *clk;
	189	+ struct clk clk, parent;
	190	+ struct device_node *parent_node;
	191	+ struct of_phandle_args clkspec;
190	192	const char *clk_name = node->name;
191	193	void __iomem *reg;
192		- int num_parents;
	194	+ int num_parents, parent_idx;
193	195	const char **parent_names;
194	196	int i;
195	197	u8 clk_mux_flags = 0;
...	...	@@ -243,6 +245,24 @@
243	245
244	246	if (!IS_ERR(clk))
245	247	of_clk_add_provider(node, of_clk_src_simple_get, clk);
	248	+
	249	+ parent_node = of_parse_phandle(node, "clock-default", 0);
	250	+
	251	+ if (parent_node) {
	252	+ parent_idx = of_count_phandle_with_args(node, "clocks",
	253	+ "#clock-cells");
	254	+ while (parent_idx--) {
	255	+ if (parent_node == of_parse_phandle(node, "clocks",
	256	+ parent_idx)) {
	257	+ clkspec.np = parent_node;
	258	+ parent = of_clk_get_from_provider(&clkspec);
	259	+ if (parent)
	260	+ clk_set_parent(clk, parent);
	261	+ break;
	262	+ }
	263	+ }
	264	+ of_node_put(parent_node);
	265	+ }
246	266	}
247	267	EXPORT_SYMBOL_GPL(of_mux_clk_setup);
248	268	CLK_OF_DECLARE(mux_clk, "mux-clock", of_mux_clk_setup);