Commit 27946315d28cb8d1ea02321c4c673b1428d9315b
Exists in
ti-lsk-linux-4.1.y
and in
10 other branches
Merge tag 'armsoc-for-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "A collection of fixes this week: - A set of clock fixes for shmobile platforms - A fix for tegra that moves serial port labels to be per board. We're choosing to merge this for 3.18 because the labels will start being parsed in 3.19, and without this change serial port numbers that used to be stable since the dawn of time will change numbers. - A few other DT tweaks for Tegra. - A fix for multi_v7_defconfig that makes it stop spewing cpufreq errors on Arndale (Exynos)" * tag 'armsoc-for-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: multi_v7_defconfig: fix failure setting CPU voltage by enabling dependent I2C controller ARM: tegra: roth: Fix SD card VDD_IO regulator ARM: tegra: Remove eMMC vmmc property for roth/tn7 ARM: dts: tegra: move serial aliases to per-board ARM: tegra: Add serial port labels to Tegra124 DT ARM: shmobile: kzm9g legacy: Set i2c clks_per_count to 2 ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module ARM: shmobile: r8a7790: Fix SD3CKCR address ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller
Showing 30 changed files Side-by-side Diff
- arch/arm/boot/dts/r8a7740.dtsi
- arch/arm/boot/dts/r8a7790.dtsi
- arch/arm/boot/dts/sun6i-a31.dtsi
- arch/arm/boot/dts/tegra114-dalmore.dts
- arch/arm/boot/dts/tegra114-roth.dts
- arch/arm/boot/dts/tegra114-tn7.dts
- arch/arm/boot/dts/tegra114.dtsi
- arch/arm/boot/dts/tegra124-jetson-tk1.dts
- arch/arm/boot/dts/tegra124-nyan-big.dts
- arch/arm/boot/dts/tegra124-venice2.dts
- arch/arm/boot/dts/tegra124.dtsi
- arch/arm/boot/dts/tegra20-harmony.dts
- arch/arm/boot/dts/tegra20-iris-512.dts
- arch/arm/boot/dts/tegra20-medcom-wide.dts
- arch/arm/boot/dts/tegra20-paz00.dts
- arch/arm/boot/dts/tegra20-seaboard.dts
- arch/arm/boot/dts/tegra20-tamonten.dtsi
- arch/arm/boot/dts/tegra20-trimslice.dts
- arch/arm/boot/dts/tegra20-ventana.dts
- arch/arm/boot/dts/tegra20-whistler.dts
- arch/arm/boot/dts/tegra20.dtsi
- arch/arm/boot/dts/tegra30-apalis-eval.dts
- arch/arm/boot/dts/tegra30-beaver.dts
- arch/arm/boot/dts/tegra30-cardhu.dtsi
- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
- arch/arm/boot/dts/tegra30.dtsi
- arch/arm/configs/multi_v7_defconfig
- arch/arm/mach-shmobile/clock-r8a7740.c
- arch/arm/mach-shmobile/clock-r8a7790.c
- arch/arm/mach-shmobile/setup-sh73a0.c
arch/arm/boot/dts/r8a7740.dtsi
... | ... | @@ -433,7 +433,7 @@ |
433 | 433 | clocks = <&cpg_clocks R8A7740_CLK_S>, |
434 | 434 | <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, |
435 | 435 | <&cpg_clocks R8A7740_CLK_B>, |
436 | - <&sub_clk>, <&sub_clk>, | |
436 | + <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, | |
437 | 437 | <&cpg_clocks R8A7740_CLK_B>; |
438 | 438 | #clock-cells = <1>; |
439 | 439 | renesas,clock-indices = < |
arch/arm/boot/dts/r8a7790.dtsi
... | ... | @@ -666,9 +666,9 @@ |
666 | 666 | #clock-cells = <0>; |
667 | 667 | clock-output-names = "sd2"; |
668 | 668 | }; |
669 | - sd3_clk: sd3_clk@e615007c { | |
669 | + sd3_clk: sd3_clk@e615026c { | |
670 | 670 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
671 | - reg = <0 0xe615007c 0 4>; | |
671 | + reg = <0 0xe615026c 0 4>; | |
672 | 672 | clocks = <&pll1_div2_clk>; |
673 | 673 | #clock-cells = <0>; |
674 | 674 | clock-output-names = "sd3"; |
arch/arm/boot/dts/sun6i-a31.dtsi
... | ... | @@ -361,6 +361,10 @@ |
361 | 361 | clocks = <&ahb1_gates 6>; |
362 | 362 | resets = <&ahb1_rst 6>; |
363 | 363 | #dma-cells = <1>; |
364 | + | |
365 | + /* DMA controller requires AHB1 clocked from PLL6 */ | |
366 | + assigned-clocks = <&ahb1_mux>; | |
367 | + assigned-clock-parents = <&pll6>; | |
364 | 368 | }; |
365 | 369 | |
366 | 370 | mmc0: mmc@01c0f000 { |
arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/tegra114-roth.dts
... | ... | @@ -15,6 +15,10 @@ |
15 | 15 | linux,initrd-end = <0x82800000>; |
16 | 16 | }; |
17 | 17 | |
18 | + aliases { | |
19 | + serial0 = &uartd; | |
20 | + }; | |
21 | + | |
18 | 22 | firmware { |
19 | 23 | trusted-foundations { |
20 | 24 | compatible = "tlm,trusted-foundations"; |
... | ... | @@ -916,8 +920,6 @@ |
916 | 920 | regulator-name = "vddio-sdmmc3"; |
917 | 921 | regulator-min-microvolt = <1800000>; |
918 | 922 | regulator-max-microvolt = <3300000>; |
919 | - regulator-always-on; | |
920 | - regulator-boot-on; | |
921 | 923 | }; |
922 | 924 | |
923 | 925 | ldousb { |
... | ... | @@ -962,7 +964,7 @@ |
962 | 964 | sdhci@78000400 { |
963 | 965 | status = "okay"; |
964 | 966 | bus-width = <4>; |
965 | - vmmc-supply = <&vddio_sdmmc3>; | |
967 | + vqmmc-supply = <&vddio_sdmmc3>; | |
966 | 968 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
967 | 969 | power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; |
968 | 970 | }; |
... | ... | @@ -971,7 +973,6 @@ |
971 | 973 | sdhci@78000600 { |
972 | 974 | status = "okay"; |
973 | 975 | bus-width = <8>; |
974 | - vmmc-supply = <&vdd_1v8>; | |
975 | 976 | non-removable; |
976 | 977 | }; |
977 | 978 |
arch/arm/boot/dts/tegra114-tn7.dts
... | ... | @@ -15,6 +15,10 @@ |
15 | 15 | linux,initrd-end = <0x82800000>; |
16 | 16 | }; |
17 | 17 | |
18 | + aliases { | |
19 | + serial0 = &uartd; | |
20 | + }; | |
21 | + | |
18 | 22 | firmware { |
19 | 23 | trusted-foundations { |
20 | 24 | compatible = "tlm,trusted-foundations"; |
... | ... | @@ -240,7 +244,6 @@ |
240 | 244 | sdhci@78000600 { |
241 | 245 | status = "okay"; |
242 | 246 | bus-width = <8>; |
243 | - vmmc-supply = <&vdd_1v8>; | |
244 | 247 | non-removable; |
245 | 248 | }; |
246 | 249 |
arch/arm/boot/dts/tegra114.dtsi
... | ... | @@ -9,13 +9,6 @@ |
9 | 9 | compatible = "nvidia,tegra114"; |
10 | 10 | interrupt-parent = <&gic>; |
11 | 11 | |
12 | - aliases { | |
13 | - serial0 = &uarta; | |
14 | - serial1 = &uartb; | |
15 | - serial2 = &uartc; | |
16 | - serial3 = &uartd; | |
17 | - }; | |
18 | - | |
19 | 12 | host1x@50000000 { |
20 | 13 | compatible = "nvidia,tegra114-host1x", "simple-bus"; |
21 | 14 | reg = <0x50000000 0x00028000>; |
arch/arm/boot/dts/tegra124-jetson-tk1.dts
arch/arm/boot/dts/tegra124-nyan-big.dts
arch/arm/boot/dts/tegra124-venice2.dts
arch/arm/boot/dts/tegra124.dtsi
... | ... | @@ -286,7 +286,7 @@ |
286 | 286 | * the APB DMA based serial driver, the comptible is |
287 | 287 | * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". |
288 | 288 | */ |
289 | - serial@0,70006000 { | |
289 | + uarta: serial@0,70006000 { | |
290 | 290 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
291 | 291 | reg = <0x0 0x70006000 0x0 0x40>; |
292 | 292 | reg-shift = <2>; |
... | ... | @@ -299,7 +299,7 @@ |
299 | 299 | status = "disabled"; |
300 | 300 | }; |
301 | 301 | |
302 | - serial@0,70006040 { | |
302 | + uartb: serial@0,70006040 { | |
303 | 303 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
304 | 304 | reg = <0x0 0x70006040 0x0 0x40>; |
305 | 305 | reg-shift = <2>; |
... | ... | @@ -312,7 +312,7 @@ |
312 | 312 | status = "disabled"; |
313 | 313 | }; |
314 | 314 | |
315 | - serial@0,70006200 { | |
315 | + uartc: serial@0,70006200 { | |
316 | 316 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
317 | 317 | reg = <0x0 0x70006200 0x0 0x40>; |
318 | 318 | reg-shift = <2>; |
... | ... | @@ -325,7 +325,7 @@ |
325 | 325 | status = "disabled"; |
326 | 326 | }; |
327 | 327 | |
328 | - serial@0,70006300 { | |
328 | + uartd: serial@0,70006300 { | |
329 | 329 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
330 | 330 | reg = <0x0 0x70006300 0x0 0x40>; |
331 | 331 | reg-shift = <2>; |
arch/arm/boot/dts/tegra20-harmony.dts
arch/arm/boot/dts/tegra20-iris-512.dts
arch/arm/boot/dts/tegra20-medcom-wide.dts
arch/arm/boot/dts/tegra20-paz00.dts
arch/arm/boot/dts/tegra20-seaboard.dts
arch/arm/boot/dts/tegra20-tamonten.dtsi
arch/arm/boot/dts/tegra20-trimslice.dts
arch/arm/boot/dts/tegra20-ventana.dts
arch/arm/boot/dts/tegra20-whistler.dts
arch/arm/boot/dts/tegra20.dtsi
... | ... | @@ -9,14 +9,6 @@ |
9 | 9 | compatible = "nvidia,tegra20"; |
10 | 10 | interrupt-parent = <&intc>; |
11 | 11 | |
12 | - aliases { | |
13 | - serial0 = &uarta; | |
14 | - serial1 = &uartb; | |
15 | - serial2 = &uartc; | |
16 | - serial3 = &uartd; | |
17 | - serial4 = &uarte; | |
18 | - }; | |
19 | - | |
20 | 12 | host1x@50000000 { |
21 | 13 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
22 | 14 | reg = <0x50000000 0x00024000>; |
arch/arm/boot/dts/tegra30-apalis-eval.dts
arch/arm/boot/dts/tegra30-beaver.dts
arch/arm/boot/dts/tegra30-cardhu.dtsi
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
arch/arm/boot/dts/tegra30.dtsi
... | ... | @@ -9,14 +9,6 @@ |
9 | 9 | compatible = "nvidia,tegra30"; |
10 | 10 | interrupt-parent = <&intc>; |
11 | 11 | |
12 | - aliases { | |
13 | - serial0 = &uarta; | |
14 | - serial1 = &uartb; | |
15 | - serial2 = &uartc; | |
16 | - serial3 = &uartd; | |
17 | - serial4 = &uarte; | |
18 | - }; | |
19 | - | |
20 | 12 | pcie-controller@00003000 { |
21 | 13 | compatible = "nvidia,tegra30-pcie"; |
22 | 14 | device_type = "pci"; |
arch/arm/configs/multi_v7_defconfig
arch/arm/mach-shmobile/clock-r8a7740.c
... | ... | @@ -455,7 +455,7 @@ |
455 | 455 | MSTP128, MSTP127, MSTP125, |
456 | 456 | MSTP116, MSTP111, MSTP100, MSTP117, |
457 | 457 | |
458 | - MSTP230, | |
458 | + MSTP230, MSTP229, | |
459 | 459 | MSTP222, |
460 | 460 | MSTP218, MSTP217, MSTP216, MSTP214, |
461 | 461 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, |
462 | 462 | |
... | ... | @@ -474,11 +474,12 @@ |
474 | 474 | [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ |
475 | 475 | [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ |
476 | 476 | [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ |
477 | - [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ | |
477 | + [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */ | |
478 | 478 | [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ |
479 | 479 | [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ |
480 | 480 | |
481 | 481 | [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ |
482 | + [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */ | |
482 | 483 | [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ |
483 | 484 | [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ |
484 | 485 | [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ |
... | ... | @@ -575,6 +576,10 @@ |
575 | 576 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), |
576 | 577 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), |
577 | 578 | CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), |
579 | + CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]), | |
580 | + CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]), | |
581 | + CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]), | |
582 | + CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]), | |
578 | 583 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), |
579 | 584 | CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), |
580 | 585 |
arch/arm/mach-shmobile/clock-r8a7790.c
arch/arm/mach-shmobile/setup-sh73a0.c
... | ... | @@ -26,6 +26,7 @@ |
26 | 26 | #include <linux/of_platform.h> |
27 | 27 | #include <linux/delay.h> |
28 | 28 | #include <linux/input.h> |
29 | +#include <linux/i2c/i2c-sh_mobile.h> | |
29 | 30 | #include <linux/io.h> |
30 | 31 | #include <linux/serial_sci.h> |
31 | 32 | #include <linux/sh_dma.h> |
32 | 33 | |
... | ... | @@ -192,11 +193,18 @@ |
192 | 193 | }, |
193 | 194 | }; |
194 | 195 | |
196 | +static struct i2c_sh_mobile_platform_data i2c_platform_data = { | |
197 | + .clks_per_count = 2, | |
198 | +}; | |
199 | + | |
195 | 200 | static struct platform_device i2c0_device = { |
196 | 201 | .name = "i2c-sh_mobile", |
197 | 202 | .id = 0, |
198 | 203 | .resource = i2c0_resources, |
199 | 204 | .num_resources = ARRAY_SIZE(i2c0_resources), |
205 | + .dev = { | |
206 | + .platform_data = &i2c_platform_data, | |
207 | + }, | |
200 | 208 | }; |
201 | 209 | |
202 | 210 | static struct platform_device i2c1_device = { |
... | ... | @@ -204,6 +212,9 @@ |
204 | 212 | .id = 1, |
205 | 213 | .resource = i2c1_resources, |
206 | 214 | .num_resources = ARRAY_SIZE(i2c1_resources), |
215 | + .dev = { | |
216 | + .platform_data = &i2c_platform_data, | |
217 | + }, | |
207 | 218 | }; |
208 | 219 | |
209 | 220 | static struct platform_device i2c2_device = { |
... | ... | @@ -211,6 +222,9 @@ |
211 | 222 | .id = 2, |
212 | 223 | .resource = i2c2_resources, |
213 | 224 | .num_resources = ARRAY_SIZE(i2c2_resources), |
225 | + .dev = { | |
226 | + .platform_data = &i2c_platform_data, | |
227 | + }, | |
214 | 228 | }; |
215 | 229 | |
216 | 230 | static struct platform_device i2c3_device = { |
... | ... | @@ -218,6 +232,9 @@ |
218 | 232 | .id = 3, |
219 | 233 | .resource = i2c3_resources, |
220 | 234 | .num_resources = ARRAY_SIZE(i2c3_resources), |
235 | + .dev = { | |
236 | + .platform_data = &i2c_platform_data, | |
237 | + }, | |
221 | 238 | }; |
222 | 239 | |
223 | 240 | static struct platform_device i2c4_device = { |
... | ... | @@ -225,6 +242,9 @@ |
225 | 242 | .id = 4, |
226 | 243 | .resource = i2c4_resources, |
227 | 244 | .num_resources = ARRAY_SIZE(i2c4_resources), |
245 | + .dev = { | |
246 | + .platform_data = &i2c_platform_data, | |
247 | + }, | |
228 | 248 | }; |
229 | 249 | |
230 | 250 | static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { |