Eric Lee / smarc-ti-linux-kernel

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Commit 28cf35675a66947b20731f6acbc9d5b131930ce3

Authored by Hao Liu
Committed by Daniel Lezcano
1 parent 4e2bec0c32
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

clocksource: sirf: Disable counter before re-setting it 

According to HW spec, we have to disable the counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.

And this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.

Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Showing 1 changed file with 4 additions and 1 deletions Side-by-side Diff

drivers/clocksource/timer-marco.c
Diff comments   View file @ 28cf356
... ... @@ -63,7 +63,7 @@
63 63 /* enable count and interrupt */
64 64 static inline void sirfsoc_timer_count_enable(int idx)
65 65 {
66   - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
  66 + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
67 67 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
68 68 }
69 69  
... ... @@ -102,6 +102,9 @@
102 102 struct clock_event_device *ce)
103 103 {
104 104 int cpu = smp_processor_id();
  105 +
  106 + /* disable timer first, then modify the related registers */
  107 + sirfsoc_timer_count_disable(cpu);
105 108  
106 109 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
107 110 4 * cpu);