Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 2a2c74b2efcb1a0ca3fdcb5fbb96ad8de6a29177

Authored by Alistair Popple 2014-03-06 11:52:27 +0800

Committed by Benjamin Herrenschmidt 2014-05-01 06:26:26 +0800

1 parent 6b11930f72

Exists in ti-lsk-linux-4.1.y and in 10 other branches

IBM Akebono: Add the Akebono platform

This patch adds support for the IBM Akebono board.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Showing 11 changed files with 901 additions and 26 deletions Inline Diff

Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
arch/powerpc/boot/Makefile
arch/powerpc/boot/dcr.h
arch/powerpc/boot/dts/akebono.dts
arch/powerpc/boot/treeboot-akebono.c
arch/powerpc/boot/wrapper
arch/powerpc/configs/44x/akebono_defconfig
arch/powerpc/platforms/44x/Kconfig
arch/powerpc/platforms/44x/Makefile
arch/powerpc/platforms/44x/ppc476.c
arch/powerpc/sysdev/ppc4xx_pci.c

Documentation/devicetree/bindings/powerpc/4xx/akebono.txt

Diff comments View file @ 2a2c74b

File was created	1
	2	IBM Akebono board device tree
	3	=============================
	4
	5	The IBM Akebono board is a development board for the PPC476GTR SoC.
	6
	7	0) The root node
	8
	9	Required properties:
	10
	11	- model : "ibm,akebono".
	12	- compatible : "ibm,akebono" , "ibm,476gtr".
	13
	14	1.a) The Secure Digital Host Controller Interface (SDHCI) node
	15
	16	Represent the Secure Digital Host Controller Interfaces.
	17
	18	Required properties:
	19
	20	- compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
	21	- reg : should contain the SDHCI registers location and length.
	22	- interrupt-parent : a phandle for the interrupt controller.
	23	- interrupts : should contain the SDHCI interrupt.
	24
	25	1.b) The Advanced Host Controller Interface (AHCI) SATA node
	26
	27	Represents the advanced host controller SATA interface.
	28
	29	Required properties:
	30
	31	- compatible : should be "ibm,476gtr-ahci".
	32	- reg : should contain the AHCI registers location and length.
	33	- interrupt-parent : a phandle for the interrupt controller.
	34	- interrupts : should contain the AHCI interrupt.
	35
	36	1.c) The FPGA node
	37
	38	The Akebono board stores some board information such as the revision
	39	number in an FPGA which is represented by this node.
	40
	41	Required properties:
	42
	43	- compatible : should be "ibm,akebono-fpga".
	44	- reg : should contain the FPGA registers location and length.
	45
	46	1.d) The AVR node
	47
	48	The Akebono board has an Atmel AVR microprocessor attached to the I2C
	49	bus as a power controller for the board.
	50
	51	Required properties:
	52
	53	- compatible : should be "ibm,akebono-avr".
	54	- reg : should contain the I2C bus address for the AVR.
	55

arch/powerpc/boot/Makefile

Diff comments View file @ 2a2c74b

 # Makefile for making ELF bootable images for booting on CHRP
 # using Open Firmware.
 #
 # Geert Uytterhoeven	September 1997
 #
 # Based on coffboot by Paul Mackerras
 # Simplified for ppc64 by Todd Inglett
 #
 # NOTE:	this code is built for 32 bit in ELF32 format even though
 #	it packages a 64 bit kernel.  We do this to simplify the
 #	bootloader and increase compatibility with OpenFirmware.
 #
 #	To this end we need to define BOOTCC, etc, as the tools
 #	needed to build the 32 bit image.  That's normally the same
 #	compiler for the rest of the kernel, with the -m32 flag added.
 #	To make it easier to setup a cross compiler,
 #	CROSS32_COMPILE is setup as a prefix just like CROSS_COMPILE
 #	in the toplevel makefile.
 all: $(obj)/zImage
 BOOTCFLAGS    := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
 		 -fno-strict-aliasing -Os -msoft-float -pipe \
 		 -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
 		 -isystem $(shell $(CROSS32CC) -print-file-name=include)
 ifdef CONFIG_PPC64_BOOT_WRAPPER
 BOOTCFLAGS	+= -m64
 endif
 ifdef CONFIG_CPU_BIG_ENDIAN
 BOOTCFLAGS	+= -mbig-endian
 endif
 BOOTAFLAGS	:= -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
 ifdef CONFIG_DEBUG_INFO
 BOOTCFLAGS	+= -g
 endif
 ifeq ($(call cc-option-yn, -fstack-protector),y)
 BOOTCFLAGS	+= -fno-stack-protector
 endif
 BOOTCFLAGS	+= -I$(obj) -I$(srctree)/$(obj)
 DTC_FLAGS	?= -p 1024
 $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
 zlib       := inffast.c inflate.c inftrees.c
 zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
 zliblinuxheader := zlib.h zconf.h zutil.h
 $(addprefix $(obj)/,$(zlib) cuboot-c2k.o gunzip_util.o main.o): \
 	$(addprefix $(obj)/,$(zliblinuxheader)) $(addprefix $(obj)/,$(zlibheader))
 libfdt       := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
 libfdtheader := fdt.h libfdt.h libfdt_internal.h
 $(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o): \
 	$(addprefix $(obj)/,$(libfdtheader))
 src-wlib-y := string.S crt0.S crtsavres.S stdio.c main.c \
 		$(libfdt) libfdt-wrapper.c \
 		ns16550.c serial.c simple_alloc.c div64.S util.S \
 		gunzip_util.c elf_util.c $(zlib) devtree.c stdlib.c \
 		oflib.c ofconsole.c cuboot.c mpsc.c cpm-serial.c \
 		uartlite.c mpc52xx-psc.c
 src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
 src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
 src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c fsl-soc.c
 src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
 src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
 src-plat-y := of.c epapr.c
 src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
 				treeboot-walnut.c cuboot-acadia.c \
 				cuboot-kilauea.c simpleboot.c \
 				virtex405-head.S virtex.c
 src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
 				cuboot-bamboo.c cuboot-sam440ep.c \
 				cuboot-sequoia.c cuboot-rainier.c \
 				cuboot-taishan.c cuboot-katmai.c \
 				cuboot-warp.c cuboot-yosemite.c \
 				treeboot-iss4xx.c treeboot-currituck.c \
+				treeboot-akebono.c \
 				simpleboot.c fixed-head.S virtex.c
 src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
 src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
 src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
 src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
 src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
 src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
 					cuboot-c2k.c gamecube-head.S \
 					gamecube.c wii-head.S wii.c holly.c \
 					fixed-head.S mvme5100.c
 src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
 src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
 src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
 src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
 src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
 src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
 src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
 src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
 src-wlib := $(sort $(src-wlib-y))
 src-plat := $(sort $(src-plat-y))
 src-boot := $(src-wlib) $(src-plat) empty.c
 src-boot := $(addprefix $(obj)/, $(src-boot))
 obj-boot := $(addsuffix .o, $(basename $(src-boot)))
 obj-wlib := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-wlib))))
 obj-plat := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-plat))))
 obj-plat: $(libfdt)
 quiet_cmd_copy_zlib = COPY    $@
       cmd_copy_zlib = sed "s@__used@@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
 quiet_cmd_copy_zlibheader = COPY    $@
       cmd_copy_zlibheader = sed "s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
 # stddef.h for NULL
 quiet_cmd_copy_zliblinuxheader = COPY    $@
       cmd_copy_zliblinuxheader = sed "s@<linux/string.h>@\"string.h\"@;s@<linux/kernel.h>@<stddef.h>@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
 $(addprefix $(obj)/,$(zlib)): $(obj)/%: $(srctree)/lib/zlib_inflate/%
 	$(call cmd,copy_zlib)
 $(addprefix $(obj)/,$(zlibheader)): $(obj)/%: $(srctree)/lib/zlib_inflate/%
 	$(call cmd,copy_zlibheader)
 $(addprefix $(obj)/,$(zliblinuxheader)): $(obj)/%: $(srctree)/include/linux/%
 	$(call cmd,copy_zliblinuxheader)
 quiet_cmd_copy_libfdt = COPY    $@
       cmd_copy_libfdt = cp $< $@
 $(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/%
 	$(call cmd,copy_libfdt)
 $(obj)/empty.c:
 	@touch $@
 $(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
 	$(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
 		-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
 $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
 	@cp $< $@
 clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
 		$(libfdt) $(libfdtheader) \
 		empty.c zImage.coff.lds zImage.ps3.lds zImage.lds
 quiet_cmd_bootcc = BOOTCC  $@
       cmd_bootcc = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTCFLAGS) -c -o $@ $<
 quiet_cmd_bootas = BOOTAS  $@
       cmd_bootas = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
 quiet_cmd_bootar = BOOTAR  $@
       cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
 $(obj-libfdt): $(obj)/%.o: $(srctree)/scripts/dtc/libfdt/%.c FORCE
 	$(call if_changed_dep,bootcc)
 $(patsubst %.c,%.o, $(filter %.c, $(src-boot))): %.o: %.c FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,bootcc)
 $(patsubst %.S,%.o, $(filter %.S, $(src-boot))): %.o: %.S FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,bootas)
 $(obj)/wrapper.a: $(obj-wlib) FORCE
 	$(call if_changed,bootar)
 hostprogs-y	:= addnote hack-coff mktree
 targets		+= $(patsubst $(obj)/%,%,$(obj-boot) wrapper.a)
 extra-y		:= $(obj)/wrapper.a $(obj-plat) $(obj)/empty.o \
 		   $(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds
 dtstree		:= $(srctree)/$(src)/dts
 wrapper		:=$(srctree)/$(src)/wrapper
 wrapperbits	:= $(extra-y) $(addprefix $(obj)/,addnote hack-coff mktree) \
 			$(wrapper) FORCE
 #############
 # Bits for building various flavours of zImage
 ifneq ($(CROSS32_COMPILE),)
 CROSSWRAP := -C "$(CROSS32_COMPILE)"
 else
 ifneq ($(CROSS_COMPILE),)
 CROSSWRAP := -C "$(CROSS_COMPILE)"
 endif
 endif
 # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd
 quiet_cmd_wrap	= WRAP    $@
       cmd_wrap	=$(CONFIG_SHELL) $(wrapper) -c -o $@ -p $2 $(CROSSWRAP) \
 		$(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) vmlinux
 image-$(CONFIG_PPC_PSERIES)		+= zImage.pseries
 image-$(CONFIG_PPC_POWERNV)		+= zImage.pseries
 image-$(CONFIG_PPC_MAPLE)		+= zImage.maple
 image-$(CONFIG_PPC_IBM_CELL_BLADE)	+= zImage.pseries
 image-$(CONFIG_PPC_PS3)			+= dtbImage.ps3
 image-$(CONFIG_PPC_CELLEB)		+= zImage.pseries
 image-$(CONFIG_PPC_CELL_QPACE)		+= zImage.pseries
 image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
 image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
 image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
 image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
 image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
 image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
 #
 # Targets which embed a device tree blob
 #
 # Theses are default targets to build images which embed device tree blobs.
 # They are only required on boards which do not have FDT support in firmware.
 # Boards with newish u-boot firmware can use the uImage target above
 #
 # Board ports in arch/powerpc/platform/40x/Kconfig
 image-$(CONFIG_EP405)			+= dtbImage.ep405
 image-$(CONFIG_HOTFOOT)			+= cuImage.hotfoot
 image-$(CONFIG_WALNUT)			+= treeImage.walnut
 image-$(CONFIG_ACADIA)			+= cuImage.acadia
 image-$(CONFIG_OBS600)			+= uImage.obs600
 # Board ports in arch/powerpc/platform/44x/Kconfig
 image-$(CONFIG_EBONY)			+= treeImage.ebony cuImage.ebony
 image-$(CONFIG_BAMBOO)			+= treeImage.bamboo cuImage.bamboo
 image-$(CONFIG_SAM440EP)		+= cuImage.sam440ep
 image-$(CONFIG_SEQUOIA)			+= cuImage.sequoia
 image-$(CONFIG_RAINIER)			+= cuImage.rainier
 image-$(CONFIG_TAISHAN)			+= cuImage.taishan
 image-$(CONFIG_KATMAI)			+= cuImage.katmai
 image-$(CONFIG_WARP)			+= cuImage.warp
 image-$(CONFIG_YOSEMITE)		+= cuImage.yosemite
 image-$(CONFIG_ISS4xx)			+= treeImage.iss4xx \
 					   treeImage.iss4xx-mpic
 image-$(CONFIG_CURRITUCK)			+= treeImage.currituck
+image-$(CONFIG_AKEBONO)			+= treeImage.akebono
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_MPC86XADS)		+= cuImage.mpc866ads
 image-$(CONFIG_MPC885ADS)		+= cuImage.mpc885ads
 image-$(CONFIG_PPC_EP88XC)		+= dtbImage.ep88xc
 image-$(CONFIG_PPC_ADDER875)		+= cuImage.adder875-uboot \
 					   dtbImage.adder875-redboot
 # Board ports in arch/powerpc/platform/52xx/Kconfig
 image-$(CONFIG_PPC_LITE5200)		+= cuImage.lite5200 lite5200.dtb
 image-$(CONFIG_PPC_LITE5200)		+= cuImage.lite5200b lite5200b.dtb
 image-$(CONFIG_PPC_MEDIA5200)		+= cuImage.media5200 media5200.dtb
 # Board ports in arch/powerpc/platform/82xx/Kconfig
 image-$(CONFIG_MPC8272_ADS)		+= cuImage.mpc8272ads
 image-$(CONFIG_PQ2FADS)			+= cuImage.pq2fads
 image-$(CONFIG_EP8248E)			+= dtbImage.ep8248e
 # Board ports in arch/powerpc/platform/83xx/Kconfig
 image-$(CONFIG_MPC832x_MDS)		+= cuImage.mpc832x_mds
 image-$(CONFIG_MPC832x_RDB)		+= cuImage.mpc832x_rdb
 image-$(CONFIG_MPC834x_ITX)		+= cuImage.mpc8349emitx \
 					   cuImage.mpc8349emitxgp
 image-$(CONFIG_MPC834x_MDS)		+= cuImage.mpc834x_mds
 image-$(CONFIG_MPC836x_MDS)		+= cuImage.mpc836x_mds
 image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
 # Board ports in arch/powerpc/platform/85xx/Kconfig
 image-$(CONFIG_MPC8540_ADS)		+= cuImage.mpc8540ads
 image-$(CONFIG_MPC8560_ADS)		+= cuImage.mpc8560ads
 image-$(CONFIG_MPC85xx_CDS)		+= cuImage.mpc8541cds \
 					   cuImage.mpc8548cds_32b \
 					   cuImage.mpc8555cds
 image-$(CONFIG_MPC85xx_MDS)		+= cuImage.mpc8568mds
 image-$(CONFIG_MPC85xx_DS)		+= cuImage.mpc8544ds \
 					   cuImage.mpc8572ds
 image-$(CONFIG_TQM8540)			+= cuImage.tqm8540
 image-$(CONFIG_TQM8541)			+= cuImage.tqm8541
 image-$(CONFIG_TQM8548)			+= cuImage.tqm8548
 image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
 image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
 image-$(CONFIG_SBC8548)			+= cuImage.sbc8548
 image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
 image-$(CONFIG_STORCENTER)		+= cuImage.storcenter
 image-$(CONFIG_MPC7448HPC2)		+= cuImage.mpc7448hpc2
 image-$(CONFIG_PPC_C2K)			+= cuImage.c2k
 image-$(CONFIG_GAMECUBE)		+= dtbImage.gamecube
 image-$(CONFIG_WII)			+= dtbImage.wii
 image-$(CONFIG_MVME5100)		+= dtbImage.mvme5100
 # Board port in arch/powerpc/platform/amigaone/Kconfig
 image-$(CONFIG_AMIGAONE)		+= cuImage.amigaone
 # For 32-bit powermacs, build the COFF and miboot images
 # as well as the ELF images.
 ifeq ($(CONFIG_PPC32),y)
 image-$(CONFIG_PPC_PMAC)	+= zImage.coff zImage.miboot
 endif
 # Allow extra targets to be added to the defconfig
 image-y	+= $(subst ",,$(CONFIG_EXTRA_TARGETS))
 initrd-  := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
 initrd-y := $(patsubst zImage%, zImage.initrd%, \
 		$(patsubst dtbImage%, dtbImage.initrd%, \
 		$(patsubst simpleImage%, simpleImage.initrd%, \
 		$(patsubst treeImage%, treeImage.initrd%, $(image-y)))))
 initrd-y := $(filter-out $(image-y), $(initrd-y))
 targets	+= $(image-y) $(initrd-y)
 $(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
 # Don't put the ramdisk on the pattern rule; when its missing make will try
 # the pattern rule with less dependencies that also matches (even with the
 # hard dependency listed).
 $(obj)/zImage.initrd.%: vmlinux $(wrapperbits)
 	$(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz)
 $(obj)/zImage.%: vmlinux $(wrapperbits)
 	$(call if_changed,wrap,$*)
 # dtbImage% - a dtbImage is a zImage with an embedded device tree blob
 $(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
 	$(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
 	$(call if_changed,wrap,$*,,$(obj)/$*.dtb)
 # This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
 # prefix
 $(obj)/vmlinux.strip: vmlinux
 	$(STRIP) -s -R .comment $< -o $@
 $(obj)/uImage: vmlinux $(wrapperbits)
 	$(call if_changed,wrap,uboot)
 $(obj)/uImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 $(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
 $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 $(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
 $(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 $(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
 $(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
 	$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
 # Rule to build device tree blobs
 $(obj)/%.dtb: $(src)/dts/%.dts FORCE
 	$(call if_changed_dep,dtc)
 # If there isn't a platform selected then just strip the vmlinux.
 ifeq (,$(image-y))
 image-y := vmlinux.strip
 endif
 $(obj)/zImage:		$(addprefix $(obj)/, $(image-y))
 	@rm -f $@; ln $< $@
 $(obj)/zImage.initrd:	$(addprefix $(obj)/, $(initrd-y))
 	@rm -f $@; ln $< $@
 install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
 	sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $^
 # anything not in $(targets)
 clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
 	zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
 	zImage.miboot zImage.pmac zImage.pseries \
 	zImage.maple simpleImage.* otheros.bld *.dtb
 # clean up files cached by wrapper
 clean-kernel := vmlinux.strip vmlinux.bin
 clean-kernel += $(addsuffix .gz,$(clean-kernel))
 # If not absolute clean-files are relative to $(obj).
 clean-files += $(addprefix $(objtree)/, $(clean-kernel))
 WRAPPER_OBJDIR := /usr/lib/kernel-wrapper
 WRAPPER_DTSDIR := /usr/lib/kernel-wrapper/dts
 WRAPPER_BINDIR := /usr/sbin
 INSTALL := install
 extra-installed		:= $(patsubst $(obj)/%, $(DESTDIR)$(WRAPPER_OBJDIR)/%, $(extra-y))
 hostprogs-installed	:= $(patsubst %, $(DESTDIR)$(WRAPPER_BINDIR)/%, $(hostprogs-y))
 wrapper-installed	:= $(DESTDIR)$(WRAPPER_BINDIR)/wrapper
 dts-installed		:= $(patsubst $(dtstree)/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%, $(wildcard $(dtstree)/*.dts))
 all-installed		:= $(extra-installed) $(hostprogs-installed) $(wrapper-installed) $(dts-installed)
 quiet_cmd_mkdir           = MKDIR   $(patsubst $(INSTALL_HDR_PATH)/%,%,$@)
       cmd_mkdir           = mkdir -p $@
 quiet_cmd_install	  = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,%,$@)
       cmd_install	  = $(INSTALL)  -m0644 $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,$(obj)/%,$@) $@
 quiet_cmd_install_dts	  = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,dts/%,$@)
       cmd_install_dts	  = $(INSTALL)  -m0644 $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,$(srctree)/$(obj)/dts/%,$@) $@
 quiet_cmd_install_exe	  = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
       cmd_install_exe	  = $(INSTALL)  -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(obj)/%,$@) $@
 quiet_cmd_install_wrapper = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
       cmd_install_wrapper = $(INSTALL)  -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(srctree)/$(obj)/%,$@) $@ ;\
 				sed -i $@ -e 's%^object=.*%object=$(WRAPPER_OBJDIR)%' \
 					  -e 's%^objbin=.*%objbin=$(WRAPPER_BINDIR)%' \
 $(DESTDIR)$(WRAPPER_OBJDIR) $(DESTDIR)$(WRAPPER_DTSDIR) $(DESTDIR)$(WRAPPER_BINDIR):
 	$(call cmd,mkdir)
 $(extra-installed)	: $(DESTDIR)$(WRAPPER_OBJDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_OBJDIR)
 	$(call cmd,install)
 $(hostprogs-installed)  : $(DESTDIR)$(WRAPPER_BINDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_BINDIR)
 	$(call cmd,install_exe)
 $(dts-installed)	: $(DESTDIR)$(WRAPPER_DTSDIR)/% : $(srctree)/$(obj)/dts/% | $(DESTDIR)$(WRAPPER_DTSDIR)
 	$(call cmd,install_dts)
 $(wrapper-installed): $(DESTDIR)$(WRAPPER_BINDIR) $(srctree)/$(obj)/wrapper | $(DESTDIR)$(WRAPPER_BINDIR)
 	$(call cmd,install_wrapper)
 $(obj)/bootwrapper_install: $(all-installed)

arch/powerpc/boot/dcr.h

Diff comments View file @ 2a2c74b

 #ifndef _PPC_BOOT_DCR_H_
 #define _PPC_BOOT_DCR_H_
 #define mfdcr(rn) \
 	({	\
 		unsigned long rval; \
 		asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
 		rval; \
 	})
 #define mtdcr(rn, val) \
 	asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
 #define mfdcrx(rn) \
 	({	\
 		unsigned long rval; \
 		asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
 		rval; \
 	})
+#define mtdcrx(rn, val) \
+	({	\
+		asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
+	})
 /* 440GP/440GX SDRAM controller DCRs */
 #define DCRN_SDRAM0_CFGADDR				0x010
 #define DCRN_SDRAM0_CFGDATA				0x011
 #define SDRAM0_READ(offset) ({\
 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
 	mfdcr(DCRN_SDRAM0_CFGDATA); })
 #define SDRAM0_WRITE(offset, data) ({\
 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
 	mtdcr(DCRN_SDRAM0_CFGDATA, data); })
 #define 	SDRAM0_B0CR				0x40
 #define 	SDRAM0_B1CR				0x44
 #define 	SDRAM0_B2CR				0x48
 #define 	SDRAM0_B3CR				0x4c
 static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
 					    SDRAM0_B2CR, SDRAM0_B3CR };
 #define			SDRAM_CONFIG_BANK_ENABLE        0x00000001
 #define			SDRAM_CONFIG_SIZE_MASK          0x000e0000
 #define			SDRAM_CONFIG_BANK_SIZE(reg)	\
 	(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
 /* 440GP External Bus Controller (EBC) */
 #define DCRN_EBC0_CFGADDR				0x012
 #define DCRN_EBC0_CFGDATA				0x013
 #define   EBC_NUM_BANKS					  8
 #define   EBC_B0CR					  0x00
 #define   EBC_B1CR					  0x01
 #define   EBC_B2CR					  0x02
 #define   EBC_B3CR					  0x03
 #define   EBC_B4CR					  0x04
 #define   EBC_B5CR					  0x05
 #define   EBC_B6CR					  0x06
 #define   EBC_B7CR					  0x07
 #define   EBC_BXCR(n)					  (n)
 #define	    EBC_BXCR_BAS				    0xfff00000
 #define	    EBC_BXCR_BS				  	    0x000e0000
 #define	    EBC_BXCR_BANK_SIZE(reg) \
 	(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
 #define	    EBC_BXCR_BU				  	    0x00018000
 #define	      EBC_BXCR_BU_OFF			  	      0x00000000
 #define	      EBC_BXCR_BU_RO			  	      0x00008000
 #define	      EBC_BXCR_BU_WO			  	      0x00010000
 #define	      EBC_BXCR_BU_RW			  	      0x00018000
 #define	    EBC_BXCR_BW				  	    0x00006000
 #define   EBC_B0AP					  0x10
 #define   EBC_B1AP					  0x11
 #define   EBC_B2AP					  0x12
 #define   EBC_B3AP					  0x13
 #define   EBC_B4AP					  0x14
 #define   EBC_B5AP					  0x15
 #define   EBC_B6AP					  0x16
 #define   EBC_B7AP					  0x17
 #define   EBC_BXAP(n)					  (0x10+(n))
 #define   EBC_BEAR					  0x20
 #define   EBC_BESR					  0x21
 #define   EBC_CFG					  0x23
 #define   EBC_CID					  0x24
 /* 440GP Clock, PM, chip control */
 #define DCRN_CPC0_SR					0x0b0
 #define DCRN_CPC0_ER					0x0b1
 #define DCRN_CPC0_FR					0x0b2
 #define DCRN_CPC0_SYS0					0x0e0
 #define	  CPC0_SYS0_TUNE				  0xffc00000
 #define	  CPC0_SYS0_FBDV_MASK				  0x003c0000
 #define	  CPC0_SYS0_FWDVA_MASK				  0x00038000
 #define	  CPC0_SYS0_FWDVB_MASK				  0x00007000
 #define	  CPC0_SYS0_OPDV_MASK				  0x00000c00
 #define	  CPC0_SYS0_EPDV_MASK				  0x00000300
 /* Helper macros to compute the actual clock divider values from the
  * encodings in the CPC0 register */
 #define	  CPC0_SYS0_FBDV(reg) \
 		((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
 #define	  CPC0_SYS0_FWDVA(reg) \
 		(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
 #define	  CPC0_SYS0_FWDVB(reg) \
 		(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
 #define	  CPC0_SYS0_OPDV(reg) \
 		((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
 #define	  CPC0_SYS0_EPDV(reg) \
 		((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
 #define	  CPC0_SYS0_EXTSL				  0x00000080
 #define	  CPC0_SYS0_RW_MASK				  0x00000060
 #define	  CPC0_SYS0_RL					  0x00000010
 #define	  CPC0_SYS0_ZMIISL_MASK				  0x0000000c
 #define	  CPC0_SYS0_BYPASS				  0x00000002
 #define	  CPC0_SYS0_NTO1				  0x00000001
 #define DCRN_CPC0_SYS1					0x0e1
 #define DCRN_CPC0_CUST0					0x0e2
 #define DCRN_CPC0_CUST1					0x0e3
 #define DCRN_CPC0_STRP0					0x0e4
 #define DCRN_CPC0_STRP1					0x0e5
 #define DCRN_CPC0_STRP2					0x0e6
 #define DCRN_CPC0_STRP3					0x0e7
 #define DCRN_CPC0_GPIO					0x0e8
 #define DCRN_CPC0_PLB					0x0e9
 #define DCRN_CPC0_CR1					0x0ea
 #define DCRN_CPC0_CR0					0x0eb
 #define	  CPC0_CR0_SWE					  0x80000000
 #define	  CPC0_CR0_CETE					  0x40000000
 #define	  CPC0_CR0_U1FCS				  0x20000000
 #define	  CPC0_CR0_U0DTE				  0x10000000
 #define	  CPC0_CR0_U0DRE				  0x08000000
 #define	  CPC0_CR0_U0DC					  0x04000000
 #define	  CPC0_CR0_U1DTE				  0x02000000
 #define	  CPC0_CR0_U1DRE				  0x01000000
 #define	  CPC0_CR0_U1DC					  0x00800000
 #define	  CPC0_CR0_U0EC					  0x00400000
 #define	  CPC0_CR0_U1EC					  0x00200000
 #define	  CPC0_CR0_UDIV_MASK				  0x001f0000
 #define	  CPC0_CR0_UDIV(reg) \
 		((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
 #define DCRN_CPC0_MIRQ0					0x0ec
 #define DCRN_CPC0_MIRQ1					0x0ed
 #define DCRN_CPC0_JTAGID				0x0ef
 #define DCRN_MAL0_CFG					0x180
 #define MAL_RESET 0x80000000
 /* 440EP Clock/Power-on Reset regs */
 #define DCRN_CPR0_ADDR	0xc
 #define DCRN_CPR0_DATA	0xd
 #define CPR0_PLLD0	0x60
 #define CPR0_OPBD0	0xc0
 #define CPR0_PERD0	0xe0
 #define CPR0_PRIMBD0	0xa0
 #define CPR0_SCPID	0x120
 #define CPR0_PLLC0	0x40
 /* 405GP Clocking/Power Management/Chip Control regs */
 #define DCRN_CPC0_PLLMR 0xb0
 #define DCRN_405_CPC0_CR0 0xb1
 #define DCRN_405_CPC0_CR1 0xb2
 #define DCRN_405_CPC0_PSR 0xb4
 /* 405EP Clocking/Power Management/Chip Control regs */
 #define DCRN_CPC0_PLLMR0  0xf0
 #define DCRN_CPC0_PLLMR1  0xf4
 #define DCRN_CPC0_UCR     0xf5
 /* 440GX/405EX Clock Control reg */
 #define DCRN_CPR0_CLKUPD				0x020
 #define DCRN_CPR0_PLLC					0x040
 #define DCRN_CPR0_PLLD					0x060
 #define DCRN_CPR0_PRIMAD				0x080
 #define DCRN_CPR0_PRIMBD				0x0a0
 #define DCRN_CPR0_OPBD					0x0c0
 #define DCRN_CPR0_PERD					0x0e0
 #define DCRN_CPR0_MALD					0x100
 #define DCRN_SDR0_CONFIG_ADDR 	0xe
 #define DCRN_SDR0_CONFIG_DATA	0xf
 /* SDR read/write helper macros */
 #define SDR0_READ(offset) ({\
 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
 	mfdcr(DCRN_SDR0_CONFIG_DATA); })
 #define SDR0_WRITE(offset, data) ({\
 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
 	mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
 #define DCRN_SDR0_UART0		0x0120
 #define DCRN_SDR0_UART1		0x0121
 #define DCRN_SDR0_UART2		0x0122
 #define DCRN_SDR0_UART3		0x0123
 /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
 #define DCRN_CPR0_CFGADDR				0xc
 #define DCRN_CPR0_CFGDATA				0xd
 #define CPR0_READ(offset) ({\
 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
 	mfdcr(DCRN_CPR0_CFGDATA); })
 #define CPR0_WRITE(offset, data) ({\
 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
 	mtdcr(DCRN_CPR0_CFGDATA, data); })
 #endif	/* _PPC_BOOT_DCR_H_ */

arch/powerpc/boot/dts/akebono.dts

Diff comments View file @ 2a2c74b

File was created	1	/*
	2	* Device Tree Source for IBM Embedded PPC 476 Platform
	3	*
	4	* Copyright © 2013 Tony Breeds IBM Corporation
	5	* Copyright © 2013 Alistair Popple IBM Corporation
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without
	9	* any warranty of any kind, whether express or implied.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/memreserve/ 0x01f00000 0x00100000; // spin table
	15
	16	/ {
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	model = "ibm,akebono";
	20	compatible = "ibm,akebono", "ibm,476gtr";
	21	dcr-parent = <&{/cpus/cpu@0}>;
	22
	23	aliases {
	24	serial0 = &UART0;
	25	};
	26
	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	cpu@0 {
	32	device_type = "cpu";
	33	model = "PowerPC,476";
	34	reg = <0>;
	35	clock-frequency = <1600000000>; // 1.6 GHz
	36	timebase-frequency = <100000000>; // 100Mhz
	37	i-cache-line-size = <32>;
	38	d-cache-line-size = <32>;
	39	i-cache-size = <32768>;
	40	d-cache-size = <32768>;
	41	dcr-controller;
	42	dcr-access-method = "native";
	43	status = "ok";
	44	};
	45	cpu@1 {
	46	device_type = "cpu";
	47	model = "PowerPC,476";
	48	reg = <1>;
	49	clock-frequency = <1600000000>; // 1.6 GHz
	50	timebase-frequency = <100000000>; // 100Mhz
	51	i-cache-line-size = <32>;
	52	d-cache-line-size = <32>;
	53	i-cache-size = <32768>;
	54	d-cache-size = <32768>;
	55	dcr-controller;
	56	dcr-access-method = "native";
	57	status = "disabled";
	58	enable-method = "spin-table";
	59	cpu-release-addr = <0x0 0x01f00000>;
	60	};
	61	};
	62
	63	memory {
	64	device_type = "memory";
	65	reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
	66	};
	67
	68	MPIC: interrupt-controller {
	69	compatible = "chrp,open-pic";
	70	interrupt-controller;
	71	dcr-reg = <0xffc00000 0x00040000>;
	72	#address-cells = <0>;
	73	#size-cells = <0>;
	74	#interrupt-cells = <2>;
	75	single-cpu-affinity;
	76	};
	77
	78	plb {
	79	compatible = "ibm,plb6";
	80	#address-cells = <2>;
	81	#size-cells = <2>;
	82	ranges;
	83	clock-frequency = <200000000>; // 200Mhz
	84
	85	MAL0: mcmal {
	86	compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
	87	dcr-reg = <0xc0000000 0x062>;
	88	num-tx-chans = <1>;
	89	num-rx-chans = <1>;
	90	#address-cells = <0>;
	91	#size-cells = <0>;
	92	interrupt-parent = <&MPIC>;
	93	interrupts = < /TXEOB/ 77 0x4
	94	/RXEOB/ 78 0x4
	95	/SERR/ 76 0x4
	96	/TXDE/ 79 0x4
	97	/RXDE/ 80 0x4>;
	98	};
	99
	100	SATA0: sata@30000010000 {
	101	compatible = "ibm,476gtr-ahci";
	102	reg = <0x300 0x00010000 0x0 0x10000>;
	103	interrupt-parent = <&MPIC>;
	104	interrupts = <93 2>;
	105	};
	106
	107	EHCI0: ehci@30010000000 {
	108	compatible = "ibm,476gtr-ehci", "generic-ehci";
	109	reg = <0x300 0x10000000 0x0 0x10000>;
	110	interrupt-parent = <&MPIC>;
	111	interrupts = <85 2>;
	112	};
	113
	114	SD0: sd@30000000000 {
	115	compatible = "ibm,476gtr-sdhci", "generic-sdhci";
	116	reg = <0x300 0x00000000 0x0 0x10000>;
	117	interrupts = <91 2>;
	118	interrupt-parent = <&MPIC>;
	119	};
	120
	121	OHCI0: ohci@30010010000 {
	122	compatible = "ibm,476gtr-ohci", "generic-ohci";
	123	reg = <0x300 0x10010000 0x0 0x10000>;
	124	interrupt-parent = <&MPIC>;
	125	interrupts = <89 1>;
	126	};
	127
	128	OHCI1: ohci@30010020000 {
	129	compatible = "ibm,476gtr-ohci", "generic-ohci";
	130	reg = <0x300 0x10020000 0x0 0x10000>;
	131	interrupt-parent = <&MPIC>;
	132	interrupts = <88 1>;
	133	};
	134
	135	POB0: opb {
	136	compatible = "ibm,opb-4xx", "ibm,opb";
	137	#address-cells = <1>;
	138	#size-cells = <1>;
	139	/* Wish there was a nicer way of specifying a full
	140	* 32-bit range
	141	*/
	142	ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
	143	0x80000000 0x0000033f 0x80000000 0x80000000>;
	144	clock-frequency = <100000000>;
	145
	146	RGMII0: emac-rgmii-wol@50004 {
	147	compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
	148	reg = <0x50004 0x00000008>;
	149	has-mdio;
	150	};
	151
	152	EMAC0: ethernet@30000 {
	153	device_type = "network";
	154	compatible = "ibm,emac-476gtr", "ibm,emac4sync";
	155	interrupt-parent = <&EMAC0>;
	156	interrupts = <0x0 0x1>;
	157	#interrupt-cells = <1>;
	158	#address-cells = <0>;
	159	#size-cells = <0>;
	160	interrupt-map = </Status/ 0x0 &MPIC 81 0x4
	161	/Wake/ 0x1 &MPIC 82 0x4>;
	162	reg = <0x30000 0x78>;
	163
	164	/* local-mac-address will normally be added by
	165	* the wrapper. If your device doesn't support
	166	* passing data to the wrapper (in the form
	167	* local-mac-addr=<hwaddr>) then you will need
	168	* to set it manually here. */
	169	//local-mac-address = [000000000000];
	170
	171	mal-device = <&MAL0>;
	172	mal-tx-channel = <0>;
	173	mal-rx-channel = <0>;
	174	cell-index = <0>;
	175	max-frame-size = <9000>;
	176	rx-fifo-size = <4096>;
	177	tx-fifo-size = <2048>;
	178	rx-fifo-size-gige = <16384>;
	179	phy-mode = "rgmii";
	180	phy-map = <0x00000000>;
	181	rgmii-wol-device = <&RGMII0>;
	182	has-inverted-stacr-oc;
	183	has-new-stacr-staopc;
	184	};
	185
	186	UART0: serial@10000 {
	187	device_type = "serial";
	188	compatible = "ns16750", "ns16550";
	189	reg = <0x10000 0x00000008>;
	190	virtual-reg = <0xe8010000>;
	191	clock-frequency = <1851851>;
	192	current-speed = <38400>;
	193	interrupt-parent = <&MPIC>;
	194	interrupts = <39 2>;
	195	};
	196
	197	IIC0: i2c@00000000 {
	198	compatible = "ibm,iic-476gtr", "ibm,iic";
	199	reg = <0x0 0x00000020>;
	200	interrupt-parent = <&MPIC>;
	201	interrupts = <37 2>;
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	rtc@68 {
	205	compatible = "stm,m41t80", "m41st85";
	206	reg = <0x68>;
	207	};
	208	};
	209
	210	IIC1: i2c@00000100 {
	211	compatible = "ibm,iic-476gtr", "ibm,iic";
	212	reg = <0x100 0x00000020>;
	213	interrupt-parent = <&MPIC>;
	214	interrupts = <38 2>;
	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	avr@58 {
	218	compatible = "ibm,akebono-avr";
	219	reg = <0x58>;
	220	};
	221	};
	222
	223	FPGA0: fpga@ebc00000 {
	224	compatible = "ibm,akebono-fpga";
	225	reg = <0xebc00000 0x8>;
	226	};
	227	};
	228
	229	PCIE0: pciex@10100000000 {
	230	device_type = "pci";
	231	#interrupt-cells = <1>;
	232	#size-cells = <2>;
	233	#address-cells = <3>;
	234	compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
	235	primary;
	236	port = <0x0>; /* port number */
	237	reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
	238	0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
	239	dcr-reg = <0xc0 0x20>;
	240
	241	// pci_space < pci_addr > < cpu_addr > < size >
	242	ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
	243	0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
	244
	245	/* Inbound starting at 0 to memsize filled in by zImage */
	246	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
	247
	248	/* This drives busses 0 to 0xf */
	249	bus-range = <0x0 0xf>;
	250
	251	/* Legacy interrupts (note the weird polarity, the bridge seems
	252	* to invert PCIe legacy interrupts).
	253	* We are de-swizzling here because the numbers are actually for
	254	* port of the root complex virtual P2P bridge. But I want
	255	* to avoid putting a node for it in the tree, so the numbers
	256	* below are basically de-swizzled numbers.
	257	* The real slot is on idsel 0, so the swizzling is 1:1
	258	*/
	259	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	260	interrupt-map = <
	261	0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
	262	0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
	263	0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
	264	0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
	265	};
	266
	267	PCIE1: pciex@20100000000 {
	268	device_type = "pci";
	269	#interrupt-cells = <1>;
	270	#size-cells = <2>;
	271	#address-cells = <3>;
	272	compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
	273	primary;
	274	port = <0x1>; /* port number */
	275	reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
	276	0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
	277	dcr-reg = <0x100 0x20>;
	278
	279	// pci_space < pci_addr > < cpu_addr > < size >
	280	ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
	281	0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
	282
	283	/* Inbound starting at 0 to memsize filled in by zImage */
	284	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
	285
	286	/* This drives busses 0 to 0xf */
	287	bus-range = <0x0 0xf>;
	288
	289	/* Legacy interrupts (note the weird polarity, the bridge seems
	290	* to invert PCIe legacy interrupts).
	291	* We are de-swizzling here because the numbers are actually for
	292	* port of the root complex virtual P2P bridge. But I want
	293	* to avoid putting a node for it in the tree, so the numbers
	294	* below are basically de-swizzled numbers.
	295	* The real slot is on idsel 0, so the swizzling is 1:1
	296	*/
	297	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	298	interrupt-map = <
	299	0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
	300	0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
	301	0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
	302	0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
	303	};
	304
	305	PCIE2: pciex@18100000000 {
	306	device_type = "pci";
	307	#interrupt-cells = <1>;
	308	#size-cells = <2>;
	309	#address-cells = <3>;
	310	compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
	311	primary;
	312	port = <0x2>; /* port number */
	313	reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
	314	0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
	315	dcr-reg = <0xe0 0x20>;
	316
	317	// pci_space < pci_addr > < cpu_addr > < size >
	318	ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
	319	0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
	320
	321	/* Inbound starting at 0 to memsize filled in by zImage */
	322	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
	323
	324	/* This drives busses 0 to 0xf */
	325	bus-range = <0x0 0xf>;
	326
	327	/* Legacy interrupts (note the weird polarity, the bridge seems
	328	* to invert PCIe legacy interrupts).
	329	* We are de-swizzling here because the numbers are actually for
	330	* port of the root complex virtual P2P bridge. But I want
	331	* to avoid putting a node for it in the tree, so the numbers
	332	* below are basically de-swizzled numbers.
	333	* The real slot is on idsel 0, so the swizzling is 1:1
	334	*/
	335	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	336	interrupt-map = <
	337	0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
	338	0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
	339	0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
	340	0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
	341	};
	342
	343	PCIE3: pciex@28100000000 {
	344	device_type = "pci";
	345	#interrupt-cells = <1>;
	346	#size-cells = <2>;
	347	#address-cells = <3>;
	348	compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
	349	primary;
	350	port = <0x3>; /* port number */
	351	reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
	352	0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
	353	dcr-reg = <0x120 0x20>;
	354
	355	// pci_space < pci_addr > < cpu_addr > < size >
	356	ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
	357	0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
	358
	359	/* Inbound starting at 0 to memsize filled in by zImage */
	360	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
	361
	362	/* This drives busses 0 to 0xf */
	363	bus-range = <0x0 0xf>;
	364
	365	/* Legacy interrupts (note the weird polarity, the bridge seems
	366	* to invert PCIe legacy interrupts).
	367	* We are de-swizzling here because the numbers are actually for
	368	* port of the root complex virtual P2P bridge. But I want
	369	* to avoid putting a node for it in the tree, so the numbers
	370	* below are basically de-swizzled numbers.
	371	* The real slot is on idsel 0, so the swizzling is 1:1
	372	*/
	373	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	374	interrupt-map = <
	375	0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
	376	0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
	377	0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
	378	0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
	379	};
	380	};
	381
	382	chosen {
	383	linux,stdout-path = &UART0;
	384	};
	385	};
	386

arch/powerpc/boot/treeboot-akebono.c

Diff comments View file @ 2a2c74b

File was created	1	/*
	2	* Copyright © 2013 Tony Breeds IBM Corporation
	3	* Copyright © 2013 Alistair Popple IBM Corporation
	4	*
	5	* Based on earlier code:
	6	* Copyright (C) Paul Mackerras 1997.
	7	*
	8	* Matt Porter <mporter@kernel.crashing.org>
	9	* Copyright 2002-2005 MontaVista Software Inc.
	10	*
	11	* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
	12	* Copyright (c) 2003, 2004 Zultys Technologies
	13	*
	14	* Copyright 2007 David Gibson, IBM Corporation.
	15	* Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
	16	* Copyright © 2011 David Kleikamp IBM Corporation
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
	23	#include <stdarg.h>
	24	#include <stddef.h>
	25	#include "types.h"
	26	#include "elf.h"
	27	#include "string.h"
	28	#include "stdlib.h"
	29	#include "stdio.h"
	30	#include "page.h"
	31	#include "ops.h"
	32	#include "reg.h"
	33	#include "io.h"
	34	#include "dcr.h"
	35	#include "4xx.h"
	36	#include "44x.h"
	37	#include "libfdt.h"
	38
	39	BSS_STACK(4096);
	40
	41	#define SPRN_PIR 0x11E /* Processor Indentification Register */
	42	#define USERDATA_LEN 256 /* Length of userdata passed in by PIBS */
	43	#define MAX_RANKS 0x4
	44	#define DDR3_MR0CF 0x80010011U
	45	#define CCTL0_MCO2 0x8000080FU
	46	#define CCTL0_MCO3 0x80000810U
	47	#define CCTL0_MCO4 0x80000811U
	48	#define CCTL0_MCO5 0x80000812U
	49	#define CCTL0_MCO6 0x80000813U
	50
	51	static unsigned long long ibm_akebono_memsize;
	52	static long long unsigned mac_addr;
	53
	54	static unsigned long long ibm_akebono_detect_memsize(void)
	55	{
	56	u32 reg;
	57	unsigned i;
	58	unsigned long long memsize = 0;
	59
	60	for (i = 0; i < MAX_RANKS; i++) {
	61	reg = mfdcrx(DDR3_MR0CF + i);
	62
	63	if (!(reg & 1))
	64	continue;
	65
	66	reg &= 0x0000f000;
	67	reg >>= 12;
	68	memsize += (0x800000ULL << reg);
	69	}
	70
	71	return memsize;
	72	}
	73
	74	static void ibm_akebono_fixups(void)
	75	{
	76	void *emac;
	77	u32 reg;
	78	void *devp = finddevice("/");
	79	u32 dma_ranges[7];
	80
	81	dt_fixup_memory(0x0ULL, ibm_akebono_memsize);
	82
	83	while ((devp = find_node_by_devtype(devp, "pci"))) {
	84	if (getprop(devp, "dma-ranges", dma_ranges,
	85	sizeof(dma_ranges)) < 0) {
	86	printf("%s: Failed to get dma-ranges\r\n", __func__);
	87	continue;
	88	}
	89
	90	dma_ranges[5] = ibm_akebono_memsize >> 32;
	91	dma_ranges[6] = ibm_akebono_memsize & 0xffffffffUL;
	92
	93	setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges));
	94	}
	95
	96	/* Fixup the SD timeout frequency */
	97	mtdcrx(CCTL0_MCO4, 0x1);
	98
	99	/* Disable SD high-speed mode (which seems to be broken) */
	100	reg = mfdcrx(CCTL0_MCO2) & ~0x2;
	101	mtdcrx(CCTL0_MCO2, reg);
	102
	103	/* Set the MAC address */
	104	emac = finddevice("/plb/opb/ethernet");
	105	if (emac > 0) {
	106	if (mac_addr)
	107	setprop(emac, "local-mac-address",
	108	((u8 *) &mac_addr) + 2 , 6);
	109	}
	110	}
	111
	112	void platform_init(char *userdata)
	113	{
	114	unsigned long end_of_ram, avail_ram;
	115	u32 pir_reg;
	116	int node, size;
	117	const u32 *timebase;
	118	int len, i, userdata_len;
	119	char *end;
	120
	121	userdata[USERDATA_LEN - 1] = '\0';
	122	userdata_len = strlen(userdata);
	123	for (i = 0; i < userdata_len - 15; i++) {
	124	if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) {
	125	if (i > 0 && userdata[i - 1] != ' ') {
	126	/* We've only found a substring ending
	127	* with local-mac-addr so this isn't
	128	* our mac address. */
	129	continue;
	130	}
	131
	132	mac_addr = strtoull(&userdata[i + 15], &end, 16);
	133
	134	/* Remove the "local-mac-addr=<...>" from the kernel
	135	* command line, including the tailing space if
	136	* present. */
	137	if (*end == ' ')
	138	end++;
	139
	140	len = ((int) end) - ((int) &userdata[i]);
	141	memmove(&userdata[i], end,
	142	userdata_len - (len + i) + 1);
	143	break;
	144	}
	145	}
	146
	147	loader_info.cmdline = userdata;
	148	loader_info.cmdline_len = 256;
	149
	150	ibm_akebono_memsize = ibm_akebono_detect_memsize();
	151	if (ibm_akebono_memsize >> 32)
	152	end_of_ram = ~0UL;
	153	else
	154	end_of_ram = ibm_akebono_memsize;
	155	avail_ram = end_of_ram - (unsigned long)_end;
	156
	157	simple_alloc_init(_end, avail_ram, 128, 64);
	158	platform_ops.fixups = ibm_akebono_fixups;
	159	platform_ops.exit = ibm44x_dbcr_reset;
	160	pir_reg = mfspr(SPRN_PIR);
	161
	162	/* Make sure FDT blob is sane */
	163	if (fdt_check_header(_dtb_start) != 0)
	164	fatal("Invalid device tree blob\n");
	165
	166	node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
	167	"cpu", sizeof("cpu"));
	168	if (!node)
	169	fatal("Cannot find cpu node\n");
	170	timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
	171	if (timebase && (size == 4))
	172	timebase_period_ns = 1000000000 / *timebase;
	173
	174	fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
	175	fdt_init(_dtb_start);
	176
	177	serial_console_init();
	178	}
	179

arch/powerpc/boot/wrapper

Diff comments View file @ 2a2c74b

 #!/bin/sh
 # Copyright (C) 2006 Paul Mackerras, IBM Corporation <paulus@samba.org>
 # This program may be used under the terms of version 2 of the GNU
 # General Public License.
 # This script takes a kernel binary and optionally an initrd image
 # and/or a device-tree blob, and creates a bootable zImage for a
 # given platform.
 # Options:
 # -o zImage	specify output file
 # -p platform	specify platform (links in $platform.o)
 # -i initrd	specify initrd file
 # -d devtree	specify device-tree blob
 # -s tree.dts	specify device-tree source file (needs dtc installed)
 # -c		cache $kernel.strip.gz (use if present & newer, else make)
 # -C prefix	specify command prefix for cross-building tools
 #		(strip, objcopy, ld)
 # -D dir	specify directory containing data files used by script
 #		(default ./arch/powerpc/boot)
 # -W dir	specify working directory for temporary files (default .)
 # Stop execution if any command fails
 set -e
 # Allow for verbose output
 if [ "$V" = 1 ]; then
     set -x
 fi
 # defaults
 kernel=
 ofile=zImage
 platform=of
 initrd=
 dtb=
 dts=
 cacheit=
 binary=
 gzip=.gz
 pie=
 format=
 # cross-compilation prefix
 CROSS=
 # mkimage wrapper script
 MKIMAGE=$srctree/scripts/mkuboot.sh
 # directory for object and other files used by this script
 object=arch/powerpc/boot
 objbin=$object
 dtc=scripts/dtc/dtc
 # directory for working files
 tmpdir=.
 usage() {
     echo 'Usage: wrapper [-o output] [-p platform] [-i initrd]' >&2
     echo '       [-d devtree] [-s tree.dts] [-c] [-C cross-prefix]' >&2
     echo '       [-D datadir] [-W workingdir] [--no-gzip] [vmlinux]' >&2
     exit 1
 }
 while [ "$#" -gt 0 ]; do
     case "$1" in
     -o)
 	shift
 	[ "$#" -gt 0 ] || usage
 	ofile="$1"
 	;;
     -p)
 	shift
 	[ "$#" -gt 0 ] || usage
 	platform="$1"
 	;;
     -i)
 	shift
 	[ "$#" -gt 0 ] || usage
 	initrd="$1"
 	;;
     -d)
 	shift
 	[ "$#" -gt 0 ] || usage
 	dtb="$1"
 	;;
     -s)
 	shift
 	[ "$#" -gt 0 ] || usage
 	dts="$1"
 	;;
     -c)
 	cacheit=y
 	;;
     -C)
 	shift
 	[ "$#" -gt 0 ] || usage
 	CROSS="$1"
 	;;
     -D)
 	shift
 	[ "$#" -gt 0 ] || usage
 	object="$1"
 	objbin="$1"
 	;;
     -W)
 	shift
 	[ "$#" -gt 0 ] || usage
 	tmpdir="$1"
 	;;
     --no-gzip)
         gzip=
         ;;
     -?)
 	usage
 	;;
     *)
 	[ -z "$kernel" ] || usage
 	kernel="$1"
 	;;
     esac
     shift
 done
 if [ -n "$dts" ]; then
     if [ ! -r "$dts" -a -r "$object/dts/$dts" ]; then
 	dts="$object/dts/$dts"
     fi
     if [ -z "$dtb" ]; then
 	dtb="$platform.dtb"
     fi
     $dtc -O dtb -o "$dtb" -b 0 "$dts"
 fi
 if [ -z "$kernel" ]; then
     kernel=vmlinux
 fi
 elfformat="`${CROSS}objdump -p "$kernel" | grep 'file format' | awk '{print $4}'`"
 case "$elfformat" in
     elf64-powerpcle)	format=elf64lppc	;;
     elf64-powerpc)	format=elf32ppc	;;
     elf32-powerpc)	format=elf32ppc	;;
 esac
 platformo=$object/"$platform".o
 lds=$object/zImage.lds
 ext=strip
 objflags=-S
 tmp=$tmpdir/zImage.$$.o
 ksection=.kernel:vmlinux.strip
 isection=.kernel:initrd
 link_address='0x400000'
 make_space=y
 case "$platform" in
 of)
     platformo="$object/of.o $object/epapr.o"
     make_space=n
     ;;
 pseries)
     platformo="$object/pseries-head.o $object/of.o $object/epapr.o"
     link_address='0x4000000'
     if [ "$format" != "elf32ppc" ]; then
 	link_address=
 	pie=-pie
     fi
     make_space=n
     ;;
 maple)
     platformo="$object/of.o $object/epapr.o"
     link_address='0x400000'
     make_space=n
     ;;
 pmac|chrp)
     platformo="$object/of.o $object/epapr.o"
     make_space=n
     ;;
 coff)
     platformo="$object/crt0.o $object/of.o $object/epapr.o"
     lds=$object/zImage.coff.lds
     link_address='0x500000'
     make_space=n
     pie=
     ;;
 miboot|uboot*)
     # miboot and U-boot want just the bare bits, not an ELF binary
     ext=bin
     objflags="-O binary"
     tmp="$ofile"
     ksection=image
     isection=initrd
     ;;
 cuboot*)
     binary=y
     gzip=
     case "$platform" in
     *-mpc866ads|*-mpc885ads|*-adder875*|*-ep88xc)
         platformo=$object/cuboot-8xx.o
         ;;
     *5200*|*-motionpro)
         platformo=$object/cuboot-52xx.o
         ;;
     *-pq2fads|*-ep8248e|*-mpc8272*|*-storcenter)
         platformo=$object/cuboot-pq2.o
         ;;
     *-mpc824*)
         platformo=$object/cuboot-824x.o
         ;;
     *-mpc83*|*-asp834x*)
         platformo=$object/cuboot-83xx.o
         ;;
     *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*)
         platformo=$object/cuboot-85xx-cpm2.o
         ;;
     *-mpc85*|*-tqm85*|*-sbc85*)
         platformo=$object/cuboot-85xx.o
         ;;
     *-amigaone)
         link_address='0x800000'
         ;;
     esac
     ;;
 ps3)
     platformo="$object/ps3-head.o $object/ps3-hvcall.o $object/ps3.o"
     lds=$object/zImage.ps3.lds
     gzip=
     ext=bin
     objflags="-O binary --set-section-flags=.bss=contents,alloc,load,data"
     ksection=.kernel:vmlinux.bin
     isection=.kernel:initrd
     link_address=''
     make_space=n
     pie=
     ;;
 ep88xc|ep405|ep8248e)
     platformo="$object/fixed-head.o $object/$platform.o"
     binary=y
     ;;
 adder875-redboot)
     platformo="$object/fixed-head.o $object/redboot-8xx.o"
     binary=y
     ;;
 simpleboot-virtex405-*)
     platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
     binary=y
     ;;
 simpleboot-virtex440-*)
     platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
     binary=y
     ;;
 simpleboot-*)
     platformo="$object/fixed-head.o $object/simpleboot.o"
     binary=y
     ;;
 asp834x-redboot)
     platformo="$object/fixed-head.o $object/redboot-83xx.o"
     binary=y
     ;;
 xpedite52*)
     link_address='0x1400000'
     platformo=$object/cuboot-85xx.o
     ;;
 gamecube|wii)
     link_address='0x600000'
     platformo="$object/$platform-head.o $object/$platform.o"
     ;;
 treeboot-currituck)
     link_address='0x1000000'
     ;;
+treeboot-akebono)
+    link_address='0x1000000'
+    ;;
 treeboot-iss4xx-mpic)
     platformo="$object/treeboot-iss4xx.o"
     ;;
 epapr)
     platformo="$object/epapr.o $object/epapr-wrapper.o"
     link_address='0x20000000'
     pie=-pie
     ;;
 mvme5100)
     platformo="$object/fixed-head.o $object/mvme5100.o"
     binary=y
     ;;
 esac
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
 if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
     ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
     strip_size=$(stat -c %s $vmz.$$)
     if [ -n "$gzip" ]; then
         gzip -n -f -9 "$vmz.$$"
     fi
     if [ -n "$cacheit" ]; then
 	mv -f "$vmz.$$$gzip" "$vmz$gzip"
     else
 	vmz="$vmz.$$"
     fi
 else
     # Calculate the vmlinux.strip size
     ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
     strip_size=$(stat -c %s $vmz.$$)
     rm -f $vmz.$$
 fi
 if [ "$make_space" = "y" ]; then
 	# Round the size to next higher MB limit
 	round_size=$(((strip_size + 0xfffff) & 0xfff00000))
 	round_size=0x$(printf "%x" $round_size)
 	link_addr=$(printf "%d" $link_address)
 	if [ $link_addr -lt $strip_size ]; then
 	    echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
 			"overlaps the address of the wrapper($link_address)"
 	    echo "INFO: Fixing the link_address of wrapper to ($round_size)"
 	    link_address=$round_size
 	fi
 fi
 vmz="$vmz$gzip"
 # Extract kernel version information, some platforms want to include
 # it in the image header
 version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \
     cut -d' ' -f3`
 if [ -n "$version" ]; then
     uboot_version="-n Linux-$version"
 fi
 # physical offset of kernel image
 membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
 case "$platform" in
 uboot)
     rm -f "$ofile"
     ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
 	$uboot_version -d "$vmz" "$ofile"
     if [ -z "$cacheit" ]; then
 	rm -f "$vmz"
     fi
     exit 0
     ;;
 uboot-obs600)
     rm -f "$ofile"
     # obs600 wants a multi image with an initrd, so we need to put a fake
     # one in even when building a "normal" image.
     if [ -n "$initrd" ]; then
 	real_rd="$initrd"
     else
 	real_rd=`mktemp`
 	echo "\0" >>"$real_rd"
     fi
     ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
 	$uboot_version -d "$vmz":"$real_rd":"$dtb" "$ofile"
     if [ -z "$initrd" ]; then
 	rm -f "$real_rd"
     fi
     if [ -z "$cacheit" ]; then
 	rm -f "$vmz"
     fi
     exit 0
     ;;
 esac
 addsec() {
     ${CROSS}objcopy $4 $1 \
 	--add-section=$3="$2" \
 	--set-section-flags=$3=contents,alloc,load,readonly,data
 }
 addsec $tmp "$vmz" $ksection $object/empty.o
 if [ -z "$cacheit" ]; then
     rm -f "$vmz"
 fi
 if [ -n "$initrd" ]; then
     addsec $tmp "$initrd" $isection
 fi
 if [ -n "$dtb" ]; then
     addsec $tmp "$dtb" .kernel:dtb
     if [ -n "$dts" ]; then
 	rm $dtb
     fi
 fi
 if [ "$platform" != "miboot" ]; then
     if [ -n "$link_address" ] ; then
         text_start="-Ttext $link_address"
     fi
     ${CROSS}ld -m $format -T $lds $text_start $pie -o "$ofile" \
 	$platformo $tmp $object/wrapper.a
     rm $tmp
 fi
 # Some platforms need the zImage's entry point and base address
 base=0x`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
 entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | cut -d' ' -f3`
 if [ -n "$binary" ]; then
     mv "$ofile" "$ofile".elf
     ${CROSS}objcopy -O binary "$ofile".elf "$ofile"
 fi
 # post-processing needed for some platforms
 case "$platform" in
 pseries|chrp|maple)
     $objbin/addnote "$ofile"
     ;;
 coff)
     ${CROSS}objcopy -O aixcoff-rs6000 --set-start "$entry" "$ofile"
     $objbin/hack-coff "$ofile"
     ;;
 cuboot*)
     gzip -n -f -9 "$ofile"
     ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
             $uboot_version -d "$ofile".gz "$ofile"
     ;;
 treeboot*)
     mv "$ofile" "$ofile.elf"
     $objbin/mktree "$ofile.elf" "$ofile" "$base" "$entry"
     if [ -z "$cacheit" ]; then
 	rm -f "$ofile.elf"
     fi
     exit 0
     ;;
 ps3)
     # The ps3's loader supports loading a gzipped binary image from flash
     # rom to ram addr zero. The loader then enters the system reset
     # vector at addr 0x100.  A bootwrapper overlay is used to arrange for
     # a binary image of the kernel to be at addr zero, and yet have a
     # suitable bootwrapper entry at 0x100.  To construct the final rom
     # image 512 bytes from offset 0x100 is copied to the bootwrapper
     # place holder at symbol __system_reset_kernel.  The 512 bytes of the
     # bootwrapper entry code at symbol __system_reset_overlay is then
     # copied to offset 0x100.  At runtime the bootwrapper program copies
     # the data at __system_reset_kernel back to addr 0x100.
     system_reset_overlay=0x`${CROSS}nm "$ofile" \
         | grep ' __system_reset_overlay$'       \
         | cut -d' ' -f1`
     system_reset_overlay=`printf "%d" $system_reset_overlay`
     system_reset_kernel=0x`${CROSS}nm "$ofile" \
         | grep ' __system_reset_kernel$'       \
         | cut -d' ' -f1`
     system_reset_kernel=`printf "%d" $system_reset_kernel`
     overlay_dest="256"
     overlay_size="512"
     ${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
     dd if="$ofile.bin" of="$ofile.bin" conv=notrunc   \
         skip=$overlay_dest seek=$system_reset_kernel  \
         count=$overlay_size bs=1
     dd if="$ofile.bin" of="$ofile.bin" conv=notrunc   \
         skip=$system_reset_overlay seek=$overlay_dest \
         count=$overlay_size bs=1
     odir="$(dirname "$ofile.bin")"
     rm -f "$odir/otheros.bld"
     gzip -n --force -9 --stdout "$ofile.bin" > "$odir/otheros.bld"
     ;;
 esac

arch/powerpc/configs/44x/akebono_defconfig

Diff comments View file @ 2a2c74b

File was created	1	CONFIG_44x=y
	2	CONFIG_SMP=y
	3	CONFIG_SYSVIPC=y
	4	CONFIG_POSIX_MQUEUE=y
	5	CONFIG_LOG_BUF_SHIFT=14
	6	CONFIG_BLK_DEV_INITRD=y
	7	CONFIG_RD_BZIP2=y
	8	CONFIG_RD_LZMA=y
	9	CONFIG_RD_XZ=y
	10	CONFIG_EXPERT=y
	11	CONFIG_KALLSYMS_ALL=y
	12	# CONFIG_SLUB_CPU_PARTIAL is not set
	13	CONFIG_PROFILING=y
	14	CONFIG_OPROFILE=y
	15	CONFIG_MODULES=y
	16	CONFIG_MODULE_UNLOAD=y
	17	# CONFIG_BLK_DEV_BSG is not set
	18	# CONFIG_POWERNV_MSI is not set
	19	CONFIG_PPC_47x=y
	20	# CONFIG_EBONY is not set
	21	CONFIG_AKEBONO=y
	22	CONFIG_HIGHMEM=y
	23	CONFIG_HZ_100=y
	24	CONFIG_IRQ_ALL_CPUS=y
	25	# CONFIG_COMPACTION is not set
	26	CONFIG_CMDLINE_BOOL=y
	27	CONFIG_CMDLINE=""
	28	# CONFIG_SUSPEND is not set
	29	CONFIG_PCI_MSI=y
	30	CONFIG_NET=y
	31	CONFIG_PACKET=y
	32	CONFIG_UNIX=y
	33	CONFIG_INET=y
	34	CONFIG_IP_PNP=y
	35	CONFIG_IP_PNP_DHCP=y
	36	CONFIG_IP_PNP_BOOTP=y
	37	# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
	38	# CONFIG_INET_XFRM_MODE_TUNNEL is not set
	39	# CONFIG_INET_XFRM_MODE_BEET is not set
	40	# CONFIG_INET_LRO is not set
	41	# CONFIG_IPV6 is not set
	42	CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
	43	CONFIG_DEVTMPFS=y
	44	CONFIG_DEVTMPFS_MOUNT=y
	45	CONFIG_CONNECTOR=y
	46	CONFIG_MTD=y
	47	CONFIG_MTD_BLOCK=y
	48	CONFIG_MTD_JEDECPROBE=y
	49	CONFIG_MTD_CFI_AMDSTD=y
	50	CONFIG_MTD_PHYSMAP_OF=y
	51	CONFIG_PROC_DEVICETREE=y
	52	CONFIG_BLK_DEV_RAM=y
	53	CONFIG_BLK_DEV_RAM_SIZE=35000
	54	# CONFIG_SCSI_PROC_FS is not set
	55	CONFIG_BLK_DEV_SD=y
	56	# CONFIG_SCSI_LOWLEVEL is not set
	57	# CONFIG_SATA_PMP is not set
	58	# CONFIG_ATA_SFF is not set
	59	# CONFIG_NET_VENDOR_3COM is not set
	60	# CONFIG_NET_VENDOR_ADAPTEC is not set
	61	# CONFIG_NET_VENDOR_ALTEON is not set
	62	# CONFIG_NET_VENDOR_AMD is not set
	63	# CONFIG_NET_VENDOR_ARC is not set
	64	# CONFIG_NET_VENDOR_ATHEROS is not set
	65	# CONFIG_NET_CADENCE is not set
	66	# CONFIG_NET_VENDOR_BROADCOM is not set
	67	# CONFIG_NET_VENDOR_BROCADE is not set
	68	# CONFIG_NET_VENDOR_CHELSIO is not set
	69	# CONFIG_NET_VENDOR_CISCO is not set
	70	# CONFIG_NET_VENDOR_DEC is not set
	71	# CONFIG_NET_VENDOR_DLINK is not set
	72	# CONFIG_NET_VENDOR_EMULEX is not set
	73	# CONFIG_NET_VENDOR_EXAR is not set
	74	# CONFIG_NET_VENDOR_HP is not set
	75	CONFIG_IBM_EMAC=y
	76	# CONFIG_NET_VENDOR_MARVELL is not set
	77	# CONFIG_NET_VENDOR_MELLANOX is not set
	78	# CONFIG_NET_VENDOR_MICREL is not set
	79	# CONFIG_NET_VENDOR_MYRI is not set
	80	# CONFIG_NET_VENDOR_NATSEMI is not set
	81	# CONFIG_NET_VENDOR_NVIDIA is not set
	82	# CONFIG_NET_VENDOR_OKI is not set
	83	# CONFIG_NET_VENDOR_QLOGIC is not set
	84	# CONFIG_NET_VENDOR_REALTEK is not set
	85	# CONFIG_NET_VENDOR_RDC is not set
	86	# CONFIG_NET_VENDOR_SEEQ is not set
	87	# CONFIG_NET_VENDOR_SILAN is not set
	88	# CONFIG_NET_VENDOR_SIS is not set
	89	# CONFIG_NET_VENDOR_SMSC is not set
	90	# CONFIG_NET_VENDOR_STMICRO is not set
	91	# CONFIG_NET_VENDOR_SUN is not set
	92	# CONFIG_NET_VENDOR_TEHUTI is not set
	93	# CONFIG_NET_VENDOR_TI is not set
	94	# CONFIG_NET_VENDOR_VIA is not set
	95	# CONFIG_NET_VENDOR_WIZNET is not set
	96	# CONFIG_NET_VENDOR_XILINX is not set
	97	# CONFIG_KEYBOARD_ATKBD is not set
	98	# CONFIG_MOUSE_PS2 is not set
	99	# CONFIG_SERIO is not set
	100	# CONFIG_VT is not set
	101	CONFIG_SERIAL_8250=y
	102	# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
	103	CONFIG_SERIAL_8250_CONSOLE=y
	104	CONFIG_SERIAL_8250_EXTENDED=y
	105	CONFIG_SERIAL_8250_SHARE_IRQ=y
	106	CONFIG_SERIAL_OF_PLATFORM=y
	107	# CONFIG_HW_RANDOM is not set
	108	CONFIG_I2C_CHARDEV=y
	109	# CONFIG_HWMON is not set
	110	CONFIG_THERMAL=y
	111	# CONFIG_USB_DEFAULT_PERSIST is not set
	112	CONFIG_USB_EHCI_HCD=y
	113	CONFIG_USB_OHCI_HCD=y
	114	# CONFIG_USB_OHCI_HCD_PCI is not set
	115	CONFIG_USB_STORAGE=y
	116	CONFIG_MMC=y
	117	CONFIG_RTC_CLASS=y
	118	CONFIG_RTC_DRV_M41T80=y
	119	CONFIG_EXT2_FS=y
	120	CONFIG_EXT3_FS=y
	121	# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
	122	CONFIG_EXT3_FS_POSIX_ACL=y
	123	CONFIG_EXT3_FS_SECURITY=y
	124	# CONFIG_DNOTIFY is not set
	125	# CONFIG_INOTIFY_USER is not set
	126	CONFIG_VFAT_FS=y
	127	CONFIG_PROC_KCORE=y
	128	CONFIG_TMPFS=y
	129	CONFIG_CRAMFS=y
	130	# CONFIG_NETWORK_FILESYSTEMS is not set
	131	CONFIG_NLS_DEFAULT="n"
	132	CONFIG_NLS_CODEPAGE_437=y
	133	CONFIG_NLS_ISO8859_1=y
	134	CONFIG_DEBUG_INFO=y
	135	CONFIG_DEBUG_FS=y
	136	CONFIG_MAGIC_SYSRQ=y
	137	CONFIG_DETECT_HUNG_TASK=y
	138	CONFIG_XMON=y
	139	CONFIG_XMON_DEFAULT=y
	140	CONFIG_PPC_EARLY_DEBUG=y
	141	CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0x00010000
	142	CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x33f
	143	CONFIG_CRYPTO_PCBC=y
	144	CONFIG_CRYPTO_MD5=y
	145	CONFIG_CRYPTO_SHA1_PPC=y
	146	CONFIG_CRYPTO_DES=y
	147	# CONFIG_CRYPTO_ANSI_CPRNG is not set
	148	# CONFIG_CRYPTO_HW is not set
	149

arch/powerpc/platforms/44x/Kconfig

Diff comments View file @ 2a2c74b

 config PPC_47x
 	bool "Support for 47x variant"
 	depends on 44x
 	default n
 	select MPIC
 	help
 	  This option enables support for the 47x family of processors and is
 	  not currently compatible with other 44x or 46x varients
 config BAMBOO
 	bool "Bamboo"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440EP
 	select PCI
 	help
 	  This option enables support for the IBM PPC440EP evaluation board.
 config BLUESTONE
 	bool "Bluestone"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select APM821xx
 	select PCI_MSI
 	select PPC4xx_MSI
 	select PPC4xx_PCI_EXPRESS
 	select IBM_EMAC_RGMII
 	help
 	  This option enables support for the APM APM821xx Evaluation board.
 config EBONY
 	bool "Ebony"
 	depends on 44x
 	default y
 	select 440GP
 	select PCI
 	select OF_RTC
 	help
 	  This option enables support for the IBM PPC440GP evaluation board.
 config SAM440EP
         bool "Sam440ep"
 	depends on 44x
         default n
         select 440EP
         select PCI
         help
           This option enables support for the ACube Sam440ep board.
 config SEQUOIA
 	bool "Sequoia"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440EPX
 	help
 	  This option enables support for the AMCC PPC440EPX evaluation board.
 config TAISHAN
 	bool "Taishan"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440GX
 	select PCI
 	help
 	  This option enables support for the AMCC PPC440GX "Taishan"
 	  evaluation board.
 config KATMAI
 	bool "Katmai"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440SPe
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	select PCI_MSI
 	select PPC4xx_MSI
 	help
 	  This option enables support for the AMCC PPC440SPe evaluation board.
 config RAINIER
 	bool "Rainier"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440GRX
 	select PCI
 	help
 	  This option enables support for the AMCC PPC440GRX evaluation board.
 config WARP
 	bool "PIKA Warp"
 	depends on 44x
 	default n
 	select 440EP
 	help
 	  This option enables support for the PIKA Warp(tm) Appliance. The Warp
 	  is a small computer replacement with up to 9 ports of FXO/FXS plus VOIP
 	  stations and trunks.
 	  See http://www.pikatechnologies.com/ and follow the "PIKA for Computer
 	  Telephony Developers" link for more information.
 config ARCHES
 	bool "Arches"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 460EX # Odd since it uses 460GT but the effects are the same
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	help
 	  This option enables support for the AMCC Dual PPC460GT evaluation board.
 config CANYONLANDS
 	bool "Canyonlands"
 	depends on 44x
 	default n
 	select 460EX
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	select PCI_MSI
 	select PPC4xx_MSI
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII
 	help
 	  This option enables support for the AMCC PPC460EX evaluation board.
 config GLACIER
 	bool "Glacier"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 460EX # Odd since it uses 460GT but the effects are the same
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII
 	help
 	  This option enables support for the AMCC PPC460GT evaluation board.
 config REDWOOD
 	bool "Redwood"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 460SX
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	select PCI_MSI
 	select PPC4xx_MSI
 	help
 	  This option enables support for the AMCC PPC460SX Redwood board.
 config EIGER
 	bool "Eiger"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 460SX
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	select IBM_EMAC_RGMII
 	help
 	  This option enables support for the AMCC PPC460SX evaluation board.
 config YOSEMITE
 	bool "Yosemite"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440EP
 	select PCI
 	help
 	  This option enables support for the AMCC PPC440EP evaluation board.
 config ISS4xx
 	bool "ISS 4xx Simulator"
 	depends on (44x || 40x)
 	default n
 	select 405GP if 40x
 	select 440GP if 44x && !PPC_47x
 	select PPC_FPU
 	select OF_RTC
 	help
 	  This option enables support for the IBM ISS simulation environment
 config CURRITUCK
 	bool "IBM Currituck (476fpe) Support"
 	depends on PPC_47x
 	default n
 	select SWIOTLB
 	select 476FPE
 	select PPC4xx_PCI_EXPRESS
 	help
 	  This option enables support for the IBM Currituck (476fpe) evaluation board
+config AKEBONO
+	bool "IBM Akebono (476gtr) Support"
+	depends on PPC_47x
+	default n
+	select SWIOTLB
+	select 476FPE
+	select PPC4xx_PCI_EXPRESS
+	select I2C
+	select I2C_IBM_IIC
+	select NETDEVICES
+	select ETHERNET
+	select NET_VENDOR_IBM
+	select IBM_EMAC_EMAC4
+	select IBM_EMAC_RGMII_WOL
+	select USB
+	select USB_OHCI_HCD_PLATFORM
+	select USB_EHCI_HCD_PLATFORM
+	select MMC_SDHCI
+	select MMC_SDHCI_PLTFM
+	select MMC_SDHCI_OF_476GTR
+	select ATA
+	select SATA_AHCI_PLATFORM
+	help
+	  This option enables support for the IBM Akebono (476gtr) evaluation board
 config ICON
 	bool "Icon"
 	depends on 44x
 	default n
 	select PPC44x_SIMPLE
 	select 440SPe
 	select PCI
 	select PPC4xx_PCI_EXPRESS
 	help
 	  This option enables support for the AMCC PPC440SPe evaluation board.
 config XILINX_VIRTEX440_GENERIC_BOARD
 	bool "Generic Xilinx Virtex 5 FXT board support"
 	depends on 44x
 	default n
 	select XILINX_VIRTEX_5_FXT
 	help
 	  This option enables generic support for Xilinx Virtex based boards
 	  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
 	  The generic virtex board support matches any device tree which
 	  specifies 'xlnx,virtex440' in its compatible field.  This includes
 	  the Xilinx ML5xx reference designs using the powerpc core.
 	  Most Virtex 5 designs should use this unless it needs to do some
 	  special configuration at board probe time.
 config XILINX_ML510
 	bool "Xilinx ML510 extra support"
 	depends on XILINX_VIRTEX440_GENERIC_BOARD
 	select PPC_PCI_CHOICE
 	select XILINX_PCI if PCI
 	select PPC_INDIRECT_PCI if PCI
 	select PPC_I8259 if PCI
 	help
 	  This option enables extra support for features on the Xilinx ML510
 	  board.  The ML510 has a PCI bus with ALI south bridge.
 config PPC44x_SIMPLE
 	bool "Simple PowerPC 44x board support"
 	depends on 44x
 	default n
 	help
 	  This option enables the simple PowerPC 44x platform support.
 config PPC4xx_GPIO
 	bool "PPC4xx GPIO support"
 	depends on 44x
 	select ARCH_REQUIRE_GPIOLIB
 	help
 	  Enable gpiolib support for ppc440 based boards
 config PPC4xx_OCM
 	bool "PPC4xx On Chip Memory (OCM) support"
 	depends on 4xx
 	select PPC_LIB_RHEAP
 	help
 	  Enable OCM support for PowerPC 4xx platforms with on chip memory,
 	  OCM provides the fast place for memory access to improve performance.
 # 44x specific CPU modules, selected based on the board above.
 config 440EP
 	bool
 	select PPC_FPU
 	select IBM440EP_ERR42
 	select IBM_EMAC_ZMII
 config 440EPX
 	bool
 	select PPC_FPU
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII
 	select USB_EHCI_BIG_ENDIAN_MMIO
 	select USB_EHCI_BIG_ENDIAN_DESC
 config 440GRX
 	bool
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII
 config 440GP
 	bool
 	select IBM_EMAC_ZMII
 config 440GX
 	bool
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII #test only
 	select IBM_EMAC_TAH  #test only
 config 440SP
 	bool
 config 440SPe
 	bool
 	select IBM_EMAC_EMAC4
 config 460EX
 	bool
 	select PPC_FPU
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_TAH
 config 460SX
 	bool
 	select PPC_FPU
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_RGMII
 	select IBM_EMAC_ZMII
 	select IBM_EMAC_TAH
 config 476FPE
 	bool
 	select PPC_FPU
 config APM821xx
 	bool
 	select PPC_FPU
 	select IBM_EMAC_EMAC4
 	select IBM_EMAC_TAH
 # 44x errata/workaround config symbols, selected by the CPU models above
 config IBM440EP_ERR42
 	bool
 # Xilinx specific config options.
 config XILINX_VIRTEX
 	bool
 	select DEFAULT_UIMAGE
 # Xilinx Virtex 5 FXT FPGA architecture, selected by a Xilinx board above
 config XILINX_VIRTEX_5_FXT
 	bool
 	select XILINX_VIRTEX

arch/powerpc/platforms/44x/Makefile

Diff comments View file @ 2a2c74b

 obj-$(CONFIG_44x)	+= misc_44x.o
 ifneq ($(CONFIG_PPC4xx_CPM),y)
 obj-$(CONFIG_44x)	+= idle.o
 endif
 obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
 obj-$(CONFIG_EBONY)	+= ebony.o
 obj-$(CONFIG_SAM440EP) 	+= sam440ep.o
 obj-$(CONFIG_WARP)	+= warp.o
 obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
 obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
 obj-$(CONFIG_ISS4xx)	+= iss4xx.o
 obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
 obj-$(CONFIG_CURRITUCK)	+= ppc476.o
+obj-$(CONFIG_AKEBONO)	+= ppc476.o

arch/powerpc/platforms/44x/ppc476.c

Diff comments View file @ 2a2c74b

 /*
  * PowerPC 476FPE board specific routines
  *
- * Copyright © 2011 Tony Breeds IBM Corporation
+ * Copyright © 2013 Tony Breeds IBM Corporation
+ * Copyright © 2013 Alistair Popple IBM Corporation
  *
  * Based on earlier code:
  *    Matt Porter <mporter@kernel.crashing.org>
  *    Copyright 2002-2005 MontaVista Software Inc.
  *
  *    Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  *    Copyright (c) 2003-2005 Zultys Technologies
  *
  *    Rewritten and ported to the merged powerpc tree:
  *    Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
  *    Copyright © 2011 David Kliekamp IBM Corporation
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/rtc.h>
 #include <asm/machdep.h>
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/ppc4xx.h>
 #include <asm/mpic.h>
 #include <asm/mmu.h>
 #include <linux/pci.h>
+#include <linux/i2c.h>
 static struct of_device_id ppc47x_of_bus[] __initdata = {
 	{ .compatible = "ibm,plb4", },
 	{ .compatible = "ibm,plb6", },
 	{ .compatible = "ibm,opb", },
 	{ .compatible = "ibm,ebc", },
 	{},
 };
 /* The EEPROM is missing and the default values are bogus.  This forces USB in
  * to EHCI mode */
 static void quirk_ppc_currituck_usb_fixup(struct pci_dev *dev)
 {
 	if (of_machine_is_compatible("ibm,currituck")) {
 		pci_write_config_dword(dev, 0xe0, 0x0114231f);
 		pci_write_config_dword(dev, 0xe4, 0x00006c40);
 	}
 }
 DECLARE_PCI_FIXUP_HEADER(0x1033, 0x0035, quirk_ppc_currituck_usb_fixup);
+/* Akebono has an AVR microcontroller attached to the I2C bus
+ * which is used to power off/reset the system. */
+/* AVR I2C Commands */
+#define AVR_PWRCTL_CMD (0x26)
+/* Flags for the power control I2C commands */
+#define AVR_PWRCTL_PWROFF (0x01)
+#define AVR_PWRCTL_RESET (0x02)
+static struct i2c_client *avr_i2c_client;
+static void avr_halt_system(int pwrctl_flags)
+{
+	/* Request the AVR to reset the system */
+	i2c_smbus_write_byte_data(avr_i2c_client,
+				  AVR_PWRCTL_CMD, pwrctl_flags);
+	/* Wait for system to be reset */
+	while (1)
+		;
+}
+static void avr_power_off_system(void)
+{
+	avr_halt_system(AVR_PWRCTL_PWROFF);
+}
+static void avr_reset_system(char *cmd)
+{
+	avr_halt_system(AVR_PWRCTL_RESET);
+}
+static int avr_probe(struct i2c_client *client,
+			    const struct i2c_device_id *id)
+{
+	avr_i2c_client = client;
+	ppc_md.restart = avr_reset_system;
+	ppc_md.power_off = avr_power_off_system;
+	return 0;
+}
+static const struct i2c_device_id avr_id[] = {
+	{ "akebono-avr", 0 },
+	{ }
+};
+static struct i2c_driver avr_driver = {
+	.driver = {
+		.name = "akebono-avr",
+	},
+	.probe = avr_probe,
+	.id_table = avr_id,
+};
 static int __init ppc47x_device_probe(void)
 {
+	i2c_add_driver(&avr_driver);
 	of_platform_bus_probe(NULL, ppc47x_of_bus, NULL);
 	return 0;
 }
 machine_device_initcall(ppc47x, ppc47x_device_probe);
-/* We can have either UICs or MPICs */
 static void __init ppc47x_init_irq(void)
 {
 	struct device_node *np;
 	/* Find top level interrupt controller */
 	for_each_node_with_property(np, "interrupt-controller") {
 		if (of_get_property(np, "interrupts", NULL) == NULL)
 			break;
 	}
 	if (np == NULL)
 		panic("Can't find top level interrupt controller");
 	/* Check type and do appropriate initialization */
 	if (of_device_is_compatible(np, "chrp,open-pic")) {
 		/* The MPIC driver will get everything it needs from the
 		 * device-tree, just pass 0 to all arguments
 		 */
 		struct mpic *mpic =
 			mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " MPIC     ");
 		BUG_ON(mpic == NULL);
 		mpic_init(mpic);
 		ppc_md.get_irq = mpic_get_irq;
 	} else
 		panic("Unrecognized top level interrupt controller");
 }
 #ifdef CONFIG_SMP
 static void smp_ppc47x_setup_cpu(int cpu)
 {
 	mpic_setup_this_cpu();
 }
 static int smp_ppc47x_kick_cpu(int cpu)
 {
 	struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
 	const u64 *spin_table_addr_prop;
 	u32 *spin_table;
 	extern void start_secondary_47x(void);
 	BUG_ON(cpunode == NULL);
 	/* Assume spin table. We could test for the enable-method in
 	 * the device-tree but currently there's little point as it's
 	 * our only supported method
 	 */
 	spin_table_addr_prop =
 		of_get_property(cpunode, "cpu-release-addr", NULL);
 	if (spin_table_addr_prop == NULL) {
 		pr_err("CPU%d: Can't start, missing cpu-release-addr !\n",
 		       cpu);
 		return 1;
 	}
 	/* Assume it's mapped as part of the linear mapping. This is a bit
 	 * fishy but will work fine for now
 	 *
 	 * XXX: Is there any reason to assume differently?
 	 */
 	spin_table = (u32 *)__va(*spin_table_addr_prop);
 	pr_debug("CPU%d: Spin table mapped at %p\n", cpu, spin_table);
 	spin_table[3] = cpu;
 	smp_wmb();
 	spin_table[1] = __pa(start_secondary_47x);
 	mb();
 	return 0;
 }
 static struct smp_ops_t ppc47x_smp_ops = {
 	.probe		= smp_mpic_probe,
 	.message_pass	= smp_mpic_message_pass,
 	.setup_cpu	= smp_ppc47x_setup_cpu,
 	.kick_cpu	= smp_ppc47x_kick_cpu,
 	.give_timebase	= smp_generic_give_timebase,
 	.take_timebase	= smp_generic_take_timebase,
 };
 static void __init ppc47x_smp_init(void)
 {
 	if (mmu_has_feature(MMU_FTR_TYPE_47x))
 		smp_ops = &ppc47x_smp_ops;
 }
 #else /* CONFIG_SMP */
 static void __init ppc47x_smp_init(void) { }
 #endif /* CONFIG_SMP */
 static void __init ppc47x_setup_arch(void)
 {
 	/* No need to check the DMA config as we /know/ our windows are all of
 	 * RAM.  Lets hope that doesn't change */
 	swiotlb_detect_4g();
 	ppc47x_smp_init();
 }
-/*
- * Called very early, MMU is off, device-tree isn't unflattened
- */
-static int __init ppc47x_probe(void)
-{
-	unsigned long root = of_get_flat_dt_root();
-	if (!of_flat_dt_is_compatible(root, "ibm,currituck"))
-		return 0;
-	return 1;
-}
 static int board_rev = -1;
 static int __init ppc47x_get_board_rev(void)
 {
-	u8 fpga_reg0;
+	int reg;
-	void *fpga;
+	u8 *fpga;
-	struct device_node *np;
+	struct device_node *np = NULL;
-	np = of_find_compatible_node(NULL, NULL, "ibm,currituck-fpga");
+	if (of_machine_is_compatible("ibm,currituck")) {
+		np = of_find_compatible_node(NULL, NULL, "ibm,currituck-fpga");
+		reg = 0;
+	} else if (of_machine_is_compatible("ibm,akebono")) {
+		np = of_find_compatible_node(NULL, NULL, "ibm,akebono-fpga");
+		reg = 2;
+	}
 	if (!np)
 		goto fail;
-	fpga = of_iomap(np, 0);
+	fpga = (u8 *) of_iomap(np, 0);
 	of_node_put(np);
 	if (!fpga)
 		goto fail;
-	fpga_reg0 = ioread8(fpga);
+	board_rev = ioread8(fpga + reg) & 0x03;
-	board_rev = fpga_reg0 & 0x03;
 	pr_info("%s: Found board revision %d\n", __func__, board_rev);
 	iounmap(fpga);
 	return 0;
 fail:
 	pr_info("%s: Unable to find board revision\n", __func__);
 	return 0;
 }
 machine_arch_initcall(ppc47x, ppc47x_get_board_rev);
 /* Use USB controller should have been hardware swizzled but it wasn't :( */
 static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
 {
 	if (dev->vendor == 0x1033 && (dev->device == 0x0035 ||
 				      dev->device == 0x00e0)) {
 		if (board_rev == 0) {
 			dev->irq = irq_create_mapping(NULL, 47);
 			pr_info("%s: Mapping irq %d\n", __func__, dev->irq);
 		} else if (board_rev == 2) {
 			dev->irq = irq_create_mapping(NULL, 49);
 			pr_info("%s: Mapping irq %d\n", __func__, dev->irq);
 		} else {
 			pr_alert("%s: Unknown board revision\n", __func__);
 		}
 	}
 }
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init ppc47x_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+	if (of_flat_dt_is_compatible(root, "ibm,akebono"))
+		return 1;
+	if (of_flat_dt_is_compatible(root, "ibm,currituck")) {
+		ppc_md.pci_irq_fixup = ppc47x_pci_irq_fixup;
+		return 1;

arch/powerpc/sysdev/ppc4xx_pci.c

Diff comments View file @ 2a2c74b

 /*
  * PCI / PCI-X / PCI-Express support for 4xx parts
  *
  * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
  *
  * Most PCI Express code is coming from Stefan Roese implementation for
  * arch/ppc in the Denx tree, slightly reworked by me.
  *
  * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * Some of that comes itself from a previous implementation for 440SPE only
  * by Roland Dreier:
  *
  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
  * Roland Dreier <rolandd@cisco.com>
  *
  */
 #undef DEBUG
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/bootmem.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <asm/io.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 #include <asm/dcr.h>
 #include <asm/dcr-regs.h>
 #include <mm/mmu_decl.h>
 #include "ppc4xx_pci.h"
 static int dma_offset_set;
 #define U64_TO_U32_LOW(val)	((u32)((val) & 0x00000000ffffffffULL))
 #define U64_TO_U32_HIGH(val)	((u32)((val) >> 32))
 #define RES_TO_U32_LOW(val)	\
 	((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
 #define RES_TO_U32_HIGH(val)	\
 	((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
 static inline int ppc440spe_revA(void)
 {
 	/* Catch both 440SPe variants, with and without RAID6 support */
         if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
                 return 1;
         else
                 return 0;
 }
 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
 {
 	struct pci_controller *hose;
 	int i;
 	if (dev->devfn != 0 || dev->bus->self != NULL)
 		return;
 	hose = pci_bus_to_host(dev->bus);
 	if (hose == NULL)
 		return;
 	if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
 	    !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
 	    !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
 		return;
 	if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
 		of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
 		hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
 	}
 	/* Hide the PCI host BARs from the kernel as their content doesn't
 	 * fit well in the resource management
 	 */
 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 		dev->resource[i].start = dev->resource[i].end = 0;
 		dev->resource[i].flags = 0;
 	}
 	printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
 	       pci_name(dev));
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
 					  void __iomem *reg,
 					  struct resource *res)
 {
 	u64 size;
 	const u32 *ranges;
 	int rlen;
 	int pna = of_n_addr_cells(hose->dn);
 	int np = pna + 5;
 	/* Default */
 	res->start = 0;
 	size = 0x80000000;
 	res->end = size - 1;
 	res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 	/* Get dma-ranges property */
 	ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
 	if (ranges == NULL)
 		goto out;
 	/* Walk it */
 	while ((rlen -= np * 4) >= 0) {
 		u32 pci_space = ranges[0];
 		u64 pci_addr = of_read_number(ranges + 1, 2);
 		u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
 		size = of_read_number(ranges + pna + 3, 2);
 		ranges += np;
 		if (cpu_addr == OF_BAD_ADDR || size == 0)
 			continue;
 		/* We only care about memory */
 		if ((pci_space & 0x03000000) != 0x02000000)
 			continue;
 		/* We currently only support memory at 0, and pci_addr
 		 * within 32 bits space
 		 */
 		if (cpu_addr != 0 || pci_addr > 0xffffffff) {
 			printk(KERN_WARNING "%s: Ignored unsupported dma range"
 			       " 0x%016llx...0x%016llx -> 0x%016llx\n",
 			       hose->dn->full_name,
 			       pci_addr, pci_addr + size - 1, cpu_addr);
 			continue;
 		}
 		/* Check if not prefetchable */
 		if (!(pci_space & 0x40000000))
 			res->flags &= ~IORESOURCE_PREFETCH;
 		/* Use that */
 		res->start = pci_addr;
 		/* Beware of 32 bits resources */
 		if (sizeof(resource_size_t) == sizeof(u32) &&
 		    (pci_addr + size) > 0x100000000ull)
 			res->end = 0xffffffff;
 		else
 			res->end = res->start + size - 1;
 		break;
 	}
 	/* We only support one global DMA offset */
 	if (dma_offset_set && pci_dram_offset != res->start) {
 		printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
 		       hose->dn->full_name);
 		return -ENXIO;
 	}
 	/* Check that we can fit all of memory as we don't support
 	 * DMA bounce buffers
 	 */
 	if (size < total_memory) {
 		printk(KERN_ERR "%s: dma-ranges too small "
 		       "(size=%llx total_memory=%llx)\n",
 		       hose->dn->full_name, size, (u64)total_memory);
 		return -ENXIO;
 	}
 	/* Check we are a power of 2 size and that base is a multiple of size*/
 	if ((size & (size - 1)) != 0  ||
 	    (res->start & (size - 1)) != 0) {
 		printk(KERN_ERR "%s: dma-ranges unaligned\n",
 		       hose->dn->full_name);
 		return -ENXIO;
 	}
 	/* Check that we are fully contained within 32 bits space */
 	if (res->end > 0xffffffff) {
 		printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
 		       hose->dn->full_name);
 		return -ENXIO;
 	}
  out:
 	dma_offset_set = 1;
 	pci_dram_offset = res->start;
 	hose->dma_window_base_cur = res->start;
 	hose->dma_window_size = resource_size(res);
 	printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
 	       pci_dram_offset);
 	printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
 	       (unsigned long long)hose->dma_window_base_cur);
 	printk(KERN_INFO "DMA window size 0x%016llx\n",
 	       (unsigned long long)hose->dma_window_size);
 	return 0;
 }
 /*
  * 4xx PCI 2.x part
  */
 static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller	*hose,
 					   void __iomem			*reg,
 					   u64				plb_addr,
 					   u64				pci_addr,
 					   u64				size,
 					   unsigned int			flags,
 					   int				index)
 {
 	u32 ma, pcila, pciha;
 	/* Hack warning ! The "old" PCI 2.x cell only let us configure the low
 	 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
 	 * address are actually hard wired to a value that appears to depend
 	 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
 	 *
 	 * The trick here is we just crop those top bits and ignore them when
 	 * programming the chip. That means the device-tree has to be right
 	 * for the specific part used (we don't print a warning if it's wrong
 	 * but on the other hand, you'll crash quickly enough), but at least
 	 * this code should work whatever the hard coded value is
 	 */
 	plb_addr &= 0xffffffffull;
 	/* Note: Due to the above hack, the test below doesn't actually test
 	 * if you address is above 4G, but it tests that address and
 	 * (address + size) are both contained in the same 4G
 	 */
 	if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
 	    size < 0x1000 || (plb_addr & (size - 1)) != 0) {
 		printk(KERN_WARNING "%s: Resource out of range\n",
 		       hose->dn->full_name);
 		return -1;
 	}
 	ma = (0xffffffffu << ilog2(size)) | 1;
 	if (flags & IORESOURCE_PREFETCH)
 		ma |= 2;
 	pciha = RES_TO_U32_HIGH(pci_addr);
 	pcila = RES_TO_U32_LOW(pci_addr);
 	writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
 	writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
 	writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
 	writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
 	return 0;
 }
 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
 					     void __iomem *reg)
 {
 	int i, j, found_isa_hole = 0;
 	/* Setup outbound memory windows */
 	for (i = j = 0; i < 3; i++) {
 		struct resource *res = &hose->mem_resources[i];
 		resource_size_t offset = hose->mem_offset[i];
 		/* we only care about memory windows */
 		if (!(res->flags & IORESOURCE_MEM))
 			continue;
 		if (j > 2) {
 			printk(KERN_WARNING "%s: Too many ranges\n",
 			       hose->dn->full_name);
 			break;
 		}
 		/* Configure the resource */
 		if (ppc4xx_setup_one_pci_PMM(hose, reg,
 					     res->start,
 					     res->start - offset,
 					     resource_size(res),
 					     res->flags,
 					     j) == 0) {
 			j++;
 			/* If the resource PCI address is 0 then we have our
 			 * ISA memory hole
 			 */
 			if (res->start == offset)
 				found_isa_hole = 1;
 		}
 	}
 	/* Handle ISA memory hole if not already covered */
 	if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
 		if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
 					     hose->isa_mem_size, 0, j) == 0)
 			printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
 			       hose->dn->full_name);
 }
 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
 					     void __iomem *reg,
 					     const struct resource *res)
 {
 	resource_size_t size = resource_size(res);
 	u32 sa;
 	/* Calculate window size */
 	sa = (0xffffffffu << ilog2(size)) | 1;
 	sa |= 0x1;
 	/* RAM is always at 0 local for now */
 	writel(0, reg + PCIL0_PTM1LA);
 	writel(sa, reg + PCIL0_PTM1MS);
 	/* Map on PCI side */
 	early_write_config_dword(hose, hose->first_busno, 0,
 				 PCI_BASE_ADDRESS_1, res->start);
 	early_write_config_dword(hose, hose->first_busno, 0,
 				 PCI_BASE_ADDRESS_2, 0x00000000);
 	early_write_config_word(hose, hose->first_busno, 0,
 				PCI_COMMAND, 0x0006);
 }
 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
 {
 	/* NYI */
 	struct resource rsrc_cfg;
 	struct resource rsrc_reg;
 	struct resource dma_window;
 	struct pci_controller *hose = NULL;
 	void __iomem *reg = NULL;
 	const int *bus_range;
 	int primary = 0;
 	/* Check if device is enabled */
 	if (!of_device_is_available(np)) {
 		printk(KERN_INFO "%s: Port disabled via device-tree\n",
 		       np->full_name);
 		return;
 	}
 	/* Fetch config space registers address */
 	if (of_address_to_resource(np, 0, &rsrc_cfg)) {
 		printk(KERN_ERR "%s: Can't get PCI config register base !",
 		       np->full_name);
 		return;
 	}
 	/* Fetch host bridge internal registers address */
 	if (of_address_to_resource(np, 3, &rsrc_reg)) {
 		printk(KERN_ERR "%s: Can't get PCI internal register base !",
 		       np->full_name);
 		return;
 	}
 	/* Check if primary bridge */
 	if (of_get_property(np, "primary", NULL))
 		primary = 1;
 	/* Get bus range if any */
 	bus_range = of_get_property(np, "bus-range", NULL);
 	/* Map registers */
 	reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
 	if (reg == NULL) {
 		printk(KERN_ERR "%s: Can't map registers !", np->full_name);
 		goto fail;
 	}
 	/* Allocate the host controller data structure */
 	hose = pcibios_alloc_controller(np);
 	if (!hose)
 		goto fail;
 	hose->first_busno = bus_range ? bus_range[0] : 0x0;
 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
 	/* Setup config space */
 	setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
 	/* Disable all windows */
 	writel(0, reg + PCIL0_PMM0MA);
 	writel(0, reg + PCIL0_PMM1MA);
 	writel(0, reg + PCIL0_PMM2MA);
 	writel(0, reg + PCIL0_PTM1MS);
 	writel(0, reg + PCIL0_PTM2MS);
 	/* Parse outbound mapping resources */
 	pci_process_bridge_OF_ranges(hose, np, primary);
 	/* Parse inbound mapping resources */
 	if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
 		goto fail;
 	/* Configure outbound ranges POMs */
 	ppc4xx_configure_pci_PMMs(hose, reg);
 	/* Configure inbound ranges PIMs */
 	ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
 	/* We don't need the registers anymore */
 	iounmap(reg);
 	return;
  fail:
 	if (hose)
 		pcibios_free_controller(hose);
 	if (reg)
 		iounmap(reg);
 }
 /*
  * 4xx PCI-X part
  */
 static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller	*hose,
 					    void __iomem		*reg,
 					    u64				plb_addr,
 					    u64				pci_addr,
 					    u64				size,
 					    unsigned int		flags,
 					    int				index)
 {
 	u32 lah, lal, pciah, pcial, sa;
 	if (!is_power_of_2(size) || size < 0x1000 ||
 	    (plb_addr & (size - 1)) != 0) {
 		printk(KERN_WARNING "%s: Resource out of range\n",
 		       hose->dn->full_name);
 		return -1;
 	}
 	/* Calculate register values */
 	lah = RES_TO_U32_HIGH(plb_addr);
 	lal = RES_TO_U32_LOW(plb_addr);
 	pciah = RES_TO_U32_HIGH(pci_addr);
 	pcial = RES_TO_U32_LOW(pci_addr);
 	sa = (0xffffffffu << ilog2(size)) | 0x1;
 	/* Program register values */
 	if (index == 0) {
 		writel(lah, reg + PCIX0_POM0LAH);
 		writel(lal, reg + PCIX0_POM0LAL);
 		writel(pciah, reg + PCIX0_POM0PCIAH);
 		writel(pcial, reg + PCIX0_POM0PCIAL);
 		writel(sa, reg + PCIX0_POM0SA);
 	} else {
 		writel(lah, reg + PCIX0_POM1LAH);
 		writel(lal, reg + PCIX0_POM1LAL);
 		writel(pciah, reg + PCIX0_POM1PCIAH);
 		writel(pcial, reg + PCIX0_POM1PCIAL);
 		writel(sa, reg + PCIX0_POM1SA);
 	}
 	return 0;
 }
 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
 					      void __iomem *reg)
 {
 	int i, j, found_isa_hole = 0;
 	/* Setup outbound memory windows */
 	for (i = j = 0; i < 3; i++) {
 		struct resource *res = &hose->mem_resources[i];
 		resource_size_t offset = hose->mem_offset[i];
 		/* we only care about memory windows */
 		if (!(res->flags & IORESOURCE_MEM))
 			continue;
 		if (j > 1) {
 			printk(KERN_WARNING "%s: Too many ranges\n",
 			       hose->dn->full_name);
 			break;
 		}
 		/* Configure the resource */
 		if (ppc4xx_setup_one_pcix_POM(hose, reg,
 					      res->start,
 					      res->start - offset,
 					      resource_size(res),
 					      res->flags,
 					      j) == 0) {
 			j++;
 			/* If the resource PCI address is 0 then we have our
 			 * ISA memory hole
 			 */
 			if (res->start == offset)
 				found_isa_hole = 1;
 		}
 	}
 	/* Handle ISA memory hole if not already covered */
 	if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
 		if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
 					      hose->isa_mem_size, 0, j) == 0)
 			printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
 			       hose->dn->full_name);
 }
 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
 					      void __iomem *reg,
 					      const struct resource *res,
 					      int big_pim,
 					      int enable_msi_hole)
 {
 	resource_size_t size = resource_size(res);
 	u32 sa;
 	/* RAM is always at 0 */
 	writel(0x00000000, reg + PCIX0_PIM0LAH);
 	writel(0x00000000, reg + PCIX0_PIM0LAL);
 	/* Calculate window size */
 	sa = (0xffffffffu << ilog2(size)) | 1;
 	sa |= 0x1;
 	if (res->flags & IORESOURCE_PREFETCH)
 		sa |= 0x2;
 	if (enable_msi_hole)
 		sa |= 0x4;
 	writel(sa, reg + PCIX0_PIM0SA);
 	if (big_pim)
 		writel(0xffffffff, reg + PCIX0_PIM0SAH);
 	/* Map on PCI side */
 	writel(0x00000000, reg + PCIX0_BAR0H);
 	writel(res->start, reg + PCIX0_BAR0L);
 	writew(0x0006, reg + PCIX0_COMMAND);
 }
 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
 {
 	struct resource rsrc_cfg;
 	struct resource rsrc_reg;
 	struct resource dma_window;
 	struct pci_controller *hose = NULL;
 	void __iomem *reg = NULL;
 	const int *bus_range;
 	int big_pim = 0, msi = 0, primary = 0;
 	/* Fetch config space registers address */
 	if (of_address_to_resource(np, 0, &rsrc_cfg)) {
 		printk(KERN_ERR "%s:Can't get PCI-X config register base !",
 		       np->full_name);
 		return;
 	}
 	/* Fetch host bridge internal registers address */
 	if (of_address_to_resource(np, 3, &rsrc_reg)) {
 		printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
 		       np->full_name);
 		return;
 	}
 	/* Check if it supports large PIMs (440GX) */
 	if (of_get_property(np, "large-inbound-windows", NULL))
 		big_pim = 1;
 	/* Check if we should enable MSIs inbound hole */
 	if (of_get_property(np, "enable-msi-hole", NULL))
 		msi = 1;
 	/* Check if primary bridge */
 	if (of_get_property(np, "primary", NULL))
 		primary = 1;
 	/* Get bus range if any */
 	bus_range = of_get_property(np, "bus-range", NULL);
 	/* Map registers */
 	reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
 	if (reg == NULL) {
 		printk(KERN_ERR "%s: Can't map registers !", np->full_name);
 		goto fail;
 	}
 	/* Allocate the host controller data structure */
 	hose = pcibios_alloc_controller(np);
 	if (!hose)
 		goto fail;
 	hose->first_busno = bus_range ? bus_range[0] : 0x0;
 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
 	/* Setup config space */
 	setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
 					PPC_INDIRECT_TYPE_SET_CFG_TYPE);
 	/* Disable all windows */
 	writel(0, reg + PCIX0_POM0SA);
 	writel(0, reg + PCIX0_POM1SA);
 	writel(0, reg + PCIX0_POM2SA);
 	writel(0, reg + PCIX0_PIM0SA);
 	writel(0, reg + PCIX0_PIM1SA);
 	writel(0, reg + PCIX0_PIM2SA);
 	if (big_pim) {
 		writel(0, reg + PCIX0_PIM0SAH);
 		writel(0, reg + PCIX0_PIM2SAH);
 	}
 	/* Parse outbound mapping resources */
 	pci_process_bridge_OF_ranges(hose, np, primary);
 	/* Parse inbound mapping resources */
 	if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
 		goto fail;
 	/* Configure outbound ranges POMs */
 	ppc4xx_configure_pcix_POMs(hose, reg);
 	/* Configure inbound ranges PIMs */
 	ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
 	/* We don't need the registers anymore */
 	iounmap(reg);
 	return;
  fail:
 	if (hose)
 		pcibios_free_controller(hose);
 	if (reg)
 		iounmap(reg);
 }
 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
 /*
  * 4xx PCI-Express part
  *
  * We support 3 parts currently based on the compatible property:
  *
  * ibm,plb-pciex-440spe
  * ibm,plb-pciex-405ex
  * ibm,plb-pciex-460ex
  *
  * Anything else will be rejected for now as they are all subtly
  * different unfortunately.
  *
  */
 #define MAX_PCIE_BUS_MAPPED	0x40
 struct ppc4xx_pciex_port
 {
 	struct pci_controller	*hose;
 	struct device_node	*node;
 	unsigned int		index;
 	int			endpoint;
 	int			link;
 	int			has_ibpre;
 	unsigned int		sdr_base;
 	dcr_host_t		dcrs;
 	struct resource		cfg_space;
 	struct resource		utl_regs;
 	void __iomem		*utl_base;
 };
 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
 static unsigned int ppc4xx_pciex_port_count;
 struct ppc4xx_pciex_hwops
 {
 	bool want_sdr;
 	int (*core_init)(struct device_node *np);
 	int (*port_init_hw)(struct ppc4xx_pciex_port *port);
 	int (*setup_utl)(struct ppc4xx_pciex_port *port);
 	void (*check_link)(struct ppc4xx_pciex_port *port);
 };
 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
 					   unsigned int sdr_offset,
 					   unsigned int mask,
 					   unsigned int value,
 					   int timeout_ms)
 {
 	u32 val;
 	while(timeout_ms--) {
 		val = mfdcri(SDR0, port->sdr_base + sdr_offset);
 		if ((val & mask) == value) {
 			pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
 				 port->index, sdr_offset, timeout_ms, val);
 			return 0;
 		}
 		msleep(1);
 	}
 	return -1;
 }
 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
 {
 	/* Wait for reset to complete */
 	if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
 		printk(KERN_WARNING "PCIE%d: PGRST failed\n",
 		       port->index);
 		return -1;
 	}
 	return 0;
 }
 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
 {
 	printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
 	/* Check for card presence detect if supported, if not, just wait for
 	 * link unconditionally.
 	 *
 	 * note that we don't fail if there is no link, we just filter out
 	 * config space accesses. That way, it will be easier to implement
 	 * hotplug later on.
 	 */
 	if (!port->has_ibpre ||
 	    !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
 				      1 << 28, 1 << 28, 100)) {
 		printk(KERN_INFO
 		       "PCIE%d: Device detected, waiting for link...\n",
 		       port->index);
 		if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
 					     0x1000, 0x1000, 2000))
 			printk(KERN_WARNING
 			       "PCIE%d: Link up failed\n", port->index);
 		else {
 			printk(KERN_INFO
 			       "PCIE%d: link is up !\n", port->index);
 			port->link = 1;
 		}
 	} else
 		printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
 }
 #ifdef CONFIG_44x
 /* Check various reset bits of the 440SPe PCIe core */
 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
 {
 	u32 valPE0, valPE1, valPE2;
 	int err = 0;
 	/* SDR0_PEGPLLLCT1 reset */
 	if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
 		/*
 		 * the PCIe core was probably already initialised
 		 * by firmware - let's re-reset RCSSET regs
 		 *
 		 * -- Shouldn't we also re-reset the whole thing ? -- BenH
 		 */
 		pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
 		mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
 		mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
 		mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
 	}
 	valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
 	valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
 	valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
 	/* SDR0_PExRCSSET rstgu */
 	if (!(valPE0 & 0x01000000) ||
 	    !(valPE1 & 0x01000000) ||
 	    !(valPE2 & 0x01000000)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
 		err = -1;
 	}
 	/* SDR0_PExRCSSET rstdl */
 	if (!(valPE0 & 0x00010000) ||
 	    !(valPE1 & 0x00010000) ||
 	    !(valPE2 & 0x00010000)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
 		err = -1;
 	}
 	/* SDR0_PExRCSSET rstpyn */
 	if ((valPE0 & 0x00001000) ||
 	    (valPE1 & 0x00001000) ||
 	    (valPE2 & 0x00001000)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
 		err = -1;
 	}
 	/* SDR0_PExRCSSET hldplb */
 	if ((valPE0 & 0x10000000) ||
 	    (valPE1 & 0x10000000) ||
 	    (valPE2 & 0x10000000)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
 		err = -1;
 	}
 	/* SDR0_PExRCSSET rdy */
 	if ((valPE0 & 0x00100000) ||
 	    (valPE1 & 0x00100000) ||
 	    (valPE2 & 0x00100000)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
 		err = -1;
 	}
 	/* SDR0_PExRCSSET shutdown */
 	if ((valPE0 & 0x00000100) ||
 	    (valPE1 & 0x00000100) ||
 	    (valPE2 & 0x00000100)) {
 		printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
 		err = -1;
 	}
 	return err;
 }
 /* Global PCIe core initializations for 440SPe core */
 static int __init ppc440spe_pciex_core_init(struct device_node *np)
 {
 	int time_out = 20;
 	/* Set PLL clock receiver to LVPECL */
 	dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
 	/* Shouldn't we do all the calibration stuff etc... here ? */
 	if (ppc440spe_pciex_check_reset(np))
 		return -ENXIO;
 	if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
 		printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
 		       "failed (0x%08x)\n",
 		       mfdcri(SDR0, PESDR0_PLLLCT2));
 		return -1;
 	}
 	/* De-assert reset of PCIe PLL, wait for lock */
 	dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
 	udelay(3);
 	while (time_out) {
 		if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
 			time_out--;
 			udelay(1);
 		} else
 			break;
 	}
 	if (!time_out) {
 		printk(KERN_INFO "PCIE: VCO output not locked\n");
 		return -1;
 	}
 	pr_debug("PCIE initialization OK\n");
 	return 3;
 }
 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	u32 val = 1 << 24;
 	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT << 20;
 	else
 		val = PTYPE_ROOT_PORT << 20;
 	if (port->index == 0)
 		val |= LNKW_X8 << 12;
 	else
 		val |= LNKW_X4 << 12;
 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
 	if (ppc440spe_revA())
 		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
 	if (port->index == 0) {
 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
 		       0x35000000);
 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
 		       0x35000000);
 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
 		       0x35000000);
 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
 		       0x35000000);
 	}
 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
 			(1 << 24) | (1 << 16), 1 << 12);
 	return ppc4xx_pciex_port_reset_sdr(port);
 }
 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	return ppc440spe_pciex_init_port_hw(port);
 }
 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	int rc = ppc440spe_pciex_init_port_hw(port);
 	port->has_ibpre = 1;
 	return rc;
 }
 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
 {
 	/* XXX Check what that value means... I hate magic */
 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
 	 */
 	out_be32(port->utl_base + PEUTL_OUTTR,   0x08000000);
 	out_be32(port->utl_base + PEUTL_INTR,    0x02000000);
 	out_be32(port->utl_base + PEUTL_OPDBSZ,  0x10000000);
 	out_be32(port->utl_base + PEUTL_PBBSZ,   0x53000000);
 	out_be32(port->utl_base + PEUTL_IPHBSZ,  0x08000000);
 	out_be32(port->utl_base + PEUTL_IPDBSZ,  0x10000000);
 	out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
 	out_be32(port->utl_base + PEUTL_PCTL,    0x80800066);
 	return 0;
 }
 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
 {
 	/* Report CRS to the operating system */
 	out_be32(port->utl_base + PEUTL_PBCTL,    0x08000000);
 	return 0;
 }
 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
 {
 	.want_sdr	= true,
 	.core_init	= ppc440spe_pciex_core_init,
 	.port_init_hw	= ppc440speA_pciex_init_port_hw,
 	.setup_utl	= ppc440speA_pciex_init_utl,
 	.check_link	= ppc4xx_pciex_check_link_sdr,
 };
 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
 {
 	.want_sdr	= true,
 	.core_init	= ppc440spe_pciex_core_init,
 	.port_init_hw	= ppc440speB_pciex_init_port_hw,
 	.setup_utl	= ppc440speB_pciex_init_utl,
 	.check_link	= ppc4xx_pciex_check_link_sdr,
 };
 static int __init ppc460ex_pciex_core_init(struct device_node *np)
 {
 	/* Nothing to do, return 2 ports */
 	return 2;
 }
 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	u32 val;
 	u32 utlset1;
 	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT << 20;
 	else
 		val = PTYPE_ROOT_PORT << 20;
 	if (port->index == 0) {
 		val |= LNKW_X1 << 12;
 		utlset1 = 0x20000000;
 	} else {
 		val |= LNKW_X4 << 12;
 		utlset1 = 0x20101101;
 	}
 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
 	switch (port->index) {
 	case 0:
 		mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
 		mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
 		mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
 		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
 		break;
 	case 1:
 		mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
 		mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
 		mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
 		mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
 		mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
 		mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
 		mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
 		mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
 		mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
 		mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
 		mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
 		mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
 		mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
 		break;
 	}
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
 	       mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
 	       (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
 	/* Poll for PHY reset */
 	/* XXX FIXME add timeout */
 	switch (port->index) {
 	case 0:
 		while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
 			udelay(10);
 		break;
 	case 1:
 		while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
 			udelay(10);
 		break;
 	}
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
 	       (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
 		~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
 	       PESDRx_RCSSET_RSTPYN);
 	port->has_ibpre = 1;
 	return ppc4xx_pciex_port_reset_sdr(port);
 }
 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 {
 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
 	 */
 	out_be32(port->utl_base + PEUTL_PBCTL,	0x0800000c);
 	out_be32(port->utl_base + PEUTL_OUTTR,	0x08000000);
 	out_be32(port->utl_base + PEUTL_INTR,	0x02000000);
 	out_be32(port->utl_base + PEUTL_OPDBSZ,	0x04000000);
 	out_be32(port->utl_base + PEUTL_PBBSZ,	0x00000000);
 	out_be32(port->utl_base + PEUTL_IPHBSZ,	0x02000000);
 	out_be32(port->utl_base + PEUTL_IPDBSZ,	0x04000000);
 	out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
 	out_be32(port->utl_base + PEUTL_PCTL,	0x80800066);
 	return 0;
 }
 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
 {
 	.want_sdr	= true,
 	.core_init	= ppc460ex_pciex_core_init,
 	.port_init_hw	= ppc460ex_pciex_init_port_hw,
 	.setup_utl	= ppc460ex_pciex_init_utl,
 	.check_link	= ppc4xx_pciex_check_link_sdr,
 };
 static int __init apm821xx_pciex_core_init(struct device_node *np)
 {
 	/* Return the number of pcie port */
 	return 1;
 }
 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	u32 val;
 	/*
 	 * Do a software reset on PCIe ports.
 	 * This code is to fix the issue that pci drivers doesn't re-assign
 	 * bus number for PCIE devices after Uboot
 	 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
 	 * PT quad port, SAS LSI 1064E)
 	 */
 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
 	mdelay(10);
 	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT << 20;
 	else
 		val = PTYPE_ROOT_PORT << 20;
 	val |= LNKW_X1 << 12;
 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
 	mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
 	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
 	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
 	mdelay(50);
 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
 		(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
 	/* Poll for PHY reset */
 	val = PESDR0_460EX_RSTSTA - port->sdr_base;
 	if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1,	100)) {
 		printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
 		return -EBUSY;
 	} else {
 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
 			(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
 			~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
 			PESDRx_RCSSET_RSTPYN);
 		port->has_ibpre = 1;
 		return 0;
 	}
 }
 static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
 	.want_sdr   = true,
 	.core_init	= apm821xx_pciex_core_init,
 	.port_init_hw	= apm821xx_pciex_init_port_hw,
 	.setup_utl	= ppc460ex_pciex_init_utl,
 	.check_link = ppc4xx_pciex_check_link_sdr,
 };
 static int __init ppc460sx_pciex_core_init(struct device_node *np)
 {
 	/* HSS drive amplitude */
 	mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
 	mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
 	/* HSS TX pre-emphasis */
 	mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
 	mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
 	/* HSS TX calibration control */
 	mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
 	mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
 	mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
 	/* HSS TX slew control */
 	mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
 	mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
 	mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
 	/* Set HSS PRBS enabled */
 	mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
 	mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
 	udelay(100);
 	/* De-assert PLLRESET */
 	dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
 	/* Reset DL, UTL, GPL before configuration */
 	mtdcri(SDR0, PESDR0_460SX_RCSSET,
 			PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
 	mtdcri(SDR0, PESDR1_460SX_RCSSET,
 			PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
 	mtdcri(SDR0, PESDR2_460SX_RCSSET,
 			PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
 	udelay(100);
 	/*
 	 * If bifurcation is not enabled, u-boot would have disabled the
 	 * third PCIe port
 	 */
 	if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
 				0x00000001)) {
 		printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
 		printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
 		return 3;
 	}
 	printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
 	return 2;
 }
 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	if (port->endpoint)
 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
 				0x01000000, 0);
 	else
 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
 				0, 0x01000000);
 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
 			(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
 			PESDRx_RCSSET_RSTPYN);
 	port->has_ibpre = 1;
 	return ppc4xx_pciex_port_reset_sdr(port);
 }
 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
 {
 	/* Max 128 Bytes */
 	out_be32 (port->utl_base + PEUTL_PBBSZ,   0x00000000);
 	/* Assert VRB and TXE - per datasheet turn off addr validation */
 	out_be32(port->utl_base + PEUTL_PCTL,  0x80800000);
 	return 0;
 }
 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
 {
 	void __iomem *mbase;
 	int attempt = 50;
 	port->link = 0;
 	mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
 	if (mbase == NULL) {
 		printk(KERN_ERR "%s: Can't map internal config space !",
 			port->node->full_name);
 		goto done;
 	}
 	while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
 			& PECFG_460SX_DLLSTA_LINKUP))) {
 		attempt--;
 		mdelay(10);
 	}
 	if (attempt)
 		port->link = 1;
 done:
 	iounmap(mbase);
 }
 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
 	.want_sdr	= true,
 	.core_init	= ppc460sx_pciex_core_init,
 	.port_init_hw	= ppc460sx_pciex_init_port_hw,
 	.setup_utl	= ppc460sx_pciex_init_utl,
 	.check_link	= ppc460sx_pciex_check_link,
 };
 #endif /* CONFIG_44x */
 #ifdef CONFIG_40x
 static int __init ppc405ex_pciex_core_init(struct device_node *np)
 {
 	/* Nothing to do, return 2 ports */
 	return 2;
 }
 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
 {
 	/* Assert the PE0_PHY reset */
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
 	msleep(1);
 	/* deassert the PE0_hotreset */
 	if (port->endpoint)
 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
 	else
 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
 	/* poll for phy !reset */
 	/* XXX FIXME add timeout */
 	while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
 		;
 	/* deassert the PE0_gpl_utl_reset */
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
 }
 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 {
 	u32 val;
 	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT;
 	else
 		val = PTYPE_ROOT_PORT;
 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
 	       1 << 24 | val << 20 | LNKW_X1 << 12);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
 	/*
 	 * Only reset the PHY when no link is currently established.
 	 * This is for the Atheros PCIe board which has problems to establish
 	 * the link (again) after this PHY reset. All other currently tested
 	 * PCIe boards don't show this problem.
 	 * This has to be re-tested and fixed in a later release!
 	 */
 	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
 	if (!(val & 0x00001000))
 		ppc405ex_pcie_phy_reset(port);
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000);  /* guarded on */
 	port->has_ibpre = 1;
 	return ppc4xx_pciex_port_reset_sdr(port);
 }
 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 {
 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
 	 */
 	out_be32(port->utl_base + PEUTL_OUTTR,   0x02000000);
 	out_be32(port->utl_base + PEUTL_INTR,    0x02000000);
 	out_be32(port->utl_base + PEUTL_OPDBSZ,  0x04000000);
 	out_be32(port->utl_base + PEUTL_PBBSZ,   0x21000000);
 	out_be32(port->utl_base + PEUTL_IPHBSZ,  0x02000000);
 	out_be32(port->utl_base + PEUTL_IPDBSZ,  0x04000000);
 	out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
 	out_be32(port->utl_base + PEUTL_PCTL,    0x80800066);
 	out_be32(port->utl_base + PEUTL_PBCTL,   0x08000000);
 	return 0;
 }
 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
 {
 	.want_sdr	= true,
 	.core_init	= ppc405ex_pciex_core_init,
 	.port_init_hw	= ppc405ex_pciex_init_port_hw,
 	.setup_utl	= ppc405ex_pciex_init_utl,
 	.check_link	= ppc4xx_pciex_check_link_sdr,
 };
 #endif /* CONFIG_40x */
 #ifdef CONFIG_476FPE
 static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
 {
 	return 4;
 }
 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
 {
 	u32 timeout_ms = 20;
 	u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
 	void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
 	                              0x1000);
 	printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
 	if (mbase == NULL) {
 		printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
 		                    port->index);
 		return;
 	}
 	while (timeout_ms--) {
 		val = in_le32(mbase + PECFG_TLDLP);
 		if ((val & mask) == mask)
 			break;
 		msleep(10);
 	}
 	if (val & PECFG_TLDLP_PRESENT) {
 		printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
 		port->link = 1;
 	} else
 		printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
 	iounmap(mbase);
 	return;
 }
 static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
 {
 	.core_init	= ppc_476fpe_pciex_core_init,
 	.check_link	= ppc_476fpe_pciex_check_link,
 };
 #endif /* CONFIG_476FPE */
 /* Check that the core has been initied and if not, do it */
 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
 {
 	static int core_init;
 	int count = -ENODEV;
 	if (core_init++)
 		return 0;
 #ifdef CONFIG_44x
 	if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
 		if (ppc440spe_revA())
 			ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
 		else
 			ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
 	}
 	if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
 		ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
 	if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
 		ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
 	if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
 		ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
 #endif /* CONFIG_44x    */
 #ifdef CONFIG_40x
 	if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
 		ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
 #endif
 #ifdef CONFIG_476FPE
-	if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
+	if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe")
+		|| of_device_is_compatible(np, "ibm,plb-pciex-476gtr"))
 		ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
 #endif
 	if (ppc4xx_pciex_hwops == NULL) {
 		printk(KERN_WARNING "PCIE: unknown host type %s\n",
 		       np->full_name);
 		return -ENODEV;
 	}
 	count = ppc4xx_pciex_hwops->core_init(np);
 	if (count > 0) {
 		ppc4xx_pciex_ports =
 		       kzalloc(count * sizeof(struct ppc4xx_pciex_port),
 			       GFP_KERNEL);
 		if (ppc4xx_pciex_ports) {
 			ppc4xx_pciex_port_count = count;
 			return 0;
 		}
 		printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
 		return -ENOMEM;
 	}
 	return -ENODEV;
 }
 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
 {
 	/* We map PCI Express configuration based on the reg property */
 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
 		  RES_TO_U32_HIGH(port->cfg_space.start));
 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
 		  RES_TO_U32_LOW(port->cfg_space.start));
 	/* XXX FIXME: Use size from reg property. For now, map 512M */
 	dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
 	/* We map UTL registers based on the reg property */
 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
 		  RES_TO_U32_HIGH(port->utl_regs.start));
 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
 		  RES_TO_U32_LOW(port->utl_regs.start));
 	/* XXX FIXME: Use size from reg property */
 	dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
 	/* Disable all other outbound windows */
 	dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
 	dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
 	dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
 	dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
 }
 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
 {
 	int rc = 0;
 	/* Init HW */
 	if (ppc4xx_pciex_hwops->port_init_hw)
 		rc = ppc4xx_pciex_hwops->port_init_hw(port);
 	if (rc != 0)
 		return rc;
 	/*
 	 * Initialize mapping: disable all regions and configure
 	 * CFG and REG regions based on resources in the device tree
 	 */
 	ppc4xx_pciex_port_init_mapping(port);
 	if (ppc4xx_pciex_hwops->check_link)
 		ppc4xx_pciex_hwops->check_link(port);
 	/*
 	 * Map UTL
 	 */
 	port->utl_base = ioremap(port->utl_regs.start, 0x100);
 	BUG_ON(port->utl_base == NULL);
 	/*
 	 * Setup UTL registers --BenH.
 	 */
 	if (ppc4xx_pciex_hwops->setup_utl)
 		ppc4xx_pciex_hwops->setup_utl(port);
 	/*
 	 * Check for VC0 active or PLL Locked and assert RDY.
 	 */
 	if (port->sdr_base) {
 		if (of_device_is_compatible(port->node,
 				"ibm,plb-pciex-460sx")){
 			if (port->link && ppc4xx_pciex_wait_on_sdr(port,
 					PESDRn_RCSSTS,
 					1 << 12, 1 << 12, 5000)) {
 				printk(KERN_INFO "PCIE%d: PLL not locked\n",
 						port->index);
 				port->link = 0;
 			}
 		} else if (port->link &&
 			ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
 				1 << 16, 1 << 16, 5000)) {
 			printk(KERN_INFO "PCIE%d: VC0 not active\n",
 					port->index);
 			port->link = 0;
 		}
 		dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
 	}
 	msleep(100);
 	return 0;
 }
 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
 				     struct pci_bus *bus,
 				     unsigned int devfn)
 {
 	static int message;
 	/* Endpoint can not generate upstream(remote) config cycles */
 	if (port->endpoint && bus->number != port->hose->first_busno)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	/* Check we are within the mapped range */
 	if (bus->number > port->hose->last_busno) {
 		if (!message) {
 			printk(KERN_WARNING "Warning! Probing bus %u"
 			       " out of range !\n", bus->number);
 			message++;
 		}
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 	/* The root complex has only one device / function */
 	if (bus->number == port->hose->first_busno && devfn != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	/* The other side of the RC has only one device as well */
 	if (bus->number == (port->hose->first_busno + 1) &&
 	    PCI_SLOT(devfn) != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	/* Check if we have a link */
 	if ((bus->number != port->hose->first_busno) && !port->link)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	return 0;
 }
 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
 						  struct pci_bus *bus,
 						  unsigned int devfn)
 {
 	int relbus;
 	/* Remove the casts when we finally remove the stupid volatile
 	 * in struct pci_controller
 	 */
 	if (bus->number == port->hose->first_busno)
 		return (void __iomem *)port->hose->cfg_addr;
 	relbus = bus->number - (port->hose->first_busno + 1);
 	return (void __iomem *)port->hose->cfg_data +
 		((relbus  << 20) | (devfn << 12));
 }
 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
 				    int offset, int len, u32 *val)
 {
 	struct pci_controller *hose = pci_bus_to_host(bus);
 	struct ppc4xx_pciex_port *port =
 		&ppc4xx_pciex_ports[hose->indirect_type];
 	void __iomem *addr;
 	u32 gpl_cfg;
 	BUG_ON(hose != port->hose);
 	if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
 	/*
 	 * Reading from configuration space of non-existing device can
 	 * generate transaction errors. For the read duration we suppress
 	 * assertion of machine check exceptions to avoid those.
 	 */
 	gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
 	/* Make sure no CRS is recorded */
 	out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
 	switch (len) {
 	case 1:
 		*val = in_8((u8 *)(addr + offset));
 		break;
 	case 2:
 		*val = in_le16((u16 *)(addr + offset));
 		break;
 	default:
 		*val = in_le32((u32 *)(addr + offset));
 		break;
 	}
 	pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
 		 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
 		 bus->number, hose->first_busno, hose->last_busno,
 		 devfn, offset, len, addr + offset, *val);
 	/* Check for CRS (440SPe rev B does that for us but heh ..) */
 	if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
 		pr_debug("Got CRS !\n");
 		if (len != 4 || offset != 0)
 			return PCIBIOS_DEVICE_NOT_FOUND;
 		*val = 0xffff0001;
 	}
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
 	return PCIBIOS_SUCCESSFUL;
 }
 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
 				     int offset, int len, u32 val)
 {
 	struct pci_controller *hose = pci_bus_to_host(bus);
 	struct ppc4xx_pciex_port *port =
 		&ppc4xx_pciex_ports[hose->indirect_type];
 	void __iomem *addr;
 	u32 gpl_cfg;
 	if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
 	/*
 	 * Reading from configuration space of non-existing device can
 	 * generate transaction errors. For the read duration we suppress
 	 * assertion of machine check exceptions to avoid those.
 	 */
 	gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
 	pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
 		 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
 		 bus->number, hose->first_busno, hose->last_busno,
 		 devfn, offset, len, addr + offset, val);
 	switch (len) {
 	case 1:
 		out_8((u8 *)(addr + offset), val);
 		break;
 	case 2:
 		out_le16((u16 *)(addr + offset), val);
 		break;
 	default:
 		out_le32((u32 *)(addr + offset), val);
 		break;
 	}
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
 	return PCIBIOS_SUCCESSFUL;
 }
 static struct pci_ops ppc4xx_pciex_pci_ops =
 {
 	.read  = ppc4xx_pciex_read_config,
 	.write = ppc4xx_pciex_write_config,
 };
 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port	*port,
 					     struct pci_controller	*hose,
 					     void __iomem		*mbase,
 					     u64			plb_addr,
 					     u64			pci_addr,
 					     u64			size,
 					     unsigned int		flags,
 					     int			index)
 {
 	u32 lah, lal, pciah, pcial, sa;
 	if (!is_power_of_2(size) ||
 	    (index < 2 && size < 0x100000) ||
 	    (index == 2 && size < 0x100) ||
 	    (plb_addr & (size - 1)) != 0) {
 		printk(KERN_WARNING "%s: Resource out of range\n",
 		       hose->dn->full_name);
 		return -1;
 	}
 	/* Calculate register values */
 	lah = RES_TO_U32_HIGH(plb_addr);
 	lal = RES_TO_U32_LOW(plb_addr);
 	pciah = RES_TO_U32_HIGH(pci_addr);
 	pcial = RES_TO_U32_LOW(pci_addr);
 	sa = (0xffffffffu << ilog2(size)) | 0x1;
 	/* Program register values */
 	switch (index) {
 	case 0:
 		out_le32(mbase + PECFG_POM0LAH, pciah);
 		out_le32(mbase + PECFG_POM0LAL, pcial);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
 		/*Enabled and single region */
 		if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
 				sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
 					| DCRO_PEGPL_OMRxMSKL_VAL);
-		else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+		else if (of_device_is_compatible(
+				port->node, "ibm,plb-pciex-476fpe") ||
+			of_device_is_compatible(
+				port->node, "ibm,plb-pciex-476gtr"))
 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
 				sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
 					| DCRO_PEGPL_OMRxMSKL_VAL);
 		else
 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
 				sa | DCRO_PEGPL_OMR1MSKL_UOT
 					| DCRO_PEGPL_OMRxMSKL_VAL);
 		break;
 	case 1:
 		out_le32(mbase + PECFG_POM1LAH, pciah);
 		out_le32(mbase + PECFG_POM1LAL, pcial);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
 				sa | DCRO_PEGPL_OMRxMSKL_VAL);
 		break;
 	case 2:
 		out_le32(mbase + PECFG_POM2LAH, pciah);
 		out_le32(mbase + PECFG_POM2LAL, pcial);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
 		/* Note that 3 here means enabled | IO space !!! */
 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
 				sa | DCRO_PEGPL_OMR3MSKL_IO
 					| DCRO_PEGPL_OMRxMSKL_VAL);
 		break;
 	}
 	return 0;
 }
 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
 					       struct pci_controller *hose,
 					       void __iomem *mbase)
 {
 	int i, j, found_isa_hole = 0;
 	/* Setup outbound memory windows */
 	for (i = j = 0; i < 3; i++) {
 		struct resource *res = &hose->mem_resources[i];
 		resource_size_t offset = hose->mem_offset[i];
 		/* we only care about memory windows */
 		if (!(res->flags & IORESOURCE_MEM))
 			continue;
 		if (j > 1) {
 			printk(KERN_WARNING "%s: Too many ranges\n",
 			       port->node->full_name);
 			break;
 		}
 		/* Configure the resource */
 		if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
 					       res->start,
 					       res->start - offset,
 					       resource_size(res),
 					       res->flags,
 					       j) == 0) {
 			j++;
 			/* If the resource PCI address is 0 then we have our
 			 * ISA memory hole
 			 */
 			if (res->start == offset)
 				found_isa_hole = 1;
 		}
 	}
 	/* Handle ISA memory hole if not already covered */
 	if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
 		if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
 					       hose->isa_mem_phys, 0,
 					       hose->isa_mem_size, 0, j) == 0)
 			printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
 			       hose->dn->full_name);
 	/* Configure IO, always 64K starting at 0. We hard wire it to 64K !
 	 * Note also that it -has- to be region index 2 on this HW
 	 */
 	if (hose->io_resource.flags & IORESOURCE_IO)
 		ppc4xx_setup_one_pciex_POM(port, hose, mbase,
 					   hose->io_base_phys, 0,
 					   0x10000, IORESOURCE_IO, 2);
 }
 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
 					       struct pci_controller *hose,
 					       void __iomem *mbase,
 					       struct resource *res)
 {
 	resource_size_t size = resource_size(res);
 	u64 sa;
 	if (port->endpoint) {
 		resource_size_t ep_addr = 0;
 		resource_size_t ep_size = 32 << 20;
 		/* Currently we map a fixed 64MByte window to PLB address
 		 * 0 (SDRAM). This should probably be configurable via a dts
 		 * property.
 		 */
 		/* Calculate window size */
 		sa = (0xffffffffffffffffull << ilog2(ep_size));
 		/* Setup BAR0 */
 		out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
 		out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
 			 PCI_BASE_ADDRESS_MEM_TYPE_64);
 		/* Disable BAR1 & BAR2 */
 		out_le32(mbase + PECFG_BAR1MPA, 0);
 		out_le32(mbase + PECFG_BAR2HMPA, 0);
 		out_le32(mbase + PECFG_BAR2LMPA, 0);
 		out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
 		out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
 		out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
 	} else {
 		/* Calculate window size */
 		sa = (0xffffffffffffffffull << ilog2(size));
 		if (res->flags & IORESOURCE_PREFETCH)
 			sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
 		if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
-		    of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+		    of_device_is_compatible(
+			    port->node, "ibm,plb-pciex-476fpe") ||
+		    of_device_is_compatible(
+			    port->node, "ibm,plb-pciex-476gtr"))
 			sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
 		out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
 		out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
 		/* The setup of the split looks weird to me ... let's see
 		 * if it works
 		 */
 		out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
 		out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
 		out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
 		out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
 		out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
 		out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
 		out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
 	}
 	/* Enable inbound mapping */
 	out_le32(mbase + PECFG_PIMEN, 0x1);
 	/* Enable I/O, Mem, and Busmaster cycles */
 	out_le16(mbase + PCI_COMMAND,
 		 in_le16(mbase + PCI_COMMAND) |
 		 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }
 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
 {
 	struct resource dma_window;
 	struct pci_controller *hose = NULL;
 	const int *bus_range;
 	int primary = 0, busses;
 	void __iomem *mbase = NULL, *cfg_data = NULL;
 	const u32 *pval;
 	u32 val;
 	/* Check if primary bridge */
 	if (of_get_property(port->node, "primary", NULL))
 		primary = 1;
 	/* Get bus range if any */
 	bus_range = of_get_property(port->node, "bus-range", NULL);
 	/* Allocate the host controller data structure */
 	hose = pcibios_alloc_controller(port->node);
 	if (!hose)
 		goto fail;
 	/* We stick the port number in "indirect_type" so the config space
 	 * ops can retrieve the port data structure easily
 	 */
 	hose->indirect_type = port->index;
 	/* Get bus range */
 	hose->first_busno = bus_range ? bus_range[0] : 0x0;
 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
 	/* Because of how big mapping the config space is (1M per bus), we
 	 * limit how many busses we support. In the long run, we could replace
 	 * that with something akin to kmap_atomic instead. We set aside 1 bus
 	 * for the host itself too.
 	 */
 	busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
 	if (busses > MAX_PCIE_BUS_MAPPED) {
 		busses = MAX_PCIE_BUS_MAPPED;
 		hose->last_busno = hose->first_busno + busses;
 	}
 	if (!port->endpoint) {
 		/* Only map the external config space in cfg_data for
 		 * PCIe root-complexes. External space is 1M per bus
 		 */
 		cfg_data = ioremap(port->cfg_space.start +
 				   (hose->first_busno + 1) * 0x100000,
 				   busses * 0x100000);
 		if (cfg_data == NULL) {
 			printk(KERN_ERR "%s: Can't map external config space !",
 			       port->node->full_name);
 			goto fail;
 		}
 		hose->cfg_data = cfg_data;
 	}
 	/* Always map the host config space in cfg_addr.
 	 * Internal space is 4K
 	 */
 	mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
 	if (mbase == NULL) {
 		printk(KERN_ERR "%s: Can't map internal config space !",
 		       port->node->full_name);
 		goto fail;
 	}
 	hose->cfg_addr = mbase;
 	pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
 		 hose->first_busno, hose->last_busno);
 	pr_debug("     config space mapped at: root @0x%p, other @0x%p\n",
 		 hose->cfg_addr, hose->cfg_data);
 	/* Setup config space */
 	hose->ops = &ppc4xx_pciex_pci_ops;
 	port->hose = hose;
 	mbase = (void __iomem *)hose->cfg_addr;
 	if (!port->endpoint) {
 		/*
 		 * Set bus numbers on our root port
 		 */
 		out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
 		out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
 		out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
 	}
 	/*
 	 * OMRs are already reset, also disable PIMs
 	 */
 	out_le32(mbase + PECFG_PIMEN, 0);
 	/* Parse outbound mapping resources */
 	pci_process_bridge_OF_ranges(hose, port->node, primary);
 	/* Parse inbound mapping resources */
 	if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
 		goto fail;
 	/* Configure outbound ranges POMs */
 	ppc4xx_configure_pciex_POMs(port, hose, mbase);
 	/* Configure inbound ranges PIMs */
 	ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
 	/* The root complex doesn't show up if we don't set some vendor
 	 * and device IDs into it. The defaults below are the same bogus
 	 * one that the initial code in arch/ppc had. This can be
 	 * overwritten by setting the "vendor-id/device-id" properties
 	 * in the pciex node.
 	 */
 	/* Get the (optional) vendor-/device-id from the device-tree */
 	pval = of_get_property(port->node, "vendor-id", NULL);
 	if (pval) {
 		val = *pval;
 	} else {
 		if (!port->endpoint)
 			val = 0xaaa0 + port->index;
 		else
 			val = 0xeee0 + port->index;
 	}
 	out_le16(mbase + 0x200, val);
 	pval = of_get_property(port->node, "device-id", NULL);
 	if (pval) {
 		val = *pval;
 	} else {
 		if (!port->endpoint)
 			val = 0xbed0 + port->index;
 		else
 			val = 0xfed0 + port->index;
 	}
 	out_le16(mbase + 0x202, val);
 	/* Enable Bus master, memory, and io space */
 	if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
 		out_le16(mbase + 0x204, 0x7);
 	if (!port->endpoint) {
 		/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
 		out_le32(mbase + 0x208, 0x06040001);
 		printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
 		       port->index);
 	} else {
 		/* Set Class Code to Processor/PPC */
 		out_le32(mbase + 0x208, 0x0b200001);
 		printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
 		       port->index);
 	}
 	return;
  fail:
 	if (hose)
 		pcibios_free_controller(hose);
 	if (cfg_data)
 		iounmap(cfg_data);
 	if (mbase)
 		iounmap(mbase);
 }
 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
 {
 	struct ppc4xx_pciex_port *port;
 	const u32 *pval;
 	int portno;
 	unsigned int dcrs;
 	const char *val;
 	/* First, proceed to core initialization as we assume there's
 	 * only one PCIe core in the system
 	 */
 	if (ppc4xx_pciex_check_core_init(np))
 		return;
 	/* Get the port number from the device-tree */
 	pval = of_get_property(np, "port", NULL);
 	if (pval == NULL) {
 		printk(KERN_ERR "PCIE: Can't find port number for %s\n",
 		       np->full_name);
 		return;
 	}
 	portno = *pval;
 	if (portno >= ppc4xx_pciex_port_count) {
 		printk(KERN_ERR "PCIE: port number out of range for %s\n",
 		       np->full_name);
 		return;
 	}
 	port = &ppc4xx_pciex_ports[portno];
 	port->index = portno;
 	/*
 	 * Check if device is enabled
 	 */
 	if (!of_device_is_available(np)) {
 		printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
 		return;
 	}
 	port->node = of_node_get(np);
 	if (ppc4xx_pciex_hwops->want_sdr) {
 		pval = of_get_property(np, "sdr-base", NULL);
 		if (pval == NULL) {
 			printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
 			       np->full_name);
 			return;
 		}
 		port->sdr_base = *pval;
 	}
 	/* Check if device_type property is set to "pci" or "pci-endpoint".
 	 * Resulting from this setup this PCIe port will be configured
 	 * as root-complex or as endpoint.
 	 */
 	val = of_get_property(port->node, "device_type", NULL);
 	if (!strcmp(val, "pci-endpoint")) {
 		port->endpoint = 1;
 	} else if (!strcmp(val, "pci")) {
 		port->endpoint = 0;
 	} else {
 		printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
 		       np->full_name);
 		return;
 	}
 	/* Fetch config space registers address */
 	if (of_address_to_resource(np, 0, &port->cfg_space)) {
 		printk(KERN_ERR "%s: Can't get PCI-E config space !",
 		       np->full_name);
 		return;
 	}
 	/* Fetch host bridge internal registers address */
 	if (of_address_to_resource(np, 1, &port->utl_regs)) {
 		printk(KERN_ERR "%s: Can't get UTL register base !",
 		       np->full_name);
 		return;
 	}
 	/* Map DCRs */
 	dcrs = dcr_resource_start(np, 0);
 	if (dcrs == 0) {
 		printk(KERN_ERR "%s: Can't get DCR register base !",
 		       np->full_name);
 		return;
 	}
 	port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
 	/* Initialize the port specific registers */
 	if (ppc4xx_pciex_port_init(port)) {
 		printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
 		return;
 	}
 	/* Setup the linux hose data structure */
 	ppc4xx_pciex_port_setup_hose(port);
 }
 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
 static int __init ppc4xx_pci_find_bridges(void)
 {
 	struct device_node *np;
 	pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
 	for_each_compatible_node(np, NULL, "ibm,plb-pciex")
 		ppc4xx_probe_pciex_bridge(np);
 #endif
 	for_each_compatible_node(np, NULL, "ibm,plb-pcix")
 		ppc4xx_probe_pcix_bridge(np);
 	for_each_compatible_node(np, NULL, "ibm,plb-pci")
 		ppc4xx_probe_pci_bridge(np);
 	return 0;
 }
 arch_initcall(ppc4xx_pci_find_bridges);

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