Commit 2afa3265b21ada7583bf4a69defe4539ad4df7cf

Authored by Slava Grigorev
Committed by Alex Deucher
1 parent b983a8f458

radeon/audio: fix DP audio on DCE6

Split DCE6 and DCE8 programming of DCCG_AUDIO_DTO1
registers to properly enable DP audio for both DCE
revisions.

Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Showing 2 changed files with 12 additions and 4 deletions Side-by-side Diff

drivers/gpu/drm/radeon/dce6_afmt.c
... ... @@ -26,6 +26,9 @@
26 26 #include "radeon_audio.h"
27 27 #include "sid.h"
28 28  
  29 +#define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
  30 +#define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
  31 +
29 32 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
30 33 u32 block_offset, u32 reg)
31 34 {
... ... @@ -284,8 +287,13 @@
284 287 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
285 288 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
286 289 */
287   - WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
288   - WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
  290 + if (ASIC_IS_DCE8(rdev)) {
  291 + WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
  292 + WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
  293 + } else {
  294 + WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
  295 + WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
  296 + }
289 297 }
290 298  
291 299 void dce6_dp_enable(struct drm_encoder *encoder, bool enable)
drivers/gpu/drm/radeon/sid.h
... ... @@ -912,8 +912,8 @@
912 912  
913 913 #define DCCG_AUDIO_DTO0_PHASE 0x05b0
914 914 #define DCCG_AUDIO_DTO0_MODULE 0x05b4
915   -#define DCCG_AUDIO_DTO1_PHASE 0x05b8
916   -#define DCCG_AUDIO_DTO1_MODULE 0x05bc
  915 +#define DCCG_AUDIO_DTO1_PHASE 0x05c0
  916 +#define DCCG_AUDIO_DTO1_MODULE 0x05c4
917 917  
918 918 #define AFMT_AUDIO_SRC_CONTROL 0x713c
919 919 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)