Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 2b9d1c050d291693f257c98605028325f8146c84

Authored by Linus Torvalds 2014-04-28 03:55:04 +0800

Exists in master and in 13 other branches

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

Pull arm fixes from Russell King:
 "A number of fixes for the PJ4/iwmmxt changes which arm-soc forced me
  to take during the merge window.  This stuff should have been better
  tested and sorted out *before* the merge window"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B
  ARM: 8041/1: pj4: fix cpu_is_pj4 check
  ARM: 8040/1: pj4: properly detect existence of iWMMXt coprocessor
  ARM: 8039/1: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
  ARM: 8038/1: iwmmxt: explicitly check for supported architectures

Showing 5 changed files Inline Diff

arch/arm/Kconfig
arch/arm/include/asm/cputype.h
arch/arm/kernel/Makefile
arch/arm/kernel/iwmmxt.S
arch/arm/kernel/pj4-cp0.c

arch/arm/Kconfig

Diff comments View file @ 2b9d1c0

1	config ARM	1	config ARM
2	bool	2	bool
3	default y	3	default y
4	select ARCH_BINFMT_ELF_RANDOMIZE_PIE	4	select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE	5	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST	6	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7	select ARCH_HAVE_CUSTOM_GPIO_H	7	select ARCH_HAVE_CUSTOM_GPIO_H
8	select ARCH_MIGHT_HAVE_PC_PARPORT	8	select ARCH_MIGHT_HAVE_PC_PARPORT
9	select ARCH_USE_BUILTIN_BSWAP	9	select ARCH_USE_BUILTIN_BSWAP
10	select ARCH_USE_CMPXCHG_LOCKREF	10	select ARCH_USE_CMPXCHG_LOCKREF
11	select ARCH_WANT_IPC_PARSE_VERSION	11	select ARCH_WANT_IPC_PARSE_VERSION
12	select BUILDTIME_EXTABLE_SORT if MMU	12	select BUILDTIME_EXTABLE_SORT if MMU
13	select CLONE_BACKWARDS	13	select CLONE_BACKWARDS
14	select CPU_PM if (SUSPEND \|\| CPU_IDLE)	14	select CPU_PM if (SUSPEND \|\| CPU_IDLE)
15	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS	15	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16	select GENERIC_ATOMIC64 if (CPU_V7M \|\| CPU_V6 \|\| !CPU_32v6K \|\| !AEABI)	16	select GENERIC_ATOMIC64 if (CPU_V7M \|\| CPU_V6 \|\| !CPU_32v6K \|\| !AEABI)
17	select GENERIC_CLOCKEVENTS_BROADCAST if SMP	17	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18	select GENERIC_IDLE_POLL_SETUP	18	select GENERIC_IDLE_POLL_SETUP
19	select GENERIC_IRQ_PROBE	19	select GENERIC_IRQ_PROBE
20	select GENERIC_IRQ_SHOW	20	select GENERIC_IRQ_SHOW
21	select GENERIC_PCI_IOMAP	21	select GENERIC_PCI_IOMAP
22	select GENERIC_SCHED_CLOCK	22	select GENERIC_SCHED_CLOCK
23	select GENERIC_SMP_IDLE_THREAD	23	select GENERIC_SMP_IDLE_THREAD
24	select GENERIC_STRNCPY_FROM_USER	24	select GENERIC_STRNCPY_FROM_USER
25	select GENERIC_STRNLEN_USER	25	select GENERIC_STRNLEN_USER
26	select HARDIRQS_SW_RESEND	26	select HARDIRQS_SW_RESEND
27	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)	27	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL	28	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29	select HAVE_ARCH_KGDB	29	select HAVE_ARCH_KGDB
30	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)	30	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31	select HAVE_ARCH_TRACEHOOK	31	select HAVE_ARCH_TRACEHOOK
32	select HAVE_BPF_JIT	32	select HAVE_BPF_JIT
33	select HAVE_CC_STACKPROTECTOR	33	select HAVE_CC_STACKPROTECTOR
34	select HAVE_CONTEXT_TRACKING	34	select HAVE_CONTEXT_TRACKING
35	select HAVE_C_RECORDMCOUNT	35	select HAVE_C_RECORDMCOUNT
36	select HAVE_DEBUG_KMEMLEAK	36	select HAVE_DEBUG_KMEMLEAK
37	select HAVE_DMA_API_DEBUG	37	select HAVE_DMA_API_DEBUG
38	select HAVE_DMA_ATTRS	38	select HAVE_DMA_ATTRS
39	select HAVE_DMA_CONTIGUOUS if MMU	39	select HAVE_DMA_CONTIGUOUS if MMU
40	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)	40	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 \|\| CPU_V6K \|\| CPU_V7) && MMU	41	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 \|\| CPU_V6K \|\| CPU_V7) && MMU
42	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)	42	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)	43	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)	44	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45	select HAVE_GENERIC_DMA_COHERENT	45	select HAVE_GENERIC_DMA_COHERENT
46	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 \|\| CPU_V6K \|\| CPU_V7))	46	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 \|\| CPU_V6K \|\| CPU_V7))
47	select HAVE_IDE if PCI \|\| ISA \|\| PCMCIA	47	select HAVE_IDE if PCI \|\| ISA \|\| PCMCIA
48	select HAVE_IRQ_TIME_ACCOUNTING	48	select HAVE_IRQ_TIME_ACCOUNTING
49	select HAVE_KERNEL_GZIP	49	select HAVE_KERNEL_GZIP
50	select HAVE_KERNEL_LZ4	50	select HAVE_KERNEL_LZ4
51	select HAVE_KERNEL_LZMA	51	select HAVE_KERNEL_LZMA
52	select HAVE_KERNEL_LZO	52	select HAVE_KERNEL_LZO
53	select HAVE_KERNEL_XZ	53	select HAVE_KERNEL_XZ
54	select HAVE_KPROBES if !XIP_KERNEL	54	select HAVE_KPROBES if !XIP_KERNEL
55	select HAVE_KRETPROBES if (HAVE_KPROBES)	55	select HAVE_KRETPROBES if (HAVE_KPROBES)
56	select HAVE_MEMBLOCK	56	select HAVE_MEMBLOCK
57	select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND	57	select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)	58	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59	select HAVE_PERF_EVENTS	59	select HAVE_PERF_EVENTS
60	select HAVE_PERF_REGS	60	select HAVE_PERF_REGS
61	select HAVE_PERF_USER_STACK_DUMP	61	select HAVE_PERF_USER_STACK_DUMP
62	select HAVE_REGS_AND_STACK_ACCESS_API	62	select HAVE_REGS_AND_STACK_ACCESS_API
63	select HAVE_SYSCALL_TRACEPOINTS	63	select HAVE_SYSCALL_TRACEPOINTS
64	select HAVE_UID16	64	select HAVE_UID16
65	select HAVE_VIRT_CPU_ACCOUNTING_GEN	65	select HAVE_VIRT_CPU_ACCOUNTING_GEN
66	select IRQ_FORCED_THREADING	66	select IRQ_FORCED_THREADING
67	select KTIME_SCALAR	67	select KTIME_SCALAR
68	select MODULES_USE_ELF_REL	68	select MODULES_USE_ELF_REL
69	select NO_BOOTMEM	69	select NO_BOOTMEM
70	select OLD_SIGACTION	70	select OLD_SIGACTION
71	select OLD_SIGSUSPEND3	71	select OLD_SIGSUSPEND3
72	select PERF_USE_VMALLOC	72	select PERF_USE_VMALLOC
73	select RTC_LIB	73	select RTC_LIB
74	select SYS_SUPPORTS_APM_EMULATION	74	select SYS_SUPPORTS_APM_EMULATION
75	# Above selects are sorted alphabetically; please add new ones	75	# Above selects are sorted alphabetically; please add new ones
76	# according to that. Thanks.	76	# according to that. Thanks.
77	help	77	help
78	The ARM series is a line of low-power-consumption RISC chip designs	78	The ARM series is a line of low-power-consumption RISC chip designs
79	licensed by ARM Ltd and targeted at embedded applications and	79	licensed by ARM Ltd and targeted at embedded applications and
80	handhelds such as the Compaq IPAQ. ARM-based PCs are no longer	80	handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81	manufactured, but legacy ARM-based PC hardware remains popular in	81	manufactured, but legacy ARM-based PC hardware remains popular in
82	Europe. There is an ARM Linux project with a web page at	82	Europe. There is an ARM Linux project with a web page at
83	<http://www.arm.linux.org.uk/>.	83	<http://www.arm.linux.org.uk/>.
84		84
85	config ARM_HAS_SG_CHAIN	85	config ARM_HAS_SG_CHAIN
86	bool	86	bool
87		87
88	config NEED_SG_DMA_LENGTH	88	config NEED_SG_DMA_LENGTH
89	bool	89	bool
90		90
91	config ARM_DMA_USE_IOMMU	91	config ARM_DMA_USE_IOMMU
92	bool	92	bool
93	select ARM_HAS_SG_CHAIN	93	select ARM_HAS_SG_CHAIN
94	select NEED_SG_DMA_LENGTH	94	select NEED_SG_DMA_LENGTH
95		95
96	if ARM_DMA_USE_IOMMU	96	if ARM_DMA_USE_IOMMU
97		97
98	config ARM_DMA_IOMMU_ALIGNMENT	98	config ARM_DMA_IOMMU_ALIGNMENT
99	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"	99	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
100	range 4 9	100	range 4 9
101	default 8	101	default 8
102	help	102	help
103	DMA mapping framework by default aligns all buffers to the smallest	103	DMA mapping framework by default aligns all buffers to the smallest
104	PAGE_SIZE order which is greater than or equal to the requested buffer	104	PAGE_SIZE order which is greater than or equal to the requested buffer
105	size. This works well for buffers up to a few hundreds kilobytes, but	105	size. This works well for buffers up to a few hundreds kilobytes, but
106	for larger buffers it just a waste of address space. Drivers which has	106	for larger buffers it just a waste of address space. Drivers which has
107	relatively small addressing window (like 64Mib) might run out of	107	relatively small addressing window (like 64Mib) might run out of
108	virtual space with just a few allocations.	108	virtual space with just a few allocations.
109		109
110	With this parameter you can specify the maximum PAGE_SIZE order for	110	With this parameter you can specify the maximum PAGE_SIZE order for
111	DMA IOMMU buffers. Larger buffers will be aligned only to this	111	DMA IOMMU buffers. Larger buffers will be aligned only to this
112	specified order. The order is expressed as a power of two multiplied	112	specified order. The order is expressed as a power of two multiplied
113	by the PAGE_SIZE.	113	by the PAGE_SIZE.
114		114
115	endif	115	endif
116		116
117	config MIGHT_HAVE_PCI	117	config MIGHT_HAVE_PCI
118	bool	118	bool
119		119
120	config SYS_SUPPORTS_APM_EMULATION	120	config SYS_SUPPORTS_APM_EMULATION
121	bool	121	bool
122		122
123	config HAVE_TCM	123	config HAVE_TCM
124	bool	124	bool
125	select GENERIC_ALLOCATOR	125	select GENERIC_ALLOCATOR
126		126
127	config HAVE_PROC_CPU	127	config HAVE_PROC_CPU
128	bool	128	bool
129		129
130	config NO_IOPORT_MAP	130	config NO_IOPORT_MAP
131	bool	131	bool
132		132
133	config EISA	133	config EISA
134	bool	134	bool
135	---help---	135	---help---
136	The Extended Industry Standard Architecture (EISA) bus was	136	The Extended Industry Standard Architecture (EISA) bus was
137	developed as an open alternative to the IBM MicroChannel bus.	137	developed as an open alternative to the IBM MicroChannel bus.
138		138
139	The EISA bus provided some of the features of the IBM MicroChannel	139	The EISA bus provided some of the features of the IBM MicroChannel
140	bus while maintaining backward compatibility with cards made for	140	bus while maintaining backward compatibility with cards made for
141	the older ISA bus. The EISA bus saw limited use between 1988 and	141	the older ISA bus. The EISA bus saw limited use between 1988 and
142	1995 when it was made obsolete by the PCI bus.	142	1995 when it was made obsolete by the PCI bus.
143		143
144	Say Y here if you are building a kernel for an EISA-based machine.	144	Say Y here if you are building a kernel for an EISA-based machine.
145		145
146	Otherwise, say N.	146	Otherwise, say N.
147		147
148	config SBUS	148	config SBUS
149	bool	149	bool
150		150
151	config STACKTRACE_SUPPORT	151	config STACKTRACE_SUPPORT
152	bool	152	bool
153	default y	153	default y
154		154
155	config HAVE_LATENCYTOP_SUPPORT	155	config HAVE_LATENCYTOP_SUPPORT
156	bool	156	bool
157	depends on !SMP	157	depends on !SMP
158	default y	158	default y
159		159
160	config LOCKDEP_SUPPORT	160	config LOCKDEP_SUPPORT
161	bool	161	bool
162	default y	162	default y
163		163
164	config TRACE_IRQFLAGS_SUPPORT	164	config TRACE_IRQFLAGS_SUPPORT
165	bool	165	bool
166	default y	166	default y
167		167
168	config RWSEM_GENERIC_SPINLOCK	168	config RWSEM_GENERIC_SPINLOCK
169	bool	169	bool
170	default y	170	default y
171		171
172	config RWSEM_XCHGADD_ALGORITHM	172	config RWSEM_XCHGADD_ALGORITHM
173	bool	173	bool
174		174
175	config ARCH_HAS_ILOG2_U32	175	config ARCH_HAS_ILOG2_U32
176	bool	176	bool
177		177
178	config ARCH_HAS_ILOG2_U64	178	config ARCH_HAS_ILOG2_U64
179	bool	179	bool
180		180
181	config ARCH_HAS_CPUFREQ	181	config ARCH_HAS_CPUFREQ
182	bool	182	bool
183	help	183	help
184	Internal node to signify that the ARCH has CPUFREQ support	184	Internal node to signify that the ARCH has CPUFREQ support
185	and that the relevant menu configurations are displayed for	185	and that the relevant menu configurations are displayed for
186	it.	186	it.
187		187
188	config ARCH_HAS_BANDGAP	188	config ARCH_HAS_BANDGAP
189	bool	189	bool
190		190
191	config GENERIC_HWEIGHT	191	config GENERIC_HWEIGHT
192	bool	192	bool
193	default y	193	default y
194		194
195	config GENERIC_CALIBRATE_DELAY	195	config GENERIC_CALIBRATE_DELAY
196	bool	196	bool
197	default y	197	default y
198		198
199	config ARCH_MAY_HAVE_PC_FDC	199	config ARCH_MAY_HAVE_PC_FDC
200	bool	200	bool
201		201
202	config ZONE_DMA	202	config ZONE_DMA
203	bool	203	bool
204		204
205	config NEED_DMA_MAP_STATE	205	config NEED_DMA_MAP_STATE
206	def_bool y	206	def_bool y
207		207
208	config ARCH_SUPPORTS_UPROBES	208	config ARCH_SUPPORTS_UPROBES
209	def_bool y	209	def_bool y
210		210
211	config ARCH_HAS_DMA_SET_COHERENT_MASK	211	config ARCH_HAS_DMA_SET_COHERENT_MASK
212	bool	212	bool
213		213
214	config GENERIC_ISA_DMA	214	config GENERIC_ISA_DMA
215	bool	215	bool
216		216
217	config FIQ	217	config FIQ
218	bool	218	bool
219		219
220	config NEED_RET_TO_USER	220	config NEED_RET_TO_USER
221	bool	221	bool
222		222
223	config ARCH_MTD_XIP	223	config ARCH_MTD_XIP
224	bool	224	bool
225		225
226	config VECTORS_BASE	226	config VECTORS_BASE
227	hex	227	hex
228	default 0xffff0000 if MMU \|\| CPU_HIGH_VECTOR	228	default 0xffff0000 if MMU \|\| CPU_HIGH_VECTOR
229	default DRAM_BASE if REMAP_VECTORS_TO_RAM	229	default DRAM_BASE if REMAP_VECTORS_TO_RAM
230	default 0x00000000	230	default 0x00000000
231	help	231	help
232	The base address of exception vectors. This must be two pages	232	The base address of exception vectors. This must be two pages
233	in size.	233	in size.
234		234
235	config ARM_PATCH_PHYS_VIRT	235	config ARM_PATCH_PHYS_VIRT
236	bool "Patch physical to virtual translations at runtime" if EMBEDDED	236	bool "Patch physical to virtual translations at runtime" if EMBEDDED
237	default y	237	default y
238	depends on !XIP_KERNEL && MMU	238	depends on !XIP_KERNEL && MMU
239	depends on !ARCH_REALVIEW \|\| !SPARSEMEM	239	depends on !ARCH_REALVIEW \|\| !SPARSEMEM
240	help	240	help
241	Patch phys-to-virt and virt-to-phys translation functions at	241	Patch phys-to-virt and virt-to-phys translation functions at
242	boot and module load time according to the position of the	242	boot and module load time according to the position of the
243	kernel in system memory.	243	kernel in system memory.
244		244
245	This can only be used with non-XIP MMU kernels where the base	245	This can only be used with non-XIP MMU kernels where the base
246	of physical memory is at a 16MB boundary.	246	of physical memory is at a 16MB boundary.
247		247
248	Only disable this option if you know that you do not require	248	Only disable this option if you know that you do not require
249	this feature (eg, building a kernel for a single machine) and	249	this feature (eg, building a kernel for a single machine) and
250	you need to shrink the kernel to the minimal size.	250	you need to shrink the kernel to the minimal size.
251		251
252	config NEED_MACH_GPIO_H	252	config NEED_MACH_GPIO_H
253	bool	253	bool
254	help	254	help
255	Select this when mach/gpio.h is required to provide special	255	Select this when mach/gpio.h is required to provide special
256	definitions for this platform. The need for mach/gpio.h should	256	definitions for this platform. The need for mach/gpio.h should
257	be avoided when possible.	257	be avoided when possible.
258		258
259	config NEED_MACH_IO_H	259	config NEED_MACH_IO_H
260	bool	260	bool
261	help	261	help
262	Select this when mach/io.h is required to provide special	262	Select this when mach/io.h is required to provide special
263	definitions for this platform. The need for mach/io.h should	263	definitions for this platform. The need for mach/io.h should
264	be avoided when possible.	264	be avoided when possible.
265		265
266	config NEED_MACH_MEMORY_H	266	config NEED_MACH_MEMORY_H
267	bool	267	bool
268	help	268	help
269	Select this when mach/memory.h is required to provide special	269	Select this when mach/memory.h is required to provide special
270	definitions for this platform. The need for mach/memory.h should	270	definitions for this platform. The need for mach/memory.h should
271	be avoided when possible.	271	be avoided when possible.
272		272
273	config PHYS_OFFSET	273	config PHYS_OFFSET
274	hex "Physical address of main memory" if MMU	274	hex "Physical address of main memory" if MMU
275	depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H	275	depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276	default DRAM_BASE if !MMU	276	default DRAM_BASE if !MMU
277	help	277	help
278	Please provide the physical address corresponding to the	278	Please provide the physical address corresponding to the
279	location of main memory in your system.	279	location of main memory in your system.
280		280
281	config GENERIC_BUG	281	config GENERIC_BUG
282	def_bool y	282	def_bool y
283	depends on BUG	283	depends on BUG
284		284
285	source "init/Kconfig"	285	source "init/Kconfig"
286		286
287	source "kernel/Kconfig.freezer"	287	source "kernel/Kconfig.freezer"
288		288
289	menu "System Type"	289	menu "System Type"
290		290
291	config MMU	291	config MMU
292	bool "MMU-based Paged Memory Management Support"	292	bool "MMU-based Paged Memory Management Support"
293	default y	293	default y
294	help	294	help
295	Select if you want MMU-based virtualised addressing space	295	Select if you want MMU-based virtualised addressing space
296	support by paged memory management. If unsure, say 'Y'.	296	support by paged memory management. If unsure, say 'Y'.
297		297
298	#	298	#
299	# The "ARM system type" choice list is ordered alphabetically by option	299	# The "ARM system type" choice list is ordered alphabetically by option
300	# text. Please add new entries in the option alphabetic order.	300	# text. Please add new entries in the option alphabetic order.
301	#	301	#
302	choice	302	choice
303	prompt "ARM system type"	303	prompt "ARM system type"
304	default ARCH_VERSATILE if !MMU	304	default ARCH_VERSATILE if !MMU
305	default ARCH_MULTIPLATFORM if MMU	305	default ARCH_MULTIPLATFORM if MMU
306		306
307	config ARCH_MULTIPLATFORM	307	config ARCH_MULTIPLATFORM
308	bool "Allow multiple platforms to be selected"	308	bool "Allow multiple platforms to be selected"
309	depends on MMU	309	depends on MMU
310	select ARCH_WANT_OPTIONAL_GPIOLIB	310	select ARCH_WANT_OPTIONAL_GPIOLIB
311	select ARM_HAS_SG_CHAIN	311	select ARM_HAS_SG_CHAIN
312	select ARM_PATCH_PHYS_VIRT	312	select ARM_PATCH_PHYS_VIRT
313	select AUTO_ZRELADDR	313	select AUTO_ZRELADDR
314	select CLKSRC_OF	314	select CLKSRC_OF
315	select COMMON_CLK	315	select COMMON_CLK
316	select GENERIC_CLOCKEVENTS	316	select GENERIC_CLOCKEVENTS
317	select MULTI_IRQ_HANDLER	317	select MULTI_IRQ_HANDLER
318	select SPARSE_IRQ	318	select SPARSE_IRQ
319	select USE_OF	319	select USE_OF
320		320
321	config ARCH_INTEGRATOR	321	config ARCH_INTEGRATOR
322	bool "ARM Ltd. Integrator family"	322	bool "ARM Ltd. Integrator family"
323	select ARCH_HAS_CPUFREQ	323	select ARCH_HAS_CPUFREQ
324	select ARM_AMBA	324	select ARM_AMBA
325	select ARM_PATCH_PHYS_VIRT	325	select ARM_PATCH_PHYS_VIRT
326	select AUTO_ZRELADDR	326	select AUTO_ZRELADDR
327	select COMMON_CLK	327	select COMMON_CLK
328	select COMMON_CLK_VERSATILE	328	select COMMON_CLK_VERSATILE
329	select GENERIC_CLOCKEVENTS	329	select GENERIC_CLOCKEVENTS
330	select HAVE_TCM	330	select HAVE_TCM
331	select ICST	331	select ICST
332	select MULTI_IRQ_HANDLER	332	select MULTI_IRQ_HANDLER
333	select NEED_MACH_MEMORY_H	333	select NEED_MACH_MEMORY_H
334	select PLAT_VERSATILE	334	select PLAT_VERSATILE
335	select SPARSE_IRQ	335	select SPARSE_IRQ
336	select USE_OF	336	select USE_OF
337	select VERSATILE_FPGA_IRQ	337	select VERSATILE_FPGA_IRQ
338	help	338	help
339	Support for ARM's Integrator platform.	339	Support for ARM's Integrator platform.
340		340
341	config ARCH_REALVIEW	341	config ARCH_REALVIEW
342	bool "ARM Ltd. RealView family"	342	bool "ARM Ltd. RealView family"
343	select ARCH_WANT_OPTIONAL_GPIOLIB	343	select ARCH_WANT_OPTIONAL_GPIOLIB
344	select ARM_AMBA	344	select ARM_AMBA
345	select ARM_TIMER_SP804	345	select ARM_TIMER_SP804
346	select COMMON_CLK	346	select COMMON_CLK
347	select COMMON_CLK_VERSATILE	347	select COMMON_CLK_VERSATILE
348	select GENERIC_CLOCKEVENTS	348	select GENERIC_CLOCKEVENTS
349	select GPIO_PL061 if GPIOLIB	349	select GPIO_PL061 if GPIOLIB
350	select ICST	350	select ICST
351	select NEED_MACH_MEMORY_H	351	select NEED_MACH_MEMORY_H
352	select PLAT_VERSATILE	352	select PLAT_VERSATILE
353	select PLAT_VERSATILE_CLCD	353	select PLAT_VERSATILE_CLCD
354	help	354	help
355	This enables support for ARM Ltd RealView boards.	355	This enables support for ARM Ltd RealView boards.
356		356
357	config ARCH_VERSATILE	357	config ARCH_VERSATILE
358	bool "ARM Ltd. Versatile family"	358	bool "ARM Ltd. Versatile family"
359	select ARCH_WANT_OPTIONAL_GPIOLIB	359	select ARCH_WANT_OPTIONAL_GPIOLIB
360	select ARM_AMBA	360	select ARM_AMBA
361	select ARM_TIMER_SP804	361	select ARM_TIMER_SP804
362	select ARM_VIC	362	select ARM_VIC
363	select CLKDEV_LOOKUP	363	select CLKDEV_LOOKUP
364	select GENERIC_CLOCKEVENTS	364	select GENERIC_CLOCKEVENTS
365	select HAVE_MACH_CLKDEV	365	select HAVE_MACH_CLKDEV
366	select ICST	366	select ICST
367	select PLAT_VERSATILE	367	select PLAT_VERSATILE
368	select PLAT_VERSATILE_CLCD	368	select PLAT_VERSATILE_CLCD
369	select PLAT_VERSATILE_CLOCK	369	select PLAT_VERSATILE_CLOCK
370	select VERSATILE_FPGA_IRQ	370	select VERSATILE_FPGA_IRQ
371	help	371	help
372	This enables support for ARM Ltd Versatile board.	372	This enables support for ARM Ltd Versatile board.
373		373
374	config ARCH_AT91	374	config ARCH_AT91
375	bool "Atmel AT91"	375	bool "Atmel AT91"
376	select ARCH_REQUIRE_GPIOLIB	376	select ARCH_REQUIRE_GPIOLIB
377	select CLKDEV_LOOKUP	377	select CLKDEV_LOOKUP
378	select IRQ_DOMAIN	378	select IRQ_DOMAIN
379	select NEED_MACH_GPIO_H	379	select NEED_MACH_GPIO_H
380	select NEED_MACH_IO_H if PCCARD	380	select NEED_MACH_IO_H if PCCARD
381	select PINCTRL	381	select PINCTRL
382	select PINCTRL_AT91 if USE_OF	382	select PINCTRL_AT91 if USE_OF
383	help	383	help
384	This enables support for systems based on Atmel	384	This enables support for systems based on Atmel
385	AT91RM9200 and AT91SAM9* processors.	385	AT91RM9200 and AT91SAM9* processors.
386		386
387	config ARCH_CLPS711X	387	config ARCH_CLPS711X
388	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"	388	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389	select ARCH_REQUIRE_GPIOLIB	389	select ARCH_REQUIRE_GPIOLIB
390	select AUTO_ZRELADDR	390	select AUTO_ZRELADDR
391	select CLKSRC_MMIO	391	select CLKSRC_MMIO
392	select COMMON_CLK	392	select COMMON_CLK
393	select CPU_ARM720T	393	select CPU_ARM720T
394	select GENERIC_CLOCKEVENTS	394	select GENERIC_CLOCKEVENTS
395	select MFD_SYSCON	395	select MFD_SYSCON
396	help	396	help
397	Support for Cirrus Logic 711x/721x/731x based boards.	397	Support for Cirrus Logic 711x/721x/731x based boards.
398		398
399	config ARCH_GEMINI	399	config ARCH_GEMINI
400	bool "Cortina Systems Gemini"	400	bool "Cortina Systems Gemini"
401	select ARCH_REQUIRE_GPIOLIB	401	select ARCH_REQUIRE_GPIOLIB
402	select CLKSRC_MMIO	402	select CLKSRC_MMIO
403	select CPU_FA526	403	select CPU_FA526
404	select GENERIC_CLOCKEVENTS	404	select GENERIC_CLOCKEVENTS
405	help	405	help
406	Support for the Cortina Systems Gemini family SoCs	406	Support for the Cortina Systems Gemini family SoCs
407		407
408	config ARCH_EBSA110	408	config ARCH_EBSA110
409	bool "EBSA-110"	409	bool "EBSA-110"
410	select ARCH_USES_GETTIMEOFFSET	410	select ARCH_USES_GETTIMEOFFSET
411	select CPU_SA110	411	select CPU_SA110
412	select ISA	412	select ISA
413	select NEED_MACH_IO_H	413	select NEED_MACH_IO_H
414	select NEED_MACH_MEMORY_H	414	select NEED_MACH_MEMORY_H
415	select NO_IOPORT_MAP	415	select NO_IOPORT_MAP
416	help	416	help
417	This is an evaluation board for the StrongARM processor available	417	This is an evaluation board for the StrongARM processor available
418	from Digital. It has limited hardware on-board, including an	418	from Digital. It has limited hardware on-board, including an
419	Ethernet interface, two PCMCIA sockets, two serial ports and a	419	Ethernet interface, two PCMCIA sockets, two serial ports and a
420	parallel port.	420	parallel port.
421		421
422	config ARCH_EFM32	422	config ARCH_EFM32
423	bool "Energy Micro efm32"	423	bool "Energy Micro efm32"
424	depends on !MMU	424	depends on !MMU
425	select ARCH_REQUIRE_GPIOLIB	425	select ARCH_REQUIRE_GPIOLIB
426	select ARM_NVIC	426	select ARM_NVIC
427	select AUTO_ZRELADDR	427	select AUTO_ZRELADDR
428	select CLKSRC_OF	428	select CLKSRC_OF
429	select COMMON_CLK	429	select COMMON_CLK
430	select CPU_V7M	430	select CPU_V7M
431	select GENERIC_CLOCKEVENTS	431	select GENERIC_CLOCKEVENTS
432	select NO_DMA	432	select NO_DMA
433	select NO_IOPORT_MAP	433	select NO_IOPORT_MAP
434	select SPARSE_IRQ	434	select SPARSE_IRQ
435	select USE_OF	435	select USE_OF
436	help	436	help
437	Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko	437	Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
438	processors.	438	processors.
439		439
440	config ARCH_EP93XX	440	config ARCH_EP93XX
441	bool "EP93xx-based"	441	bool "EP93xx-based"
442	select ARCH_HAS_HOLES_MEMORYMODEL	442	select ARCH_HAS_HOLES_MEMORYMODEL
443	select ARCH_REQUIRE_GPIOLIB	443	select ARCH_REQUIRE_GPIOLIB
444	select ARCH_USES_GETTIMEOFFSET	444	select ARCH_USES_GETTIMEOFFSET
445	select ARM_AMBA	445	select ARM_AMBA
446	select ARM_VIC	446	select ARM_VIC
447	select CLKDEV_LOOKUP	447	select CLKDEV_LOOKUP
448	select CPU_ARM920T	448	select CPU_ARM920T
449	select NEED_MACH_MEMORY_H	449	select NEED_MACH_MEMORY_H
450	help	450	help
451	This enables support for the Cirrus EP93xx series of CPUs.	451	This enables support for the Cirrus EP93xx series of CPUs.
452		452
453	config ARCH_FOOTBRIDGE	453	config ARCH_FOOTBRIDGE
454	bool "FootBridge"	454	bool "FootBridge"
455	select CPU_SA110	455	select CPU_SA110
456	select FOOTBRIDGE	456	select FOOTBRIDGE
457	select GENERIC_CLOCKEVENTS	457	select GENERIC_CLOCKEVENTS
458	select HAVE_IDE	458	select HAVE_IDE
459	select NEED_MACH_IO_H if !MMU	459	select NEED_MACH_IO_H if !MMU
460	select NEED_MACH_MEMORY_H	460	select NEED_MACH_MEMORY_H
461	help	461	help
462	Support for systems based on the DC21285 companion chip	462	Support for systems based on the DC21285 companion chip
463	("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.	463	("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
464		464
465	config ARCH_NETX	465	config ARCH_NETX
466	bool "Hilscher NetX based"	466	bool "Hilscher NetX based"
467	select ARM_VIC	467	select ARM_VIC
468	select CLKSRC_MMIO	468	select CLKSRC_MMIO
469	select CPU_ARM926T	469	select CPU_ARM926T
470	select GENERIC_CLOCKEVENTS	470	select GENERIC_CLOCKEVENTS
471	help	471	help
472	This enables support for systems based on the Hilscher NetX Soc	472	This enables support for systems based on the Hilscher NetX Soc
473		473
474	config ARCH_IOP13XX	474	config ARCH_IOP13XX
475	bool "IOP13xx-based"	475	bool "IOP13xx-based"
476	depends on MMU	476	depends on MMU
477	select CPU_XSC3	477	select CPU_XSC3
478	select NEED_MACH_MEMORY_H	478	select NEED_MACH_MEMORY_H
479	select NEED_RET_TO_USER	479	select NEED_RET_TO_USER
480	select PCI	480	select PCI
481	select PLAT_IOP	481	select PLAT_IOP
482	select VMSPLIT_1G	482	select VMSPLIT_1G
483	help	483	help
484	Support for Intel's IOP13XX (XScale) family of processors.	484	Support for Intel's IOP13XX (XScale) family of processors.
485		485
486	config ARCH_IOP32X	486	config ARCH_IOP32X
487	bool "IOP32x-based"	487	bool "IOP32x-based"
488	depends on MMU	488	depends on MMU
489	select ARCH_REQUIRE_GPIOLIB	489	select ARCH_REQUIRE_GPIOLIB
490	select CPU_XSCALE	490	select CPU_XSCALE
491	select GPIO_IOP	491	select GPIO_IOP
492	select NEED_RET_TO_USER	492	select NEED_RET_TO_USER
493	select PCI	493	select PCI
494	select PLAT_IOP	494	select PLAT_IOP
495	help	495	help
496	Support for Intel's 80219 and IOP32X (XScale) family of	496	Support for Intel's 80219 and IOP32X (XScale) family of
497	processors.	497	processors.
498		498
499	config ARCH_IOP33X	499	config ARCH_IOP33X
500	bool "IOP33x-based"	500	bool "IOP33x-based"
501	depends on MMU	501	depends on MMU
502	select ARCH_REQUIRE_GPIOLIB	502	select ARCH_REQUIRE_GPIOLIB
503	select CPU_XSCALE	503	select CPU_XSCALE
504	select GPIO_IOP	504	select GPIO_IOP
505	select NEED_RET_TO_USER	505	select NEED_RET_TO_USER
506	select PCI	506	select PCI
507	select PLAT_IOP	507	select PLAT_IOP
508	help	508	help
509	Support for Intel's IOP33X (XScale) family of processors.	509	Support for Intel's IOP33X (XScale) family of processors.
510		510
511	config ARCH_IXP4XX	511	config ARCH_IXP4XX
512	bool "IXP4xx-based"	512	bool "IXP4xx-based"
513	depends on MMU	513	depends on MMU
514	select ARCH_HAS_DMA_SET_COHERENT_MASK	514	select ARCH_HAS_DMA_SET_COHERENT_MASK
515	select ARCH_REQUIRE_GPIOLIB	515	select ARCH_REQUIRE_GPIOLIB
516	select ARCH_SUPPORTS_BIG_ENDIAN	516	select ARCH_SUPPORTS_BIG_ENDIAN
517	select CLKSRC_MMIO	517	select CLKSRC_MMIO
518	select CPU_XSCALE	518	select CPU_XSCALE
519	select DMABOUNCE if PCI	519	select DMABOUNCE if PCI
520	select GENERIC_CLOCKEVENTS	520	select GENERIC_CLOCKEVENTS
521	select MIGHT_HAVE_PCI	521	select MIGHT_HAVE_PCI
522	select NEED_MACH_IO_H	522	select NEED_MACH_IO_H
523	select USB_EHCI_BIG_ENDIAN_DESC	523	select USB_EHCI_BIG_ENDIAN_DESC
524	select USB_EHCI_BIG_ENDIAN_MMIO	524	select USB_EHCI_BIG_ENDIAN_MMIO
525	help	525	help
526	Support for Intel's IXP4XX (XScale) family of processors.	526	Support for Intel's IXP4XX (XScale) family of processors.
527		527
528	config ARCH_DOVE	528	config ARCH_DOVE
529	bool "Marvell Dove"	529	bool "Marvell Dove"
530	select ARCH_REQUIRE_GPIOLIB	530	select ARCH_REQUIRE_GPIOLIB
531	select CPU_PJ4	531	select CPU_PJ4
532	select GENERIC_CLOCKEVENTS	532	select GENERIC_CLOCKEVENTS
533	select MIGHT_HAVE_PCI	533	select MIGHT_HAVE_PCI
534	select MVEBU_MBUS	534	select MVEBU_MBUS
535	select PINCTRL	535	select PINCTRL
536	select PINCTRL_DOVE	536	select PINCTRL_DOVE
537	select PLAT_ORION_LEGACY	537	select PLAT_ORION_LEGACY
538	help	538	help
539	Support for the Marvell Dove SoC 88AP510	539	Support for the Marvell Dove SoC 88AP510
540		540
541	config ARCH_KIRKWOOD	541	config ARCH_KIRKWOOD
542	bool "Marvell Kirkwood"	542	bool "Marvell Kirkwood"
543	select ARCH_HAS_CPUFREQ	543	select ARCH_HAS_CPUFREQ
544	select ARCH_REQUIRE_GPIOLIB	544	select ARCH_REQUIRE_GPIOLIB
545	select CPU_FEROCEON	545	select CPU_FEROCEON
546	select GENERIC_CLOCKEVENTS	546	select GENERIC_CLOCKEVENTS
547	select MVEBU_MBUS	547	select MVEBU_MBUS
548	select PCI	548	select PCI
549	select PCI_QUIRKS	549	select PCI_QUIRKS
550	select PINCTRL	550	select PINCTRL
551	select PINCTRL_KIRKWOOD	551	select PINCTRL_KIRKWOOD
552	select PLAT_ORION_LEGACY	552	select PLAT_ORION_LEGACY
553	help	553	help
554	Support for the following Marvell Kirkwood series SoCs:	554	Support for the following Marvell Kirkwood series SoCs:
555	88F6180, 88F6192 and 88F6281.	555	88F6180, 88F6192 and 88F6281.
556		556
557	config ARCH_MV78XX0	557	config ARCH_MV78XX0
558	bool "Marvell MV78xx0"	558	bool "Marvell MV78xx0"
559	select ARCH_REQUIRE_GPIOLIB	559	select ARCH_REQUIRE_GPIOLIB
560	select CPU_FEROCEON	560	select CPU_FEROCEON
561	select GENERIC_CLOCKEVENTS	561	select GENERIC_CLOCKEVENTS
562	select MVEBU_MBUS	562	select MVEBU_MBUS
563	select PCI	563	select PCI
564	select PLAT_ORION_LEGACY	564	select PLAT_ORION_LEGACY
565	help	565	help
566	Support for the following Marvell MV78xx0 series SoCs:	566	Support for the following Marvell MV78xx0 series SoCs:
567	MV781x0, MV782x0.	567	MV781x0, MV782x0.
568		568
569	config ARCH_ORION5X	569	config ARCH_ORION5X
570	bool "Marvell Orion"	570	bool "Marvell Orion"
571	depends on MMU	571	depends on MMU
572	select ARCH_REQUIRE_GPIOLIB	572	select ARCH_REQUIRE_GPIOLIB
573	select CPU_FEROCEON	573	select CPU_FEROCEON
574	select GENERIC_CLOCKEVENTS	574	select GENERIC_CLOCKEVENTS
575	select MVEBU_MBUS	575	select MVEBU_MBUS
576	select PCI	576	select PCI
577	select PLAT_ORION_LEGACY	577	select PLAT_ORION_LEGACY
578	help	578	help
579	Support for the following Marvell Orion 5x series SoCs:	579	Support for the following Marvell Orion 5x series SoCs:
580	Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),	580	Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
581	Orion-2 (5281), Orion-1-90 (6183).	581	Orion-2 (5281), Orion-1-90 (6183).
582		582
583	config ARCH_MMP	583	config ARCH_MMP
584	bool "Marvell PXA168/910/MMP2"	584	bool "Marvell PXA168/910/MMP2"
585	depends on MMU	585	depends on MMU
586	select ARCH_REQUIRE_GPIOLIB	586	select ARCH_REQUIRE_GPIOLIB
587	select CLKDEV_LOOKUP	587	select CLKDEV_LOOKUP
588	select GENERIC_ALLOCATOR	588	select GENERIC_ALLOCATOR
589	select GENERIC_CLOCKEVENTS	589	select GENERIC_CLOCKEVENTS
590	select GPIO_PXA	590	select GPIO_PXA
591	select IRQ_DOMAIN	591	select IRQ_DOMAIN
592	select MULTI_IRQ_HANDLER	592	select MULTI_IRQ_HANDLER
593	select PINCTRL	593	select PINCTRL
594	select PLAT_PXA	594	select PLAT_PXA
595	select SPARSE_IRQ	595	select SPARSE_IRQ
596	help	596	help
597	Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.	597	Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598		598
599	config ARCH_KS8695	599	config ARCH_KS8695
600	bool "Micrel/Kendin KS8695"	600	bool "Micrel/Kendin KS8695"
601	select ARCH_REQUIRE_GPIOLIB	601	select ARCH_REQUIRE_GPIOLIB
602	select CLKSRC_MMIO	602	select CLKSRC_MMIO
603	select CPU_ARM922T	603	select CPU_ARM922T
604	select GENERIC_CLOCKEVENTS	604	select GENERIC_CLOCKEVENTS
605	select NEED_MACH_MEMORY_H	605	select NEED_MACH_MEMORY_H
606	help	606	help
607	Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based	607	Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
608	System-on-Chip devices.	608	System-on-Chip devices.
609		609
610	config ARCH_W90X900	610	config ARCH_W90X900
611	bool "Nuvoton W90X900 CPU"	611	bool "Nuvoton W90X900 CPU"
612	select ARCH_REQUIRE_GPIOLIB	612	select ARCH_REQUIRE_GPIOLIB
613	select CLKDEV_LOOKUP	613	select CLKDEV_LOOKUP
614	select CLKSRC_MMIO	614	select CLKSRC_MMIO
615	select CPU_ARM926T	615	select CPU_ARM926T
616	select GENERIC_CLOCKEVENTS	616	select GENERIC_CLOCKEVENTS
617	help	617	help
618	Support for Nuvoton (Winbond logic dept.) ARM9 processor,	618	Support for Nuvoton (Winbond logic dept.) ARM9 processor,
619	At present, the w90x900 has been renamed nuc900, regarding	619	At present, the w90x900 has been renamed nuc900, regarding
620	the ARM series product line, you can login the following	620	the ARM series product line, you can login the following
621	link address to know more.	621	link address to know more.
622		622
623	<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/	623	<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
624	ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>	624	ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625		625
626	config ARCH_LPC32XX	626	config ARCH_LPC32XX
627	bool "NXP LPC32XX"	627	bool "NXP LPC32XX"
628	select ARCH_REQUIRE_GPIOLIB	628	select ARCH_REQUIRE_GPIOLIB
629	select ARM_AMBA	629	select ARM_AMBA
630	select CLKDEV_LOOKUP	630	select CLKDEV_LOOKUP
631	select CLKSRC_MMIO	631	select CLKSRC_MMIO
632	select CPU_ARM926T	632	select CPU_ARM926T
633	select GENERIC_CLOCKEVENTS	633	select GENERIC_CLOCKEVENTS
634	select HAVE_IDE	634	select HAVE_IDE
635	select USE_OF	635	select USE_OF
636	help	636	help
637	Support for the NXP LPC32XX family of processors	637	Support for the NXP LPC32XX family of processors
638		638
639	config ARCH_PXA	639	config ARCH_PXA
640	bool "PXA2xx/PXA3xx-based"	640	bool "PXA2xx/PXA3xx-based"
641	depends on MMU	641	depends on MMU
642	select ARCH_HAS_CPUFREQ	642	select ARCH_HAS_CPUFREQ
643	select ARCH_MTD_XIP	643	select ARCH_MTD_XIP
644	select ARCH_REQUIRE_GPIOLIB	644	select ARCH_REQUIRE_GPIOLIB
645	select ARM_CPU_SUSPEND if PM	645	select ARM_CPU_SUSPEND if PM
646	select AUTO_ZRELADDR	646	select AUTO_ZRELADDR
647	select CLKDEV_LOOKUP	647	select CLKDEV_LOOKUP
648	select CLKSRC_MMIO	648	select CLKSRC_MMIO
649	select GENERIC_CLOCKEVENTS	649	select GENERIC_CLOCKEVENTS
650	select GPIO_PXA	650	select GPIO_PXA
651	select HAVE_IDE	651	select HAVE_IDE
652	select MULTI_IRQ_HANDLER	652	select MULTI_IRQ_HANDLER
653	select PLAT_PXA	653	select PLAT_PXA
654	select SPARSE_IRQ	654	select SPARSE_IRQ
655	help	655	help
656	Support for Intel/Marvell's PXA2xx/PXA3xx processor line.	656	Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
657		657
658	config ARCH_MSM	658	config ARCH_MSM
659	bool "Qualcomm MSM (non-multiplatform)"	659	bool "Qualcomm MSM (non-multiplatform)"
660	select ARCH_REQUIRE_GPIOLIB	660	select ARCH_REQUIRE_GPIOLIB
661	select COMMON_CLK	661	select COMMON_CLK
662	select GENERIC_CLOCKEVENTS	662	select GENERIC_CLOCKEVENTS
663	help	663	help
664	Support for Qualcomm MSM/QSD based systems. This runs on the	664	Support for Qualcomm MSM/QSD based systems. This runs on the
665	apps processor of the MSM/QSD and depends on a shared memory	665	apps processor of the MSM/QSD and depends on a shared memory
666	interface to the modem processor which runs the baseband	666	interface to the modem processor which runs the baseband
667	stack and controls some vital subsystems	667	stack and controls some vital subsystems
668	(clock and power control, etc).	668	(clock and power control, etc).
669		669
670	config ARCH_SHMOBILE_LEGACY	670	config ARCH_SHMOBILE_LEGACY
671	bool "Renesas ARM SoCs (non-multiplatform)"	671	bool "Renesas ARM SoCs (non-multiplatform)"
672	select ARCH_SHMOBILE	672	select ARCH_SHMOBILE
673	select ARM_PATCH_PHYS_VIRT	673	select ARM_PATCH_PHYS_VIRT
674	select CLKDEV_LOOKUP	674	select CLKDEV_LOOKUP
675	select GENERIC_CLOCKEVENTS	675	select GENERIC_CLOCKEVENTS
676	select HAVE_ARM_SCU if SMP	676	select HAVE_ARM_SCU if SMP
677	select HAVE_ARM_TWD if SMP	677	select HAVE_ARM_TWD if SMP
678	select HAVE_MACH_CLKDEV	678	select HAVE_MACH_CLKDEV
679	select HAVE_SMP	679	select HAVE_SMP
680	select MIGHT_HAVE_CACHE_L2X0	680	select MIGHT_HAVE_CACHE_L2X0
681	select MULTI_IRQ_HANDLER	681	select MULTI_IRQ_HANDLER
682	select NO_IOPORT_MAP	682	select NO_IOPORT_MAP
683	select PINCTRL	683	select PINCTRL
684	select PM_GENERIC_DOMAINS if PM	684	select PM_GENERIC_DOMAINS if PM
685	select SPARSE_IRQ	685	select SPARSE_IRQ
686	help	686	help
687	Support for Renesas ARM SoC platforms using a non-multiplatform	687	Support for Renesas ARM SoC platforms using a non-multiplatform
688	kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car	688	kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
689	and RZ families.	689	and RZ families.
690		690
691	config ARCH_RPC	691	config ARCH_RPC
692	bool "RiscPC"	692	bool "RiscPC"
693	select ARCH_ACORN	693	select ARCH_ACORN
694	select ARCH_MAY_HAVE_PC_FDC	694	select ARCH_MAY_HAVE_PC_FDC
695	select ARCH_SPARSEMEM_ENABLE	695	select ARCH_SPARSEMEM_ENABLE
696	select ARCH_USES_GETTIMEOFFSET	696	select ARCH_USES_GETTIMEOFFSET
697	select CPU_SA110	697	select CPU_SA110
698	select FIQ	698	select FIQ
699	select HAVE_IDE	699	select HAVE_IDE
700	select HAVE_PATA_PLATFORM	700	select HAVE_PATA_PLATFORM
701	select ISA_DMA_API	701	select ISA_DMA_API
702	select NEED_MACH_IO_H	702	select NEED_MACH_IO_H
703	select NEED_MACH_MEMORY_H	703	select NEED_MACH_MEMORY_H
704	select NO_IOPORT_MAP	704	select NO_IOPORT_MAP
705	select VIRT_TO_BUS	705	select VIRT_TO_BUS
706	help	706	help
707	On the Acorn Risc-PC, Linux can support the internal IDE disk and	707	On the Acorn Risc-PC, Linux can support the internal IDE disk and
708	CD-ROM interface, serial and parallel port, and the floppy drive.	708	CD-ROM interface, serial and parallel port, and the floppy drive.
709		709
710	config ARCH_SA1100	710	config ARCH_SA1100
711	bool "SA1100-based"	711	bool "SA1100-based"
712	select ARCH_HAS_CPUFREQ	712	select ARCH_HAS_CPUFREQ
713	select ARCH_MTD_XIP	713	select ARCH_MTD_XIP
714	select ARCH_REQUIRE_GPIOLIB	714	select ARCH_REQUIRE_GPIOLIB
715	select ARCH_SPARSEMEM_ENABLE	715	select ARCH_SPARSEMEM_ENABLE
716	select CLKDEV_LOOKUP	716	select CLKDEV_LOOKUP
717	select CLKSRC_MMIO	717	select CLKSRC_MMIO
718	select CPU_FREQ	718	select CPU_FREQ
719	select CPU_SA1100	719	select CPU_SA1100
720	select GENERIC_CLOCKEVENTS	720	select GENERIC_CLOCKEVENTS
721	select HAVE_IDE	721	select HAVE_IDE
722	select ISA	722	select ISA
723	select NEED_MACH_MEMORY_H	723	select NEED_MACH_MEMORY_H
724	select SPARSE_IRQ	724	select SPARSE_IRQ
725	help	725	help
726	Support for StrongARM 11x0 based boards.	726	Support for StrongARM 11x0 based boards.
727		727
728	config ARCH_S3C24XX	728	config ARCH_S3C24XX
729	bool "Samsung S3C24XX SoCs"	729	bool "Samsung S3C24XX SoCs"
730	select ARCH_HAS_CPUFREQ	730	select ARCH_HAS_CPUFREQ
731	select ARCH_REQUIRE_GPIOLIB	731	select ARCH_REQUIRE_GPIOLIB
732	select ATAGS	732	select ATAGS
733	select CLKDEV_LOOKUP	733	select CLKDEV_LOOKUP
734	select CLKSRC_SAMSUNG_PWM	734	select CLKSRC_SAMSUNG_PWM
735	select GENERIC_CLOCKEVENTS	735	select GENERIC_CLOCKEVENTS
736	select GPIO_SAMSUNG	736	select GPIO_SAMSUNG
737	select HAVE_S3C2410_I2C if I2C	737	select HAVE_S3C2410_I2C if I2C
738	select HAVE_S3C2410_WATCHDOG if WATCHDOG	738	select HAVE_S3C2410_WATCHDOG if WATCHDOG
739	select HAVE_S3C_RTC if RTC_CLASS	739	select HAVE_S3C_RTC if RTC_CLASS
740	select MULTI_IRQ_HANDLER	740	select MULTI_IRQ_HANDLER
741	select NEED_MACH_IO_H	741	select NEED_MACH_IO_H
742	select SAMSUNG_ATAGS	742	select SAMSUNG_ATAGS
743	help	743	help
744	Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443	744	Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
745	and S3C2450 SoCs based systems, such as the Simtec Electronics BAST	745	and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
746	(<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the	746	(<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
747	Samsung SMDK2410 development board (and derivatives).	747	Samsung SMDK2410 development board (and derivatives).
748		748
749	config ARCH_S3C64XX	749	config ARCH_S3C64XX
750	bool "Samsung S3C64XX"	750	bool "Samsung S3C64XX"
751	select ARCH_HAS_CPUFREQ	751	select ARCH_HAS_CPUFREQ
752	select ARCH_REQUIRE_GPIOLIB	752	select ARCH_REQUIRE_GPIOLIB
753	select ARM_AMBA	753	select ARM_AMBA
754	select ARM_VIC	754	select ARM_VIC
755	select ATAGS	755	select ATAGS
756	select CLKDEV_LOOKUP	756	select CLKDEV_LOOKUP
757	select CLKSRC_SAMSUNG_PWM	757	select CLKSRC_SAMSUNG_PWM
758	select COMMON_CLK	758	select COMMON_CLK
759	select CPU_V6K	759	select CPU_V6K
760	select GENERIC_CLOCKEVENTS	760	select GENERIC_CLOCKEVENTS
761	select GPIO_SAMSUNG	761	select GPIO_SAMSUNG
762	select HAVE_S3C2410_I2C if I2C	762	select HAVE_S3C2410_I2C if I2C
763	select HAVE_S3C2410_WATCHDOG if WATCHDOG	763	select HAVE_S3C2410_WATCHDOG if WATCHDOG
764	select HAVE_TCM	764	select HAVE_TCM
765	select NO_IOPORT_MAP	765	select NO_IOPORT_MAP
766	select PLAT_SAMSUNG	766	select PLAT_SAMSUNG
767	select PM_GENERIC_DOMAINS if PM	767	select PM_GENERIC_DOMAINS if PM
768	select S3C_DEV_NAND	768	select S3C_DEV_NAND
769	select S3C_GPIO_TRACK	769	select S3C_GPIO_TRACK
770	select SAMSUNG_ATAGS	770	select SAMSUNG_ATAGS
771	select SAMSUNG_WAKEMASK	771	select SAMSUNG_WAKEMASK
772	select SAMSUNG_WDT_RESET	772	select SAMSUNG_WDT_RESET
773	help	773	help
774	Samsung S3C64XX series based systems	774	Samsung S3C64XX series based systems
775		775
776	config ARCH_S5P64X0	776	config ARCH_S5P64X0
777	bool "Samsung S5P6440 S5P6450"	777	bool "Samsung S5P6440 S5P6450"
778	select ATAGS	778	select ATAGS
779	select CLKDEV_LOOKUP	779	select CLKDEV_LOOKUP
780	select CLKSRC_SAMSUNG_PWM	780	select CLKSRC_SAMSUNG_PWM
781	select CPU_V6	781	select CPU_V6
782	select GENERIC_CLOCKEVENTS	782	select GENERIC_CLOCKEVENTS
783	select GPIO_SAMSUNG	783	select GPIO_SAMSUNG
784	select HAVE_S3C2410_I2C if I2C	784	select HAVE_S3C2410_I2C if I2C
785	select HAVE_S3C2410_WATCHDOG if WATCHDOG	785	select HAVE_S3C2410_WATCHDOG if WATCHDOG
786	select HAVE_S3C_RTC if RTC_CLASS	786	select HAVE_S3C_RTC if RTC_CLASS
787	select NEED_MACH_GPIO_H	787	select NEED_MACH_GPIO_H
788	select SAMSUNG_ATAGS	788	select SAMSUNG_ATAGS
789	select SAMSUNG_WDT_RESET	789	select SAMSUNG_WDT_RESET
790	help	790	help
791	Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,	791	Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
792	SMDK6450.	792	SMDK6450.
793		793
794	config ARCH_S5PC100	794	config ARCH_S5PC100
795	bool "Samsung S5PC100"	795	bool "Samsung S5PC100"
796	select ARCH_REQUIRE_GPIOLIB	796	select ARCH_REQUIRE_GPIOLIB
797	select ATAGS	797	select ATAGS
798	select CLKDEV_LOOKUP	798	select CLKDEV_LOOKUP
799	select CLKSRC_SAMSUNG_PWM	799	select CLKSRC_SAMSUNG_PWM
800	select CPU_V7	800	select CPU_V7
801	select GENERIC_CLOCKEVENTS	801	select GENERIC_CLOCKEVENTS
802	select GPIO_SAMSUNG	802	select GPIO_SAMSUNG
803	select HAVE_S3C2410_I2C if I2C	803	select HAVE_S3C2410_I2C if I2C
804	select HAVE_S3C2410_WATCHDOG if WATCHDOG	804	select HAVE_S3C2410_WATCHDOG if WATCHDOG
805	select HAVE_S3C_RTC if RTC_CLASS	805	select HAVE_S3C_RTC if RTC_CLASS
806	select NEED_MACH_GPIO_H	806	select NEED_MACH_GPIO_H
807	select SAMSUNG_ATAGS	807	select SAMSUNG_ATAGS
808	select SAMSUNG_WDT_RESET	808	select SAMSUNG_WDT_RESET
809	help	809	help
810	Samsung S5PC100 series based systems	810	Samsung S5PC100 series based systems
811		811
812	config ARCH_S5PV210	812	config ARCH_S5PV210
813	bool "Samsung S5PV210/S5PC110"	813	bool "Samsung S5PV210/S5PC110"
814	select ARCH_HAS_CPUFREQ	814	select ARCH_HAS_CPUFREQ
815	select ARCH_HAS_HOLES_MEMORYMODEL	815	select ARCH_HAS_HOLES_MEMORYMODEL
816	select ARCH_SPARSEMEM_ENABLE	816	select ARCH_SPARSEMEM_ENABLE
817	select ATAGS	817	select ATAGS
818	select CLKDEV_LOOKUP	818	select CLKDEV_LOOKUP
819	select CLKSRC_SAMSUNG_PWM	819	select CLKSRC_SAMSUNG_PWM
820	select CPU_V7	820	select CPU_V7
821	select GENERIC_CLOCKEVENTS	821	select GENERIC_CLOCKEVENTS
822	select GPIO_SAMSUNG	822	select GPIO_SAMSUNG
823	select HAVE_S3C2410_I2C if I2C	823	select HAVE_S3C2410_I2C if I2C
824	select HAVE_S3C2410_WATCHDOG if WATCHDOG	824	select HAVE_S3C2410_WATCHDOG if WATCHDOG
825	select HAVE_S3C_RTC if RTC_CLASS	825	select HAVE_S3C_RTC if RTC_CLASS
826	select NEED_MACH_GPIO_H	826	select NEED_MACH_GPIO_H
827	select NEED_MACH_MEMORY_H	827	select NEED_MACH_MEMORY_H
828	select SAMSUNG_ATAGS	828	select SAMSUNG_ATAGS
829	help	829	help
830	Samsung S5PV210/S5PC110 series based systems	830	Samsung S5PV210/S5PC110 series based systems
831		831
832	config ARCH_EXYNOS	832	config ARCH_EXYNOS
833	bool "Samsung EXYNOS"	833	bool "Samsung EXYNOS"
834	select ARCH_HAS_CPUFREQ	834	select ARCH_HAS_CPUFREQ
835	select ARCH_HAS_HOLES_MEMORYMODEL	835	select ARCH_HAS_HOLES_MEMORYMODEL
836	select ARCH_REQUIRE_GPIOLIB	836	select ARCH_REQUIRE_GPIOLIB
837	select ARCH_SPARSEMEM_ENABLE	837	select ARCH_SPARSEMEM_ENABLE
838	select ARM_GIC	838	select ARM_GIC
839	select COMMON_CLK	839	select COMMON_CLK
840	select CPU_V7	840	select CPU_V7
841	select GENERIC_CLOCKEVENTS	841	select GENERIC_CLOCKEVENTS
842	select HAVE_S3C2410_I2C if I2C	842	select HAVE_S3C2410_I2C if I2C
843	select HAVE_S3C2410_WATCHDOG if WATCHDOG	843	select HAVE_S3C2410_WATCHDOG if WATCHDOG
844	select HAVE_S3C_RTC if RTC_CLASS	844	select HAVE_S3C_RTC if RTC_CLASS
845	select NEED_MACH_MEMORY_H	845	select NEED_MACH_MEMORY_H
846	select SPARSE_IRQ	846	select SPARSE_IRQ
847	select USE_OF	847	select USE_OF
848	help	848	help
849	Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)	849	Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
850		850
851	config ARCH_DAVINCI	851	config ARCH_DAVINCI
852	bool "TI DaVinci"	852	bool "TI DaVinci"
853	select ARCH_HAS_HOLES_MEMORYMODEL	853	select ARCH_HAS_HOLES_MEMORYMODEL
854	select ARCH_REQUIRE_GPIOLIB	854	select ARCH_REQUIRE_GPIOLIB
855	select CLKDEV_LOOKUP	855	select CLKDEV_LOOKUP
856	select GENERIC_ALLOCATOR	856	select GENERIC_ALLOCATOR
857	select GENERIC_CLOCKEVENTS	857	select GENERIC_CLOCKEVENTS
858	select GENERIC_IRQ_CHIP	858	select GENERIC_IRQ_CHIP
859	select HAVE_IDE	859	select HAVE_IDE
860	select TI_PRIV_EDMA	860	select TI_PRIV_EDMA
861	select USE_OF	861	select USE_OF
862	select ZONE_DMA	862	select ZONE_DMA
863	help	863	help
864	Support for TI's DaVinci platform.	864	Support for TI's DaVinci platform.
865		865
866	config ARCH_OMAP1	866	config ARCH_OMAP1
867	bool "TI OMAP1"	867	bool "TI OMAP1"
868	depends on MMU	868	depends on MMU
869	select ARCH_HAS_CPUFREQ	869	select ARCH_HAS_CPUFREQ
870	select ARCH_HAS_HOLES_MEMORYMODEL	870	select ARCH_HAS_HOLES_MEMORYMODEL
871	select ARCH_OMAP	871	select ARCH_OMAP
872	select ARCH_REQUIRE_GPIOLIB	872	select ARCH_REQUIRE_GPIOLIB
873	select CLKDEV_LOOKUP	873	select CLKDEV_LOOKUP
874	select CLKSRC_MMIO	874	select CLKSRC_MMIO
875	select GENERIC_CLOCKEVENTS	875	select GENERIC_CLOCKEVENTS
876	select GENERIC_IRQ_CHIP	876	select GENERIC_IRQ_CHIP
877	select HAVE_IDE	877	select HAVE_IDE
878	select IRQ_DOMAIN	878	select IRQ_DOMAIN
879	select NEED_MACH_IO_H if PCCARD	879	select NEED_MACH_IO_H if PCCARD
880	select NEED_MACH_MEMORY_H	880	select NEED_MACH_MEMORY_H
881	help	881	help
882	Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)	882	Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
883		883
884	endchoice	884	endchoice
885		885
886	menu "Multiple platform selection"	886	menu "Multiple platform selection"
887	depends on ARCH_MULTIPLATFORM	887	depends on ARCH_MULTIPLATFORM
888		888
889	comment "CPU Core family selection"	889	comment "CPU Core family selection"
890		890
891	config ARCH_MULTI_V4	891	config ARCH_MULTI_V4
892	bool "ARMv4 based platforms (FA526)"	892	bool "ARMv4 based platforms (FA526)"
893	depends on !ARCH_MULTI_V6_V7	893	depends on !ARCH_MULTI_V6_V7
894	select ARCH_MULTI_V4_V5	894	select ARCH_MULTI_V4_V5
895	select CPU_FA526	895	select CPU_FA526
896		896
897	config ARCH_MULTI_V4T	897	config ARCH_MULTI_V4T
898	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"	898	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
899	depends on !ARCH_MULTI_V6_V7	899	depends on !ARCH_MULTI_V6_V7
900	select ARCH_MULTI_V4_V5	900	select ARCH_MULTI_V4_V5
901	select CPU_ARM920T if !(CPU_ARM7TDMI \|\| CPU_ARM720T \|\| \	901	select CPU_ARM920T if !(CPU_ARM7TDMI \|\| CPU_ARM720T \|\| \
902	CPU_ARM740T \|\| CPU_ARM9TDMI \|\| CPU_ARM922T \|\| \	902	CPU_ARM740T \|\| CPU_ARM9TDMI \|\| CPU_ARM922T \|\| \
903	CPU_ARM925T \|\| CPU_ARM940T)	903	CPU_ARM925T \|\| CPU_ARM940T)
904		904
905	config ARCH_MULTI_V5	905	config ARCH_MULTI_V5
906	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"	906	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
907	depends on !ARCH_MULTI_V6_V7	907	depends on !ARCH_MULTI_V6_V7
908	select ARCH_MULTI_V4_V5	908	select ARCH_MULTI_V4_V5
909	select CPU_ARM926T if !(CPU_ARM946E \|\| CPU_ARM1020 \|\| \	909	select CPU_ARM926T if !(CPU_ARM946E \|\| CPU_ARM1020 \|\| \
910	CPU_ARM1020E \|\| CPU_ARM1022 \|\| CPU_ARM1026 \|\| \	910	CPU_ARM1020E \|\| CPU_ARM1022 \|\| CPU_ARM1026 \|\| \
911	CPU_XSCALE \|\| CPU_XSC3 \|\| CPU_MOHAWK \|\| CPU_FEROCEON)	911	CPU_XSCALE \|\| CPU_XSC3 \|\| CPU_MOHAWK \|\| CPU_FEROCEON)
912		912
913	config ARCH_MULTI_V4_V5	913	config ARCH_MULTI_V4_V5
914	bool	914	bool
915		915
916	config ARCH_MULTI_V6	916	config ARCH_MULTI_V6
917	bool "ARMv6 based platforms (ARM11)"	917	bool "ARMv6 based platforms (ARM11)"
918	select ARCH_MULTI_V6_V7	918	select ARCH_MULTI_V6_V7
919	select CPU_V6K	919	select CPU_V6K
920		920
921	config ARCH_MULTI_V7	921	config ARCH_MULTI_V7
922	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"	922	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
923	default y	923	default y
924	select ARCH_MULTI_V6_V7	924	select ARCH_MULTI_V6_V7
925	select CPU_V7	925	select CPU_V7
926	select HAVE_SMP	926	select HAVE_SMP
927		927
928	config ARCH_MULTI_V6_V7	928	config ARCH_MULTI_V6_V7
929	bool	929	bool
930	select MIGHT_HAVE_CACHE_L2X0	930	select MIGHT_HAVE_CACHE_L2X0
931		931
932	config ARCH_MULTI_CPU_AUTO	932	config ARCH_MULTI_CPU_AUTO
933	def_bool !(ARCH_MULTI_V4 \|\| ARCH_MULTI_V4T \|\| ARCH_MULTI_V6_V7)	933	def_bool !(ARCH_MULTI_V4 \|\| ARCH_MULTI_V4T \|\| ARCH_MULTI_V6_V7)
934	select ARCH_MULTI_V5	934	select ARCH_MULTI_V5
935		935
936	endmenu	936	endmenu
937		937
938	config ARCH_VIRT	938	config ARCH_VIRT
939	bool "Dummy Virtual Machine" if ARCH_MULTI_V7	939	bool "Dummy Virtual Machine" if ARCH_MULTI_V7
940	select ARM_AMBA	940	select ARM_AMBA
941	select ARM_GIC	941	select ARM_GIC
942	select ARM_PSCI	942	select ARM_PSCI
943	select HAVE_ARM_ARCH_TIMER	943	select HAVE_ARM_ARCH_TIMER
944		944
945	#	945	#
946	# This is sorted alphabetically by mach-* pathname. However, plat-*	946	# This is sorted alphabetically by mach-* pathname. However, plat-*
947	# Kconfigs may be included either alphabetically (according to the	947	# Kconfigs may be included either alphabetically (according to the
948	# plat- suffix) or along side the corresponding mach-* source.	948	# plat- suffix) or along side the corresponding mach-* source.
949	#	949	#
950	source "arch/arm/mach-mvebu/Kconfig"	950	source "arch/arm/mach-mvebu/Kconfig"
951		951
952	source "arch/arm/mach-at91/Kconfig"	952	source "arch/arm/mach-at91/Kconfig"
953		953
954	source "arch/arm/mach-bcm/Kconfig"	954	source "arch/arm/mach-bcm/Kconfig"
955		955
956	source "arch/arm/mach-berlin/Kconfig"	956	source "arch/arm/mach-berlin/Kconfig"
957		957
958	source "arch/arm/mach-clps711x/Kconfig"	958	source "arch/arm/mach-clps711x/Kconfig"
959		959
960	source "arch/arm/mach-cns3xxx/Kconfig"	960	source "arch/arm/mach-cns3xxx/Kconfig"
961		961
962	source "arch/arm/mach-davinci/Kconfig"	962	source "arch/arm/mach-davinci/Kconfig"
963		963
964	source "arch/arm/mach-dove/Kconfig"	964	source "arch/arm/mach-dove/Kconfig"
965		965
966	source "arch/arm/mach-ep93xx/Kconfig"	966	source "arch/arm/mach-ep93xx/Kconfig"
967		967
968	source "arch/arm/mach-footbridge/Kconfig"	968	source "arch/arm/mach-footbridge/Kconfig"
969		969
970	source "arch/arm/mach-gemini/Kconfig"	970	source "arch/arm/mach-gemini/Kconfig"
971		971
972	source "arch/arm/mach-highbank/Kconfig"	972	source "arch/arm/mach-highbank/Kconfig"
973		973
974	source "arch/arm/mach-hisi/Kconfig"	974	source "arch/arm/mach-hisi/Kconfig"
975		975
976	source "arch/arm/mach-integrator/Kconfig"	976	source "arch/arm/mach-integrator/Kconfig"
977		977
978	source "arch/arm/mach-iop32x/Kconfig"	978	source "arch/arm/mach-iop32x/Kconfig"
979		979
980	source "arch/arm/mach-iop33x/Kconfig"	980	source "arch/arm/mach-iop33x/Kconfig"
981		981
982	source "arch/arm/mach-iop13xx/Kconfig"	982	source "arch/arm/mach-iop13xx/Kconfig"
983		983
984	source "arch/arm/mach-ixp4xx/Kconfig"	984	source "arch/arm/mach-ixp4xx/Kconfig"
985		985
986	source "arch/arm/mach-keystone/Kconfig"	986	source "arch/arm/mach-keystone/Kconfig"
987		987
988	source "arch/arm/mach-kirkwood/Kconfig"	988	source "arch/arm/mach-kirkwood/Kconfig"
989		989
990	source "arch/arm/mach-ks8695/Kconfig"	990	source "arch/arm/mach-ks8695/Kconfig"
991		991
992	source "arch/arm/mach-msm/Kconfig"	992	source "arch/arm/mach-msm/Kconfig"
993		993
994	source "arch/arm/mach-moxart/Kconfig"	994	source "arch/arm/mach-moxart/Kconfig"
995		995
996	source "arch/arm/mach-mv78xx0/Kconfig"	996	source "arch/arm/mach-mv78xx0/Kconfig"
997		997
998	source "arch/arm/mach-imx/Kconfig"	998	source "arch/arm/mach-imx/Kconfig"
999		999
1000	source "arch/arm/mach-mxs/Kconfig"	1000	source "arch/arm/mach-mxs/Kconfig"
1001		1001
1002	source "arch/arm/mach-netx/Kconfig"	1002	source "arch/arm/mach-netx/Kconfig"
1003		1003
1004	source "arch/arm/mach-nomadik/Kconfig"	1004	source "arch/arm/mach-nomadik/Kconfig"
1005		1005
1006	source "arch/arm/mach-nspire/Kconfig"	1006	source "arch/arm/mach-nspire/Kconfig"
1007		1007
1008	source "arch/arm/plat-omap/Kconfig"	1008	source "arch/arm/plat-omap/Kconfig"
1009		1009
1010	source "arch/arm/mach-omap1/Kconfig"	1010	source "arch/arm/mach-omap1/Kconfig"
1011		1011
1012	source "arch/arm/mach-omap2/Kconfig"	1012	source "arch/arm/mach-omap2/Kconfig"
1013		1013
1014	source "arch/arm/mach-orion5x/Kconfig"	1014	source "arch/arm/mach-orion5x/Kconfig"
1015		1015
1016	source "arch/arm/mach-picoxcell/Kconfig"	1016	source "arch/arm/mach-picoxcell/Kconfig"
1017		1017
1018	source "arch/arm/mach-pxa/Kconfig"	1018	source "arch/arm/mach-pxa/Kconfig"
1019	source "arch/arm/plat-pxa/Kconfig"	1019	source "arch/arm/plat-pxa/Kconfig"
1020		1020
1021	source "arch/arm/mach-mmp/Kconfig"	1021	source "arch/arm/mach-mmp/Kconfig"
1022		1022
1023	source "arch/arm/mach-qcom/Kconfig"	1023	source "arch/arm/mach-qcom/Kconfig"
1024		1024
1025	source "arch/arm/mach-realview/Kconfig"	1025	source "arch/arm/mach-realview/Kconfig"
1026		1026
1027	source "arch/arm/mach-rockchip/Kconfig"	1027	source "arch/arm/mach-rockchip/Kconfig"
1028		1028
1029	source "arch/arm/mach-sa1100/Kconfig"	1029	source "arch/arm/mach-sa1100/Kconfig"
1030		1030
1031	source "arch/arm/plat-samsung/Kconfig"	1031	source "arch/arm/plat-samsung/Kconfig"
1032		1032
1033	source "arch/arm/mach-socfpga/Kconfig"	1033	source "arch/arm/mach-socfpga/Kconfig"
1034		1034
1035	source "arch/arm/mach-spear/Kconfig"	1035	source "arch/arm/mach-spear/Kconfig"
1036		1036
1037	source "arch/arm/mach-sti/Kconfig"	1037	source "arch/arm/mach-sti/Kconfig"
1038		1038
1039	source "arch/arm/mach-s3c24xx/Kconfig"	1039	source "arch/arm/mach-s3c24xx/Kconfig"
1040		1040
1041	source "arch/arm/mach-s3c64xx/Kconfig"	1041	source "arch/arm/mach-s3c64xx/Kconfig"
1042		1042
1043	source "arch/arm/mach-s5p64x0/Kconfig"	1043	source "arch/arm/mach-s5p64x0/Kconfig"
1044		1044
1045	source "arch/arm/mach-s5pc100/Kconfig"	1045	source "arch/arm/mach-s5pc100/Kconfig"
1046		1046
1047	source "arch/arm/mach-s5pv210/Kconfig"	1047	source "arch/arm/mach-s5pv210/Kconfig"
1048		1048
1049	source "arch/arm/mach-exynos/Kconfig"	1049	source "arch/arm/mach-exynos/Kconfig"
1050		1050
1051	source "arch/arm/mach-shmobile/Kconfig"	1051	source "arch/arm/mach-shmobile/Kconfig"
1052		1052
1053	source "arch/arm/mach-sunxi/Kconfig"	1053	source "arch/arm/mach-sunxi/Kconfig"
1054		1054
1055	source "arch/arm/mach-prima2/Kconfig"	1055	source "arch/arm/mach-prima2/Kconfig"
1056		1056
1057	source "arch/arm/mach-tegra/Kconfig"	1057	source "arch/arm/mach-tegra/Kconfig"
1058		1058
1059	source "arch/arm/mach-u300/Kconfig"	1059	source "arch/arm/mach-u300/Kconfig"
1060		1060
1061	source "arch/arm/mach-ux500/Kconfig"	1061	source "arch/arm/mach-ux500/Kconfig"
1062		1062
1063	source "arch/arm/mach-versatile/Kconfig"	1063	source "arch/arm/mach-versatile/Kconfig"
1064		1064
1065	source "arch/arm/mach-vexpress/Kconfig"	1065	source "arch/arm/mach-vexpress/Kconfig"
1066	source "arch/arm/plat-versatile/Kconfig"	1066	source "arch/arm/plat-versatile/Kconfig"
1067		1067
1068	source "arch/arm/mach-vt8500/Kconfig"	1068	source "arch/arm/mach-vt8500/Kconfig"
1069		1069
1070	source "arch/arm/mach-w90x900/Kconfig"	1070	source "arch/arm/mach-w90x900/Kconfig"
1071		1071
1072	source "arch/arm/mach-zynq/Kconfig"	1072	source "arch/arm/mach-zynq/Kconfig"
1073		1073
1074	# Definitions to make life easier	1074	# Definitions to make life easier
1075	config ARCH_ACORN	1075	config ARCH_ACORN
1076	bool	1076	bool
1077		1077
1078	config PLAT_IOP	1078	config PLAT_IOP
1079	bool	1079	bool
1080	select GENERIC_CLOCKEVENTS	1080	select GENERIC_CLOCKEVENTS
1081		1081
1082	config PLAT_ORION	1082	config PLAT_ORION
1083	bool	1083	bool
1084	select CLKSRC_MMIO	1084	select CLKSRC_MMIO
1085	select COMMON_CLK	1085	select COMMON_CLK
1086	select GENERIC_IRQ_CHIP	1086	select GENERIC_IRQ_CHIP
1087	select IRQ_DOMAIN	1087	select IRQ_DOMAIN
1088		1088
1089	config PLAT_ORION_LEGACY	1089	config PLAT_ORION_LEGACY
1090	bool	1090	bool
1091	select PLAT_ORION	1091	select PLAT_ORION
1092		1092
1093	config PLAT_PXA	1093	config PLAT_PXA
1094	bool	1094	bool
1095		1095
1096	config PLAT_VERSATILE	1096	config PLAT_VERSATILE
1097	bool	1097	bool
1098		1098
1099	config ARM_TIMER_SP804	1099	config ARM_TIMER_SP804
1100	bool	1100	bool
1101	select CLKSRC_MMIO	1101	select CLKSRC_MMIO
1102	select CLKSRC_OF if OF	1102	select CLKSRC_OF if OF
1103		1103
1104	source "arch/arm/firmware/Kconfig"	1104	source "arch/arm/firmware/Kconfig"
1105		1105
1106	source arch/arm/mm/Kconfig	1106	source arch/arm/mm/Kconfig
1107		1107
1108	config ARM_NR_BANKS	1108	config ARM_NR_BANKS
1109	int	1109	int
1110	default 16 if ARCH_EP93XX	1110	default 16 if ARCH_EP93XX
1111	default 8	1111	default 8
1112		1112
1113	config IWMMXT	1113	config IWMMXT
1114	bool "Enable iWMMXt support" if !CPU_PJ4	1114	bool "Enable iWMMXt support"
1115	depends on CPU_XSCALE \|\| CPU_XSC3 \|\| CPU_MOHAWK \|\| CPU_PJ4	1115	depends on CPU_XSCALE \|\| CPU_XSC3 \|\| CPU_MOHAWK \|\| CPU_PJ4 \|\| CPU_PJ4B
1116	default y if PXA27x \|\| PXA3xx \|\| ARCH_MMP \|\| CPU_PJ4	1116	default y if PXA27x \|\| PXA3xx \|\| ARCH_MMP \|\| CPU_PJ4 \|\| CPU_PJ4B
1117	help	1117	help
1118	Enable support for iWMMXt context switching at run time if	1118	Enable support for iWMMXt context switching at run time if
1119	running on a CPU that supports it.	1119	running on a CPU that supports it.
1120		1120
1121	config MULTI_IRQ_HANDLER	1121	config MULTI_IRQ_HANDLER
1122	bool	1122	bool
1123	help	1123	help
1124	Allow each machine to specify it's own IRQ handler at run time.	1124	Allow each machine to specify it's own IRQ handler at run time.
1125		1125
1126	if !MMU	1126	if !MMU
1127	source "arch/arm/Kconfig-nommu"	1127	source "arch/arm/Kconfig-nommu"
1128	endif	1128	endif
1129		1129
1130	config PJ4B_ERRATA_4742	1130	config PJ4B_ERRATA_4742
1131	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"	1131	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1132	depends on CPU_PJ4B && MACH_ARMADA_370	1132	depends on CPU_PJ4B && MACH_ARMADA_370
1133	default y	1133	default y
1134	help	1134	help
1135	When coming out of either a Wait for Interrupt (WFI) or a Wait for	1135	When coming out of either a Wait for Interrupt (WFI) or a Wait for
1136	Event (WFE) IDLE states, a specific timing sensitivity exists between	1136	Event (WFE) IDLE states, a specific timing sensitivity exists between
1137	the retiring WFI/WFE instructions and the newly issued subsequent	1137	the retiring WFI/WFE instructions and the newly issued subsequent
1138	instructions. This sensitivity can result in a CPU hang scenario.	1138	instructions. This sensitivity can result in a CPU hang scenario.
1139	Workaround:	1139	Workaround:
1140	The software must insert either a Data Synchronization Barrier (DSB)	1140	The software must insert either a Data Synchronization Barrier (DSB)
1141	or Data Memory Barrier (DMB) command immediately after the WFI/WFE	1141	or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1142	instruction	1142	instruction
1143		1143
1144	config ARM_ERRATA_326103	1144	config ARM_ERRATA_326103
1145	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"	1145	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1146	depends on CPU_V6	1146	depends on CPU_V6
1147	help	1147	help
1148	Executing a SWP instruction to read-only memory does not set bit 11	1148	Executing a SWP instruction to read-only memory does not set bit 11
1149	of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to	1149	of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1150	treat the access as a read, preventing a COW from occurring and	1150	treat the access as a read, preventing a COW from occurring and
1151	causing the faulting task to livelock.	1151	causing the faulting task to livelock.
1152		1152
1153	config ARM_ERRATA_411920	1153	config ARM_ERRATA_411920
1154	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"	1154	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1155	depends on CPU_V6 \|\| CPU_V6K	1155	depends on CPU_V6 \|\| CPU_V6K
1156	help	1156	help
1157	Invalidation of the Instruction Cache operation can	1157	Invalidation of the Instruction Cache operation can
1158	fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.	1158	fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1159	It does not affect the MPCore. This option enables the ARM Ltd.	1159	It does not affect the MPCore. This option enables the ARM Ltd.
1160	recommended workaround.	1160	recommended workaround.
1161		1161
1162	config ARM_ERRATA_430973	1162	config ARM_ERRATA_430973
1163	bool "ARM errata: Stale prediction on replaced interworking branch"	1163	bool "ARM errata: Stale prediction on replaced interworking branch"
1164	depends on CPU_V7	1164	depends on CPU_V7
1165	help	1165	help
1166	This option enables the workaround for the 430973 Cortex-A8	1166	This option enables the workaround for the 430973 Cortex-A8
1167	(r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb	1167	(r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1168	interworking branch is replaced with another code sequence at the	1168	interworking branch is replaced with another code sequence at the
1169	same virtual address, whether due to self-modifying code or virtual	1169	same virtual address, whether due to self-modifying code or virtual
1170	to physical address re-mapping, Cortex-A8 does not recover from the	1170	to physical address re-mapping, Cortex-A8 does not recover from the
1171	stale interworking branch prediction. This results in Cortex-A8	1171	stale interworking branch prediction. This results in Cortex-A8
1172	executing the new code sequence in the incorrect ARM or Thumb state.	1172	executing the new code sequence in the incorrect ARM or Thumb state.
1173	The workaround enables the BTB/BTAC operations by setting ACTLR.IBE	1173	The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1174	and also flushes the branch target cache at every context switch.	1174	and also flushes the branch target cache at every context switch.
1175	Note that setting specific bits in the ACTLR register may not be	1175	Note that setting specific bits in the ACTLR register may not be
1176	available in non-secure mode.	1176	available in non-secure mode.
1177		1177
1178	config ARM_ERRATA_458693	1178	config ARM_ERRATA_458693
1179	bool "ARM errata: Processor deadlock when a false hazard is created"	1179	bool "ARM errata: Processor deadlock when a false hazard is created"
1180	depends on CPU_V7	1180	depends on CPU_V7
1181	depends on !ARCH_MULTIPLATFORM	1181	depends on !ARCH_MULTIPLATFORM
1182	help	1182	help
1183	This option enables the workaround for the 458693 Cortex-A8 (r2p0)	1183	This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1184	erratum. For very specific sequences of memory operations, it is	1184	erratum. For very specific sequences of memory operations, it is
1185	possible for a hazard condition intended for a cache line to instead	1185	possible for a hazard condition intended for a cache line to instead
1186	be incorrectly associated with a different cache line. This false	1186	be incorrectly associated with a different cache line. This false
1187	hazard might then cause a processor deadlock. The workaround enables	1187	hazard might then cause a processor deadlock. The workaround enables
1188	the L1 caching of the NEON accesses and disables the PLD instruction	1188	the L1 caching of the NEON accesses and disables the PLD instruction
1189	in the ACTLR register. Note that setting specific bits in the ACTLR	1189	in the ACTLR register. Note that setting specific bits in the ACTLR
1190	register may not be available in non-secure mode.	1190	register may not be available in non-secure mode.
1191		1191
1192	config ARM_ERRATA_460075	1192	config ARM_ERRATA_460075
1193	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"	1193	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1194	depends on CPU_V7	1194	depends on CPU_V7
1195	depends on !ARCH_MULTIPLATFORM	1195	depends on !ARCH_MULTIPLATFORM
1196	help	1196	help
1197	This option enables the workaround for the 460075 Cortex-A8 (r2p0)	1197	This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1198	erratum. Any asynchronous access to the L2 cache may encounter a	1198	erratum. Any asynchronous access to the L2 cache may encounter a
1199	situation in which recent store transactions to the L2 cache are lost	1199	situation in which recent store transactions to the L2 cache are lost
1200	and overwritten with stale memory contents from external memory. The	1200	and overwritten with stale memory contents from external memory. The
1201	workaround disables the write-allocate mode for the L2 cache via the	1201	workaround disables the write-allocate mode for the L2 cache via the
1202	ACTLR register. Note that setting specific bits in the ACTLR register	1202	ACTLR register. Note that setting specific bits in the ACTLR register
1203	may not be available in non-secure mode.	1203	may not be available in non-secure mode.
1204		1204
1205	config ARM_ERRATA_742230	1205	config ARM_ERRATA_742230
1206	bool "ARM errata: DMB operation may be faulty"	1206	bool "ARM errata: DMB operation may be faulty"
1207	depends on CPU_V7 && SMP	1207	depends on CPU_V7 && SMP
1208	depends on !ARCH_MULTIPLATFORM	1208	depends on !ARCH_MULTIPLATFORM
1209	help	1209	help
1210	This option enables the workaround for the 742230 Cortex-A9	1210	This option enables the workaround for the 742230 Cortex-A9
1211	(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction	1211	(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1212	between two write operations may not ensure the correct visibility	1212	between two write operations may not ensure the correct visibility
1213	ordering of the two writes. This workaround sets a specific bit in	1213	ordering of the two writes. This workaround sets a specific bit in
1214	the diagnostic register of the Cortex-A9 which causes the DMB	1214	the diagnostic register of the Cortex-A9 which causes the DMB
1215	instruction to behave as a DSB, ensuring the correct behaviour of	1215	instruction to behave as a DSB, ensuring the correct behaviour of
1216	the two writes.	1216	the two writes.
1217		1217
1218	config ARM_ERRATA_742231	1218	config ARM_ERRATA_742231
1219	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"	1219	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1220	depends on CPU_V7 && SMP	1220	depends on CPU_V7 && SMP
1221	depends on !ARCH_MULTIPLATFORM	1221	depends on !ARCH_MULTIPLATFORM
1222	help	1222	help
1223	This option enables the workaround for the 742231 Cortex-A9	1223	This option enables the workaround for the 742231 Cortex-A9
1224	(r2p0..r2p2) erratum. Under certain conditions, specific to the	1224	(r2p0..r2p2) erratum. Under certain conditions, specific to the
1225	Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,	1225	Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1226	accessing some data located in the same cache line, may get corrupted	1226	accessing some data located in the same cache line, may get corrupted
1227	data due to bad handling of the address hazard when the line gets	1227	data due to bad handling of the address hazard when the line gets
1228	replaced from one of the CPUs at the same time as another CPU is	1228	replaced from one of the CPUs at the same time as another CPU is
1229	accessing it. This workaround sets specific bits in the diagnostic	1229	accessing it. This workaround sets specific bits in the diagnostic
1230	register of the Cortex-A9 which reduces the linefill issuing	1230	register of the Cortex-A9 which reduces the linefill issuing
1231	capabilities of the processor.	1231	capabilities of the processor.
1232		1232
1233	config PL310_ERRATA_588369	1233	config PL310_ERRATA_588369
1234	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"	1234	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235	depends on CACHE_L2X0	1235	depends on CACHE_L2X0
1236	help	1236	help
1237	The PL310 L2 cache controller implements three types of Clean &	1237	The PL310 L2 cache controller implements three types of Clean &
1238	Invalidate maintenance operations: by Physical Address	1238	Invalidate maintenance operations: by Physical Address
1239	(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).	1239	(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1240	They are architecturally defined to behave as the execution of a	1240	They are architecturally defined to behave as the execution of a
1241	clean operation followed immediately by an invalidate operation,	1241	clean operation followed immediately by an invalidate operation,
1242	both performing to the same memory location. This functionality	1242	both performing to the same memory location. This functionality
1243	is not correctly implemented in PL310 as clean lines are not	1243	is not correctly implemented in PL310 as clean lines are not
1244	invalidated as a result of these operations.	1244	invalidated as a result of these operations.
1245		1245
1246	config ARM_ERRATA_643719	1246	config ARM_ERRATA_643719
1247	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"	1247	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1248	depends on CPU_V7 && SMP	1248	depends on CPU_V7 && SMP
1249	help	1249	help
1250	This option enables the workaround for the 643719 Cortex-A9 (prior to	1250	This option enables the workaround for the 643719 Cortex-A9 (prior to
1251	r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR	1251	r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1252	register returns zero when it should return one. The workaround	1252	register returns zero when it should return one. The workaround
1253	corrects this value, ensuring cache maintenance operations which use	1253	corrects this value, ensuring cache maintenance operations which use
1254	it behave as intended and avoiding data corruption.	1254	it behave as intended and avoiding data corruption.
1255		1255
1256	config ARM_ERRATA_720789	1256	config ARM_ERRATA_720789
1257	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"	1257	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1258	depends on CPU_V7	1258	depends on CPU_V7
1259	help	1259	help
1260	This option enables the workaround for the 720789 Cortex-A9 (prior to	1260	This option enables the workaround for the 720789 Cortex-A9 (prior to
1261	r2p0) erratum. A faulty ASID can be sent to the other CPUs for the	1261	r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1262	broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.	1262	broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1263	As a consequence of this erratum, some TLB entries which should be	1263	As a consequence of this erratum, some TLB entries which should be
1264	invalidated are not, resulting in an incoherency in the system page	1264	invalidated are not, resulting in an incoherency in the system page
1265	tables. The workaround changes the TLB flushing routines to invalidate	1265	tables. The workaround changes the TLB flushing routines to invalidate
1266	entries regardless of the ASID.	1266	entries regardless of the ASID.
1267		1267
1268	config PL310_ERRATA_727915	1268	config PL310_ERRATA_727915
1269	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"	1269	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1270	depends on CACHE_L2X0	1270	depends on CACHE_L2X0
1271	help	1271	help
1272	PL310 implements the Clean & Invalidate by Way L2 cache maintenance	1272	PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1273	operation (offset 0x7FC). This operation runs in background so that	1273	operation (offset 0x7FC). This operation runs in background so that
1274	PL310 can handle normal accesses while it is in progress. Under very	1274	PL310 can handle normal accesses while it is in progress. Under very
1275	rare circumstances, due to this erratum, write data can be lost when	1275	rare circumstances, due to this erratum, write data can be lost when
1276	PL310 treats a cacheable write transaction during a Clean &	1276	PL310 treats a cacheable write transaction during a Clean &
1277	Invalidate by Way operation.	1277	Invalidate by Way operation.
1278		1278
1279	config ARM_ERRATA_743622	1279	config ARM_ERRATA_743622
1280	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"	1280	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1281	depends on CPU_V7	1281	depends on CPU_V7
1282	depends on !ARCH_MULTIPLATFORM	1282	depends on !ARCH_MULTIPLATFORM
1283	help	1283	help
1284	This option enables the workaround for the 743622 Cortex-A9	1284	This option enables the workaround for the 743622 Cortex-A9
1285	(r2p*) erratum. Under very rare conditions, a faulty	1285	(r2p*) erratum. Under very rare conditions, a faulty
1286	optimisation in the Cortex-A9 Store Buffer may lead to data	1286	optimisation in the Cortex-A9 Store Buffer may lead to data
1287	corruption. This workaround sets a specific bit in the diagnostic	1287	corruption. This workaround sets a specific bit in the diagnostic
1288	register of the Cortex-A9 which disables the Store Buffer	1288	register of the Cortex-A9 which disables the Store Buffer
1289	optimisation, preventing the defect from occurring. This has no	1289	optimisation, preventing the defect from occurring. This has no
1290	visible impact on the overall performance or power consumption of the	1290	visible impact on the overall performance or power consumption of the
1291	processor.	1291	processor.
1292		1292
1293	config ARM_ERRATA_751472	1293	config ARM_ERRATA_751472
1294	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"	1294	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1295	depends on CPU_V7	1295	depends on CPU_V7
1296	depends on !ARCH_MULTIPLATFORM	1296	depends on !ARCH_MULTIPLATFORM
1297	help	1297	help
1298	This option enables the workaround for the 751472 Cortex-A9 (prior	1298	This option enables the workaround for the 751472 Cortex-A9 (prior
1299	to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the	1299	to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1300	completion of a following broadcasted operation if the second	1300	completion of a following broadcasted operation if the second
1301	operation is received by a CPU before the ICIALLUIS has completed,	1301	operation is received by a CPU before the ICIALLUIS has completed,
1302	potentially leading to corrupted entries in the cache or TLB.	1302	potentially leading to corrupted entries in the cache or TLB.
1303		1303
1304	config PL310_ERRATA_753970	1304	config PL310_ERRATA_753970
1305	bool "PL310 errata: cache sync operation may be faulty"	1305	bool "PL310 errata: cache sync operation may be faulty"
1306	depends on CACHE_PL310	1306	depends on CACHE_PL310
1307	help	1307	help
1308	This option enables the workaround for the 753970 PL310 (r3p0) erratum.	1308	This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1309		1309
1310	Under some condition the effect of cache sync operation on	1310	Under some condition the effect of cache sync operation on
1311	the store buffer still remains when the operation completes.	1311	the store buffer still remains when the operation completes.
1312	This means that the store buffer is always asked to drain and	1312	This means that the store buffer is always asked to drain and
1313	this prevents it from merging any further writes. The workaround	1313	this prevents it from merging any further writes. The workaround
1314	is to replace the normal offset of cache sync operation (0x730)	1314	is to replace the normal offset of cache sync operation (0x730)
1315	by another offset targeting an unmapped PL310 register 0x740.	1315	by another offset targeting an unmapped PL310 register 0x740.
1316	This has the same effect as the cache sync operation: store buffer	1316	This has the same effect as the cache sync operation: store buffer
1317	drain and waiting for all buffers empty.	1317	drain and waiting for all buffers empty.
1318		1318
1319	config ARM_ERRATA_754322	1319	config ARM_ERRATA_754322
1320	bool "ARM errata: possible faulty MMU translations following an ASID switch"	1320	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1321	depends on CPU_V7	1321	depends on CPU_V7
1322	help	1322	help
1323	This option enables the workaround for the 754322 Cortex-A9 (r2p*,	1323	This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1324	r3p*) erratum. A speculative memory access may cause a page table walk	1324	r3p*) erratum. A speculative memory access may cause a page table walk
1325	which starts prior to an ASID switch but completes afterwards. This	1325	which starts prior to an ASID switch but completes afterwards. This
1326	can populate the micro-TLB with a stale entry which may be hit with	1326	can populate the micro-TLB with a stale entry which may be hit with
1327	the new ASID. This workaround places two dsb instructions in the mm	1327	the new ASID. This workaround places two dsb instructions in the mm
1328	switching code so that no page table walks can cross the ASID switch.	1328	switching code so that no page table walks can cross the ASID switch.
1329		1329
1330	config ARM_ERRATA_754327	1330	config ARM_ERRATA_754327
1331	bool "ARM errata: no automatic Store Buffer drain"	1331	bool "ARM errata: no automatic Store Buffer drain"
1332	depends on CPU_V7 && SMP	1332	depends on CPU_V7 && SMP
1333	help	1333	help
1334	This option enables the workaround for the 754327 Cortex-A9 (prior to	1334	This option enables the workaround for the 754327 Cortex-A9 (prior to
1335	r2p0) erratum. The Store Buffer does not have any automatic draining	1335	r2p0) erratum. The Store Buffer does not have any automatic draining
1336	mechanism and therefore a livelock may occur if an external agent	1336	mechanism and therefore a livelock may occur if an external agent
1337	continuously polls a memory location waiting to observe an update.	1337	continuously polls a memory location waiting to observe an update.
1338	This workaround defines cpu_relax() as smp_mb(), preventing correctly	1338	This workaround defines cpu_relax() as smp_mb(), preventing correctly
1339	written polling loops from denying visibility of updates to memory.	1339	written polling loops from denying visibility of updates to memory.
1340		1340
1341	config ARM_ERRATA_364296	1341	config ARM_ERRATA_364296
1342	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"	1342	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1343	depends on CPU_V6	1343	depends on CPU_V6
1344	help	1344	help
1345	This options enables the workaround for the 364296 ARM1136	1345	This options enables the workaround for the 364296 ARM1136
1346	r0p2 erratum (possible cache data corruption with	1346	r0p2 erratum (possible cache data corruption with
1347	hit-under-miss enabled). It sets the undocumented bit 31 in	1347	hit-under-miss enabled). It sets the undocumented bit 31 in
1348	the auxiliary control register and the FI bit in the control	1348	the auxiliary control register and the FI bit in the control
1349	register, thus disabling hit-under-miss without putting the	1349	register, thus disabling hit-under-miss without putting the
1350	processor into full low interrupt latency mode. ARM11MPCore	1350	processor into full low interrupt latency mode. ARM11MPCore
1351	is not affected.	1351	is not affected.
1352		1352
1353	config ARM_ERRATA_764369	1353	config ARM_ERRATA_764369
1354	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"	1354	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1355	depends on CPU_V7 && SMP	1355	depends on CPU_V7 && SMP
1356	help	1356	help
1357	This option enables the workaround for erratum 764369	1357	This option enables the workaround for erratum 764369
1358	affecting Cortex-A9 MPCore with two or more processors (all	1358	affecting Cortex-A9 MPCore with two or more processors (all
1359	current revisions). Under certain timing circumstances, a data	1359	current revisions). Under certain timing circumstances, a data
1360	cache line maintenance operation by MVA targeting an Inner	1360	cache line maintenance operation by MVA targeting an Inner
1361	Shareable memory region may fail to proceed up to either the	1361	Shareable memory region may fail to proceed up to either the
1362	Point of Coherency or to the Point of Unification of the	1362	Point of Coherency or to the Point of Unification of the
1363	system. This workaround adds a DSB instruction before the	1363	system. This workaround adds a DSB instruction before the
1364	relevant cache maintenance functions and sets a specific bit	1364	relevant cache maintenance functions and sets a specific bit
1365	in the diagnostic control register of the SCU.	1365	in the diagnostic control register of the SCU.
1366		1366
1367	config PL310_ERRATA_769419	1367	config PL310_ERRATA_769419
1368	bool "PL310 errata: no automatic Store Buffer drain"	1368	bool "PL310 errata: no automatic Store Buffer drain"
1369	depends on CACHE_L2X0	1369	depends on CACHE_L2X0
1370	help	1370	help
1371	On revisions of the PL310 prior to r3p2, the Store Buffer does	1371	On revisions of the PL310 prior to r3p2, the Store Buffer does
1372	not automatically drain. This can cause normal, non-cacheable	1372	not automatically drain. This can cause normal, non-cacheable
1373	writes to be retained when the memory system is idle, leading	1373	writes to be retained when the memory system is idle, leading
1374	to suboptimal I/O performance for drivers using coherent DMA.	1374	to suboptimal I/O performance for drivers using coherent DMA.
1375	This option adds a write barrier to the cpu_idle loop so that,	1375	This option adds a write barrier to the cpu_idle loop so that,
1376	on systems with an outer cache, the store buffer is drained	1376	on systems with an outer cache, the store buffer is drained
1377	explicitly.	1377	explicitly.
1378		1378
1379	config ARM_ERRATA_775420	1379	config ARM_ERRATA_775420
1380	bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"	1380	bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1381	depends on CPU_V7	1381	depends on CPU_V7
1382	help	1382	help
1383	This option enables the workaround for the 775420 Cortex-A9 (r2p2,	1383	This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1384	r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance	1384	r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1385	operation aborts with MMU exception, it might cause the processor	1385	operation aborts with MMU exception, it might cause the processor
1386	to deadlock. This workaround puts DSB before executing ISB if	1386	to deadlock. This workaround puts DSB before executing ISB if
1387	an abort may occur on cache maintenance.	1387	an abort may occur on cache maintenance.
1388		1388
1389	config ARM_ERRATA_798181	1389	config ARM_ERRATA_798181
1390	bool "ARM errata: TLBI/DSB failure on Cortex-A15"	1390	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1391	depends on CPU_V7 && SMP	1391	depends on CPU_V7 && SMP
1392	help	1392	help
1393	On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not	1393	On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1394	adequately shooting down all use of the old entries. This	1394	adequately shooting down all use of the old entries. This
1395	option enables the Linux kernel workaround for this erratum	1395	option enables the Linux kernel workaround for this erratum
1396	which sends an IPI to the CPUs that are running the same ASID	1396	which sends an IPI to the CPUs that are running the same ASID
1397	as the one being invalidated.	1397	as the one being invalidated.
1398		1398
1399	config ARM_ERRATA_773022	1399	config ARM_ERRATA_773022
1400	bool "ARM errata: incorrect instructions may be executed from loop buffer"	1400	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1401	depends on CPU_V7	1401	depends on CPU_V7
1402	help	1402	help
1403	This option enables the workaround for the 773022 Cortex-A15	1403	This option enables the workaround for the 773022 Cortex-A15
1404	(up to r0p4) erratum. In certain rare sequences of code, the	1404	(up to r0p4) erratum. In certain rare sequences of code, the
1405	loop buffer may deliver incorrect instructions. This	1405	loop buffer may deliver incorrect instructions. This
1406	workaround disables the loop buffer to avoid the erratum.	1406	workaround disables the loop buffer to avoid the erratum.
1407		1407
1408	endmenu	1408	endmenu
1409		1409
1410	source "arch/arm/common/Kconfig"	1410	source "arch/arm/common/Kconfig"
1411		1411
1412	menu "Bus support"	1412	menu "Bus support"
1413		1413
1414	config ARM_AMBA	1414	config ARM_AMBA
1415	bool	1415	bool
1416		1416
1417	config ISA	1417	config ISA
1418	bool	1418	bool
1419	help	1419	help
1420	Find out whether you have ISA slots on your motherboard. ISA is the	1420	Find out whether you have ISA slots on your motherboard. ISA is the
1421	name of a bus system, i.e. the way the CPU talks to the other stuff	1421	name of a bus system, i.e. the way the CPU talks to the other stuff
1422	inside your box. Other bus systems are PCI, EISA, MicroChannel	1422	inside your box. Other bus systems are PCI, EISA, MicroChannel
1423	(MCA) or VESA. ISA is an older system, now being displaced by PCI;	1423	(MCA) or VESA. ISA is an older system, now being displaced by PCI;
1424	newer boards don't support it. If you have ISA, say Y, otherwise N.	1424	newer boards don't support it. If you have ISA, say Y, otherwise N.
1425		1425
1426	# Select ISA DMA controller support	1426	# Select ISA DMA controller support
1427	config ISA_DMA	1427	config ISA_DMA
1428	bool	1428	bool
1429	select ISA_DMA_API	1429	select ISA_DMA_API
1430		1430
1431	# Select ISA DMA interface	1431	# Select ISA DMA interface
1432	config ISA_DMA_API	1432	config ISA_DMA_API
1433	bool	1433	bool
1434		1434
1435	config PCI	1435	config PCI
1436	bool "PCI support" if MIGHT_HAVE_PCI	1436	bool "PCI support" if MIGHT_HAVE_PCI
1437	help	1437	help
1438	Find out whether you have a PCI motherboard. PCI is the name of a	1438	Find out whether you have a PCI motherboard. PCI is the name of a
1439	bus system, i.e. the way the CPU talks to the other stuff inside	1439	bus system, i.e. the way the CPU talks to the other stuff inside
1440	your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or	1440	your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1441	VESA. If you have PCI, say Y, otherwise N.	1441	VESA. If you have PCI, say Y, otherwise N.
1442		1442
1443	config PCI_DOMAINS	1443	config PCI_DOMAINS
1444	bool	1444	bool
1445	depends on PCI	1445	depends on PCI
1446		1446
1447	config PCI_NANOENGINE	1447	config PCI_NANOENGINE
1448	bool "BSE nanoEngine PCI support"	1448	bool "BSE nanoEngine PCI support"
1449	depends on SA1100_NANOENGINE	1449	depends on SA1100_NANOENGINE
1450	help	1450	help
1451	Enable PCI on the BSE nanoEngine board.	1451	Enable PCI on the BSE nanoEngine board.
1452		1452
1453	config PCI_SYSCALL	1453	config PCI_SYSCALL
1454	def_bool PCI	1454	def_bool PCI
1455		1455
1456	config PCI_HOST_ITE8152	1456	config PCI_HOST_ITE8152
1457	bool	1457	bool
1458	depends on PCI && MACH_ARMCORE	1458	depends on PCI && MACH_ARMCORE
1459	default y	1459	default y
1460	select DMABOUNCE	1460	select DMABOUNCE
1461		1461
1462	source "drivers/pci/Kconfig"	1462	source "drivers/pci/Kconfig"
1463	source "drivers/pci/pcie/Kconfig"	1463	source "drivers/pci/pcie/Kconfig"
1464		1464
1465	source "drivers/pcmcia/Kconfig"	1465	source "drivers/pcmcia/Kconfig"
1466		1466
1467	endmenu	1467	endmenu
1468		1468
1469	menu "Kernel Features"	1469	menu "Kernel Features"
1470		1470
1471	config HAVE_SMP	1471	config HAVE_SMP
1472	bool	1472	bool
1473	help	1473	help
1474	This option should be selected by machines which have an SMP-	1474	This option should be selected by machines which have an SMP-
1475	capable CPU.	1475	capable CPU.
1476		1476
1477	The only effect of this option is to make the SMP-related	1477	The only effect of this option is to make the SMP-related
1478	options available to the user for configuration.	1478	options available to the user for configuration.
1479		1479
1480	config SMP	1480	config SMP
1481	bool "Symmetric Multi-Processing"	1481	bool "Symmetric Multi-Processing"
1482	depends on CPU_V6K \|\| CPU_V7	1482	depends on CPU_V6K \|\| CPU_V7
1483	depends on GENERIC_CLOCKEVENTS	1483	depends on GENERIC_CLOCKEVENTS
1484	depends on HAVE_SMP	1484	depends on HAVE_SMP
1485	depends on MMU \|\| ARM_MPU	1485	depends on MMU \|\| ARM_MPU
1486	help	1486	help
1487	This enables support for systems with more than one CPU. If you have	1487	This enables support for systems with more than one CPU. If you have
1488	a system with only one CPU, say N. If you have a system with more	1488	a system with only one CPU, say N. If you have a system with more
1489	than one CPU, say Y.	1489	than one CPU, say Y.
1490		1490
1491	If you say N here, the kernel will run on uni- and multiprocessor	1491	If you say N here, the kernel will run on uni- and multiprocessor
1492	machines, but will use only one CPU of a multiprocessor machine. If	1492	machines, but will use only one CPU of a multiprocessor machine. If
1493	you say Y here, the kernel will run on many, but not all,	1493	you say Y here, the kernel will run on many, but not all,
1494	uniprocessor machines. On a uniprocessor machine, the kernel	1494	uniprocessor machines. On a uniprocessor machine, the kernel
1495	will run faster if you say N here.	1495	will run faster if you say N here.
1496		1496
1497	See also <file:Documentation/x86/i386/IO-APIC.txt>,	1497	See also <file:Documentation/x86/i386/IO-APIC.txt>,
1498	<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at	1498	<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1499	<http://tldp.org/HOWTO/SMP-HOWTO.html>.	1499	<http://tldp.org/HOWTO/SMP-HOWTO.html>.
1500		1500
1501	If you don't know what to do here, say N.	1501	If you don't know what to do here, say N.
1502		1502
1503	config SMP_ON_UP	1503	config SMP_ON_UP
1504	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"	1504	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1505	depends on SMP && !XIP_KERNEL && MMU	1505	depends on SMP && !XIP_KERNEL && MMU
1506	default y	1506	default y
1507	help	1507	help
1508	SMP kernels contain instructions which fail on non-SMP processors.	1508	SMP kernels contain instructions which fail on non-SMP processors.
1509	Enabling this option allows the kernel to modify itself to make	1509	Enabling this option allows the kernel to modify itself to make
1510	these instructions safe. Disabling it allows about 1K of space	1510	these instructions safe. Disabling it allows about 1K of space
1511	savings.	1511	savings.
1512		1512
1513	If you don't know what to do here, say Y.	1513	If you don't know what to do here, say Y.
1514		1514
1515	config ARM_CPU_TOPOLOGY	1515	config ARM_CPU_TOPOLOGY
1516	bool "Support cpu topology definition"	1516	bool "Support cpu topology definition"
1517	depends on SMP && CPU_V7	1517	depends on SMP && CPU_V7
1518	default y	1518	default y
1519	help	1519	help
1520	Support ARM cpu topology definition. The MPIDR register defines	1520	Support ARM cpu topology definition. The MPIDR register defines
1521	affinity between processors which is then used to describe the cpu	1521	affinity between processors which is then used to describe the cpu
1522	topology of an ARM System.	1522	topology of an ARM System.
1523		1523
1524	config SCHED_MC	1524	config SCHED_MC
1525	bool "Multi-core scheduler support"	1525	bool "Multi-core scheduler support"
1526	depends on ARM_CPU_TOPOLOGY	1526	depends on ARM_CPU_TOPOLOGY
1527	help	1527	help
1528	Multi-core scheduler support improves the CPU scheduler's decision	1528	Multi-core scheduler support improves the CPU scheduler's decision
1529	making when dealing with multi-core CPU chips at a cost of slightly	1529	making when dealing with multi-core CPU chips at a cost of slightly
1530	increased overhead in some places. If unsure say N here.	1530	increased overhead in some places. If unsure say N here.
1531		1531
1532	config SCHED_SMT	1532	config SCHED_SMT
1533	bool "SMT scheduler support"	1533	bool "SMT scheduler support"
1534	depends on ARM_CPU_TOPOLOGY	1534	depends on ARM_CPU_TOPOLOGY
1535	help	1535	help
1536	Improves the CPU scheduler's decision making when dealing with	1536	Improves the CPU scheduler's decision making when dealing with
1537	MultiThreading at a cost of slightly increased overhead in some	1537	MultiThreading at a cost of slightly increased overhead in some
1538	places. If unsure say N here.	1538	places. If unsure say N here.
1539		1539
1540	config HAVE_ARM_SCU	1540	config HAVE_ARM_SCU
1541	bool	1541	bool
1542	help	1542	help
1543	This option enables support for the ARM system coherency unit	1543	This option enables support for the ARM system coherency unit
1544		1544
1545	config HAVE_ARM_ARCH_TIMER	1545	config HAVE_ARM_ARCH_TIMER
1546	bool "Architected timer support"	1546	bool "Architected timer support"
1547	depends on CPU_V7	1547	depends on CPU_V7
1548	select ARM_ARCH_TIMER	1548	select ARM_ARCH_TIMER
1549	select GENERIC_CLOCKEVENTS	1549	select GENERIC_CLOCKEVENTS
1550	help	1550	help
1551	This option enables support for the ARM architected timer	1551	This option enables support for the ARM architected timer
1552		1552
1553	config HAVE_ARM_TWD	1553	config HAVE_ARM_TWD
1554	bool	1554	bool
1555	depends on SMP	1555	depends on SMP
1556	select CLKSRC_OF if OF	1556	select CLKSRC_OF if OF
1557	help	1557	help
1558	This options enables support for the ARM timer and watchdog unit	1558	This options enables support for the ARM timer and watchdog unit
1559		1559
1560	config MCPM	1560	config MCPM
1561	bool "Multi-Cluster Power Management"	1561	bool "Multi-Cluster Power Management"
1562	depends on CPU_V7 && SMP	1562	depends on CPU_V7 && SMP
1563	help	1563	help
1564	This option provides the common power management infrastructure	1564	This option provides the common power management infrastructure
1565	for (multi-)cluster based systems, such as big.LITTLE based	1565	for (multi-)cluster based systems, such as big.LITTLE based
1566	systems.	1566	systems.
1567		1567
1568	config BIG_LITTLE	1568	config BIG_LITTLE
1569	bool "big.LITTLE support (Experimental)"	1569	bool "big.LITTLE support (Experimental)"
1570	depends on CPU_V7 && SMP	1570	depends on CPU_V7 && SMP
1571	select MCPM	1571	select MCPM
1572	help	1572	help
1573	This option enables support selections for the big.LITTLE	1573	This option enables support selections for the big.LITTLE
1574	system architecture.	1574	system architecture.
1575		1575
1576	config BL_SWITCHER	1576	config BL_SWITCHER
1577	bool "big.LITTLE switcher support"	1577	bool "big.LITTLE switcher support"
1578	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU	1578	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1579	select ARM_CPU_SUSPEND	1579	select ARM_CPU_SUSPEND
1580	select CPU_PM	1580	select CPU_PM
1581	help	1581	help
1582	The big.LITTLE "switcher" provides the core functionality to	1582	The big.LITTLE "switcher" provides the core functionality to
1583	transparently handle transition between a cluster of A15's	1583	transparently handle transition between a cluster of A15's
1584	and a cluster of A7's in a big.LITTLE system.	1584	and a cluster of A7's in a big.LITTLE system.
1585		1585
1586	config BL_SWITCHER_DUMMY_IF	1586	config BL_SWITCHER_DUMMY_IF
1587	tristate "Simple big.LITTLE switcher user interface"	1587	tristate "Simple big.LITTLE switcher user interface"
1588	depends on BL_SWITCHER && DEBUG_KERNEL	1588	depends on BL_SWITCHER && DEBUG_KERNEL
1589	help	1589	help
1590	This is a simple and dummy char dev interface to control	1590	This is a simple and dummy char dev interface to control
1591	the big.LITTLE switcher core code. It is meant for	1591	the big.LITTLE switcher core code. It is meant for
1592	debugging purposes only.	1592	debugging purposes only.
1593		1593
1594	choice	1594	choice
1595	prompt "Memory split"	1595	prompt "Memory split"
1596	depends on MMU	1596	depends on MMU
1597	default VMSPLIT_3G	1597	default VMSPLIT_3G
1598	help	1598	help
1599	Select the desired split between kernel and user memory.	1599	Select the desired split between kernel and user memory.
1600		1600
1601	If you are not absolutely sure what you are doing, leave this	1601	If you are not absolutely sure what you are doing, leave this
1602	option alone!	1602	option alone!
1603		1603
1604	config VMSPLIT_3G	1604	config VMSPLIT_3G
1605	bool "3G/1G user/kernel split"	1605	bool "3G/1G user/kernel split"
1606	config VMSPLIT_2G	1606	config VMSPLIT_2G
1607	bool "2G/2G user/kernel split"	1607	bool "2G/2G user/kernel split"
1608	config VMSPLIT_1G	1608	config VMSPLIT_1G
1609	bool "1G/3G user/kernel split"	1609	bool "1G/3G user/kernel split"
1610	endchoice	1610	endchoice
1611		1611
1612	config PAGE_OFFSET	1612	config PAGE_OFFSET
1613	hex	1613	hex
1614	default PHYS_OFFSET if !MMU	1614	default PHYS_OFFSET if !MMU
1615	default 0x40000000 if VMSPLIT_1G	1615	default 0x40000000 if VMSPLIT_1G
1616	default 0x80000000 if VMSPLIT_2G	1616	default 0x80000000 if VMSPLIT_2G
1617	default 0xC0000000	1617	default 0xC0000000
1618		1618
1619	config NR_CPUS	1619	config NR_CPUS
1620	int "Maximum number of CPUs (2-32)"	1620	int "Maximum number of CPUs (2-32)"
1621	range 2 32	1621	range 2 32
1622	depends on SMP	1622	depends on SMP
1623	default "4"	1623	default "4"
1624		1624
1625	config HOTPLUG_CPU	1625	config HOTPLUG_CPU
1626	bool "Support for hot-pluggable CPUs"	1626	bool "Support for hot-pluggable CPUs"
1627	depends on SMP	1627	depends on SMP
1628	help	1628	help
1629	Say Y here to experiment with turning CPUs off and on. CPUs	1629	Say Y here to experiment with turning CPUs off and on. CPUs
1630	can be controlled through /sys/devices/system/cpu.	1630	can be controlled through /sys/devices/system/cpu.
1631		1631
1632	config ARM_PSCI	1632	config ARM_PSCI
1633	bool "Support for the ARM Power State Coordination Interface (PSCI)"	1633	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1634	depends on CPU_V7	1634	depends on CPU_V7
1635	help	1635	help
1636	Say Y here if you want Linux to communicate with system firmware	1636	Say Y here if you want Linux to communicate with system firmware
1637	implementing the PSCI specification for CPU-centric power	1637	implementing the PSCI specification for CPU-centric power
1638	management operations described in ARM document number ARM DEN	1638	management operations described in ARM document number ARM DEN
1639	0022A ("Power State Coordination Interface System Software on	1639	0022A ("Power State Coordination Interface System Software on
1640	ARM processors").	1640	ARM processors").
1641		1641
1642	# The GPIO number here must be sorted by descending number. In case of	1642	# The GPIO number here must be sorted by descending number. In case of
1643	# a multiplatform kernel, we just want the highest value required by the	1643	# a multiplatform kernel, we just want the highest value required by the
1644	# selected platforms.	1644	# selected platforms.
1645	config ARCH_NR_GPIO	1645	config ARCH_NR_GPIO
1646	int	1646	int
1647	default 1024 if ARCH_SHMOBILE \|\| ARCH_TEGRA	1647	default 1024 if ARCH_SHMOBILE \|\| ARCH_TEGRA
1648	default 512 if ARCH_EXYNOS \|\| ARCH_KEYSTONE \|\| SOC_OMAP5 \|\| SOC_DRA7XX \|\| ARCH_S3C24XX \|\| ARCH_S3C64XX	1648	default 512 if ARCH_EXYNOS \|\| ARCH_KEYSTONE \|\| SOC_OMAP5 \|\| SOC_DRA7XX \|\| ARCH_S3C24XX \|\| ARCH_S3C64XX
1649	default 392 if ARCH_U8500	1649	default 392 if ARCH_U8500
1650	default 352 if ARCH_VT8500	1650	default 352 if ARCH_VT8500
1651	default 288 if ARCH_SUNXI	1651	default 288 if ARCH_SUNXI
1652	default 264 if MACH_H4700	1652	default 264 if MACH_H4700
1653	default 0	1653	default 0
1654	help	1654	help
1655	Maximum number of GPIOs in the system.	1655	Maximum number of GPIOs in the system.
1656		1656
1657	If unsure, leave the default value.	1657	If unsure, leave the default value.
1658		1658
1659	source kernel/Kconfig.preempt	1659	source kernel/Kconfig.preempt
1660		1660
1661	config HZ_FIXED	1661	config HZ_FIXED
1662	int	1662	int
1663	default 200 if ARCH_EBSA110 \|\| ARCH_S3C24XX \|\| ARCH_S5P64X0 \|\| \	1663	default 200 if ARCH_EBSA110 \|\| ARCH_S3C24XX \|\| ARCH_S5P64X0 \|\| \
1664	ARCH_S5PV210 \|\| ARCH_EXYNOS4	1664	ARCH_S5PV210 \|\| ARCH_EXYNOS4
1665	default AT91_TIMER_HZ if ARCH_AT91	1665	default AT91_TIMER_HZ if ARCH_AT91
1666	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY	1666	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1667	default 0	1667	default 0
1668		1668
1669	choice	1669	choice
1670	depends on HZ_FIXED = 0	1670	depends on HZ_FIXED = 0
1671	prompt "Timer frequency"	1671	prompt "Timer frequency"
1672		1672
1673	config HZ_100	1673	config HZ_100
1674	bool "100 Hz"	1674	bool "100 Hz"
1675		1675
1676	config HZ_200	1676	config HZ_200
1677	bool "200 Hz"	1677	bool "200 Hz"
1678		1678
1679	config HZ_250	1679	config HZ_250
1680	bool "250 Hz"	1680	bool "250 Hz"
1681		1681
1682	config HZ_300	1682	config HZ_300
1683	bool "300 Hz"	1683	bool "300 Hz"
1684		1684
1685	config HZ_500	1685	config HZ_500
1686	bool "500 Hz"	1686	bool "500 Hz"
1687		1687
1688	config HZ_1000	1688	config HZ_1000
1689	bool "1000 Hz"	1689	bool "1000 Hz"
1690		1690
1691	endchoice	1691	endchoice
1692		1692
1693	config HZ	1693	config HZ
1694	int	1694	int
1695	default HZ_FIXED if HZ_FIXED != 0	1695	default HZ_FIXED if HZ_FIXED != 0
1696	default 100 if HZ_100	1696	default 100 if HZ_100
1697	default 200 if HZ_200	1697	default 200 if HZ_200
1698	default 250 if HZ_250	1698	default 250 if HZ_250
1699	default 300 if HZ_300	1699	default 300 if HZ_300
1700	default 500 if HZ_500	1700	default 500 if HZ_500
1701	default 1000	1701	default 1000
1702		1702
1703	config SCHED_HRTICK	1703	config SCHED_HRTICK
1704	def_bool HIGH_RES_TIMERS	1704	def_bool HIGH_RES_TIMERS
1705		1705
1706	config THUMB2_KERNEL	1706	config THUMB2_KERNEL
1707	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY	1707	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1708	depends on (CPU_V7 \|\| CPU_V7M) && !CPU_V6 && !CPU_V6K	1708	depends on (CPU_V7 \|\| CPU_V7M) && !CPU_V6 && !CPU_V6K
1709	default y if CPU_THUMBONLY	1709	default y if CPU_THUMBONLY
1710	select AEABI	1710	select AEABI
1711	select ARM_ASM_UNIFIED	1711	select ARM_ASM_UNIFIED
1712	select ARM_UNWIND	1712	select ARM_UNWIND
1713	help	1713	help
1714	By enabling this option, the kernel will be compiled in	1714	By enabling this option, the kernel will be compiled in
1715	Thumb-2 mode. A compiler/assembler that understand the unified	1715	Thumb-2 mode. A compiler/assembler that understand the unified
1716	ARM-Thumb syntax is needed.	1716	ARM-Thumb syntax is needed.
1717		1717
1718	If unsure, say N.	1718	If unsure, say N.
1719		1719
1720	config THUMB2_AVOID_R_ARM_THM_JUMP11	1720	config THUMB2_AVOID_R_ARM_THM_JUMP11
1721	bool "Work around buggy Thumb-2 short branch relocations in gas"	1721	bool "Work around buggy Thumb-2 short branch relocations in gas"
1722	depends on THUMB2_KERNEL && MODULES	1722	depends on THUMB2_KERNEL && MODULES
1723	default y	1723	default y
1724	help	1724	help
1725	Various binutils versions can resolve Thumb-2 branches to	1725	Various binutils versions can resolve Thumb-2 branches to
1726	locally-defined, preemptible global symbols as short-range "b.n"	1726	locally-defined, preemptible global symbols as short-range "b.n"
1727	branch instructions.	1727	branch instructions.
1728		1728
1729	This is a problem, because there's no guarantee the final	1729	This is a problem, because there's no guarantee the final
1730	destination of the symbol, or any candidate locations for a	1730	destination of the symbol, or any candidate locations for a
1731	trampoline, are within range of the branch. For this reason, the	1731	trampoline, are within range of the branch. For this reason, the
1732	kernel does not support fixing up the R_ARM_THM_JUMP11 (102)	1732	kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1733	relocation in modules at all, and it makes little sense to add	1733	relocation in modules at all, and it makes little sense to add
1734	support.	1734	support.
1735		1735
1736	The symptom is that the kernel fails with an "unsupported	1736	The symptom is that the kernel fails with an "unsupported
1737	relocation" error when loading some modules.	1737	relocation" error when loading some modules.
1738		1738
1739	Until fixed tools are available, passing	1739	Until fixed tools are available, passing
1740	-fno-optimize-sibling-calls to gcc should prevent gcc generating	1740	-fno-optimize-sibling-calls to gcc should prevent gcc generating
1741	code which hits this problem, at the cost of a bit of extra runtime	1741	code which hits this problem, at the cost of a bit of extra runtime
1742	stack usage in some cases.	1742	stack usage in some cases.
1743		1743
1744	The problem is described in more detail at:	1744	The problem is described in more detail at:
1745	https://bugs.launchpad.net/binutils-linaro/+bug/725126	1745	https://bugs.launchpad.net/binutils-linaro/+bug/725126
1746		1746
1747	Only Thumb-2 kernels are affected.	1747	Only Thumb-2 kernels are affected.
1748		1748
1749	Unless you are sure your tools don't have this problem, say Y.	1749	Unless you are sure your tools don't have this problem, say Y.
1750		1750
1751	config ARM_ASM_UNIFIED	1751	config ARM_ASM_UNIFIED
1752	bool	1752	bool
1753		1753
1754	config AEABI	1754	config AEABI
1755	bool "Use the ARM EABI to compile the kernel"	1755	bool "Use the ARM EABI to compile the kernel"
1756	help	1756	help
1757	This option allows for the kernel to be compiled using the latest	1757	This option allows for the kernel to be compiled using the latest
1758	ARM ABI (aka EABI). This is only useful if you are using a user	1758	ARM ABI (aka EABI). This is only useful if you are using a user
1759	space environment that is also compiled with EABI.	1759	space environment that is also compiled with EABI.
1760		1760
1761	Since there are major incompatibilities between the legacy ABI and	1761	Since there are major incompatibilities between the legacy ABI and
1762	EABI, especially with regard to structure member alignment, this	1762	EABI, especially with regard to structure member alignment, this
1763	option also changes the kernel syscall calling convention to	1763	option also changes the kernel syscall calling convention to
1764	disambiguate both ABIs and allow for backward compatibility support	1764	disambiguate both ABIs and allow for backward compatibility support
1765	(selected with CONFIG_OABI_COMPAT).	1765	(selected with CONFIG_OABI_COMPAT).
1766		1766
1767	To use this you need GCC version 4.0.0 or later.	1767	To use this you need GCC version 4.0.0 or later.
1768		1768
1769	config OABI_COMPAT	1769	config OABI_COMPAT
1770	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"	1770	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1771	depends on AEABI && !THUMB2_KERNEL	1771	depends on AEABI && !THUMB2_KERNEL
1772	help	1772	help
1773	This option preserves the old syscall interface along with the	1773	This option preserves the old syscall interface along with the
1774	new (ARM EABI) one. It also provides a compatibility layer to	1774	new (ARM EABI) one. It also provides a compatibility layer to
1775	intercept syscalls that have structure arguments which layout	1775	intercept syscalls that have structure arguments which layout
1776	in memory differs between the legacy ABI and the new ARM EABI	1776	in memory differs between the legacy ABI and the new ARM EABI
1777	(only for non "thumb" binaries). This option adds a tiny	1777	(only for non "thumb" binaries). This option adds a tiny
1778	overhead to all syscalls and produces a slightly larger kernel.	1778	overhead to all syscalls and produces a slightly larger kernel.
1779		1779
1780	The seccomp filter system will not be available when this is	1780	The seccomp filter system will not be available when this is
1781	selected, since there is no way yet to sensibly distinguish	1781	selected, since there is no way yet to sensibly distinguish
1782	between calling conventions during filtering.	1782	between calling conventions during filtering.
1783		1783
1784	If you know you'll be using only pure EABI user space then you	1784	If you know you'll be using only pure EABI user space then you
1785	can say N here. If this option is not selected and you attempt	1785	can say N here. If this option is not selected and you attempt
1786	to execute a legacy ABI binary then the result will be	1786	to execute a legacy ABI binary then the result will be
1787	UNPREDICTABLE (in fact it can be predicted that it won't work	1787	UNPREDICTABLE (in fact it can be predicted that it won't work
1788	at all). If in doubt say N.	1788	at all). If in doubt say N.
1789		1789
1790	config ARCH_HAS_HOLES_MEMORYMODEL	1790	config ARCH_HAS_HOLES_MEMORYMODEL
1791	bool	1791	bool
1792		1792
1793	config ARCH_SPARSEMEM_ENABLE	1793	config ARCH_SPARSEMEM_ENABLE
1794	bool	1794	bool
1795		1795
1796	config ARCH_SPARSEMEM_DEFAULT	1796	config ARCH_SPARSEMEM_DEFAULT
1797	def_bool ARCH_SPARSEMEM_ENABLE	1797	def_bool ARCH_SPARSEMEM_ENABLE
1798		1798
1799	config ARCH_SELECT_MEMORY_MODEL	1799	config ARCH_SELECT_MEMORY_MODEL
1800	def_bool ARCH_SPARSEMEM_ENABLE	1800	def_bool ARCH_SPARSEMEM_ENABLE
1801		1801
1802	config HAVE_ARCH_PFN_VALID	1802	config HAVE_ARCH_PFN_VALID
1803	def_bool ARCH_HAS_HOLES_MEMORYMODEL \|\| !SPARSEMEM	1803	def_bool ARCH_HAS_HOLES_MEMORYMODEL \|\| !SPARSEMEM
1804		1804
1805	config HIGHMEM	1805	config HIGHMEM
1806	bool "High Memory Support"	1806	bool "High Memory Support"
1807	depends on MMU	1807	depends on MMU
1808	help	1808	help
1809	The address space of ARM processors is only 4 Gigabytes large	1809	The address space of ARM processors is only 4 Gigabytes large
1810	and it has to accommodate user address space, kernel address	1810	and it has to accommodate user address space, kernel address
1811	space as well as some memory mapped IO. That means that, if you	1811	space as well as some memory mapped IO. That means that, if you
1812	have a large amount of physical memory and/or IO, not all of the	1812	have a large amount of physical memory and/or IO, not all of the
1813	memory can be "permanently mapped" by the kernel. The physical	1813	memory can be "permanently mapped" by the kernel. The physical
1814	memory that is not permanently mapped is called "high memory".	1814	memory that is not permanently mapped is called "high memory".
1815		1815
1816	Depending on the selected kernel/user memory split, minimum	1816	Depending on the selected kernel/user memory split, minimum
1817	vmalloc space and actual amount of RAM, you may not need this	1817	vmalloc space and actual amount of RAM, you may not need this
1818	option which should result in a slightly faster kernel.	1818	option which should result in a slightly faster kernel.
1819		1819
1820	If unsure, say n.	1820	If unsure, say n.
1821		1821
1822	config HIGHPTE	1822	config HIGHPTE
1823	bool "Allocate 2nd-level pagetables from highmem"	1823	bool "Allocate 2nd-level pagetables from highmem"
1824	depends on HIGHMEM	1824	depends on HIGHMEM
1825		1825
1826	config HW_PERF_EVENTS	1826	config HW_PERF_EVENTS
1827	bool "Enable hardware performance counter support for perf events"	1827	bool "Enable hardware performance counter support for perf events"
1828	depends on PERF_EVENTS	1828	depends on PERF_EVENTS
1829	default y	1829	default y
1830	help	1830	help
1831	Enable hardware performance counter support for perf events. If	1831	Enable hardware performance counter support for perf events. If
1832	disabled, perf events will use software events only.	1832	disabled, perf events will use software events only.
1833		1833
1834	config SYS_SUPPORTS_HUGETLBFS	1834	config SYS_SUPPORTS_HUGETLBFS
1835	def_bool y	1835	def_bool y
1836	depends on ARM_LPAE	1836	depends on ARM_LPAE
1837		1837
1838	config HAVE_ARCH_TRANSPARENT_HUGEPAGE	1838	config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1839	def_bool y	1839	def_bool y
1840	depends on ARM_LPAE	1840	depends on ARM_LPAE
1841		1841
1842	config ARCH_WANT_GENERAL_HUGETLB	1842	config ARCH_WANT_GENERAL_HUGETLB
1843	def_bool y	1843	def_bool y
1844		1844
1845	source "mm/Kconfig"	1845	source "mm/Kconfig"
1846		1846
1847	config FORCE_MAX_ZONEORDER	1847	config FORCE_MAX_ZONEORDER
1848	int "Maximum zone order" if ARCH_SHMOBILE_LEGACY	1848	int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1849	range 11 64 if ARCH_SHMOBILE_LEGACY	1849	range 11 64 if ARCH_SHMOBILE_LEGACY
1850	default "12" if SOC_AM33XX	1850	default "12" if SOC_AM33XX
1851	default "9" if SA1111 \|\| ARCH_EFM32	1851	default "9" if SA1111 \|\| ARCH_EFM32
1852	default "11"	1852	default "11"
1853	help	1853	help
1854	The kernel memory allocator divides physically contiguous memory	1854	The kernel memory allocator divides physically contiguous memory
1855	blocks into "zones", where each zone is a power of two number of	1855	blocks into "zones", where each zone is a power of two number of
1856	pages. This option selects the largest power of two that the kernel	1856	pages. This option selects the largest power of two that the kernel
1857	keeps in the memory allocator. If you need to allocate very large	1857	keeps in the memory allocator. If you need to allocate very large
1858	blocks of physically contiguous memory, then you may need to	1858	blocks of physically contiguous memory, then you may need to
1859	increase this value.	1859	increase this value.
1860		1860
1861	This config option is actually maximum order plus one. For example,	1861	This config option is actually maximum order plus one. For example,
1862	a value of 11 means that the largest free memory block is 2^10 pages.	1862	a value of 11 means that the largest free memory block is 2^10 pages.
1863		1863
1864	config ALIGNMENT_TRAP	1864	config ALIGNMENT_TRAP
1865	bool	1865	bool
1866	depends on CPU_CP15_MMU	1866	depends on CPU_CP15_MMU
1867	default y if !ARCH_EBSA110	1867	default y if !ARCH_EBSA110
1868	select HAVE_PROC_CPU if PROC_FS	1868	select HAVE_PROC_CPU if PROC_FS
1869	help	1869	help
1870	ARM processors cannot fetch/store information which is not	1870	ARM processors cannot fetch/store information which is not
1871	naturally aligned on the bus, i.e., a 4 byte fetch must start at an	1871	naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1872	address divisible by 4. On 32-bit ARM processors, these non-aligned	1872	address divisible by 4. On 32-bit ARM processors, these non-aligned
1873	fetch/store instructions will be emulated in software if you say	1873	fetch/store instructions will be emulated in software if you say
1874	here, which has a severe performance impact. This is necessary for	1874	here, which has a severe performance impact. This is necessary for
1875	correct operation of some network protocols. With an IP-only	1875	correct operation of some network protocols. With an IP-only
1876	configuration it is safe to say N, otherwise say Y.	1876	configuration it is safe to say N, otherwise say Y.
1877		1877
1878	config UACCESS_WITH_MEMCPY	1878	config UACCESS_WITH_MEMCPY
1879	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"	1879	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1880	depends on MMU	1880	depends on MMU
1881	default y if CPU_FEROCEON	1881	default y if CPU_FEROCEON
1882	help	1882	help
1883	Implement faster copy_to_user and clear_user methods for CPU	1883	Implement faster copy_to_user and clear_user methods for CPU
1884	cores where a 8-word STM instruction give significantly higher	1884	cores where a 8-word STM instruction give significantly higher
1885	memory write throughput than a sequence of individual 32bit stores.	1885	memory write throughput than a sequence of individual 32bit stores.
1886		1886
1887	A possible side effect is a slight increase in scheduling latency	1887	A possible side effect is a slight increase in scheduling latency
1888	between threads sharing the same address space if they invoke	1888	between threads sharing the same address space if they invoke
1889	such copy operations with large buffers.	1889	such copy operations with large buffers.
1890		1890
1891	However, if the CPU data cache is using a write-allocate mode,	1891	However, if the CPU data cache is using a write-allocate mode,
1892	this option is unlikely to provide any performance gain.	1892	this option is unlikely to provide any performance gain.
1893		1893
1894	config SECCOMP	1894	config SECCOMP
1895	bool	1895	bool
1896	prompt "Enable seccomp to safely compute untrusted bytecode"	1896	prompt "Enable seccomp to safely compute untrusted bytecode"
1897	---help---	1897	---help---
1898	This kernel feature is useful for number crunching applications	1898	This kernel feature is useful for number crunching applications
1899	that may need to compute untrusted bytecode during their	1899	that may need to compute untrusted bytecode during their
1900	execution. By using pipes or other transports made available to	1900	execution. By using pipes or other transports made available to
1901	the process as file descriptors supporting the read/write	1901	the process as file descriptors supporting the read/write
1902	syscalls, it's possible to isolate those applications in	1902	syscalls, it's possible to isolate those applications in
1903	their own address space using seccomp. Once seccomp is	1903	their own address space using seccomp. Once seccomp is
1904	enabled via prctl(PR_SET_SECCOMP), it cannot be disabled	1904	enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1905	and the task is only allowed to execute a few safe syscalls	1905	and the task is only allowed to execute a few safe syscalls
1906	defined by each seccomp mode.	1906	defined by each seccomp mode.
1907		1907
1908	config SWIOTLB	1908	config SWIOTLB
1909	def_bool y	1909	def_bool y
1910		1910
1911	config IOMMU_HELPER	1911	config IOMMU_HELPER
1912	def_bool SWIOTLB	1912	def_bool SWIOTLB
1913		1913
1914	config XEN_DOM0	1914	config XEN_DOM0
1915	def_bool y	1915	def_bool y
1916	depends on XEN	1916	depends on XEN
1917		1917
1918	config XEN	1918	config XEN
1919	bool "Xen guest support on ARM (EXPERIMENTAL)"	1919	bool "Xen guest support on ARM (EXPERIMENTAL)"
1920	depends on ARM && AEABI && OF	1920	depends on ARM && AEABI && OF
1921	depends on CPU_V7 && !CPU_V6	1921	depends on CPU_V7 && !CPU_V6
1922	depends on !GENERIC_ATOMIC64	1922	depends on !GENERIC_ATOMIC64
1923	depends on MMU	1923	depends on MMU
1924	select ARCH_DMA_ADDR_T_64BIT	1924	select ARCH_DMA_ADDR_T_64BIT
1925	select ARM_PSCI	1925	select ARM_PSCI
1926	select SWIOTLB_XEN	1926	select SWIOTLB_XEN
1927	help	1927	help
1928	Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.	1928	Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1929		1929
1930	endmenu	1930	endmenu
1931		1931
1932	menu "Boot options"	1932	menu "Boot options"
1933		1933
1934	config USE_OF	1934	config USE_OF
1935	bool "Flattened Device Tree support"	1935	bool "Flattened Device Tree support"
1936	select IRQ_DOMAIN	1936	select IRQ_DOMAIN
1937	select OF	1937	select OF
1938	select OF_EARLY_FLATTREE	1938	select OF_EARLY_FLATTREE
1939	select OF_RESERVED_MEM	1939	select OF_RESERVED_MEM
1940	help	1940	help
1941	Include support for flattened device tree machine descriptions.	1941	Include support for flattened device tree machine descriptions.
1942		1942
1943	config ATAGS	1943	config ATAGS
1944	bool "Support for the traditional ATAGS boot data passing" if USE_OF	1944	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1945	default y	1945	default y
1946	help	1946	help
1947	This is the traditional way of passing data to the kernel at boot	1947	This is the traditional way of passing data to the kernel at boot
1948	time. If you are solely relying on the flattened device tree (or	1948	time. If you are solely relying on the flattened device tree (or
1949	the ARM_ATAG_DTB_COMPAT option) then you may unselect this option	1949	the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1950	to remove ATAGS support from your kernel binary. If unsure,	1950	to remove ATAGS support from your kernel binary. If unsure,
1951	leave this to y.	1951	leave this to y.
1952		1952
1953	config DEPRECATED_PARAM_STRUCT	1953	config DEPRECATED_PARAM_STRUCT
1954	bool "Provide old way to pass kernel parameters"	1954	bool "Provide old way to pass kernel parameters"
1955	depends on ATAGS	1955	depends on ATAGS
1956	help	1956	help
1957	This was deprecated in 2001 and announced to live on for 5 years.	1957	This was deprecated in 2001 and announced to live on for 5 years.
1958	Some old boot loaders still use this way.	1958	Some old boot loaders still use this way.
1959		1959
1960	# Compressed boot loader in ROM. Yes, we really want to ask about	1960	# Compressed boot loader in ROM. Yes, we really want to ask about
1961	# TEXT and BSS so we preserve their values in the config files.	1961	# TEXT and BSS so we preserve their values in the config files.
1962	config ZBOOT_ROM_TEXT	1962	config ZBOOT_ROM_TEXT
1963	hex "Compressed ROM boot loader base address"	1963	hex "Compressed ROM boot loader base address"
1964	default "0"	1964	default "0"
1965	help	1965	help
1966	The physical address at which the ROM-able zImage is to be	1966	The physical address at which the ROM-able zImage is to be
1967	placed in the target. Platforms which normally make use of	1967	placed in the target. Platforms which normally make use of
1968	ROM-able zImage formats normally set this to a suitable	1968	ROM-able zImage formats normally set this to a suitable
1969	value in their defconfig file.	1969	value in their defconfig file.
1970		1970
1971	If ZBOOT_ROM is not enabled, this has no effect.	1971	If ZBOOT_ROM is not enabled, this has no effect.
1972		1972
1973	config ZBOOT_ROM_BSS	1973	config ZBOOT_ROM_BSS
1974	hex "Compressed ROM boot loader BSS address"	1974	hex "Compressed ROM boot loader BSS address"
1975	default "0"	1975	default "0"
1976	help	1976	help
1977	The base address of an area of read/write memory in the target	1977	The base address of an area of read/write memory in the target
1978	for the ROM-able zImage which must be available while the	1978	for the ROM-able zImage which must be available while the
1979	decompressor is running. It must be large enough to hold the	1979	decompressor is running. It must be large enough to hold the
1980	entire decompressed kernel plus an additional 128 KiB.	1980	entire decompressed kernel plus an additional 128 KiB.
1981	Platforms which normally make use of ROM-able zImage formats	1981	Platforms which normally make use of ROM-able zImage formats
1982	normally set this to a suitable value in their defconfig file.	1982	normally set this to a suitable value in their defconfig file.
1983		1983
1984	If ZBOOT_ROM is not enabled, this has no effect.	1984	If ZBOOT_ROM is not enabled, this has no effect.
1985		1985
1986	config ZBOOT_ROM	1986	config ZBOOT_ROM
1987	bool "Compressed boot loader in ROM/flash"	1987	bool "Compressed boot loader in ROM/flash"
1988	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS	1988	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1989	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR	1989	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1990	help	1990	help
1991	Say Y here if you intend to execute your compressed kernel image	1991	Say Y here if you intend to execute your compressed kernel image
1992	(zImage) directly from ROM or flash. If unsure, say N.	1992	(zImage) directly from ROM or flash. If unsure, say N.
1993		1993
1994	choice	1994	choice
1995	prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"	1995	prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1996	depends on ZBOOT_ROM && ARCH_SH7372	1996	depends on ZBOOT_ROM && ARCH_SH7372
1997	default ZBOOT_ROM_NONE	1997	default ZBOOT_ROM_NONE
1998	help	1998	help
1999	Include experimental SD/MMC loading code in the ROM-able zImage.	1999	Include experimental SD/MMC loading code in the ROM-able zImage.
2000	With this enabled it is possible to write the ROM-able zImage	2000	With this enabled it is possible to write the ROM-able zImage
2001	kernel image to an MMC or SD card and boot the kernel straight	2001	kernel image to an MMC or SD card and boot the kernel straight
2002	from the reset vector. At reset the processor Mask ROM will load	2002	from the reset vector. At reset the processor Mask ROM will load
2003	the first part of the ROM-able zImage which in turn loads the	2003	the first part of the ROM-able zImage which in turn loads the
2004	rest the kernel image to RAM.	2004	rest the kernel image to RAM.
2005		2005
2006	config ZBOOT_ROM_NONE	2006	config ZBOOT_ROM_NONE
2007	bool "No SD/MMC loader in zImage (EXPERIMENTAL)"	2007	bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2008	help	2008	help
2009	Do not load image from SD or MMC	2009	Do not load image from SD or MMC
2010		2010
2011	config ZBOOT_ROM_MMCIF	2011	config ZBOOT_ROM_MMCIF
2012	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"	2012	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2013	help	2013	help
2014	Load image from MMCIF hardware block.	2014	Load image from MMCIF hardware block.
2015		2015
2016	config ZBOOT_ROM_SH_MOBILE_SDHI	2016	config ZBOOT_ROM_SH_MOBILE_SDHI
2017	bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"	2017	bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2018	help	2018	help
2019	Load image from SDHI hardware block	2019	Load image from SDHI hardware block
2020		2020
2021	endchoice	2021	endchoice
2022		2022
2023	config ARM_APPENDED_DTB	2023	config ARM_APPENDED_DTB
2024	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"	2024	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2025	depends on OF	2025	depends on OF
2026	help	2026	help
2027	With this option, the boot code will look for a device tree binary	2027	With this option, the boot code will look for a device tree binary
2028	(DTB) appended to zImage	2028	(DTB) appended to zImage
2029	(e.g. cat zImage <filename>.dtb > zImage_w_dtb).	2029	(e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2030		2030
2031	This is meant as a backward compatibility convenience for those	2031	This is meant as a backward compatibility convenience for those
2032	systems with a bootloader that can't be upgraded to accommodate	2032	systems with a bootloader that can't be upgraded to accommodate
2033	the documented boot protocol using a device tree.	2033	the documented boot protocol using a device tree.
2034		2034
2035	Beware that there is very little in terms of protection against	2035	Beware that there is very little in terms of protection against
2036	this option being confused by leftover garbage in memory that might	2036	this option being confused by leftover garbage in memory that might
2037	look like a DTB header after a reboot if no actual DTB is appended	2037	look like a DTB header after a reboot if no actual DTB is appended
2038	to zImage. Do not leave this option active in a production kernel	2038	to zImage. Do not leave this option active in a production kernel
2039	if you don't intend to always append a DTB. Proper passing of the	2039	if you don't intend to always append a DTB. Proper passing of the
2040	location into r2 of a bootloader provided DTB is always preferable	2040	location into r2 of a bootloader provided DTB is always preferable
2041	to this option.	2041	to this option.
2042		2042
2043	config ARM_ATAG_DTB_COMPAT	2043	config ARM_ATAG_DTB_COMPAT
2044	bool "Supplement the appended DTB with traditional ATAG information"	2044	bool "Supplement the appended DTB with traditional ATAG information"
2045	depends on ARM_APPENDED_DTB	2045	depends on ARM_APPENDED_DTB
2046	help	2046	help
2047	Some old bootloaders can't be updated to a DTB capable one, yet	2047	Some old bootloaders can't be updated to a DTB capable one, yet
2048	they provide ATAGs with memory configuration, the ramdisk address,	2048	they provide ATAGs with memory configuration, the ramdisk address,
2049	the kernel cmdline string, etc. Such information is dynamically	2049	the kernel cmdline string, etc. Such information is dynamically
2050	provided by the bootloader and can't always be stored in a static	2050	provided by the bootloader and can't always be stored in a static
2051	DTB. To allow a device tree enabled kernel to be used with such	2051	DTB. To allow a device tree enabled kernel to be used with such
2052	bootloaders, this option allows zImage to extract the information	2052	bootloaders, this option allows zImage to extract the information
2053	from the ATAG list and store it at run time into the appended DTB.	2053	from the ATAG list and store it at run time into the appended DTB.
2054		2054
2055	choice	2055	choice
2056	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT	2056	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2057	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER	2057	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2058		2058
2059	config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER	2059	config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2060	bool "Use bootloader kernel arguments if available"	2060	bool "Use bootloader kernel arguments if available"
2061	help	2061	help
2062	Uses the command-line options passed by the boot loader instead of	2062	Uses the command-line options passed by the boot loader instead of
2063	the device tree bootargs property. If the boot loader doesn't provide	2063	the device tree bootargs property. If the boot loader doesn't provide
2064	any, the device tree bootargs property will be used.	2064	any, the device tree bootargs property will be used.
2065		2065
2066	config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND	2066	config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2067	bool "Extend with bootloader kernel arguments"	2067	bool "Extend with bootloader kernel arguments"
2068	help	2068	help
2069	The command-line arguments provided by the boot loader will be	2069	The command-line arguments provided by the boot loader will be
2070	appended to the the device tree bootargs property.	2070	appended to the the device tree bootargs property.
2071		2071
2072	endchoice	2072	endchoice
2073		2073
2074	config CMDLINE	2074	config CMDLINE
2075	string "Default kernel command string"	2075	string "Default kernel command string"
2076	default ""	2076	default ""
2077	help	2077	help
2078	On some architectures (EBSA110 and CATS), there is currently no way	2078	On some architectures (EBSA110 and CATS), there is currently no way
2079	for the boot loader to pass arguments to the kernel. For these	2079	for the boot loader to pass arguments to the kernel. For these
2080	architectures, you should supply some command-line options at build	2080	architectures, you should supply some command-line options at build
2081	time by entering them here. As a minimum, you should specify the	2081	time by entering them here. As a minimum, you should specify the
2082	memory size and the root device (e.g., mem=64M root=/dev/nfs).	2082	memory size and the root device (e.g., mem=64M root=/dev/nfs).
2083		2083
2084	choice	2084	choice
2085	prompt "Kernel command line type" if CMDLINE != ""	2085	prompt "Kernel command line type" if CMDLINE != ""
2086	default CMDLINE_FROM_BOOTLOADER	2086	default CMDLINE_FROM_BOOTLOADER
2087	depends on ATAGS	2087	depends on ATAGS
2088		2088
2089	config CMDLINE_FROM_BOOTLOADER	2089	config CMDLINE_FROM_BOOTLOADER
2090	bool "Use bootloader kernel arguments if available"	2090	bool "Use bootloader kernel arguments if available"
2091	help	2091	help
2092	Uses the command-line options passed by the boot loader. If	2092	Uses the command-line options passed by the boot loader. If
2093	the boot loader doesn't provide any, the default kernel command	2093	the boot loader doesn't provide any, the default kernel command
2094	string provided in CMDLINE will be used.	2094	string provided in CMDLINE will be used.
2095		2095
2096	config CMDLINE_EXTEND	2096	config CMDLINE_EXTEND
2097	bool "Extend bootloader kernel arguments"	2097	bool "Extend bootloader kernel arguments"
2098	help	2098	help
2099	The command-line arguments provided by the boot loader will be	2099	The command-line arguments provided by the boot loader will be
2100	appended to the default kernel command string.	2100	appended to the default kernel command string.
2101		2101
2102	config CMDLINE_FORCE	2102	config CMDLINE_FORCE
2103	bool "Always use the default kernel command string"	2103	bool "Always use the default kernel command string"
2104	help	2104	help
2105	Always use the default kernel command string, even if the boot	2105	Always use the default kernel command string, even if the boot
2106	loader passes other arguments to the kernel.	2106	loader passes other arguments to the kernel.
2107	This is useful if you cannot or don't want to change the	2107	This is useful if you cannot or don't want to change the
2108	command-line options your boot loader passes to the kernel.	2108	command-line options your boot loader passes to the kernel.
2109	endchoice	2109	endchoice
2110		2110
2111	config XIP_KERNEL	2111	config XIP_KERNEL
2112	bool "Kernel Execute-In-Place from ROM"	2112	bool "Kernel Execute-In-Place from ROM"
2113	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM	2113	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2114	help	2114	help
2115	Execute-In-Place allows the kernel to run from non-volatile storage	2115	Execute-In-Place allows the kernel to run from non-volatile storage
2116	directly addressable by the CPU, such as NOR flash. This saves RAM	2116	directly addressable by the CPU, such as NOR flash. This saves RAM
2117	space since the text section of the kernel is not loaded from flash	2117	space since the text section of the kernel is not loaded from flash
2118	to RAM. Read-write sections, such as the data section and stack,	2118	to RAM. Read-write sections, such as the data section and stack,
2119	are still copied to RAM. The XIP kernel is not compressed since	2119	are still copied to RAM. The XIP kernel is not compressed since
2120	it has to run directly from flash, so it will take more space to	2120	it has to run directly from flash, so it will take more space to
2121	store it. The flash address used to link the kernel object files,	2121	store it. The flash address used to link the kernel object files,
2122	and for storing it, is configuration dependent. Therefore, if you	2122	and for storing it, is configuration dependent. Therefore, if you
2123	say Y here, you must know the proper physical address where to	2123	say Y here, you must know the proper physical address where to
2124	store the kernel image depending on your own flash memory usage.	2124	store the kernel image depending on your own flash memory usage.
2125		2125
2126	Also note that the make target becomes "make xipImage" rather than	2126	Also note that the make target becomes "make xipImage" rather than
2127	"make zImage" or "make Image". The final kernel binary to put in	2127	"make zImage" or "make Image". The final kernel binary to put in
2128	ROM memory will be arch/arm/boot/xipImage.	2128	ROM memory will be arch/arm/boot/xipImage.
2129		2129
2130	If unsure, say N.	2130	If unsure, say N.
2131		2131
2132	config XIP_PHYS_ADDR	2132	config XIP_PHYS_ADDR
2133	hex "XIP Kernel Physical Location"	2133	hex "XIP Kernel Physical Location"
2134	depends on XIP_KERNEL	2134	depends on XIP_KERNEL
2135	default "0x00080000"	2135	default "0x00080000"
2136	help	2136	help
2137	This is the physical address in your flash memory the kernel will	2137	This is the physical address in your flash memory the kernel will
2138	be linked for and stored to. This address is dependent on your	2138	be linked for and stored to. This address is dependent on your
2139	own flash usage.	2139	own flash usage.
2140		2140
2141	config KEXEC	2141	config KEXEC
2142	bool "Kexec system call (EXPERIMENTAL)"	2142	bool "Kexec system call (EXPERIMENTAL)"
2143	depends on (!SMP \|\| PM_SLEEP_SMP)	2143	depends on (!SMP \|\| PM_SLEEP_SMP)
2144	help	2144	help
2145	kexec is a system call that implements the ability to shutdown your	2145	kexec is a system call that implements the ability to shutdown your
2146	current kernel, and to start another kernel. It is like a reboot	2146	current kernel, and to start another kernel. It is like a reboot
2147	but it is independent of the system firmware. And like a reboot	2147	but it is independent of the system firmware. And like a reboot
2148	you can start any kernel with it, not just Linux.	2148	you can start any kernel with it, not just Linux.
2149		2149
2150	It is an ongoing process to be certain the hardware in a machine	2150	It is an ongoing process to be certain the hardware in a machine
2151	is properly shutdown, so do not be surprised if this code does not	2151	is properly shutdown, so do not be surprised if this code does not
2152	initially work for you.	2152	initially work for you.
2153		2153
2154	config ATAGS_PROC	2154	config ATAGS_PROC
2155	bool "Export atags in procfs"	2155	bool "Export atags in procfs"
2156	depends on ATAGS && KEXEC	2156	depends on ATAGS && KEXEC
2157	default y	2157	default y
2158	help	2158	help
2159	Should the atags used to boot the kernel be exported in an "atags"	2159	Should the atags used to boot the kernel be exported in an "atags"
2160	file in procfs. Useful with kexec.	2160	file in procfs. Useful with kexec.
2161		2161
2162	config CRASH_DUMP	2162	config CRASH_DUMP
2163	bool "Build kdump crash kernel (EXPERIMENTAL)"	2163	bool "Build kdump crash kernel (EXPERIMENTAL)"
2164	help	2164	help
2165	Generate crash dump after being started by kexec. This should	2165	Generate crash dump after being started by kexec. This should
2166	be normally only set in special crash dump kernels which are	2166	be normally only set in special crash dump kernels which are
2167	loaded in the main kernel with kexec-tools into a specially	2167	loaded in the main kernel with kexec-tools into a specially
2168	reserved region and then later executed after a crash by	2168	reserved region and then later executed after a crash by
2169	kdump/kexec. The crash dump kernel must be compiled to a	2169	kdump/kexec. The crash dump kernel must be compiled to a
2170	memory address not used by the main kernel	2170	memory address not used by the main kernel
2171		2171
2172	For more details see Documentation/kdump/kdump.txt	2172	For more details see Documentation/kdump/kdump.txt
2173		2173
2174	config AUTO_ZRELADDR	2174	config AUTO_ZRELADDR
2175	bool "Auto calculation of the decompressed kernel image address"	2175	bool "Auto calculation of the decompressed kernel image address"
2176	help	2176	help
2177	ZRELADDR is the physical address where the decompressed kernel	2177	ZRELADDR is the physical address where the decompressed kernel
2178	image will be placed. If AUTO_ZRELADDR is selected, the address	2178	image will be placed. If AUTO_ZRELADDR is selected, the address
2179	will be determined at run-time by masking the current IP with	2179	will be determined at run-time by masking the current IP with
2180	0xf8000000. This assumes the zImage being placed in the first 128MB	2180	0xf8000000. This assumes the zImage being placed in the first 128MB
2181	from start of memory.	2181	from start of memory.
2182		2182
2183	endmenu	2183	endmenu
2184		2184
2185	menu "CPU Power Management"	2185	menu "CPU Power Management"
2186		2186
2187	if ARCH_HAS_CPUFREQ	2187	if ARCH_HAS_CPUFREQ
2188	source "drivers/cpufreq/Kconfig"	2188	source "drivers/cpufreq/Kconfig"
2189	endif	2189	endif
2190		2190
2191	source "drivers/cpuidle/Kconfig"	2191	source "drivers/cpuidle/Kconfig"
2192		2192
2193	endmenu	2193	endmenu
2194		2194
2195	menu "Floating point emulation"	2195	menu "Floating point emulation"
2196		2196
2197	comment "At least one emulation must be selected"	2197	comment "At least one emulation must be selected"
2198		2198
2199	config FPE_NWFPE	2199	config FPE_NWFPE
2200	bool "NWFPE math emulation"	2200	bool "NWFPE math emulation"
2201	depends on (!AEABI \|\| OABI_COMPAT) && !THUMB2_KERNEL	2201	depends on (!AEABI \|\| OABI_COMPAT) && !THUMB2_KERNEL
2202	---help---	2202	---help---
2203	Say Y to include the NWFPE floating point emulator in the kernel.	2203	Say Y to include the NWFPE floating point emulator in the kernel.
2204	This is necessary to run most binaries. Linux does not currently	2204	This is necessary to run most binaries. Linux does not currently
2205	support floating point hardware so you need to say Y here even if	2205	support floating point hardware so you need to say Y here even if
2206	your machine has an FPA or floating point co-processor podule.	2206	your machine has an FPA or floating point co-processor podule.
2207		2207
2208	You may say N here if you are going to load the Acorn FPEmulator	2208	You may say N here if you are going to load the Acorn FPEmulator
2209	early in the bootup.	2209	early in the bootup.
2210		2210
2211	config FPE_NWFPE_XP	2211	config FPE_NWFPE_XP
2212	bool "Support extended precision"	2212	bool "Support extended precision"
2213	depends on FPE_NWFPE	2213	depends on FPE_NWFPE
2214	help	2214	help
2215	Say Y to include 80-bit support in the kernel floating-point	2215	Say Y to include 80-bit support in the kernel floating-point
2216	emulator. Otherwise, only 32 and 64-bit support is compiled in.	2216	emulator. Otherwise, only 32 and 64-bit support is compiled in.
2217	Note that gcc does not generate 80-bit operations by default,	2217	Note that gcc does not generate 80-bit operations by default,
2218	so in most cases this option only enlarges the size of the	2218	so in most cases this option only enlarges the size of the
2219	floating point emulator without any good reason.	2219	floating point emulator without any good reason.
2220		2220
2221	You almost surely want to say N here.	2221	You almost surely want to say N here.
2222		2222
2223	config FPE_FASTFPE	2223	config FPE_FASTFPE
2224	bool "FastFPE math emulation (EXPERIMENTAL)"	2224	bool "FastFPE math emulation (EXPERIMENTAL)"
2225	depends on (!AEABI \|\| OABI_COMPAT) && !CPU_32v3	2225	depends on (!AEABI \|\| OABI_COMPAT) && !CPU_32v3
2226	---help---	2226	---help---
2227	Say Y here to include the FAST floating point emulator in the kernel.	2227	Say Y here to include the FAST floating point emulator in the kernel.
2228	This is an experimental much faster emulator which now also has full	2228	This is an experimental much faster emulator which now also has full
2229	precision for the mantissa. It does not support any exceptions.	2229	precision for the mantissa. It does not support any exceptions.
2230	It is very simple, and approximately 3-6 times faster than NWFPE.	2230	It is very simple, and approximately 3-6 times faster than NWFPE.
2231		2231
2232	It should be sufficient for most programs. It may be not suitable	2232	It should be sufficient for most programs. It may be not suitable
2233	for scientific calculations, but you have to check this for yourself.	2233	for scientific calculations, but you have to check this for yourself.
2234	If you do not feel you need a faster FP emulation you should better	2234	If you do not feel you need a faster FP emulation you should better
2235	choose NWFPE.	2235	choose NWFPE.
2236		2236
2237	config VFP	2237	config VFP
2238	bool "VFP-format floating point maths"	2238	bool "VFP-format floating point maths"
2239	depends on CPU_V6 \|\| CPU_V6K \|\| CPU_ARM926T \|\| CPU_V7 \|\| CPU_FEROCEON	2239	depends on CPU_V6 \|\| CPU_V6K \|\| CPU_ARM926T \|\| CPU_V7 \|\| CPU_FEROCEON
2240	help	2240	help
2241	Say Y to include VFP support code in the kernel. This is needed	2241	Say Y to include VFP support code in the kernel. This is needed
2242	if your hardware includes a VFP unit.	2242	if your hardware includes a VFP unit.
2243		2243
2244	Please see <file:Documentation/arm/VFP/release-notes.txt> for	2244	Please see <file:Documentation/arm/VFP/release-notes.txt> for
2245	release notes and additional status information.	2245	release notes and additional status information.
2246		2246
2247	Say N if your target does not have VFP hardware.	2247	Say N if your target does not have VFP hardware.
2248		2248
2249	config VFPv3	2249	config VFPv3
2250	bool	2250	bool
2251	depends on VFP	2251	depends on VFP
2252	default y if CPU_V7	2252	default y if CPU_V7
2253		2253
2254	config NEON	2254	config NEON
2255	bool "Advanced SIMD (NEON) Extension support"	2255	bool "Advanced SIMD (NEON) Extension support"
2256	depends on VFPv3 && CPU_V7	2256	depends on VFPv3 && CPU_V7
2257	help	2257	help
2258	Say Y to include support code for NEON, the ARMv7 Advanced SIMD	2258	Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2259	Extension.	2259	Extension.
2260		2260
2261	config KERNEL_MODE_NEON	2261	config KERNEL_MODE_NEON
2262	bool "Support for NEON in kernel mode"	2262	bool "Support for NEON in kernel mode"
2263	depends on NEON && AEABI	2263	depends on NEON && AEABI
2264	help	2264	help
2265	Say Y to include support for NEON in kernel mode.	2265	Say Y to include support for NEON in kernel mode.
2266		2266
2267	endmenu	2267	endmenu
2268		2268
2269	menu "Userspace binary formats"	2269	menu "Userspace binary formats"
2270		2270
2271	source "fs/Kconfig.binfmt"	2271	source "fs/Kconfig.binfmt"
2272		2272
2273	config ARTHUR	2273	config ARTHUR
2274	tristate "RISC OS personality"	2274	tristate "RISC OS personality"
2275	depends on !AEABI	2275	depends on !AEABI
2276	help	2276	help
2277	Say Y here to include the kernel code necessary if you want to run	2277	Say Y here to include the kernel code necessary if you want to run
2278	Acorn RISC OS/Arthur binaries under Linux. This code is still very	2278	Acorn RISC OS/Arthur binaries under Linux. This code is still very
2279	experimental; if this sounds frightening, say N and sleep in peace.	2279	experimental; if this sounds frightening, say N and sleep in peace.
2280	You can also say M here to compile this support as a module (which	2280	You can also say M here to compile this support as a module (which
2281	will be called arthur).	2281	will be called arthur).
2282		2282
2283	endmenu	2283	endmenu
2284		2284
2285	menu "Power management options"	2285	menu "Power management options"
2286		2286
2287	source "kernel/power/Kconfig"	2287	source "kernel/power/Kconfig"
2288		2288
2289	config ARCH_SUSPEND_POSSIBLE	2289	config ARCH_SUSPEND_POSSIBLE
2290	depends on !ARCH_S5PC100	2290	depends on !ARCH_S5PC100
2291	depends on CPU_ARM920T \|\| CPU_ARM926T \|\| CPU_FEROCEON \|\| CPU_SA1100 \|\| \	2291	depends on CPU_ARM920T \|\| CPU_ARM926T \|\| CPU_FEROCEON \|\| CPU_SA1100 \|\| \
2292	CPU_V6 \|\| CPU_V6K \|\| CPU_V7 \|\| CPU_V7M \|\| CPU_XSC3 \|\| CPU_XSCALE \|\| CPU_MOHAWK	2292	CPU_V6 \|\| CPU_V6K \|\| CPU_V7 \|\| CPU_V7M \|\| CPU_XSC3 \|\| CPU_XSCALE \|\| CPU_MOHAWK
2293	def_bool y	2293	def_bool y
2294		2294
2295	config ARM_CPU_SUSPEND	2295	config ARM_CPU_SUSPEND
2296	def_bool PM_SLEEP	2296	def_bool PM_SLEEP
2297		2297
2298	endmenu	2298	endmenu
2299		2299
2300	source "net/Kconfig"	2300	source "net/Kconfig"
2301		2301
2302	source "drivers/Kconfig"	2302	source "drivers/Kconfig"
2303		2303
2304	source "fs/Kconfig"	2304	source "fs/Kconfig"
2305		2305
2306	source "arch/arm/Kconfig.debug"	2306	source "arch/arm/Kconfig.debug"
2307		2307
2308	source "security/Kconfig"	2308	source "security/Kconfig"
2309		2309
2310	source "crypto/Kconfig"	2310	source "crypto/Kconfig"
2311		2311
2312	source "lib/Kconfig"	2312	source "lib/Kconfig"
2313		2313
2314	source "arch/arm/kvm/Kconfig"	2314	source "arch/arm/kvm/Kconfig"
2315		2315

arch/arm/include/asm/cputype.h

Diff comments View file @ 2b9d1c0

 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 #include <linux/stringify.h>
 #include <linux/kernel.h>
 #define CPUID_ID	0
 #define CPUID_CACHETYPE	1
 #define CPUID_TCM	2
 #define CPUID_TLBTYPE	3
 #define CPUID_MPUIR	4
 #define CPUID_MPIDR	5
 #define CPUID_REVIDR	6
 #ifdef CONFIG_CPU_V7M
 #define CPUID_EXT_PFR0	0x40
 #define CPUID_EXT_PFR1	0x44
 #define CPUID_EXT_DFR0	0x48
 #define CPUID_EXT_AFR0	0x4c
 #define CPUID_EXT_MMFR0	0x50
 #define CPUID_EXT_MMFR1	0x54
 #define CPUID_EXT_MMFR2	0x58
 #define CPUID_EXT_MMFR3	0x5c
 #define CPUID_EXT_ISAR0	0x60
 #define CPUID_EXT_ISAR1	0x64
 #define CPUID_EXT_ISAR2	0x68
 #define CPUID_EXT_ISAR3	0x6c
 #define CPUID_EXT_ISAR4	0x70
 #define CPUID_EXT_ISAR5	0x74
 #else
 #define CPUID_EXT_PFR0	"c1, 0"
 #define CPUID_EXT_PFR1	"c1, 1"
 #define CPUID_EXT_DFR0	"c1, 2"
 #define CPUID_EXT_AFR0	"c1, 3"
 #define CPUID_EXT_MMFR0	"c1, 4"
 #define CPUID_EXT_MMFR1	"c1, 5"
 #define CPUID_EXT_MMFR2	"c1, 6"
 #define CPUID_EXT_MMFR3	"c1, 7"
 #define CPUID_EXT_ISAR0	"c2, 0"
 #define CPUID_EXT_ISAR1	"c2, 1"
 #define CPUID_EXT_ISAR2	"c2, 2"
 #define CPUID_EXT_ISAR3	"c2, 3"
 #define CPUID_EXT_ISAR4	"c2, 4"
 #define CPUID_EXT_ISAR5	"c2, 5"
 #endif
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
 #define MPIDR_MT_BITMASK (0x1 << 24)
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
 	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 #define ARM_CPU_IMP_ARM			0x41
 #define ARM_CPU_IMP_INTEL		0x69
 #define ARM_CPU_PART_ARM1136		0xB360
 #define ARM_CPU_PART_ARM1156		0xB560
 #define ARM_CPU_PART_ARM1176		0xB760
 #define ARM_CPU_PART_ARM11MPCORE	0xB020
 #define ARM_CPU_PART_CORTEX_A8		0xC080
 #define ARM_CPU_PART_CORTEX_A9		0xC090
 #define ARM_CPU_PART_CORTEX_A5		0xC050
 #define ARM_CPU_PART_CORTEX_A15		0xC0F0
 #define ARM_CPU_PART_CORTEX_A7		0xC070
 #define ARM_CPU_PART_CORTEX_A12		0xC0D0
 #define ARM_CPU_XSCALE_ARCH_MASK	0xe000
 #define ARM_CPU_XSCALE_ARCH_V1		0x2000
 #define ARM_CPU_XSCALE_ARCH_V2		0x4000
 #define ARM_CPU_XSCALE_ARCH_V3		0x6000
 extern unsigned int processor_id;
 #ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)							\
 	({								\
 		unsigned int __val;					\
 		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
 		    : "=r" (__val)					\
 		    :							\
 		    : "cc");						\
 		__val;							\
 	})
 /*
  * The memory clobber prevents gcc 4.5 from reordering the mrc before
  * any is_smp() tests, which can cause undefined instruction aborts on
  * ARM1136 r0 due to the missing extended CP15 registers.
  */
 #define read_cpuid_ext(ext_reg)						\
 	({								\
 		unsigned int __val;					\
 		asm("mrc	p15, 0, %0, c0, " ext_reg		\
 		    : "=r" (__val)					\
 		    :							\
 		    : "memory");					\
 		__val;							\
 	})
 #elif defined(CONFIG_CPU_V7M)
 #include <asm/io.h>
 #include <asm/v7m.h>
 #define read_cpuid(reg)							\
 	({								\
 		WARN_ON_ONCE(1);					\
 		0;							\
 	})
 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 {
 	return readl(BASEADDR_V7M_SCB + offset);
 }
 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 /*
  * read_cpuid and read_cpuid_ext should only ever be called on machines that
  * have cp15 so warn on other usages.
  */
 #define read_cpuid(reg)							\
 	({								\
 		WARN_ON_ONCE(1);					\
 		0;							\
 	})
 #define read_cpuid_ext(reg) read_cpuid(reg)
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 #ifdef CONFIG_CPU_CP15
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
  * rather than directly reading processor_id or read_cpuid() directly.
  */
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
 	return read_cpuid(CPUID_ID);
 }
 #elif defined(CONFIG_CPU_V7M)
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 }
 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
 	return processor_id;
 }
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 {
 	return (read_cpuid_id() & 0xFF000000) >> 24;
 }
 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 {
 	return read_cpuid_id() & 0xFFF0;
 }
 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 {
 	return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 }
 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 {
 	return read_cpuid(CPUID_CACHETYPE);
 }
 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 {
 	return read_cpuid(CPUID_TCM);
 }
 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 {
 	return read_cpuid(CPUID_MPIDR);
 }
 /*
  * Intel's XScale3 core supports some v6 features (supersections, L2)
  * but advertises itself as v5 as it does not support the v6 ISA.  For
  * this reason, we need a way to explicitly test for this type of CPU.
  */
 #ifndef CONFIG_CPU_XSC3
 #define cpu_is_xsc3()	0
 #else
 static inline int cpu_is_xsc3(void)
 {
 	unsigned int id;
 	id = read_cpuid_id() & 0xffffe000;
 	/* It covers both Intel ID and Marvell ID */
 	if ((id == 0x69056000) || (id == 0x56056000))
 		return 1;
 	return 0;
 }
 #endif
 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 #define	cpu_is_xscale()	0
 #else
 #define	cpu_is_xscale()	1
 #endif
 /*
- * Marvell's PJ4 core is based on V7 version. It has some modification
+ * Marvell's PJ4 and PJ4B cores are based on V7 version,
- * for coprocessor setting. For this reason, we need a way to distinguish
+ * but require a specical sequence for enabling coprocessors.
- * it.
+ * For this reason, we need a way to distinguish them.
  */
-#ifndef CONFIG_CPU_PJ4
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
-#define cpu_is_pj4()	0
-#else
 static inline int cpu_is_pj4(void)
 {
 	unsigned int id;
 	id = read_cpuid_id();
-	if ((id & 0xfffffff0) == 0x562f5840)
+	if ((id & 0xff0fff00) == 0x560f5800)
 		return 1;
 	return 0;
 }
+#else
+#define cpu_is_pj4()	0
 #endif

arch/arm/kernel/Makefile

Diff comments View file @ 2b9d1c0

 #
 # Makefile for the linux kernel.
 #
 CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
 AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
 ifdef CONFIG_FUNCTION_TRACER
 CFLAGS_REMOVE_ftrace.o = -pg
 CFLAGS_REMOVE_insn.o = -pg
 CFLAGS_REMOVE_patch.o = -pg
 endif
 CFLAGS_REMOVE_return_address.o = -pg
 # Object file lists.
 obj-y		:= elf.o entry-common.o irq.o opcodes.o \
 		   process.o ptrace.o return_address.o \
 		   setup.o signal.o sigreturn_codes.o \
 		   stacktrace.o sys_arm.o time.o traps.o
 obj-$(CONFIG_ATAGS)		+= atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 ifeq ($(CONFIG_CPU_V7M),y)
 obj-y		+= entry-v7m.o v7m.o
 else
 obj-y		+= entry-armv.o
 endif
 obj-$(CONFIG_OC_ETM)		+= etm.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)	+= dma.o
 obj-$(CONFIG_FIQ)		+= fiq.o fiqasm.o
 obj-$(CONFIG_MODULES)		+= armksyms.o module.o
 obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
 obj-$(CONFIG_SMP)		+= smp.o
 ifdef CONFIG_MMU
 obj-$(CONFIG_SMP)		+= smp_tlb.o
 endif
 obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)	+= arch_timer.o
 obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o insn.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)	+= ftrace.o insn.o
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o insn.o patch.o
 obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_UPROBES)		+= probes.o probes-arm.o uprobes.o uprobes-arm.o
 obj-$(CONFIG_KPROBES)		+= probes.o kprobes.o kprobes-common.o patch.o
 ifdef CONFIG_THUMB2_KERNEL
 obj-$(CONFIG_KPROBES)		+= kprobes-thumb.o probes-thumb.o
 else
 obj-$(CONFIG_KPROBES)		+= kprobes-arm.o probes-arm.o
 endif
 obj-$(CONFIG_ARM_KPROBES_TEST)	+= test-kprobes.o
 test-kprobes-objs		:= kprobes-test.o
 ifdef CONFIG_THUMB2_KERNEL
 test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs		+= kprobes-test-arm.o
 endif
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
 obj-$(CONFIG_OF)		+= devtree.o
 obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
 obj-$(CONFIG_SWP_EMULATE)	+= swp_emulate.o
 CFLAGS_swp_emulate.o		:= -Wa,-march=armv7-a
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
+obj-$(CONFIG_CPU_PJ4B)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
 obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o
 obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o
 AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 ifneq ($(CONFIG_ARCH_EBSA110),y)
   obj-y		+= io.o
 endif
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 obj-$(CONFIG_ARM_VIRT_EXT)	+= hyp-stub.o
 ifeq ($(CONFIG_ARM_PSCI),y)
 obj-y				+= psci.o
 obj-$(CONFIG_SMP)		+= psci_smp.o
 endif
 extra-y := $(head-y) vmlinux.lds

arch/arm/kernel/iwmmxt.S

Diff comments View file @ 2b9d1c0

 /*
  *  linux/arch/arm/kernel/iwmmxt.S
  *
  *  XScale iWMMXt (Concan) context switching and handling
  *
  *  Initial code:
  *  Copyright (c) 2003, Intel Corporation
  *
  *  Full lazy switching support, optimizations and more, by Nicolas Pitre
 *   Copyright (c) 2003-2004, MontaVista Software, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
-#if defined(CONFIG_CPU_PJ4)
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)		code
 #define XSC(code...)
-#else
+#elif defined(CONFIG_CPU_MOHAWK) || \
+	defined(CONFIG_CPU_XSC3) || \
+	defined(CONFIG_CPU_XSCALE)
 #define PJ4(code...)
 #define XSC(code...)		code
+#else
+#error "Unsupported iWMMXt architecture"
 #endif
 #define MMX_WR0		 	(0x00)
 #define MMX_WR1		 	(0x08)
 #define MMX_WR2		 	(0x10)
 #define MMX_WR3			(0x18)
 #define MMX_WR4		 	(0x20)
 #define MMX_WR5		 	(0x28)
 #define MMX_WR6		 	(0x30)
 #define MMX_WR7		 	(0x38)
 #define MMX_WR8		 	(0x40)
 #define MMX_WR9		 	(0x48)
 #define MMX_WR10		(0x50)
 #define MMX_WR11		(0x58)
 #define MMX_WR12		(0x60)
 #define MMX_WR13		(0x68)
 #define MMX_WR14		(0x70)
 #define MMX_WR15		(0x78)
 #define MMX_WCSSF		(0x80)
 #define MMX_WCASF		(0x84)
 #define MMX_WCGR0		(0x88)
 #define MMX_WCGR1		(0x8C)
 #define MMX_WCGR2		(0x90)
 #define MMX_WCGR3		(0x94)
 #define MMX_SIZE		(0x98)
 	.text
 /*
  * Lazy switching of Concan coprocessor context
  *
  * r10 = struct thread_info pointer
  * r9  = ret_from_exception
  * lr  = undefined instr exit
  *
  * called from prefetch exception handler with interrupts disabled
  */
 ENTRY(iwmmxt_task_enable)
 	XSC(mrc	p15, 0, r2, c15, c1, 0)
 	PJ4(mrc p15, 0, r2, c1, c0, 2)
 	@ CP0 and CP1 accessible?
 	XSC(tst	r2, #0x3)
 	PJ4(tst	r2, #0xf)
 	movne	pc, lr				@ if so no business here
 	@ enable access to CP0 and CP1
 	XSC(orr	r2, r2, #0x3)
 	XSC(mcr	p15, 0, r2, c15, c1, 0)
 	PJ4(orr	r2, r2, #0xf)
 	PJ4(mcr	p15, 0, r2, c1, c0, 2)
 	ldr	r3, =concan_owner
 	add	r0, r10, #TI_IWMMXT_STATE	@ get task Concan save area
 	ldr	r2, [sp, #60]			@ current task pc value
 	ldr	r1, [r3]			@ get current Concan owner
 	str	r0, [r3]			@ this task now owns Concan regs
 	sub	r2, r2, #4			@ adjust pc back
 	str	r2, [sp, #60]
 	mrc	p15, 0, r2, c2, c0, 0
 	mov	r2, r2				@ cpwait
 	teq	r1, #0				@ test for last ownership
 	mov	lr, r9				@ normal exit from exception
 	beq	concan_load			@ no owner, skip save
 concan_save:
 	tmrc	r2, wCon
 	@ CUP? wCx
 	tst	r2, #0x1
 	beq 	1f
 concan_dump:
 	wstrw	wCSSF, [r1, #MMX_WCSSF]
 	wstrw	wCASF, [r1, #MMX_WCASF]
 	wstrw	wCGR0, [r1, #MMX_WCGR0]
 	wstrw	wCGR1, [r1, #MMX_WCGR1]
 	wstrw	wCGR2, [r1, #MMX_WCGR2]
 	wstrw	wCGR3, [r1, #MMX_WCGR3]
 1:	@ MUP? wRn
 	tst	r2, #0x2
 	beq	2f
 	wstrd	wR0,  [r1, #MMX_WR0]
 	wstrd	wR1,  [r1, #MMX_WR1]
 	wstrd	wR2,  [r1, #MMX_WR2]
 	wstrd	wR3,  [r1, #MMX_WR3]
 	wstrd	wR4,  [r1, #MMX_WR4]
 	wstrd	wR5,  [r1, #MMX_WR5]
 	wstrd	wR6,  [r1, #MMX_WR6]
 	wstrd	wR7,  [r1, #MMX_WR7]
 	wstrd	wR8,  [r1, #MMX_WR8]
 	wstrd	wR9,  [r1, #MMX_WR9]
 	wstrd	wR10, [r1, #MMX_WR10]
 	wstrd	wR11, [r1, #MMX_WR11]
 	wstrd	wR12, [r1, #MMX_WR12]
 	wstrd	wR13, [r1, #MMX_WR13]
 	wstrd	wR14, [r1, #MMX_WR14]
 	wstrd	wR15, [r1, #MMX_WR15]
 2:	teq	r0, #0				@ anything to load?
 	moveq	pc, lr
 concan_load:
 	@ Load wRn
 	wldrd	wR0,  [r0, #MMX_WR0]
 	wldrd	wR1,  [r0, #MMX_WR1]
 	wldrd	wR2,  [r0, #MMX_WR2]
 	wldrd	wR3,  [r0, #MMX_WR3]
 	wldrd	wR4,  [r0, #MMX_WR4]
 	wldrd	wR5,  [r0, #MMX_WR5]
 	wldrd	wR6,  [r0, #MMX_WR6]
 	wldrd	wR7,  [r0, #MMX_WR7]
 	wldrd	wR8,  [r0, #MMX_WR8]
 	wldrd	wR9,  [r0, #MMX_WR9]
 	wldrd	wR10, [r0, #MMX_WR10]
 	wldrd	wR11, [r0, #MMX_WR11]
 	wldrd	wR12, [r0, #MMX_WR12]
 	wldrd	wR13, [r0, #MMX_WR13]
 	wldrd	wR14, [r0, #MMX_WR14]
 	wldrd	wR15, [r0, #MMX_WR15]
 	@ Load wCx
 	wldrw	wCSSF, [r0, #MMX_WCSSF]
 	wldrw	wCASF, [r0, #MMX_WCASF]
 	wldrw	wCGR0, [r0, #MMX_WCGR0]
 	wldrw	wCGR1, [r0, #MMX_WCGR1]
 	wldrw	wCGR2, [r0, #MMX_WCGR2]
 	wldrw	wCGR3, [r0, #MMX_WCGR3]
 	@ clear CUP/MUP (only if r1 != 0)
 	teq	r1, #0
 	mov 	r2, #0
 	moveq	pc, lr
 	tmcr	wCon, r2
 	mov	pc, lr
 /*
  * Back up Concan regs to save area and disable access to them
  * (mainly for gdb or sleep mode usage)
  *
  * r0 = struct thread_info pointer of target task or NULL for any
  */
 ENTRY(iwmmxt_task_disable)
 	stmfd	sp!, {r4, lr}
 	mrs	ip, cpsr
 	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
 	msr	cpsr_c, r2
 	ldr	r3, =concan_owner
 	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
 	ldr	r1, [r3]			@ get current Concan owner
 	teq	r1, #0				@ any current owner?
 	beq	1f				@ no: quit
 	teq	r0, #0				@ any owner?
 	teqne	r1, r2				@ or specified one?
 	bne	1f				@ no: quit
 	@ enable access to CP0 and CP1
 	XSC(mrc	p15, 0, r4, c15, c1, 0)
 	XSC(orr	r4, r4, #0x3)
 	XSC(mcr	p15, 0, r4, c15, c1, 0)
 	PJ4(mrc p15, 0, r4, c1, c0, 2)
 	PJ4(orr	r4, r4, #0xf)
 	PJ4(mcr	p15, 0, r4, c1, c0, 2)
 	mov	r0, #0				@ nothing to load
 	str	r0, [r3]			@ no more current owner
 	mrc	p15, 0, r2, c2, c0, 0
 	mov	r2, r2				@ cpwait
 	bl	concan_save
 	@ disable access to CP0 and CP1
 	XSC(bic	r4, r4, #0x3)
 	XSC(mcr	p15, 0, r4, c15, c1, 0)
 	PJ4(bic	r4, r4, #0xf)
 	PJ4(mcr	p15, 0, r4, c1, c0, 2)
 	mrc	p15, 0, r2, c2, c0, 0
 	mov	r2, r2				@ cpwait
 1:	msr	cpsr_c, ip			@ restore interrupt mode
 	ldmfd	sp!, {r4, pc}
 /*
  * Copy Concan state to given memory address
  *
  * r0 = struct thread_info pointer of target task
  * r1 = memory address where to store Concan state
  *
  * this is called mainly in the creation of signal stack frames
  */
 ENTRY(iwmmxt_task_copy)
 	mrs	ip, cpsr
 	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
 	msr	cpsr_c, r2
 	ldr	r3, =concan_owner
 	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
 	ldr	r3, [r3]			@ get current Concan owner
 	teq	r2, r3				@ does this task own it...
 	beq	1f
 	@ current Concan values are in the task save area
 	msr	cpsr_c, ip			@ restore interrupt mode
 	mov	r0, r1
 	mov	r1, r2
 	mov	r2, #MMX_SIZE
 	b	memcpy
 1:	@ this task owns Concan regs -- grab a copy from there
 	mov	r0, #0				@ nothing to load
 	mov	r2, #3				@ save all regs
 	mov	r3, lr				@ preserve return address
 	bl	concan_dump
 	msr	cpsr_c, ip			@ restore interrupt mode
 	mov	pc, r3
 /*
  * Restore Concan state from given memory address
  *
  * r0 = struct thread_info pointer of target task
  * r1 = memory address where to get Concan state from
  *
  * this is used to restore Concan state when unwinding a signal stack frame
  */
 ENTRY(iwmmxt_task_restore)
 	mrs	ip, cpsr
 	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
 	msr	cpsr_c, r2
 	ldr	r3, =concan_owner
 	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
 	ldr	r3, [r3]			@ get current Concan owner
 	bic	r2, r2, #0x7			@ 64-bit alignment
 	teq	r2, r3				@ does this task own it...
 	beq	1f
 	@ this task doesn't own Concan regs -- use its save area
 	msr	cpsr_c, ip			@ restore interrupt mode
 	mov	r0, r2
 	mov	r2, #MMX_SIZE
 	b	memcpy
 1:	@ this task owns Concan regs -- load them directly
 	mov	r0, r1
 	mov	r1, #0				@ don't clear CUP/MUP
 	mov	r3, lr				@ preserve return address
 	bl	concan_load
 	msr	cpsr_c, ip			@ restore interrupt mode
 	mov	pc, r3
 /*
  * Concan handling on task switch
  *
  * r0 = next thread_info pointer
  *
  * Called only from the iwmmxt notifier with task preemption disabled.
  */
 ENTRY(iwmmxt_task_switch)
 	XSC(mrc	p15, 0, r1, c15, c1, 0)
 	PJ4(mrc	p15, 0, r1, c1, c0, 2)
 	@ CP0 and CP1 accessible?
 	XSC(tst	r1, #0x3)
 	PJ4(tst	r1, #0xf)
 	bne	1f				@ yes: block them for next task
 	ldr	r2, =concan_owner
 	add	r3, r0, #TI_IWMMXT_STATE	@ get next task Concan save area
 	ldr	r2, [r2]			@ get current Concan owner
 	teq	r2, r3				@ next task owns it?
 	movne	pc, lr				@ no: leave Concan disabled
 1:	@ flip Concan access
 	XSC(eor	r1, r1, #0x3)
 	XSC(mcr	p15, 0, r1, c15, c1, 0)
 	PJ4(eor r1, r1, #0xf)
 	PJ4(mcr	p15, 0, r1, c1, c0, 2)
 	mrc	p15, 0, r1, c2, c0, 0
 	sub	pc, lr, r1, lsr #32		@ cpwait and return
 /*
  * Remove Concan ownership of given task
  *
  * r0 = struct thread_info pointer
  */
 ENTRY(iwmmxt_task_release)
 	mrs	r2, cpsr
 	orr	ip, r2, #PSR_I_BIT		@ disable interrupts
 	msr	cpsr_c, ip
 	ldr	r3, =concan_owner
 	add	r0, r0, #TI_IWMMXT_STATE	@ get task Concan save area
 	ldr	r1, [r3]			@ get current Concan owner
 	eors	r0, r0, r1			@ if equal...
 	streq	r0, [r3]			@ then clear ownership
 	msr	cpsr_c, r2			@ restore interrupts
 	mov	pc, lr
 	.data
 concan_owner:
 	.word	0

arch/arm/kernel/pj4-cp0.c

Diff comments View file @ 2b9d1c0

 /*
  * linux/arch/arm/kernel/pj4-cp0.c
  *
  * PJ4 iWMMXt coprocessor context switching and handling
  *
  * Copyright (c) 2010 Marvell International Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <asm/thread_notify.h>
 #include <asm/cputype.h>
 static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
 {
 	struct thread_info *thread = t;
 	switch (cmd) {
 	case THREAD_NOTIFY_FLUSH:
 		/*
 		 * flush_thread() zeroes thread->fpstate, so no need
 		 * to do anything here.
 		 *
 		 * FALLTHROUGH: Ensure we don't try to overwrite our newly
 		 * initialised state information on the first fault.
 		 */
 	case THREAD_NOTIFY_EXIT:
 		iwmmxt_task_release(thread);
 		break;
 	case THREAD_NOTIFY_SWITCH:
 		iwmmxt_task_switch(thread);
 		break;
 	}
 	return NOTIFY_DONE;
 }
-static struct notifier_block iwmmxt_notifier_block = {
+static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
 	.notifier_call	= iwmmxt_do,
 };
 static u32 __init pj4_cp_access_read(void)
 {
 	u32 value;
 	__asm__ __volatile__ (
 		"mrc	p15, 0, %0, c1, c0, 2\n\t"
 		: "=r" (value));
 	return value;
 }
 static void __init pj4_cp_access_write(u32 value)
 {
 	u32 temp;
 	__asm__ __volatile__ (
 		"mcr	p15, 0, %1, c1, c0, 2\n\t"
 		"mrc	p15, 0, %0, c1, c0, 2\n\t"
 		"mov	%0, %0\n\t"
 		"sub	pc, pc, #4\n\t"
 		: "=r" (temp) : "r" (value));
 }
+static int __init pj4_get_iwmmxt_version(void)
+{
+	u32 cp_access, wcid;
+	cp_access = pj4_cp_access_read();
+	pj4_cp_access_write(cp_access | 0xf);
+	/* check if coprocessor 0 and 1 are available */
+	if ((pj4_cp_access_read() & 0xf) != 0xf) {
+		pj4_cp_access_write(cp_access);
+		return -ENODEV;
+	}
+	/* read iWMMXt coprocessor id register p1, c0 */
+	__asm__ __volatile__ ("mrc    p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
+	pj4_cp_access_write(cp_access);
+	/* iWMMXt v1 */
+	if ((wcid & 0xffffff00) == 0x56051000)
+		return 1;
+	/* iWMMXt v2 */
+	if ((wcid & 0xffffff00) == 0x56052000)
+		return 2;
+	return -EINVAL;
+}
 /*
  * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
  * switch code handle iWMMXt context switching.
  */
 static int __init pj4_cp0_init(void)
 {
-	u32 cp_access;
+	u32 __maybe_unused cp_access;
+	int vers;
 	if (!cpu_is_pj4())
 		return 0;
+	vers = pj4_get_iwmmxt_version();
+	if (vers < 0)
+		return 0;
+#ifndef CONFIG_IWMMXT
+	pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
+#else
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
-	printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
+	pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
 	elf_hwcap |= HWCAP_IWMMXT;
 	thread_register_notifier(&iwmmxt_notifier_block);
+#endif
 	return 0;
 }
 late_initcall(pj4_cp0_init);