Eric Lee / smarc-ti-linux-kernel

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Commit 2b9d1c050d291693f257c98605028325f8146c84

Authored by Linus Torvalds
2 parents afa3cad746 d93003e8e4
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm 

Pull arm fixes from Russell King:
 "A number of fixes for the PJ4/iwmmxt changes which arm-soc forced me
  to take during the merge window.  This stuff should have been better
  tested and sorted out *before* the merge window"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B
  ARM: 8041/1: pj4: fix cpu_is_pj4 check
  ARM: 8040/1: pj4: properly detect existence of iWMMXt coprocessor
  ARM: 8039/1: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
  ARM: 8038/1: iwmmxt: explicitly check for supported architectures

Showing 5 changed files Side-by-side Diff

... ... @@ -1111,9 +1111,9 @@
1111 1111 default 8
1112 1112  
1113 1113 config IWMMXT
1114   - bool "Enable iWMMXt support" if !CPU_PJ4
1115   - depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1116   - default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
  1114 + bool "Enable iWMMXt support"
  1115 + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
  1116 + default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1117 1117 help
1118 1118 Enable support for iWMMXt context switching at run time if
1119 1119 running on a CPU that supports it.
arch/arm/include/asm/cputype.h
Diff comments   View file @ 2b9d1c0
... ... @@ -222,23 +222,23 @@
222 222 #endif
223 223  
224 224 /*
225   - * Marvell's PJ4 core is based on V7 version. It has some modification
226   - * for coprocessor setting. For this reason, we need a way to distinguish
227   - * it.
  225 + * Marvell's PJ4 and PJ4B cores are based on V7 version,
  226 + * but require a specical sequence for enabling coprocessors.
  227 + * For this reason, we need a way to distinguish them.
228 228 */
229   -#ifndef CONFIG_CPU_PJ4
230   -#define cpu_is_pj4() 0
231   -#else
  229 +#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
232 230 static inline int cpu_is_pj4(void)
233 231 {
234 232 unsigned int id;
235 233  
236 234 id = read_cpuid_id();
237   - if ((id & 0xfffffff0) == 0x562f5840)
  235 + if ((id & 0xff0fff00) == 0x560f5800)
238 236 return 1;
239 237  
240 238 return 0;
241 239 }
  240 +#else
  241 +#define cpu_is_pj4() 0
242 242 #endif
243 243 #endif
arch/arm/kernel/Makefile
Diff comments   View file @ 2b9d1c0
... ... @@ -79,6 +79,7 @@
79 79 obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
80 80 obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
81 81 obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
  82 +obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o
82 83 obj-$(CONFIG_IWMMXT) += iwmmxt.o
83 84 obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
84 85 obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
arch/arm/kernel/iwmmxt.S
Diff comments   View file @ 2b9d1c0
... ... @@ -19,12 +19,16 @@
19 19 #include <asm/thread_info.h>
20 20 #include <asm/asm-offsets.h>
21 21  
22   -#if defined(CONFIG_CPU_PJ4)
  22 +#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
23 23 #define PJ4(code...) code
24 24 #define XSC(code...)
25   -#else
  25 +#elif defined(CONFIG_CPU_MOHAWK) || \
  26 + defined(CONFIG_CPU_XSC3) || \
  27 + defined(CONFIG_CPU_XSCALE)
26 28 #define PJ4(code...)
27 29 #define XSC(code...) code
  30 +#else
  31 +#error "Unsupported iWMMXt architecture"
28 32 #endif
29 33  
30 34 #define MMX_WR0 (0x00)
arch/arm/kernel/pj4-cp0.c
Diff comments   View file @ 2b9d1c0
... ... @@ -45,7 +45,7 @@
45 45 return NOTIFY_DONE;
46 46 }
47 47  
48   -static struct notifier_block iwmmxt_notifier_block = {
  48 +static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
49 49 .notifier_call = iwmmxt_do,
50 50 };
51 51  
52 52  
53 53  
54 54  
55 55  
56 56  
... ... @@ -72,24 +72,60 @@
72 72 : "=r" (temp) : "r" (value));
73 73 }
74 74  
  75 +static int __init pj4_get_iwmmxt_version(void)
  76 +{
  77 + u32 cp_access, wcid;
75 78  
  79 + cp_access = pj4_cp_access_read();
  80 + pj4_cp_access_write(cp_access | 0xf);
  81 +
  82 + /* check if coprocessor 0 and 1 are available */
  83 + if ((pj4_cp_access_read() & 0xf) != 0xf) {
  84 + pj4_cp_access_write(cp_access);
  85 + return -ENODEV;
  86 + }
  87 +
  88 + /* read iWMMXt coprocessor id register p1, c0 */
  89 + __asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
  90 +
  91 + pj4_cp_access_write(cp_access);
  92 +
  93 + /* iWMMXt v1 */
  94 + if ((wcid & 0xffffff00) == 0x56051000)
  95 + return 1;
  96 + /* iWMMXt v2 */
  97 + if ((wcid & 0xffffff00) == 0x56052000)
  98 + return 2;
  99 +
  100 + return -EINVAL;
  101 +}
  102 +
76 103 /*
77 104 * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
78 105 * switch code handle iWMMXt context switching.
79 106 */
80 107 static int __init pj4_cp0_init(void)
81 108 {
82   - u32 cp_access;
  109 + u32 __maybe_unused cp_access;
  110 + int vers;
83 111  
84 112 if (!cpu_is_pj4())
85 113 return 0;
86 114  
  115 + vers = pj4_get_iwmmxt_version();
  116 + if (vers < 0)
  117 + return 0;
  118 +
  119 +#ifndef CONFIG_IWMMXT
  120 + pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
  121 +#else
87 122 cp_access = pj4_cp_access_read() & ~0xf;
88 123 pj4_cp_access_write(cp_access);
89 124  
90   - printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
  125 + pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
91 126 elf_hwcap |= HWCAP_IWMMXT;
92 127 thread_register_notifier(&iwmmxt_notifier_block);
  128 +#endif
93 129  
94 130 return 0;
95 131 }