x86, intel_txt: Intel TXT boot support

This patch adds kernel configuration and boot support for Intel Trusted Execution Technology (Intel TXT). Intel's technology for safer computing, Intel Trusted Execution Technology (Intel TXT), defines platform-level enhancements that provide the building blocks for creating trusted platforms. Intel TXT was formerly known by the code name LaGrande Technology (LT). Intel TXT in Brief: o Provides dynamic root of trust for measurement (DRTM) o Data protection in case of improper shutdown o Measurement and verification of launched environment Intel TXT is part of the vPro(TM) brand and is also available some non-vPro systems. It is currently available on desktop systems based on the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell Optiplex 755, HP dc7800, etc.) and mobile systems based on the GM45, PM45, and GS45 Express chipsets. For more information, see http://www.intel.com/technology/security/. This site also has a link to the Intel TXT MLE Developers Manual, which has been updated for the new released platforms. A much more complete description of how these patches support TXT, how to configure a system for it, etc. is in the Documentation/intel_txt.txt file in this patch. This patch provides the TXT support routines for complete functionality, documentation for TXT support and for the changes to the boot_params structure, and boot detection of a TXT launch. Attempts to shutdown (reboot, Sx) the system will result in platform resets; subsequent patches will support these shutdown modes properly. Documentation/intel_txt.txt | 210 +++++++++++++++++++++ Documentation/x86/zero-page.txt | 1 arch/x86/include/asm/bootparam.h | 3 arch/x86/include/asm/fixmap.h | 3 arch/x86/include/asm/tboot.h | 197 ++++++++++++++++++++ arch/x86/kernel/Makefile | 1 arch/x86/kernel/setup.c | 4 arch/x86/kernel/tboot.c | 379 +++++++++++++++++++++++++++++++++++++++ security/Kconfig | 30 +++ 9 files changed, 827 insertions(+), 1 deletion(-) Signed-off-by: Joseph Cihula <joseph.cihula@intel.com> Signed-off-by: Shane Wang <shane.wang@intel.com> Signed-off-by: Gang Wei <gang.wei@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>

x86, intel_txt: Intel TXT boot support
This patch adds kernel configuration and boot support for Intel Trusted Execution Technology (Intel TXT). Intel's technology for safer computing, Intel Trusted Execution Technology (Intel TXT), defines platform-level enhancements that provide the building blocks for creating trusted platforms. Intel TXT was formerly known by the code name LaGrande Technology (LT). Intel TXT in Brief: o Provides dynamic root of trust for measurement (DRTM) o Data protection in case of improper shutdown o Measurement and verification of launched environment Intel TXT is part of the vPro(TM) brand and is also available some non-vPro systems. It is currently available on desktop systems based on the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell Optiplex 755, HP dc7800, etc.) and mobile systems based on the GM45, PM45, and GS45 Express chipsets. For more information, see http://www.intel.com/technology/security/. This site also has a link to the Intel TXT MLE Developers Manual, which has been updated for the new released platforms. A much more complete description of how these patches support TXT, how to configure a system for it, etc. is in the Documentation/intel_txt.txt file in this patch. This patch provides the TXT support routines for complete functionality, documentation for TXT support and for the changes to the boot_params structure, and boot detection of a TXT launch. Attempts to shutdown (reboot, Sx) the system will result in platform resets; subsequent patches will support these shutdown modes properly. Documentation/intel_txt.txt | 210 +++++++++++++++++++++ Documentation/x86/zero-page.txt | 1 arch/x86/include/asm/bootparam.h | 3 arch/x86/include/asm/fixmap.h | 3 arch/x86/include/asm/tboot.h | 197 ++++++++++++++++++++ arch/x86/kernel/Makefile | 1 arch/x86/kernel/setup.c | 4 arch/x86/kernel/tboot.c | 379 +++++++++++++++++++++++++++++++++++++++ security/Kconfig | 30 +++ 9 files changed, 827 insertions(+), 1 deletion(-) Signed-off-by: Joseph Cihula <joseph.cihula@intel.com> Signed-off-by: Shane Wang <shane.wang@intel.com> Signed-off-by: Gang Wei <gang.wei@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Joseph Cihula · H. Peter Anvin
1 parent aea1f7964a
Showing 9 changed files with 827 additions and 1 deletions Side-by-side Diff
Documentation/intel_txt.txt
Documentation/x86/zero-page.txt
arch/x86/include/asm/bootparam.h
arch/x86/include/asm/fixmap.h
arch/x86/include/asm/tboot.h
arch/x86/kernel/Makefile
arch/x86/kernel/setup.c
arch/x86/kernel/tboot.c
security/Kconfig
+Intel(R) TXT Overview:
+=====================
+
+Intel's technology for safer computing, Intel(R) Trusted Execution
+Technology (Intel(R) TXT), defines platform-level enhancements that
+provide the building blocks for creating trusted platforms.
+
+Intel TXT was formerly known by the code name LaGrande Technology (LT).
+
+Intel TXT in Brief:
+o  Provides dynamic root of trust for measurement (DRTM)
+o  Data protection in case of improper shutdown
+o  Measurement and verification of launched environment
+
+Intel TXT is part of the vPro(TM) brand and is also available some
+non-vPro systems.  It is currently available on desktop systems
+based on the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell
+Optiplex 755, HP dc7800, etc.) and mobile systems based on the GM45,
+PM45, and GS45 Express chipsets.
+
+For more information, see http://www.intel.com/technology/security/.
+This site also has a link to the Intel TXT MLE Developers Manual,
+which has been updated for the new released platforms.
+
+Intel TXT has been presented at various events over the past few
+years, some of which are:
+      LinuxTAG 2008:
+          http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag/
+          details.html?talkid=110
+      TRUST2008:
+          http://www.trust2008.eu/downloads/Keynote-Speakers/
+          3_David-Grawrock_The-Front-Door-of-Trusted-Computing.pdf
+      IDF 2008, Shanghai:
+          http://inteldeveloperforum.com.edgesuite.net/shanghai_2008/
+          aep/PROS003/index.html
+      IDFs 2006, 2007 (I'm not sure if/where they are online)
+
+Trusted Boot Project Overview:
+=============================
+
+Trusted Boot (tboot) is an open source, pre- kernel/VMM module that
+uses Intel TXT to perform a measured and verified launch of an OS
+kernel/VMM.
+
+It is hosted on SourceForge at http://sourceforge.net/projects/tboot.
+The mercurial source repo is available at http://www.bughost.org/
+repos.hg/tboot.hg.
+
+Tboot currently supports launching Xen (open source VMM/hypervisor
+w/ TXT support since v3.2), and now Linux kernels.
+
+
+Value Proposition for Linux or "Why should you care?"
+=====================================================
+
+While there are many products and technologies that attempt to
+measure or protect the integrity of a running kernel, they all
+assume the kernel is "good" to begin with.  The Integrity
+Measurement Architecture (IMA) and Linux Integrity Module interface
+are examples of such solutions.
+
+To get trust in the initial kernel without using Intel TXT, a
+static root of trust must be used.  This bases trust in BIOS
+starting at system reset and requires measurement of all code
+executed between system reset through the completion of the kernel
+boot as well as data objects used by that code.  In the case of a
+Linux kernel, this means all of BIOS, any option ROMs, the
+bootloader and the boot config.  In practice, this is a lot of
+code/data, much of which is subject to change from boot to boot
+(e.g. changing NICs may change option ROMs).  Without reference
+hashes, these measurement changes are difficult to assess or
+confirm as benign.  This process also does not provide DMA
+protection, memory configuration/alias checks and locks, crash
+protection, or policy support.
+
+By using the hardware-based root of trust that Intel TXT provides,
+many of these issues can be mitigated.  Specifically: many
+pre-launch components can be removed from the trust chain, DMA
+protection is provided to all launched components, a large number
+of platform configuration checks are performed and values locked,
+protection is provided for any data in the event of an improper
+shutdown, and there is support for policy-based execution/verification.
+This provides a more stable measurement and a higher assurance of
+system configuration and initial state than would be otherwise
+possible.  Since the tboot project is open source, source code for
+almost all parts of the trust chain is available (excepting SMM and
+Intel-provided firmware).
+
+How Does it Work?
+=================
+
+o  Tboot is an executable that is launched by the bootloader as
+   the "kernel" (the binary the bootloader executes).
+o  It performs all of the work necessary to determine if the
+   platform supports Intel TXT and, if so, executes the GETSEC[SENTER]
+   processor instruction that initiates the dynamic root of trust.
+   -  If tboot determines that the system does not support Intel TXT
+      or is not configured correctly (e.g. the SINIT AC Module was
+      incorrect), it will directly launch the kernel with no changes
+      to any state.
+   -  Tboot will output various information about its progress to the
+      terminal, serial port, and/or an in-memory log; the output
+      locations can be configured with a command line switch.
+o  The GETSEC[SENTER] instruction will return control to tboot and
+   tboot then verifies certain aspects of the environment (e.g. TPM NV
+   lock, e820 table does not have invalid entries, etc.).
+o  It will wake the APs from the special sleep state the GETSEC[SENTER]
+   instruction had put them in and place them into a wait-for-SIPI
+   state.
+   -  Because the processors will not respond to an INIT or SIPI when
+      in the TXT environment, it is necessary to create a small VT-x
+      guest for the APs.  When they run in this guest, they will
+      simply wait for the INIT-SIPI-SIPI sequence, which will cause
+      VMEXITs, and then disable VT and jump to the SIPI vector.  This
+      approach seemed like a better choice than having to insert
+      special code into the kernel's MP wakeup sequence.
+o  Tboot then applies an (optional) user-defined launch policy to
+   verify the kernel and initrd.
+   -  This policy is rooted in TPM NV and is described in the tboot
+      project.  The tboot project also contains code for tools to
+      create and provision the policy.
+   -  Policies are completely under user control and if not present
+      then any kernel will be launched.
+   -  Policy action is flexible and can include halting on failures
+      or simply logging them and continuing.
+o  Tboot adjusts the e820 table provided by the bootloader to reserve
+   its own location in memory as well as to reserve certain other
+   TXT-related regions.
+o  As part of it's launch, tboot DMA protects all of RAM (using the
+   VT-d PMRs).  Thus, the kernel must be booted with 'intel_iommu=on'
+   in order to remove this blanket protection and use VT-d's
+   page-level protection.
+o  Tboot will populate a shared page with some data about itself and
+   pass this to the Linux kernel as it transfers control.
+   -  The location of the shared page is passed via the boot_params
+      struct as a physical address.
+o  The kernel will look for the tboot shared page address and, if it
+   exists, map it.
+o  As one of the checks/protections provided by TXT, it makes a copy
+   of the VT-d DMARs in a DMA-protected region of memory and verifies
+   them for correctness.  The VT-d code will detect if the kernel was
+   launched with tboot and use this copy instead of the one in the
+   ACPI table.
+o  At this point, tboot and TXT are out of the picture until a
+   shutdown (S<n>)
+o  In order to put a system into any of the sleep states after a TXT
+   launch, TXT must first be exited.  This is to prevent attacks that
+   attempt to crash the system to gain control on reboot and steal
+   data left in memory.
+   -  The kernel will perform all of its sleep preparation and
+      populate the shared page with the ACPI data needed to put the
+      platform in the desired sleep state.
+   -  Then the kernel jumps into tboot via the vector specified in the
+      shared page.
+   -  Tboot will clean up the environment and disable TXT, then use the
+      kernel-provided ACPI information to actually place the platform
+      into the desired sleep state.
+   -  In the case of S3, tboot will also register itself as the resume
+      vector.  This is necessary because it must re-establish the
+      measured environment upon resume.  Once the TXT environment
+      has been restored, it will restore the TPM PCRs and then
+      transfer control back to the kernel's S3 resume vector.
+      In order to preserve system integrity across S3, the kernel
+      provides tboot with a set of memory ranges (kernel
+      code/data/bss, S3 resume code, and AP trampoline) that tboot
+      will calculate a MAC (message authentication code) over and then
+      seal with the TPM.  On resume and once the measured environment
+      has been re-established, tboot will re-calculate the MAC and
+      verify it against the sealed value.  Tboot's policy determines
+      what happens if the verification fails.
+
+That's pretty much it for TXT support.
+
+
+Configuring the System:
+======================
+
+This code works with 32bit, 32bit PAE, and 64bit (x86_64) kernels.
+
+In BIOS, the user must enable:  TPM, TXT, VT-x, VT-d.  Not all BIOSes
+allow these to be individually enabled/disabled and the screens in
+which to find them are BIOS-specific.
+
+grub.conf needs to be modified as follows:
+        title Linux 2.6.29-tip w/ tboot
+          root (hd0,0)
+                kernel /tboot.gz logging=serial,vga,memory
+                module /vmlinuz-2.6.29-tip intel_iommu=on ro
+                       root=LABEL=/ rhgb console=ttyS0,115200 3
+                module /initrd-2.6.29-tip.img
+                module /Q35_SINIT_17.BIN
+
+The kernel option for enabling Intel TXT support is found under the
+Security top-level menu and is called "Enable Intel(R) Trusted
+Execution Technology (TXT)".  It is marked as EXPERIMENTAL and
+depends on the generic x86 support (to allow maximum flexibility in
+kernel build options), since the tboot code will detect whether the
+platform actually supports Intel TXT and thus whether any of the
+kernel code is executed.
+
+The Q35_SINIT_17.BIN file is what Intel TXT refers to as an
+Authenticated Code Module.  It is specific to the chipset in the
+system and can also be found on the Trusted Boot site.  It is an
+(unencrypted) module signed by Intel that is used as part of the
+DRTM process to verify and configure the system.  It is signed
+because it operates at a higher privilege level in the system than
+any other macrocode and its correct operation is critical to the
+establishment of the DRTM.  The process for determining the correct
+SINIT ACM for a system is documented in the SINIT-guide.txt file
+that is on the tboot SourceForge site under the SINIT ACM downloads.
@@ -12,6 +12,7 @@
 000/040	ALL	screen_info	Text mode or frame buffer information
 				(struct screen_info)
 040/014	ALL	apm_bios_info	APM BIOS information (struct apm_bios_info)
+058/008	ALL	tboot_addr      Physical address of tboot shared page
 060/010	ALL	ist_info	Intel SpeedStep (IST) BIOS support information
 				(struct ist_info)
 080/010	ALL	hd0_info	hd0 disk parameter, OBSOLETE!!
@@ -85,7 +85,8 @@
 struct boot_params {
 	struct screen_info screen_info;			/* 0x000 */
 	struct apm_bios_info apm_bios_info;		/* 0x040 */
-	__u8  _pad2[12];				/* 0x054 */
+	__u8  _pad2[4];					/* 0x054 */
+	__u64  tboot_addr;				/* 0x058 */
 	struct ist_info ist_info;			/* 0x060 */
 	__u8  _pad3[16];				/* 0x070 */
 	__u8  hd0_info[16];	/* obsolete! */		/* 0x080 */
@@ -132,6 +132,9 @@
 #ifdef CONFIG_X86_32
 	FIX_WP_TEST,
 #endif
+#ifdef CONFIG_INTEL_TXT
+	FIX_TBOOT_BASE,
+#endif
 	__end_of_fixed_addresses
 };
  
+/*
+ * tboot.h: shared data structure with tboot and kernel and functions
+ *          used by kernel for runtime support of Intel(R) Trusted
+ *          Execution Technology
+ *
+ * Copyright (c) 2006-2009, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef _ASM_TBOOT_H
+#define _ASM_TBOOT_H
+
+#include <acpi/acpi.h>
+
+/* these must have the values from 0-5 in this order */
+enum {
+	TB_SHUTDOWN_REBOOT = 0,
+	TB_SHUTDOWN_S5,
+	TB_SHUTDOWN_S4,
+	TB_SHUTDOWN_S3,
+	TB_SHUTDOWN_HALT,
+	TB_SHUTDOWN_WFS
+};
+
+#ifdef CONFIG_INTEL_TXT
+
+/* used to communicate between tboot and the launched kernel */
+
+#define TB_KEY_SIZE             64   /* 512 bits */
+
+#define MAX_TB_MAC_REGIONS      32
+
+struct tboot_mac_region {
+	u64  start;         /* must be 64 byte -aligned */
+	u32  size;          /* must be 64 byte -granular */
+} __packed;
+
+/* GAS - Generic Address Structure (ACPI 2.0+) */
+struct tboot_acpi_generic_address {
+	u8  space_id;
+	u8  bit_width;
+	u8  bit_offset;
+	u8  access_width;
+	u64 address;
+} __packed;
+
+/*
+ * combines Sx info from FADT and FACS tables per ACPI 2.0+ spec
+ * (http://www.acpi.info/)
+ */
+struct tboot_acpi_sleep_info {
+	struct tboot_acpi_generic_address pm1a_cnt_blk;
+	struct tboot_acpi_generic_address pm1b_cnt_blk;
+	struct tboot_acpi_generic_address pm1a_evt_blk;
+	struct tboot_acpi_generic_address pm1b_evt_blk;
+	u16 pm1a_cnt_val;
+	u16 pm1b_cnt_val;
+	u64 wakeup_vector;
+	u32 vector_width;
+	u64 kernel_s3_resume_vector;
+} __packed;
+
+/*
+ * shared memory page used for communication between tboot and kernel
+ */
+struct tboot {
+	/*
+	 * version 3+ fields:
+	 */
+
+	/* TBOOT_UUID */
+	u8 uuid[16];
+
+	/* version number: 5 is current */
+	u32 version;
+
+	/* physical addr of tb_log_t log */
+	u32 log_addr;
+
+	/*
+	 * physical addr of entry point for tboot shutdown and
+	 * type of shutdown (TB_SHUTDOWN_*) being requested
+	 */
+	u32 shutdown_entry;
+	u32 shutdown_type;
+
+	/* kernel-specified ACPI info for Sx shutdown */
+	struct tboot_acpi_sleep_info acpi_sinfo;
+
+	/* tboot location in memory (physical) */
+	u32 tboot_base;
+	u32 tboot_size;
+
+	/* memory regions (phys addrs) for tboot to MAC on S3 */
+	u8 num_mac_regions;
+	struct tboot_mac_region mac_regions[MAX_TB_MAC_REGIONS];
+
+
+	/*
+	 * version 4+ fields:
+	 */
+
+	/* symmetric key for use by kernel; will be encrypted on S3 */
+	u8 s3_key[TB_KEY_SIZE];
+
+
+	/*
+	 * version 5+ fields:
+	 */
+
+	/* used to 4byte-align num_in_wfs */
+	u8 reserved_align[3];
+
+	/* number of processors in wait-for-SIPI */
+	u32 num_in_wfs;
+} __packed;
+
+/*
+ * UUID for tboot data struct to facilitate matching
+ * defined as {663C8DFF-E8B3-4b82-AABF-19EA4D057A08} by tboot, which is
+ * represented as {} in the char array used here
+ */
+#define TBOOT_UUID	{0xff, 0x8d, 0x3c, 0x66, 0xb3, 0xe8, 0x82, 0x4b, 0xbf,\
+			 0xaa, 0x19, 0xea, 0x4d, 0x5, 0x7a, 0x8}
+
+extern struct tboot *tboot;
+
+static inline int tboot_enabled(void)
+{
+	return tboot != NULL;
+}
+
+extern void tboot_probe(void);
+extern void tboot_create_trampoline(void);
+extern void tboot_shutdown(u32 shutdown_type);
+extern void tboot_sleep(u8 sleep_state, u32 pm1a_control, u32 pm1b_control);
+extern int tboot_wait_for_aps(int num_aps);
+extern struct acpi_table_header *tboot_get_dmar_table(
+				      struct acpi_table_header *dmar_tbl);
+extern int tboot_force_iommu(void);
+
+#else     /* CONFIG_INTEL_TXT */
+
+static inline int tboot_enabled(void)
+{
+	return 0;
+}
+
+static inline void tboot_probe(void)
+{
+}
+
+static inline void tboot_create_trampoline(void)
+{
+}
+
+static inline void tboot_shutdown(u32 shutdown_type)
+{
+}
+
+static inline void tboot_sleep(u8 sleep_state, u32 pm1a_control,
+			       u32 pm1b_control)
+{
+}
+
+static inline int tboot_wait_for_aps(int num_aps)
+{
+	return 0;
+}
+
+static inline struct acpi_table_header *tboot_get_dmar_table(
+					struct acpi_table_header *dmar_tbl)
+{
+	return dmar_tbl;
+}
+
+static inline int tboot_force_iommu(void)
+{
+	return 0;
+}
+
+#endif /* !CONFIG_INTEL_TXT */
+
+#endif /* _ASM_TBOOT_H */
@@ -52,6 +52,7 @@
 obj-$(CONFIG_X86_32)		+= tls.o
 obj-$(CONFIG_IA32_EMULATION)	+= tls.o
 obj-y				+= step.o
+obj-$(CONFIG_INTEL_TXT)		+= tboot.o
 obj-$(CONFIG_STACKTRACE)	+= stacktrace.o
 obj-y				+= cpu/
 obj-y				+= acpi/
@@ -145,6 +145,8 @@
 struct boot_params boot_params;
 #endif
  
+#include <asm/tboot.h>
+
 /*
  * Machine setup..
  */
@@ -963,6 +965,8 @@
 	paging_init();
 	paravirt_pagetable_setup_done(swapper_pg_dir);
 	paravirt_post_allocator_init();
+
+	tboot_probe();
  
 #ifdef CONFIG_X86_64
 	map_vsyscall();
+/*
+ * tboot.c: main implementation of helper functions used by kernel for
+ *          runtime support of Intel(R) Trusted Execution Technology
+ *
+ * Copyright (c) 2006-2009, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/dma_remapping.h>
+#include <linux/init_task.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/dmar.h>
+#include <linux/pfn.h>
+#include <linux/mm.h>
+
+#include <asm/trampoline.h>
+#include <asm/processor.h>
+#include <asm/bootparam.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/setup.h>
+#include <asm/tboot.h>
+#include <asm/e820.h>
+#include <asm/io.h>
+
+#include "acpi/realmode/wakeup.h"
+
+/* Global pointer to shared data; NULL means no measured launch. */
+struct tboot *tboot __read_mostly;
+
+/* timeout for APs (in secs) to enter wait-for-SIPI state during shutdown */
+#define AP_WAIT_TIMEOUT		1
+
+#undef pr_fmt
+#define pr_fmt(fmt)	"tboot: " fmt
+
+static u8 tboot_uuid[16] __initdata = TBOOT_UUID;
+
+void __init tboot_probe(void)
+{
+	/* Look for valid page-aligned address for shared page. */
+	if (!boot_params.tboot_addr)
+		return;
+	/*
+	 * also verify that it is mapped as we expect it before calling
+	 * set_fixmap(), to reduce chance of garbage value causing crash
+	 */
+	if (!e820_any_mapped(boot_params.tboot_addr,
+			     boot_params.tboot_addr, E820_RESERVED)) {
+		pr_warning("non-0 tboot_addr but it is not of type E820_RESERVED\n");
+		return;
+	}
+
+	/* only a natively booted kernel should be using TXT */
+	if (paravirt_enabled()) {
+		pr_warning("non-0 tboot_addr but pv_ops is enabled\n");
+		return;
+	}
+
+	/* Map and check for tboot UUID. */
+	set_fixmap(FIX_TBOOT_BASE, boot_params.tboot_addr);
+	tboot = (struct tboot *)fix_to_virt(FIX_TBOOT_BASE);
+	if (memcmp(&tboot_uuid, &tboot->uuid, sizeof(tboot->uuid))) {
+		pr_warning("tboot at 0x%llx is invalid\n",
+			   boot_params.tboot_addr);
+		tboot = NULL;
+		return;
+	}
+	if (tboot->version < 5) {
+		pr_warning("tboot version is invalid: %u\n", tboot->version);
+		tboot = NULL;
+		return;
+	}
+
+	pr_info("found shared page at phys addr 0x%llx:\n",
+		boot_params.tboot_addr);
+	pr_debug("version: %d\n", tboot->version);
+	pr_debug("log_addr: 0x%08x\n", tboot->log_addr);
+	pr_debug("shutdown_entry: 0x%x\n", tboot->shutdown_entry);
+	pr_debug("tboot_base: 0x%08x\n", tboot->tboot_base);
+	pr_debug("tboot_size: 0x%x\n", tboot->tboot_size);
+}
+
+static pgd_t *tboot_pg_dir;
+static struct mm_struct tboot_mm = {
+	.mm_rb          = RB_ROOT,
+	.pgd            = swapper_pg_dir,
+	.mm_users       = ATOMIC_INIT(2),
+	.mm_count       = ATOMIC_INIT(1),
+	.mmap_sem       = __RWSEM_INITIALIZER(init_mm.mmap_sem),
+	.page_table_lock =  __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
+	.mmlist         = LIST_HEAD_INIT(init_mm.mmlist),
+	.cpu_vm_mask    = CPU_MASK_ALL,
+};
+
+static inline void switch_to_tboot_pt(void)
+{
+	write_cr3(virt_to_phys(tboot_pg_dir));
+}
+
+static int map_tboot_page(unsigned long vaddr, unsigned long pfn,
+			  pgprot_t prot)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	pgd = pgd_offset(&tboot_mm, vaddr);
+	pud = pud_alloc(&tboot_mm, pgd, vaddr);
+	if (!pud)
+		return -1;
+	pmd = pmd_alloc(&tboot_mm, pud, vaddr);
+	if (!pmd)
+		return -1;
+	pte = pte_alloc_map(&tboot_mm, pmd, vaddr);
+	if (!pte)
+		return -1;
+	set_pte_at(&tboot_mm, vaddr, pte, pfn_pte(pfn, prot));
+	pte_unmap(pte);
+	return 0;
+}
+
+static int map_tboot_pages(unsigned long vaddr, unsigned long start_pfn,
+			   unsigned long nr)
+{
+	/* Reuse the original kernel mapping */
+	tboot_pg_dir = pgd_alloc(&tboot_mm);
+	if (!tboot_pg_dir)
+		return -1;
+
+	for (; nr > 0; nr--, vaddr += PAGE_SIZE, start_pfn++) {
+		if (map_tboot_page(vaddr, start_pfn, PAGE_KERNEL_EXEC))
+			return -1;
+	}
+
+	return 0;
+}
+
+void tboot_create_trampoline(void)
+{
+	u32 map_base, map_size;
+
+	if (!tboot_enabled())
+		return;
+
+	/* Create identity map for tboot shutdown code. */
+	map_base = PFN_DOWN(tboot->tboot_base);
+	map_size = PFN_UP(tboot->tboot_size);
+	if (map_tboot_pages(map_base << PAGE_SHIFT, map_base, map_size))
+		panic("tboot: Error mapping tboot pages (mfns) @ 0x%x, 0x%x\n", map_base, map_size);
+}
+
+static void set_mac_regions(void)
+{
+	tboot->num_mac_regions = 3;
+	/* S3 resume code */
+	tboot->mac_regions[0].start = PFN_PHYS(PFN_DOWN(acpi_wakeup_address));
+	tboot->mac_regions[0].size = PFN_UP(WAKEUP_SIZE) << PAGE_SHIFT;
+	/* AP trampoline code */
+	tboot->mac_regions[1].start =
+			PFN_PHYS(PFN_DOWN(virt_to_phys(trampoline_base)));
+	tboot->mac_regions[1].size = PFN_UP(TRAMPOLINE_SIZE) << PAGE_SHIFT;
+	/* kernel code + data + bss */
+	tboot->mac_regions[2].start = PFN_PHYS(PFN_DOWN(virt_to_phys(&_text)));
+	tboot->mac_regions[2].size = PFN_PHYS(PFN_UP(virt_to_phys(&_end))) -
+				     PFN_PHYS(PFN_DOWN(virt_to_phys(&_text)));
+}
+
+void tboot_shutdown(u32 shutdown_type)
+{
+	void (*shutdown)(void);
+
+	if (!tboot_enabled())
+		return;
+
+	/*
+	 * if we're being called before the 1:1 mapping is set up then just
+	 * return and let the normal shutdown happen; this should only be
+	 * due to very early panic()
+	 */
+	if (!tboot_pg_dir)
+		return;
+
+	/* if this is S3 then set regions to MAC */
+	if (shutdown_type == TB_SHUTDOWN_S3)
+		set_mac_regions();
+
+	tboot->shutdown_type = shutdown_type;
+
+	switch_to_tboot_pt();
+
+	shutdown = (void(*)(void))(unsigned long)tboot->shutdown_entry;
+	shutdown();
+
+	/* should not reach here */
+	while (1)
+		halt();
+}
+
+static void tboot_copy_fadt(const struct acpi_table_fadt *fadt)
+{
+#define TB_COPY_GAS(tbg, g)			\
+	tbg.space_id     = g.space_id;		\
+	tbg.bit_width    = g.bit_width;		\
+	tbg.bit_offset   = g.bit_offset;	\
+	tbg.access_width = g.access_width;	\
+	tbg.address      = g.address;
+
+	TB_COPY_GAS(tboot->acpi_sinfo.pm1a_cnt_blk, fadt->xpm1a_control_block);
+	TB_COPY_GAS(tboot->acpi_sinfo.pm1b_cnt_blk, fadt->xpm1b_control_block);
+	TB_COPY_GAS(tboot->acpi_sinfo.pm1a_evt_blk, fadt->xpm1a_event_block);
+	TB_COPY_GAS(tboot->acpi_sinfo.pm1b_evt_blk, fadt->xpm1b_event_block);
+
+	/*
+	 * We need phys addr of waking vector, but can't use virt_to_phys() on
+	 * &acpi_gbl_FACS because it is ioremap'ed, so calc from FACS phys
+	 * addr.
+	 */
+	tboot->acpi_sinfo.wakeup_vector = fadt->facs +
+		offsetof(struct acpi_table_facs, firmware_waking_vector);
+}
+
+void tboot_sleep(u8 sleep_state, u32 pm1a_control, u32 pm1b_control)
+{
+	static u32 acpi_shutdown_map[ACPI_S_STATE_COUNT] = {
+		/* S0,1,2: */ -1, -1, -1,
+		/* S3: */ TB_SHUTDOWN_S3,
+		/* S4: */ TB_SHUTDOWN_S4,
+		/* S5: */ TB_SHUTDOWN_S5 };
+
+	if (!tboot_enabled())
+		return;
+
+	tboot_copy_fadt(&acpi_gbl_FADT);
+	tboot->acpi_sinfo.pm1a_cnt_val = pm1a_control;
+	tboot->acpi_sinfo.pm1b_cnt_val = pm1b_control;
+	/* we always use the 32b wakeup vector */
+	tboot->acpi_sinfo.vector_width = 32;
+	tboot->acpi_sinfo.kernel_s3_resume_vector = acpi_wakeup_address;
+
+	if (sleep_state >= ACPI_S_STATE_COUNT ||
+	    acpi_shutdown_map[sleep_state] == -1) {
+		pr_warning("unsupported sleep state 0x%x\n", sleep_state);
+		return;
+	}
+
+	tboot_shutdown(acpi_shutdown_map[sleep_state]);
+}
+
+int tboot_wait_for_aps(int num_aps)
+{
+	unsigned long timeout;
+
+	if (!tboot_enabled())
+		return 0;
+
+	timeout = jiffies + AP_WAIT_TIMEOUT*HZ;
+	while (atomic_read((atomic_t *)&tboot->num_in_wfs) != num_aps &&
+	       time_before(jiffies, timeout))
+		cpu_relax();
+
+	return time_before(jiffies, timeout) ? 0 : 1;
+}
+
+/*
+ * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE)
+ */
+
+#define TXT_PUB_CONFIG_REGS_BASE       0xfed30000
+#define TXT_PRIV_CONFIG_REGS_BASE      0xfed20000
+
+/* # pages for each config regs space - used by fixmap */
+#define NR_TXT_CONFIG_PAGES     ((TXT_PUB_CONFIG_REGS_BASE -                \
+				  TXT_PRIV_CONFIG_REGS_BASE) >> PAGE_SHIFT)
+
+/* offsets from pub/priv config space */
+#define TXTCR_HEAP_BASE             0x0300
+#define TXTCR_HEAP_SIZE             0x0308
+
+#define SHA1_SIZE      20
+
+struct sha1_hash {
+	u8 hash[SHA1_SIZE];
+};
+
+struct sinit_mle_data {
+	u32               version;             /* currently 6 */
+	struct sha1_hash  bios_acm_id;
+	u32               edx_senter_flags;
+	u64               mseg_valid;
+	struct sha1_hash  sinit_hash;
+	struct sha1_hash  mle_hash;
+	struct sha1_hash  stm_hash;
+	struct sha1_hash  lcp_policy_hash;
+	u32               lcp_policy_control;
+	u32               rlp_wakeup_addr;
+	u32               reserved;
+	u32               num_mdrs;
+	u32               mdrs_off;
+	u32               num_vtd_dmars;
+	u32               vtd_dmars_off;
+} __packed;
+
+struct acpi_table_header *tboot_get_dmar_table(struct acpi_table_header *dmar_tbl)
+{
+	void *heap_base, *heap_ptr, *config;
+
+	if (!tboot_enabled())
+		return dmar_tbl;
+
+	/*
+	 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
+	 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
+	 */
+
+	/* map config space in order to get heap addr */
+	config = ioremap(TXT_PUB_CONFIG_REGS_BASE, NR_TXT_CONFIG_PAGES *
+			 PAGE_SIZE);
+	if (!config)
+		return NULL;
+
+	/* now map TXT heap */
+	heap_base = ioremap(*(u64 *)(config + TXTCR_HEAP_BASE),
+			    *(u64 *)(config + TXTCR_HEAP_SIZE));
+	iounmap(config);
+	if (!heap_base)
+		return NULL;
+
+	/* walk heap to SinitMleData */
+	/* skip BiosData */
+	heap_ptr = heap_base + *(u64 *)heap_base;
+	/* skip OsMleData */
+	heap_ptr += *(u64 *)heap_ptr;
+	/* skip OsSinitData */
+	heap_ptr += *(u64 *)heap_ptr;
+	/* now points to SinitMleDataSize; set to SinitMleData */
+	heap_ptr += sizeof(u64);
+	/* get addr of DMAR table */
+	dmar_tbl = (struct acpi_table_header *)(heap_ptr +
+		   ((struct sinit_mle_data *)heap_ptr)->vtd_dmars_off -
+		   sizeof(u64));
+
+	/* don't unmap heap because dmar.c needs access to this */
+
+	return dmar_tbl;
+}
+
+int tboot_force_iommu(void)
+{
+	if (!tboot_enabled())
+		return 0;
+
+	if (no_iommu || swiotlb || dmar_disabled)
+		pr_warning("Forcing Intel-IOMMU to enabled\n");
+
+	dmar_disabled = 0;
+#ifdef CONFIG_SWIOTLB
+	swiotlb = 0;
+#endif
+	no_iommu = 0;
+
+	return 1;
+}
@@ -113,6 +113,36 @@
  
 	  If you are unsure how to answer this question, answer N.
  
+config INTEL_TXT
+	bool "Enable Intel(R) Trusted Execution Technology (Intel(R) TXT)"
+	depends on EXPERIMENTAL && X86 && DMAR && ACPI
+	help
+	  This option enables support for booting the kernel with the
+	  Trusted Boot (tboot) module. This will utilize
+	  Intel(R) Trusted Execution Technology to perform a measured launch
+	  of the kernel. If the system does not support Intel(R) TXT, this
+	  will have no effect.
+
+	  Intel TXT will provide higher assurance of sysem configuration and
+	  initial state as well as data reset protection.  This is used to
+	  create a robust initial kernel measurement and verification, which
+	  helps to ensure that kernel security mechanisms are functioning
+	  correctly. This level of protection requires a root of trust outside
+	  of the kernel itself.
+
+	  Intel TXT also helps solve real end user concerns about having
+	  confidence that their hardware is running the VMM or kernel that
+	  it was conigured with, especially since they may be responsible for
+	  providing such assurances to VMs and services running on it.
+
+	  See <http://www.intel.com/technology/security/> for more information
+	  about Intel(R) TXT.
+	  See <http://tboot.sourceforge.net> for more information about tboot.
+	  See Documentation/intel_txt.txt for a description of how to enable
+	  Intel TXT support in a kernel boot.
+
+	  If you are unsure as to whether this is required, answer N.
+
 source security/selinux/Kconfig
 source security/smack/Kconfig
 source security/tomoyo/Kconfig
	1	+Intel(R) TXT Overview:
	2	+=====================
	3	+
	4	+Intel's technology for safer computing, Intel(R) Trusted Execution
	5	+Technology (Intel(R) TXT), defines platform-level enhancements that
	6	+provide the building blocks for creating trusted platforms.
	7	+
	8	+Intel TXT was formerly known by the code name LaGrande Technology (LT).
	9	+
	10	+Intel TXT in Brief:
	11	+o Provides dynamic root of trust for measurement (DRTM)
	12	+o Data protection in case of improper shutdown
	13	+o Measurement and verification of launched environment
	14	+
	15	+Intel TXT is part of the vPro(TM) brand and is also available some
	16	+non-vPro systems. It is currently available on desktop systems
	17	+based on the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell
	18	+Optiplex 755, HP dc7800, etc.) and mobile systems based on the GM45,
	19	+PM45, and GS45 Express chipsets.
	20	+
	21	+For more information, see http://www.intel.com/technology/security/.
	22	+This site also has a link to the Intel TXT MLE Developers Manual,
	23	+which has been updated for the new released platforms.
	24	+
	25	+Intel TXT has been presented at various events over the past few
	26	+years, some of which are:
	27	+ LinuxTAG 2008:
	28	+ http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag/
	29	+ details.html?talkid=110
	30	+ TRUST2008:
	31	+ http://www.trust2008.eu/downloads/Keynote-Speakers/
	32	+ 3_David-Grawrock_The-Front-Door-of-Trusted-Computing.pdf
	33	+ IDF 2008, Shanghai:
	34	+ http://inteldeveloperforum.com.edgesuite.net/shanghai_2008/
	35	+ aep/PROS003/index.html
	36	+ IDFs 2006, 2007 (I'm not sure if/where they are online)
	37	+
	38	+Trusted Boot Project Overview:
	39	+=============================
	40	+
	41	+Trusted Boot (tboot) is an open source, pre- kernel/VMM module that
	42	+uses Intel TXT to perform a measured and verified launch of an OS
	43	+kernel/VMM.
	44	+
	45	+It is hosted on SourceForge at http://sourceforge.net/projects/tboot.
	46	+The mercurial source repo is available at http://www.bughost.org/
	47	+repos.hg/tboot.hg.
	48	+
	49	+Tboot currently supports launching Xen (open source VMM/hypervisor
	50	+w/ TXT support since v3.2), and now Linux kernels.
	51	+
	52	+
	53	+Value Proposition for Linux or "Why should you care?"
	54	+=====================================================
	55	+
	56	+While there are many products and technologies that attempt to
	57	+measure or protect the integrity of a running kernel, they all
	58	+assume the kernel is "good" to begin with. The Integrity
	59	+Measurement Architecture (IMA) and Linux Integrity Module interface
	60	+are examples of such solutions.
	61	+
	62	+To get trust in the initial kernel without using Intel TXT, a
	63	+static root of trust must be used. This bases trust in BIOS
	64	+starting at system reset and requires measurement of all code
	65	+executed between system reset through the completion of the kernel
	66	+boot as well as data objects used by that code. In the case of a
	67	+Linux kernel, this means all of BIOS, any option ROMs, the
	68	+bootloader and the boot config. In practice, this is a lot of
	69	+code/data, much of which is subject to change from boot to boot
	70	+(e.g. changing NICs may change option ROMs). Without reference
	71	+hashes, these measurement changes are difficult to assess or
	72	+confirm as benign. This process also does not provide DMA
	73	+protection, memory configuration/alias checks and locks, crash
	74	+protection, or policy support.
	75	+
	76	+By using the hardware-based root of trust that Intel TXT provides,
	77	+many of these issues can be mitigated. Specifically: many
	78	+pre-launch components can be removed from the trust chain, DMA
	79	+protection is provided to all launched components, a large number
	80	+of platform configuration checks are performed and values locked,
	81	+protection is provided for any data in the event of an improper
	82	+shutdown, and there is support for policy-based execution/verification.
	83	+This provides a more stable measurement and a higher assurance of
	84	+system configuration and initial state than would be otherwise
	85	+possible. Since the tboot project is open source, source code for
	86	+almost all parts of the trust chain is available (excepting SMM and
	87	+Intel-provided firmware).
	88	+
	89	+How Does it Work?
	90	+=================
	91	+
	92	+o Tboot is an executable that is launched by the bootloader as
	93	+ the "kernel" (the binary the bootloader executes).
	94	+o It performs all of the work necessary to determine if the
	95	+ platform supports Intel TXT and, if so, executes the GETSEC[SENTER]
	96	+ processor instruction that initiates the dynamic root of trust.
	97	+ - If tboot determines that the system does not support Intel TXT
	98	+ or is not configured correctly (e.g. the SINIT AC Module was
	99	+ incorrect), it will directly launch the kernel with no changes
	100	+ to any state.
	101	+ - Tboot will output various information about its progress to the
	102	+ terminal, serial port, and/or an in-memory log; the output
	103	+ locations can be configured with a command line switch.
	104	+o The GETSEC[SENTER] instruction will return control to tboot and
	105	+ tboot then verifies certain aspects of the environment (e.g. TPM NV
	106	+ lock, e820 table does not have invalid entries, etc.).
	107	+o It will wake the APs from the special sleep state the GETSEC[SENTER]
	108	+ instruction had put them in and place them into a wait-for-SIPI
	109	+ state.
	110	+ - Because the processors will not respond to an INIT or SIPI when
	111	+ in the TXT environment, it is necessary to create a small VT-x
	112	+ guest for the APs. When they run in this guest, they will
	113	+ simply wait for the INIT-SIPI-SIPI sequence, which will cause
	114	+ VMEXITs, and then disable VT and jump to the SIPI vector. This
	115	+ approach seemed like a better choice than having to insert
	116	+ special code into the kernel's MP wakeup sequence.
	117	+o Tboot then applies an (optional) user-defined launch policy to
	118	+ verify the kernel and initrd.
	119	+ - This policy is rooted in TPM NV and is described in the tboot
	120	+ project. The tboot project also contains code for tools to
	121	+ create and provision the policy.
	122	+ - Policies are completely under user control and if not present
	123	+ then any kernel will be launched.
	124	+ - Policy action is flexible and can include halting on failures
	125	+ or simply logging them and continuing.
	126	+o Tboot adjusts the e820 table provided by the bootloader to reserve
	127	+ its own location in memory as well as to reserve certain other
	128	+ TXT-related regions.
	129	+o As part of it's launch, tboot DMA protects all of RAM (using the
	130	+ VT-d PMRs). Thus, the kernel must be booted with 'intel_iommu=on'
	131	+ in order to remove this blanket protection and use VT-d's
	132	+ page-level protection.
	133	+o Tboot will populate a shared page with some data about itself and
	134	+ pass this to the Linux kernel as it transfers control.
	135	+ - The location of the shared page is passed via the boot_params
	136	+ struct as a physical address.
	137	+o The kernel will look for the tboot shared page address and, if it
	138	+ exists, map it.
	139	+o As one of the checks/protections provided by TXT, it makes a copy
	140	+ of the VT-d DMARs in a DMA-protected region of memory and verifies
	141	+ them for correctness. The VT-d code will detect if the kernel was
	142	+ launched with tboot and use this copy instead of the one in the
	143	+ ACPI table.
	144	+o At this point, tboot and TXT are out of the picture until a
	145	+ shutdown (S<n>)
	146	+o In order to put a system into any of the sleep states after a TXT
	147	+ launch, TXT must first be exited. This is to prevent attacks that
	148	+ attempt to crash the system to gain control on reboot and steal
	149	+ data left in memory.
	150	+ - The kernel will perform all of its sleep preparation and
	151	+ populate the shared page with the ACPI data needed to put the
	152	+ platform in the desired sleep state.
	153	+ - Then the kernel jumps into tboot via the vector specified in the
	154	+ shared page.
	155	+ - Tboot will clean up the environment and disable TXT, then use the
	156	+ kernel-provided ACPI information to actually place the platform
	157	+ into the desired sleep state.
	158	+ - In the case of S3, tboot will also register itself as the resume
	159	+ vector. This is necessary because it must re-establish the
	160	+ measured environment upon resume. Once the TXT environment
	161	+ has been restored, it will restore the TPM PCRs and then
	162	+ transfer control back to the kernel's S3 resume vector.
	163	+ In order to preserve system integrity across S3, the kernel
	164	+ provides tboot with a set of memory ranges (kernel
	165	+ code/data/bss, S3 resume code, and AP trampoline) that tboot
	166	+ will calculate a MAC (message authentication code) over and then
	167	+ seal with the TPM. On resume and once the measured environment
	168	+ has been re-established, tboot will re-calculate the MAC and
	169	+ verify it against the sealed value. Tboot's policy determines
	170	+ what happens if the verification fails.
	171	+
	172	+That's pretty much it for TXT support.
	173	+
	174	+
	175	+Configuring the System:
	176	+======================
	177	+
	178	+This code works with 32bit, 32bit PAE, and 64bit (x86_64) kernels.
	179	+
	180	+In BIOS, the user must enable: TPM, TXT, VT-x, VT-d. Not all BIOSes
	181	+allow these to be individually enabled/disabled and the screens in
	182	+which to find them are BIOS-specific.
	183	+
	184	+grub.conf needs to be modified as follows:
	185	+ title Linux 2.6.29-tip w/ tboot
	186	+ root (hd0,0)
	187	+ kernel /tboot.gz logging=serial,vga,memory
	188	+ module /vmlinuz-2.6.29-tip intel_iommu=on ro
	189	+ root=LABEL=/ rhgb console=ttyS0,115200 3
	190	+ module /initrd-2.6.29-tip.img
	191	+ module /Q35_SINIT_17.BIN
	192	+
	193	+The kernel option for enabling Intel TXT support is found under the
	194	+Security top-level menu and is called "Enable Intel(R) Trusted
	195	+Execution Technology (TXT)". It is marked as EXPERIMENTAL and
	196	+depends on the generic x86 support (to allow maximum flexibility in
	197	+kernel build options), since the tboot code will detect whether the
	198	+platform actually supports Intel TXT and thus whether any of the
	199	+kernel code is executed.
	200	+
	201	+The Q35_SINIT_17.BIN file is what Intel TXT refers to as an
	202	+Authenticated Code Module. It is specific to the chipset in the
	203	+system and can also be found on the Trusted Boot site. It is an
	204	+(unencrypted) module signed by Intel that is used as part of the
	205	+DRTM process to verify and configure the system. It is signed
	206	+because it operates at a higher privilege level in the system than
	207	+any other macrocode and its correct operation is critical to the
	208	+establishment of the DRTM. The process for determining the correct
	209	+SINIT ACM for a system is documented in the SINIT-guide.txt file
	210	+that is on the tboot SourceForge site under the SINIT ACM downloads.
...	...	@@ -12,6 +12,7 @@
12	12	000/040 ALL screen_info Text mode or frame buffer information
13	13	(struct screen_info)
14	14	040/014 ALL apm_bios_info APM BIOS information (struct apm_bios_info)
	15	+058/008 ALL tboot_addr Physical address of tboot shared page
15	16	060/010 ALL ist_info Intel SpeedStep (IST) BIOS support information
16	17	(struct ist_info)
17	18	080/010 ALL hd0_info hd0 disk parameter, OBSOLETE!!
...	...	@@ -85,7 +85,8 @@
85	85	struct boot_params {
86	86	struct screen_info screen_info; /* 0x000 */
87	87	struct apm_bios_info apm_bios_info; /* 0x040 */
88		- __u8 _pad2[12]; /* 0x054 */
	88	+ __u8 _pad2[4]; /* 0x054 */
	89	+ __u64 tboot_addr; /* 0x058 */
89	90	struct ist_info ist_info; /* 0x060 */
90	91	__u8 _pad3[16]; /* 0x070 */
91	92	__u8 hd0_info[16]; /* obsolete! / / 0x080 */
...	...	@@ -132,6 +132,9 @@
132	132	#ifdef CONFIG_X86_32
133	133	FIX_WP_TEST,
134	134	#endif
	135	+#ifdef CONFIG_INTEL_TXT
	136	+ FIX_TBOOT_BASE,
	137	+#endif
135	138	__end_of_fixed_addresses
136	139	};
137	140
	1	+/*
	2	+ * tboot.h: shared data structure with tboot and kernel and functions
	3	+ * used by kernel for runtime support of Intel(R) Trusted
	4	+ * Execution Technology
	5	+ *
	6	+ * Copyright (c) 2006-2009, Intel Corporation
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or modify it
	9	+ * under the terms and conditions of the GNU General Public License,
	10	+ * version 2, as published by the Free Software Foundation.
	11	+ *
	12	+ * This program is distributed in the hope it will be useful, but WITHOUT
	13	+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	+ * more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License along with
	18	+ * this program; if not, write to the Free Software Foundation, Inc.,
	19	+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	20	+ *
	21	+ */
	22	+
	23	+#ifndef _ASM_TBOOT_H
	24	+#define _ASM_TBOOT_H
	25	+
	26	+#include <acpi/acpi.h>
	27	+
	28	+/* these must have the values from 0-5 in this order */
	29	+enum {
	30	+ TB_SHUTDOWN_REBOOT = 0,
	31	+ TB_SHUTDOWN_S5,
	32	+ TB_SHUTDOWN_S4,
	33	+ TB_SHUTDOWN_S3,
	34	+ TB_SHUTDOWN_HALT,
	35	+ TB_SHUTDOWN_WFS
	36	+};
	37	+
	38	+#ifdef CONFIG_INTEL_TXT
	39	+
	40	+/* used to communicate between tboot and the launched kernel */
	41	+
	42	+#define TB_KEY_SIZE 64 /* 512 bits */
	43	+
	44	+#define MAX_TB_MAC_REGIONS 32
	45	+
	46	+struct tboot_mac_region {
	47	+ u64 start; /* must be 64 byte -aligned */
	48	+ u32 size; /* must be 64 byte -granular */
	49	+} __packed;
	50	+
	51	+/* GAS - Generic Address Structure (ACPI 2.0+) */
	52	+struct tboot_acpi_generic_address {
	53	+ u8 space_id;
	54	+ u8 bit_width;
	55	+ u8 bit_offset;
	56	+ u8 access_width;
	57	+ u64 address;
	58	+} __packed;
	59	+
	60	+/*
	61	+ * combines Sx info from FADT and FACS tables per ACPI 2.0+ spec
	62	+ * (http://www.acpi.info/)
	63	+ */
	64	+struct tboot_acpi_sleep_info {
	65	+ struct tboot_acpi_generic_address pm1a_cnt_blk;
	66	+ struct tboot_acpi_generic_address pm1b_cnt_blk;
	67	+ struct tboot_acpi_generic_address pm1a_evt_blk;
	68	+ struct tboot_acpi_generic_address pm1b_evt_blk;
	69	+ u16 pm1a_cnt_val;
	70	+ u16 pm1b_cnt_val;
	71	+ u64 wakeup_vector;
	72	+ u32 vector_width;
	73	+ u64 kernel_s3_resume_vector;
	74	+} __packed;
	75	+
	76	+/*
	77	+ * shared memory page used for communication between tboot and kernel
	78	+ */
	79	+struct tboot {
	80	+ /*
	81	+ * version 3+ fields:
	82	+ */
	83	+
	84	+ /* TBOOT_UUID */
	85	+ u8 uuid[16];
	86	+
	87	+ /* version number: 5 is current */
	88	+ u32 version;
	89	+
	90	+ /* physical addr of tb_log_t log */
	91	+ u32 log_addr;
	92	+
	93	+ /*
	94	+ * physical addr of entry point for tboot shutdown and
	95	+ * type of shutdown (TB_SHUTDOWN_*) being requested
	96	+ */
	97	+ u32 shutdown_entry;
	98	+ u32 shutdown_type;
	99	+
	100	+ /* kernel-specified ACPI info for Sx shutdown */
	101	+ struct tboot_acpi_sleep_info acpi_sinfo;
	102	+
	103	+ /* tboot location in memory (physical) */
	104	+ u32 tboot_base;
	105	+ u32 tboot_size;
	106	+
	107	+ /* memory regions (phys addrs) for tboot to MAC on S3 */
	108	+ u8 num_mac_regions;
	109	+ struct tboot_mac_region mac_regions[MAX_TB_MAC_REGIONS];
	110	+
	111	+
	112	+ /*
	113	+ * version 4+ fields:
	114	+ */
	115	+
	116	+ /* symmetric key for use by kernel; will be encrypted on S3 */
	117	+ u8 s3_key[TB_KEY_SIZE];
	118	+
	119	+
	120	+ /*
	121	+ * version 5+ fields:
	122	+ */
	123	+
	124	+ /* used to 4byte-align num_in_wfs */
	125	+ u8 reserved_align[3];
	126	+
	127	+ /* number of processors in wait-for-SIPI */
	128	+ u32 num_in_wfs;
	129	+} __packed;
	130	+
	131	+/*
	132	+ * UUID for tboot data struct to facilitate matching
	133	+ * defined as {663C8DFF-E8B3-4b82-AABF-19EA4D057A08} by tboot, which is
	134	+ * represented as {} in the char array used here
	135	+ */
	136	+#define TBOOT_UUID {0xff, 0x8d, 0x3c, 0x66, 0xb3, 0xe8, 0x82, 0x4b, 0xbf,\
	137	+ 0xaa, 0x19, 0xea, 0x4d, 0x5, 0x7a, 0x8}
	138	+
	139	+extern struct tboot *tboot;
	140	+
	141	+static inline int tboot_enabled(void)
	142	+{
	143	+ return tboot != NULL;
	144	+}
	145	+
	146	+extern void tboot_probe(void);
	147	+extern void tboot_create_trampoline(void);
	148	+extern void tboot_shutdown(u32 shutdown_type);
	149	+extern void tboot_sleep(u8 sleep_state, u32 pm1a_control, u32 pm1b_control);
	150	+extern int tboot_wait_for_aps(int num_aps);
	151	+extern struct acpi_table_header *tboot_get_dmar_table(
	152	+ struct acpi_table_header *dmar_tbl);
	153	+extern int tboot_force_iommu(void);
	154	+
	155	+#else /* CONFIG_INTEL_TXT */
	156	+
	157	+static inline int tboot_enabled(void)
	158	+{
	159	+ return 0;
	160	+}
	161	+
	162	+static inline void tboot_probe(void)
	163	+{
	164	+}
	165	+
	166	+static inline void tboot_create_trampoline(void)
	167	+{
	168	+}
	169	+
	170	+static inline void tboot_shutdown(u32 shutdown_type)
	171	+{
	172	+}
	173	+
	174	+static inline void tboot_sleep(u8 sleep_state, u32 pm1a_control,
	175	+ u32 pm1b_control)
	176	+{
	177	+}
	178	+
	179	+static inline int tboot_wait_for_aps(int num_aps)
	180	+{
	181	+ return 0;
	182	+}
	183	+
	184	+static inline struct acpi_table_header *tboot_get_dmar_table(
	185	+ struct acpi_table_header *dmar_tbl)
	186	+{
	187	+ return dmar_tbl;
	188	+}
	189	+
	190	+static inline int tboot_force_iommu(void)
	191	+{
	192	+ return 0;
	193	+}
	194	+
	195	+#endif /* !CONFIG_INTEL_TXT */
	196	+
	197	+#endif /* _ASM_TBOOT_H */
...	...	@@ -52,6 +52,7 @@
52	52	obj-$(CONFIG_X86_32) += tls.o
53	53	obj-$(CONFIG_IA32_EMULATION) += tls.o
54	54	obj-y += step.o
	55	+obj-$(CONFIG_INTEL_TXT) += tboot.o
55	56	obj-$(CONFIG_STACKTRACE) += stacktrace.o
56	57	obj-y += cpu/
57	58	obj-y += acpi/
...	...	@@ -145,6 +145,8 @@
145	145	struct boot_params boot_params;
146	146	#endif
147	147
	148	+#include <asm/tboot.h>
	149	+
148	150	/*
149	151	* Machine setup..
150	152	*/
...	...	@@ -963,6 +965,8 @@
963	965	paging_init();
964	966	paravirt_pagetable_setup_done(swapper_pg_dir);
965	967	paravirt_post_allocator_init();
	968	+
	969	+ tboot_probe();
966	970
967	971	#ifdef CONFIG_X86_64
968	972	map_vsyscall();
	1	+/*
	2	+ * tboot.c: main implementation of helper functions used by kernel for
	3	+ * runtime support of Intel(R) Trusted Execution Technology
	4	+ *
	5	+ * Copyright (c) 2006-2009, Intel Corporation
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or modify it
	8	+ * under the terms and conditions of the GNU General Public License,
	9	+ * version 2, as published by the Free Software Foundation.
	10	+ *
	11	+ * This program is distributed in the hope it will be useful, but WITHOUT
	12	+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	+ * more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License along with
	17	+ * this program; if not, write to the Free Software Foundation, Inc.,
	18	+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	+ *
	20	+ */
	21	+
	22	+#include <linux/dma_remapping.h>
	23	+#include <linux/init_task.h>
	24	+#include <linux/spinlock.h>
	25	+#include <linux/sched.h>
	26	+#include <linux/init.h>
	27	+#include <linux/dmar.h>
	28	+#include <linux/pfn.h>
	29	+#include <linux/mm.h>
	30	+
	31	+#include <asm/trampoline.h>
	32	+#include <asm/processor.h>
	33	+#include <asm/bootparam.h>
	34	+#include <asm/pgtable.h>
	35	+#include <asm/pgalloc.h>
	36	+#include <asm/setup.h>
	37	+#include <asm/tboot.h>
	38	+#include <asm/e820.h>
	39	+#include <asm/io.h>
	40	+
	41	+#include "acpi/realmode/wakeup.h"
	42	+
	43	+/* Global pointer to shared data; NULL means no measured launch. */
	44	+struct tboot *tboot __read_mostly;
	45	+
	46	+/* timeout for APs (in secs) to enter wait-for-SIPI state during shutdown */
	47	+#define AP_WAIT_TIMEOUT 1
	48	+
	49	+#undef pr_fmt
	50	+#define pr_fmt(fmt) "tboot: " fmt
	51	+
	52	+static u8 tboot_uuid[16] __initdata = TBOOT_UUID;
	53	+
	54	+void __init tboot_probe(void)
	55	+{
	56	+ /* Look for valid page-aligned address for shared page. */
	57	+ if (!boot_params.tboot_addr)
	58	+ return;
	59	+ /*
	60	+ * also verify that it is mapped as we expect it before calling
	61	+ * set_fixmap(), to reduce chance of garbage value causing crash
	62	+ */
	63	+ if (!e820_any_mapped(boot_params.tboot_addr,
	64	+ boot_params.tboot_addr, E820_RESERVED)) {
	65	+ pr_warning("non-0 tboot_addr but it is not of type E820_RESERVED\n");
	66	+ return;
	67	+ }
	68	+
	69	+ /* only a natively booted kernel should be using TXT */
	70	+ if (paravirt_enabled()) {
	71	+ pr_warning("non-0 tboot_addr but pv_ops is enabled\n");
	72	+ return;
	73	+ }
	74	+
	75	+ /* Map and check for tboot UUID. */
	76	+ set_fixmap(FIX_TBOOT_BASE, boot_params.tboot_addr);
	77	+ tboot = (struct tboot *)fix_to_virt(FIX_TBOOT_BASE);
	78	+ if (memcmp(&tboot_uuid, &tboot->uuid, sizeof(tboot->uuid))) {
	79	+ pr_warning("tboot at 0x%llx is invalid\n",
	80	+ boot_params.tboot_addr);
	81	+ tboot = NULL;
	82	+ return;
	83	+ }
	84	+ if (tboot->version < 5) {
	85	+ pr_warning("tboot version is invalid: %u\n", tboot->version);
	86	+ tboot = NULL;
	87	+ return;
	88	+ }
	89	+
	90	+ pr_info("found shared page at phys addr 0x%llx:\n",
	91	+ boot_params.tboot_addr);
	92	+ pr_debug("version: %d\n", tboot->version);
	93	+ pr_debug("log_addr: 0x%08x\n", tboot->log_addr);
	94	+ pr_debug("shutdown_entry: 0x%x\n", tboot->shutdown_entry);
	95	+ pr_debug("tboot_base: 0x%08x\n", tboot->tboot_base);
	96	+ pr_debug("tboot_size: 0x%x\n", tboot->tboot_size);
	97	+}
	98	+
	99	+static pgd_t *tboot_pg_dir;
	100	+static struct mm_struct tboot_mm = {
	101	+ .mm_rb = RB_ROOT,
	102	+ .pgd = swapper_pg_dir,
	103	+ .mm_users = ATOMIC_INIT(2),
	104	+ .mm_count = ATOMIC_INIT(1),
	105	+ .mmap_sem = __RWSEM_INITIALIZER(init_mm.mmap_sem),
	106	+ .page_table_lock = __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
	107	+ .mmlist = LIST_HEAD_INIT(init_mm.mmlist),
	108	+ .cpu_vm_mask = CPU_MASK_ALL,
	109	+};
	110	+
	111	+static inline void switch_to_tboot_pt(void)
	112	+{
	113	+ write_cr3(virt_to_phys(tboot_pg_dir));
	114	+}
	115	+
	116	+static int map_tboot_page(unsigned long vaddr, unsigned long pfn,
	117	+ pgprot_t prot)
	118	+{
	119	+ pgd_t *pgd;
	120	+ pud_t *pud;
	121	+ pmd_t *pmd;
	122	+ pte_t *pte;
	123	+
	124	+ pgd = pgd_offset(&tboot_mm, vaddr);
	125	+ pud = pud_alloc(&tboot_mm, pgd, vaddr);
	126	+ if (!pud)
	127	+ return -1;
	128	+ pmd = pmd_alloc(&tboot_mm, pud, vaddr);
	129	+ if (!pmd)
	130	+ return -1;
	131	+ pte = pte_alloc_map(&tboot_mm, pmd, vaddr);
	132	+ if (!pte)
	133	+ return -1;
	134	+ set_pte_at(&tboot_mm, vaddr, pte, pfn_pte(pfn, prot));
	135	+ pte_unmap(pte);
	136	+ return 0;
	137	+}
	138	+
	139	+static int map_tboot_pages(unsigned long vaddr, unsigned long start_pfn,
	140	+ unsigned long nr)
	141	+{
	142	+ /* Reuse the original kernel mapping */
	143	+ tboot_pg_dir = pgd_alloc(&tboot_mm);
	144	+ if (!tboot_pg_dir)
	145	+ return -1;
	146	+
	147	+ for (; nr > 0; nr--, vaddr += PAGE_SIZE, start_pfn++) {
	148	+ if (map_tboot_page(vaddr, start_pfn, PAGE_KERNEL_EXEC))
	149	+ return -1;
	150	+ }
	151	+
	152	+ return 0;
	153	+}
	154	+
	155	+void tboot_create_trampoline(void)
	156	+{
	157	+ u32 map_base, map_size;
	158	+
	159	+ if (!tboot_enabled())
	160	+ return;
	161	+
	162	+ /* Create identity map for tboot shutdown code. */
	163	+ map_base = PFN_DOWN(tboot->tboot_base);
	164	+ map_size = PFN_UP(tboot->tboot_size);
	165	+ if (map_tboot_pages(map_base << PAGE_SHIFT, map_base, map_size))
	166	+ panic("tboot: Error mapping tboot pages (mfns) @ 0x%x, 0x%x\n", map_base, map_size);
	167	+}
	168	+
	169	+static void set_mac_regions(void)
	170	+{
	171	+ tboot->num_mac_regions = 3;
	172	+ /* S3 resume code */
	173	+ tboot->mac_regions[0].start = PFN_PHYS(PFN_DOWN(acpi_wakeup_address));
	174	+ tboot->mac_regions[0].size = PFN_UP(WAKEUP_SIZE) << PAGE_SHIFT;
	175	+ /* AP trampoline code */
	176	+ tboot->mac_regions[1].start =
	177	+ PFN_PHYS(PFN_DOWN(virt_to_phys(trampoline_base)));
	178	+ tboot->mac_regions[1].size = PFN_UP(TRAMPOLINE_SIZE) << PAGE_SHIFT;
	179	+ /* kernel code + data + bss */
	180	+ tboot->mac_regions[2].start = PFN_PHYS(PFN_DOWN(virt_to_phys(&_text)));
	181	+ tboot->mac_regions[2].size = PFN_PHYS(PFN_UP(virt_to_phys(&_end))) -
	182	+ PFN_PHYS(PFN_DOWN(virt_to_phys(&_text)));
	183	+}
	184	+
	185	+void tboot_shutdown(u32 shutdown_type)
	186	+{
	187	+ void (*shutdown)(void);
	188	+
	189	+ if (!tboot_enabled())
	190	+ return;
	191	+
	192	+ /*
	193	+ * if we're being called before the 1:1 mapping is set up then just
	194	+ * return and let the normal shutdown happen; this should only be
	195	+ * due to very early panic()
	196	+ */
	197	+ if (!tboot_pg_dir)
	198	+ return;
	199	+
	200	+ /* if this is S3 then set regions to MAC */
	201	+ if (shutdown_type == TB_SHUTDOWN_S3)
	202	+ set_mac_regions();
	203	+
	204	+ tboot->shutdown_type = shutdown_type;
	205	+
	206	+ switch_to_tboot_pt();
	207	+
	208	+ shutdown = (void(*)(void))(unsigned long)tboot->shutdown_entry;
	209	+ shutdown();
	210	+
	211	+ /* should not reach here */
	212	+ while (1)
	213	+ halt();
	214	+}
	215	+
	216	+static void tboot_copy_fadt(const struct acpi_table_fadt *fadt)
	217	+{
	218	+#define TB_COPY_GAS(tbg, g) \
	219	+ tbg.space_id = g.space_id; \
	220	+ tbg.bit_width = g.bit_width; \
	221	+ tbg.bit_offset = g.bit_offset; \
	222	+ tbg.access_width = g.access_width; \
	223	+ tbg.address = g.address;
	224	+
	225	+ TB_COPY_GAS(tboot->acpi_sinfo.pm1a_cnt_blk, fadt->xpm1a_control_block);
	226	+ TB_COPY_GAS(tboot->acpi_sinfo.pm1b_cnt_blk, fadt->xpm1b_control_block);
	227	+ TB_COPY_GAS(tboot->acpi_sinfo.pm1a_evt_blk, fadt->xpm1a_event_block);
	228	+ TB_COPY_GAS(tboot->acpi_sinfo.pm1b_evt_blk, fadt->xpm1b_event_block);
	229	+
	230	+ /*
	231	+ * We need phys addr of waking vector, but can't use virt_to_phys() on
	232	+ * &acpi_gbl_FACS because it is ioremap'ed, so calc from FACS phys
	233	+ * addr.
	234	+ */
	235	+ tboot->acpi_sinfo.wakeup_vector = fadt->facs +
	236	+ offsetof(struct acpi_table_facs, firmware_waking_vector);
	237	+}
	238	+
	239	+void tboot_sleep(u8 sleep_state, u32 pm1a_control, u32 pm1b_control)
	240	+{
	241	+ static u32 acpi_shutdown_map[ACPI_S_STATE_COUNT] = {
	242	+ /* S0,1,2: */ -1, -1, -1,
	243	+ /* S3: */ TB_SHUTDOWN_S3,
	244	+ /* S4: */ TB_SHUTDOWN_S4,
	245	+ /* S5: */ TB_SHUTDOWN_S5 };
	246	+
	247	+ if (!tboot_enabled())
	248	+ return;
	249	+
	250	+ tboot_copy_fadt(&acpi_gbl_FADT);
	251	+ tboot->acpi_sinfo.pm1a_cnt_val = pm1a_control;
	252	+ tboot->acpi_sinfo.pm1b_cnt_val = pm1b_control;
	253	+ /* we always use the 32b wakeup vector */
	254	+ tboot->acpi_sinfo.vector_width = 32;
	255	+ tboot->acpi_sinfo.kernel_s3_resume_vector = acpi_wakeup_address;
	256	+
	257	+ if (sleep_state >= ACPI_S_STATE_COUNT \|\|
	258	+ acpi_shutdown_map[sleep_state] == -1) {
	259	+ pr_warning("unsupported sleep state 0x%x\n", sleep_state);
	260	+ return;
	261	+ }
	262	+
	263	+ tboot_shutdown(acpi_shutdown_map[sleep_state]);
	264	+}
	265	+
	266	+int tboot_wait_for_aps(int num_aps)
	267	+{
	268	+ unsigned long timeout;
	269	+
	270	+ if (!tboot_enabled())
	271	+ return 0;
	272	+
	273	+ timeout = jiffies + AP_WAIT_TIMEOUT*HZ;
	274	+ while (atomic_read((atomic_t *)&tboot->num_in_wfs) != num_aps &&
	275	+ time_before(jiffies, timeout))
	276	+ cpu_relax();
	277	+
	278	+ return time_before(jiffies, timeout) ? 0 : 1;
	279	+}
	280	+
	281	+/*
	282	+ * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE)
	283	+ */
	284	+
	285	+#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000
	286	+#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000
	287	+
	288	+/* # pages for each config regs space - used by fixmap */
	289	+#define NR_TXT_CONFIG_PAGES ((TXT_PUB_CONFIG_REGS_BASE - \
	290	+ TXT_PRIV_CONFIG_REGS_BASE) >> PAGE_SHIFT)
	291	+
	292	+/* offsets from pub/priv config space */
	293	+#define TXTCR_HEAP_BASE 0x0300
	294	+#define TXTCR_HEAP_SIZE 0x0308
	295	+
	296	+#define SHA1_SIZE 20
	297	+
	298	+struct sha1_hash {
	299	+ u8 hash[SHA1_SIZE];
	300	+};
	301	+
	302	+struct sinit_mle_data {
	303	+ u32 version; /* currently 6 */
	304	+ struct sha1_hash bios_acm_id;
	305	+ u32 edx_senter_flags;
	306	+ u64 mseg_valid;
	307	+ struct sha1_hash sinit_hash;
	308	+ struct sha1_hash mle_hash;
	309	+ struct sha1_hash stm_hash;
	310	+ struct sha1_hash lcp_policy_hash;
	311	+ u32 lcp_policy_control;
	312	+ u32 rlp_wakeup_addr;
	313	+ u32 reserved;
	314	+ u32 num_mdrs;
	315	+ u32 mdrs_off;
	316	+ u32 num_vtd_dmars;
	317	+ u32 vtd_dmars_off;
	318	+} __packed;
	319	+
	320	+struct acpi_table_header tboot_get_dmar_table(struct acpi_table_header dmar_tbl)
	321	+{
	322	+ void heap_base, heap_ptr, *config;
	323	+
	324	+ if (!tboot_enabled())
	325	+ return dmar_tbl;
	326	+
	327	+ /*
	328	+ * ACPI tables may not be DMA protected by tboot, so use DMAR copy
	329	+ * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
	330	+ */
	331	+
	332	+ /* map config space in order to get heap addr */
	333	+ config = ioremap(TXT_PUB_CONFIG_REGS_BASE, NR_TXT_CONFIG_PAGES *
	334	+ PAGE_SIZE);
	335	+ if (!config)
	336	+ return NULL;
	337	+
	338	+ /* now map TXT heap */
	339	+ heap_base = ioremap((u64 )(config + TXTCR_HEAP_BASE),
	340	+ (u64 )(config + TXTCR_HEAP_SIZE));
	341	+ iounmap(config);
	342	+ if (!heap_base)
	343	+ return NULL;
	344	+
	345	+ /* walk heap to SinitMleData */
	346	+ /* skip BiosData */
	347	+ heap_ptr = heap_base + (u64 )heap_base;
	348	+ /* skip OsMleData */
	349	+ heap_ptr += (u64 )heap_ptr;
	350	+ /* skip OsSinitData */
	351	+ heap_ptr += (u64 )heap_ptr;
	352	+ /* now points to SinitMleDataSize; set to SinitMleData */
	353	+ heap_ptr += sizeof(u64);
	354	+ /* get addr of DMAR table */
	355	+ dmar_tbl = (struct acpi_table_header *)(heap_ptr +
	356	+ ((struct sinit_mle_data *)heap_ptr)->vtd_dmars_off -
	357	+ sizeof(u64));
	358	+
	359	+ /* don't unmap heap because dmar.c needs access to this */
	360	+
	361	+ return dmar_tbl;
	362	+}
	363	+
	364	+int tboot_force_iommu(void)
	365	+{
	366	+ if (!tboot_enabled())
	367	+ return 0;
	368	+
	369	+ if (no_iommu \|\| swiotlb \|\| dmar_disabled)
	370	+ pr_warning("Forcing Intel-IOMMU to enabled\n");
	371	+
	372	+ dmar_disabled = 0;
	373	+#ifdef CONFIG_SWIOTLB
	374	+ swiotlb = 0;
	375	+#endif
	376	+ no_iommu = 0;
	377	+
	378	+ return 1;
	379	+}
...	...	@@ -113,6 +113,36 @@
113	113
114	114	If you are unsure how to answer this question, answer N.
115	115
	116	+config INTEL_TXT
	117	+ bool "Enable Intel(R) Trusted Execution Technology (Intel(R) TXT)"
	118	+ depends on EXPERIMENTAL && X86 && DMAR && ACPI
	119	+ help
	120	+ This option enables support for booting the kernel with the
	121	+ Trusted Boot (tboot) module. This will utilize
	122	+ Intel(R) Trusted Execution Technology to perform a measured launch
	123	+ of the kernel. If the system does not support Intel(R) TXT, this
	124	+ will have no effect.
	125	+
	126	+ Intel TXT will provide higher assurance of sysem configuration and
	127	+ initial state as well as data reset protection. This is used to
	128	+ create a robust initial kernel measurement and verification, which
	129	+ helps to ensure that kernel security mechanisms are functioning
	130	+ correctly. This level of protection requires a root of trust outside
	131	+ of the kernel itself.
	132	+
	133	+ Intel TXT also helps solve real end user concerns about having
	134	+ confidence that their hardware is running the VMM or kernel that
	135	+ it was conigured with, especially since they may be responsible for
	136	+ providing such assurances to VMs and services running on it.
	137	+
	138	+ See <http://www.intel.com/technology/security/> for more information
	139	+ about Intel(R) TXT.
	140	+ See <http://tboot.sourceforge.net> for more information about tboot.
	141	+ See Documentation/intel_txt.txt for a description of how to enable
	142	+ Intel TXT support in a kernel boot.
	143	+
	144	+ If you are unsure as to whether this is required, answer N.
	145	+
116	146	source security/selinux/Kconfig
117	147	source security/smack/Kconfig
118	148	source security/tomoyo/Kconfig