Commit 39f6cde27db27f77cc133cab8ee5121d8b2be0d1

Authored by Ravikumar Kattekola
Committed by Jacob Stiffler
1 parent e75d80d8d4

DRA7: IVA: Set iva initial frequency to OPP_NOM

By default IVA_DPLL is in bypass mode and clkout_m2 which
is going to iva_gclk is 20 MHz.
Set iva_gclk to IVA OPP_NOM 388MHz as multimnedia usecases need this

Signed-off-by: Ravikumar Kattekola <rk@ti.com>

Showing 1 changed file with 17 additions and 0 deletions Side-by-side Diff

drivers/clk/ti/clk-7xx.c
... ... @@ -21,6 +21,9 @@
21 21 #define DRA7_DPLL_DSP_DEFFREQ 600000000
22 22 #define DRA7_DPLL_DSP_GFCLK_NOMFREQ 600000000
23 23 #define DRA7_DPLL_EVE_GCLK_NOMFREQ 400000000
  24 +#define DRA7_ATL2_DEFFREQ 5644800
  25 +#define DRA7_DPLL_IVA_DEFFREQ 776666666
  26 +#define DRA7_DPLL_IVA_GFCLK_NOMFREQ 388333333
24 27  
25 28 #define DRA7_ATL_DEFFREQ 5644800
26 29 #define DRA7_DPLL_USB_DEFFREQ 960000000
... ... @@ -323,6 +326,7 @@
323 326 struct clk *ipu1_gfclk, *ipu1_gfclk_parent;
324 327 struct clk *dsp_dpll, *dsp_m2_dpll, *dsp_m3x2_dpll;
325 328 struct clk *atl_fck, *atl_parent;
  329 + struct clk *iva_dpll, *iva_m2_dpll;
326 330  
327 331 ti_dt_clocks_register(dra7xx_clks);
328 332  
... ... @@ -402,6 +406,19 @@
402 406 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
403 407 if (rc)
404 408 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
  409 +
  410 + iva_dpll = clk_get_sys(NULL, "dpll_iva_ck");
  411 + rc = clk_set_rate(iva_dpll, DRA7_DPLL_IVA_DEFFREQ);
  412 + if (!rc) {
  413 + iva_m2_dpll = clk_get_sys(NULL, "dpll_iva_m2_ck");
  414 + rc = clk_set_rate(iva_m2_dpll, DRA7_DPLL_IVA_GFCLK_NOMFREQ);
  415 + if (rc)
  416 + pr_err("%s: failed to configure IVA DPLL m2 output!\n",
  417 + __func__);
  418 +
  419 + } else {
  420 + pr_err("%s: failed to configure IVA DPLL!\n", __func__);
  421 + }
405 422  
406 423 return rc;
407 424 }