arm:dra7xx: Add gpu hwmod data

GPU hwmod data for DRA7xx Change-Id: I0a7a3fc85f664a404a3510d64ef8891414b2fd98 Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com>

arm:dra7xx: Add gpu hwmod data
GPU hwmod data for DRA7xx Change-Id: I0a7a3fc85f664a404a3510d64ef8891414b2fd98 Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Hemant Hariyani · Jacob Stiffler
1 parent 1b7ce40a93
Showing 1 changed file with 74 additions and 0 deletions Side-by-side Diff
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1271,6 +1271,40 @@
 };
  
 /*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
+	.rev_offs       = 0x0000,
+	.sysc_offs      = 0x0010,
+	.sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+	.idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
+	.name   = "gpu",
+	.sysc   = &dra7xx_gpu_sysc,
+};
+
+static struct omap_hwmod dra7xx_gpu_hwmod = {
+	.name           = "gpu",
+	.class          = &dra7xx_gpu_hwmod_class,
+	.clkdm_name     = "gpu_clkdm",
+	.main_clk       = "gpu_core_gclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'hdq1w' class
  *
  */
@@ -3664,6 +3698,45 @@
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
  
+static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
+	{
+		.name           = "klio",
+		.pa_start       = 0x56000000,
+		.pa_end         = 0x56001fff,
+	},
+	{
+		.name           = "hydra2",
+		.pa_start       = 0x56004000,
+		.pa_end         = 0x56004fff,
+	},
+	{
+		.name           = "klio_0",
+		.pa_start       = 0x56008000,
+		.pa_end         = 0x56009fff,
+	},
+	{
+		.name           = "klio_1",
+		.pa_start       = 0x5600c000,
+		.pa_end         = 0x5600dfff,
+	},
+	{
+		.name           = "klio_hl",
+		.pa_start       = 0x5600fe00,
+		.pa_end         = 0x5600ffff,
+		.flags          = ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l3_main_1 -> gpu */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
+	.master         = &dra7xx_l3_main_1_hwmod,
+	.slave          = &dra7xx_gpu_hwmod,
+	.clk            = "l3_iclk_div",
+	.addr           = dra7xx_gpu_addrs,
+	.user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
 	{
 		.pa_start	= 0x480b2000,
@@ -4453,6 +4526,7 @@
 	&dra7xx_l4_per1__gpio7,
 	&dra7xx_l4_per1__gpio8,
 	&dra7xx_l3_main_1__gpmc,
+	&dra7xx_l3_main_1__gpu,
 	&dra7xx_l4_per1__hdq1w,
 	&dra7xx_l4_per1__i2c1,
 	&dra7xx_l4_per1__i2c2,
...	...	@@ -1271,6 +1271,40 @@
1271	1271	};
1272	1272
1273	1273	/*
	1274	+ * 'gpu' class
	1275	+ * 2d/3d graphics accelerator
	1276	+ */
	1277	+
	1278	+static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
	1279	+ .rev_offs = 0x0000,
	1280	+ .sysc_offs = 0x0010,
	1281	+ .sysc_flags = (SYSC_HAS_MIDLEMODE \| SYSC_HAS_SIDLEMODE),
	1282	+ .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	1283	+ SIDLE_SMART_WKUP \| MSTANDBY_FORCE \| MSTANDBY_NO \|
	1284	+ MSTANDBY_SMART \| MSTANDBY_SMART_WKUP),
	1285	+ .sysc_fields = &omap_hwmod_sysc_type2,
	1286	+};
	1287	+
	1288	+static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
	1289	+ .name = "gpu",
	1290	+ .sysc = &dra7xx_gpu_sysc,
	1291	+};
	1292	+
	1293	+static struct omap_hwmod dra7xx_gpu_hwmod = {
	1294	+ .name = "gpu",
	1295	+ .class = &dra7xx_gpu_hwmod_class,
	1296	+ .clkdm_name = "gpu_clkdm",
	1297	+ .main_clk = "gpu_core_gclk_mux",
	1298	+ .prcm = {
	1299	+ .omap4 = {
	1300	+ .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
	1301	+ .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
	1302	+ .modulemode = MODULEMODE_SWCTRL,
	1303	+ },
	1304	+ },
	1305	+};
	1306	+
	1307	+/*
1274	1308	* 'hdq1w' class
1275	1309	*
1276	1310	*/
...	...	@@ -3664,6 +3698,45 @@
3664	3698	.user = OCP_USER_MPU \| OCP_USER_SDMA,
3665	3699	};
3666	3700
	3701	+static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
	3702	+ {
	3703	+ .name = "klio",
	3704	+ .pa_start = 0x56000000,
	3705	+ .pa_end = 0x56001fff,
	3706	+ },
	3707	+ {
	3708	+ .name = "hydra2",
	3709	+ .pa_start = 0x56004000,
	3710	+ .pa_end = 0x56004fff,
	3711	+ },
	3712	+ {
	3713	+ .name = "klio_0",
	3714	+ .pa_start = 0x56008000,
	3715	+ .pa_end = 0x56009fff,
	3716	+ },
	3717	+ {
	3718	+ .name = "klio_1",
	3719	+ .pa_start = 0x5600c000,
	3720	+ .pa_end = 0x5600dfff,
	3721	+ },
	3722	+ {
	3723	+ .name = "klio_hl",
	3724	+ .pa_start = 0x5600fe00,
	3725	+ .pa_end = 0x5600ffff,
	3726	+ .flags = ADDR_TYPE_RT
	3727	+ },
	3728	+ { }
	3729	+};
	3730	+
	3731	+/* l3_main_1 -> gpu */
	3732	+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
	3733	+ .master = &dra7xx_l3_main_1_hwmod,
	3734	+ .slave = &dra7xx_gpu_hwmod,
	3735	+ .clk = "l3_iclk_div",
	3736	+ .addr = dra7xx_gpu_addrs,
	3737	+ .user = OCP_USER_MPU \| OCP_USER_SDMA,
	3738	+};
	3739	+
3667	3740	static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3668	3741	{
3669	3742	.pa_start = 0x480b2000,
...	...	@@ -4453,6 +4526,7 @@
4453	4526	&dra7xx_l4_per1__gpio7,
4454	4527	&dra7xx_l4_per1__gpio8,
4455	4528	&dra7xx_l3_main_1__gpmc,
	4529	+ &dra7xx_l3_main_1__gpu,
4456	4530	&dra7xx_l4_per1__hdq1w,
4457	4531	&dra7xx_l4_per1__i2c1,
4458	4532	&dra7xx_l4_per1__i2c2,