Eric Lee / smarc-ti-linux-kernel

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Commit 3be8142951e87beb9a69efbfea0f4041c893c09f

Authored by Olof Johansson
2 parents 1591dc44a0 7a9f0604bd
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Merge tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shaw… 

…nguo/linux into fixes

Merge "ARM: imx: fixes for 3.19" from Shawn Guo:

The i.MX fixes for 3.19:
 - One fix for incorrect i.MX25 SPI1 clock assignment in device tree,
   which causes system hang when accessing SPI1.
 - Correct i.MX6SX QSPI parent clock configuration to fix a kernel Oops.
 - Fix ULPI PHY reset modelling on imx51-babbage board to remove the
   dependency on bootloader for USB3317 ULPI PHY reset.
 - Correct video divider setting on i.MX6Q rev T0 1.0 to fix the issue
   that HDMI is not working at high resolution on T0 1.0.
 - One incremental fix for CODA960 VPU enabling in device tree to
   correct interrupt order.
 - LS1021A SCFG block works in BE mode, add device tree property
   big-endian to make it right.

* tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling
  ARM: imx6sx: Set PLL2 as parent of QSPI clocks
  ARM: dts: imx25: Fix the SPI1 clocks
  ARM: clk-imx6q: fix video divider for rev T0 1.0
  ARM: dts: imx6qdl: Fix CODA960 interrupt order
  ARM: ls1021a: dtsi: add 'big-endian' property for scfg node

Signed-off-by: Olof Johansson <olof@lixom.net>

Showing 6 changed files Side-by-side Diff

arch/arm/boot/dts/imx25.dtsi
Diff comments   View file @ 3be8142
... ... @@ -162,7 +162,7 @@
162 162 #size-cells = <0>;
163 163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
164 164 reg = <0x43fa4000 0x4000>;
165   - clocks = <&clks 62>, <&clks 62>;
  165 + clocks = <&clks 78>, <&clks 78>;
166 166 clock-names = "ipg", "per";
167 167 interrupts = <14>;
168 168 status = "disabled";
arch/arm/boot/dts/imx51-babbage.dts
Diff comments   View file @ 3be8142
... ... @@ -127,26 +127,14 @@
127 127 #address-cells = <1>;
128 128 #size-cells = <0>;
129 129  
130   - reg_usbh1_vbus: regulator@0 {
  130 + reg_hub_reset: regulator@0 {
131 131 compatible = "regulator-fixed";
132 132 pinctrl-names = "default";
133   - pinctrl-0 = <&pinctrl_usbh1reg>;
  133 + pinctrl-0 = <&pinctrl_usbotgreg>;
134 134 reg = <0>;
135   - regulator-name = "usbh1_vbus";
  135 + regulator-name = "hub_reset";
136 136 regulator-min-microvolt = <5000000>;
137 137 regulator-max-microvolt = <5000000>;
138   - gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139   - enable-active-high;
140   - };
141   -
142   - reg_usbotg_vbus: regulator@1 {
143   - compatible = "regulator-fixed";
144   - pinctrl-names = "default";
145   - pinctrl-0 = <&pinctrl_usbotgreg>;
146   - reg = <1>;
147   - regulator-name = "usbotg_vbus";
148   - regulator-min-microvolt = <5000000>;
149   - regulator-max-microvolt = <5000000>;
150 138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
151 139 enable-active-high;
152 140 };
... ... @@ -176,6 +164,7 @@
176 164 reg = <0>;
177 165 clocks = <&clks IMX5_CLK_DUMMY>;
178 166 clock-names = "main_clk";
  167 + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
179 168 };
180 169 };
181 170 };
... ... @@ -419,7 +408,7 @@
419 408 &usbh1 {
420 409 pinctrl-names = "default";
421 410 pinctrl-0 = <&pinctrl_usbh1>;
422   - vbus-supply = <&reg_usbh1_vbus>;
  411 + vbus-supply = <&reg_hub_reset>;
423 412 fsl,usbphy = <&usbh1phy>;
424 413 phy_type = "ulpi";
425 414 status = "okay";
... ... @@ -429,7 +418,6 @@
429 418 dr_mode = "otg";
430 419 disable-over-current;
431 420 phy_type = "utmi_wide";
432   - vbus-supply = <&reg_usbotg_vbus>;
433 421 status = "okay";
434 422 };
435 423  
arch/arm/boot/dts/imx6qdl.dtsi
Diff comments   View file @ 3be8142
... ... @@ -335,8 +335,8 @@
335 335 vpu: vpu@02040000 {
336 336 compatible = "cnm,coda960";
337 337 reg = <0x02040000 0x3c000>;
338   - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
339   - <0 12 IRQ_TYPE_LEVEL_HIGH>;
  338 + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
  339 + <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 340 interrupt-names = "bit", "jpeg";
341 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
arch/arm/boot/dts/ls1021a.dtsi
Diff comments   View file @ 3be8142
... ... @@ -142,6 +142,7 @@
142 142 scfg: scfg@1570000 {
143 143 compatible = "fsl,ls1021a-scfg", "syscon";
144 144 reg = <0x0 0x1570000 0x0 0x10000>;
  145 + big-endian;
145 146 };
146 147  
147 148 clockgen: clocking@1ee1000 {
arch/arm/mach-imx/clk-imx6q.c
Diff comments   View file @ 3be8142
... ... @@ -144,7 +144,7 @@
144 144 post_div_table[1].div = 1;
145 145 post_div_table[2].div = 1;
146 146 video_div_table[1].div = 1;
147   - video_div_table[2].div = 1;
  147 + video_div_table[3].div = 1;
148 148 }
149 149  
150 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
arch/arm/mach-imx/clk-imx6sx.c
Diff comments   View file @ 3be8142
... ... @@ -558,6 +558,9 @@
558 558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
559 559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
560 560  
  561 + clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
  562 + clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
  563 +
561 564 /* Set initial power mode */
562 565 imx6q_set_lpm(WAIT_CLOCKED);
563 566 }