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Commit 3ed4d18f39bcd8cb8d8218c0a5f89a4d81ba8730

Authored by Russell King
1 parent 2f0d13bdf6
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

dmaengine: omap-dma: consolidate setup of CCR 

Consolidate the setup of the channel control register.  Prepare the
basic value in the preparation of the DMA descriptor, and write it into
the register upon descriptor execution.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 61 additions and 86 deletions Side-by-side Diff

drivers/dma/omap-dma.c
Diff comments   View file @ 3ed4d18
... ... @@ -58,8 +58,7 @@
58 58  
59 59 int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
60 60 uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
61   - uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
62   - uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
  61 + uint32_t ccr; /* CCR value */
63 62 uint16_t cicr; /* CICR value */
64 63 uint32_t csdp; /* CSDP value */
65 64  
... ... @@ -227,7 +226,6 @@
227 226 {
228 227 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
229 228 struct omap_desc *d;
230   - uint32_t val;
231 229  
232 230 if (!vd) {
233 231 c->desc = NULL;
234 232  
235 233  
... ... @@ -239,23 +237,15 @@
239 237 c->desc = d = to_omap_dma_desc(&vd->tx);
240 238 c->sgidx = 0;
241 239  
242   - if (d->dir == DMA_DEV_TO_MEM) {
243   - val = c->plat->dma_read(CCR, c->dma_ch);
244   - val &= ~(0x03 << 14 | 0x03 << 12);
245   - val |= OMAP_DMA_AMODE_POST_INC << 14;
246   - val |= OMAP_DMA_AMODE_CONSTANT << 12;
247   - c->plat->dma_write(val, CCR, c->dma_ch);
  240 + c->plat->dma_write(d->ccr, CCR, c->dma_ch);
  241 + if (dma_omap1())
  242 + c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
248 243  
  244 + if (d->dir == DMA_DEV_TO_MEM) {
249 245 c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
250 246 c->plat->dma_write(0, CSEI, c->dma_ch);
251 247 c->plat->dma_write(d->fi, CSFI, c->dma_ch);
252 248 } else {
253   - val = c->plat->dma_read(CCR, c->dma_ch);
254   - val &= ~(0x03 << 12 | 0x03 << 14);
255   - val |= OMAP_DMA_AMODE_CONSTANT << 14;
256   - val |= OMAP_DMA_AMODE_POST_INC << 12;
257   - c->plat->dma_write(val, CCR, c->dma_ch);
258   -
259 249 c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
260 250 c->plat->dma_write(0, CDEI, c->dma_ch);
261 251 c->plat->dma_write(d->fi, CDFI, c->dma_ch);
... ... @@ -263,45 +253,6 @@
263 253  
264 254 c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
265 255  
266   - if (dma_omap1()) {
267   - val = c->plat->dma_read(CCR, c->dma_ch);
268   - val &= ~(1 << 5);
269   - if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
270   - val |= 1 << 5;
271   - c->plat->dma_write(val, CCR, c->dma_ch);
272   -
273   - val = c->plat->dma_read(CCR2, c->dma_ch);
274   - val &= ~(1 << 2);
275   - if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
276   - val |= 1 << 2;
277   - c->plat->dma_write(val, CCR2, c->dma_ch);
278   - } else if (c->dma_sig) {
279   - val = c->plat->dma_read(CCR, c->dma_ch);
280   -
281   - /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
282   - val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
283   - val |= (c->dma_sig & ~0x1f) << 14;
284   - val |= c->dma_sig & 0x1f;
285   -
286   - if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
287   - val |= 1 << 5;
288   -
289   - if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
290   - val |= 1 << 18;
291   -
292   - switch (d->sync_type) {
293   - case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
294   - val |= 1 << 23; /* Prefetch */
295   - break;
296   - case 0:
297   - break;
298   - default:
299   - val |= 1 << 24; /* source synch */
300   - break;
301   - }
302   - c->plat->dma_write(val, CCR, c->dma_ch);
303   - }
304   -
305 256 omap_dma_start_sg(c, d, 0);
306 257 }
307 258  
308 259  
309 260  
... ... @@ -540,19 +491,17 @@
540 491 struct scatterlist *sgent;
541 492 struct omap_desc *d;
542 493 dma_addr_t dev_addr;
543   - unsigned i, j = 0, es, en, frame_bytes, sync_type;
  494 + unsigned i, j = 0, es, en, frame_bytes;
544 495 u32 burst;
545 496  
546 497 if (dir == DMA_DEV_TO_MEM) {
547 498 dev_addr = c->cfg.src_addr;
548 499 dev_width = c->cfg.src_addr_width;
549 500 burst = c->cfg.src_maxburst;
550   - sync_type = OMAP_DMA_SRC_SYNC;
551 501 } else if (dir == DMA_MEM_TO_DEV) {
552 502 dev_addr = c->cfg.dst_addr;
553 503 dev_width = c->cfg.dst_addr_width;
554 504 burst = c->cfg.dst_maxburst;
555   - sync_type = OMAP_DMA_DST_SYNC;
556 505 } else {
557 506 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
558 507 return NULL;
559 508  
... ... @@ -581,12 +530,28 @@
581 530 d->dir = dir;
582 531 d->dev_addr = dev_addr;
583 532 d->es = es;
584   - d->sync_mode = OMAP_DMA_SYNC_FRAME;
585   - d->sync_type = sync_type;
  533 +
  534 + d->ccr = 0;
  535 + if (dir == DMA_DEV_TO_MEM)
  536 + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
  537 + OMAP_DMA_AMODE_CONSTANT << 12;
  538 + else
  539 + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
  540 + OMAP_DMA_AMODE_POST_INC << 12;
  541 +
586 542 d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
587 543 d->csdp = es;
588 544  
589 545 if (dma_omap1()) {
  546 + d->ccr |= 1 << 5; /* frame sync */
  547 + if (__dma_omap16xx(od->plat->dma_attr)) {
  548 + d->ccr |= 1 << 10; /* disable 3.0/3.1 compatibility mode */
  549 + /* Duplicate what plat-omap/dma.c does */
  550 + d->ccr |= c->dma_ch + 1;
  551 + } else {
  552 + d->ccr |= c->dma_sig & 0x1f;
  553 + }
  554 +
590 555 d->cicr |= OMAP1_DMA_TOUT_IRQ;
591 556  
592 557 if (dir == DMA_DEV_TO_MEM)
... ... @@ -596,6 +561,13 @@
596 561 d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
597 562 OMAP_DMA_PORT_EMIFF << 2;
598 563 } else {
  564 + d->ccr |= (c->dma_sig & ~0x1f) << 14;
  565 + d->ccr |= c->dma_sig & 0x1f;
  566 + d->ccr |= 1 << 5; /* frame sync */
  567 +
  568 + if (dir == DMA_DEV_TO_MEM)
  569 + d->ccr |= 1 << 24; /* source synch */
  570 +
599 571 d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
600 572 }
601 573  
602 574  
603 575  
... ... @@ -632,19 +604,17 @@
632 604 enum dma_slave_buswidth dev_width;
633 605 struct omap_desc *d;
634 606 dma_addr_t dev_addr;
635   - unsigned es, sync_type;
  607 + unsigned es;
636 608 u32 burst;
637 609  
638 610 if (dir == DMA_DEV_TO_MEM) {
639 611 dev_addr = c->cfg.src_addr;
640 612 dev_width = c->cfg.src_addr_width;
641 613 burst = c->cfg.src_maxburst;
642   - sync_type = OMAP_DMA_SRC_SYNC;
643 614 } else if (dir == DMA_MEM_TO_DEV) {
644 615 dev_addr = c->cfg.dst_addr;
645 616 dev_width = c->cfg.dst_addr_width;
646 617 burst = c->cfg.dst_maxburst;
647   - sync_type = OMAP_DMA_DST_SYNC;
648 618 } else {
649 619 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
650 620 return NULL;
651 621  
... ... @@ -674,15 +644,21 @@
674 644 d->dev_addr = dev_addr;
675 645 d->fi = burst;
676 646 d->es = es;
677   - if (burst)
678   - d->sync_mode = OMAP_DMA_SYNC_PACKET;
679   - else
680   - d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
681   - d->sync_type = sync_type;
682 647 d->sg[0].addr = buf_addr;
683 648 d->sg[0].en = period_len / es_bytes[es];
684 649 d->sg[0].fn = buf_len / period_len;
685 650 d->sglen = 1;
  651 +
  652 + d->ccr = 0;
  653 + if (__dma_omap15xx(od->plat->dma_attr))
  654 + d->ccr = 3 << 8;
  655 + if (dir == DMA_DEV_TO_MEM)
  656 + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
  657 + OMAP_DMA_AMODE_CONSTANT << 12;
  658 + else
  659 + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
  660 + OMAP_DMA_AMODE_POST_INC << 12;
  661 +
686 662 d->cicr = OMAP_DMA_DROP_IRQ;
687 663 if (flags & DMA_PREP_INTERRUPT)
688 664 d->cicr |= OMAP_DMA_FRAME_IRQ;
... ... @@ -690,6 +666,14 @@
690 666 d->csdp = es;
691 667  
692 668 if (dma_omap1()) {
  669 + if (__dma_omap16xx(od->plat->dma_attr)) {
  670 + d->ccr |= 1 << 10; /* disable 3.0/3.1 compatibility mode */
  671 + /* Duplicate what plat-omap/dma.c does */
  672 + d->ccr |= c->dma_ch + 1;
  673 + } else {
  674 + d->ccr |= c->dma_sig & 0x1f;
  675 + }
  676 +
693 677 d->cicr |= OMAP1_DMA_TOUT_IRQ;
694 678  
695 679 if (dir == DMA_DEV_TO_MEM)
696 680  
697 681  
... ... @@ -699,24 +683,23 @@
699 683 d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
700 684 OMAP_DMA_PORT_EMIFF << 2;
701 685 } else {
  686 + d->ccr |= (c->dma_sig & ~0x1f) << 14;
  687 + d->ccr |= c->dma_sig & 0x1f;
  688 +
  689 + if (burst)
  690 + d->ccr |= 1 << 18 | 1 << 5; /* packet */
  691 +
  692 + if (dir == DMA_DEV_TO_MEM)
  693 + d->ccr |= 1 << 24; /* source synch */
  694 +
702 695 d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
703 696  
704 697 /* src and dst burst mode 16 */
705 698 d->csdp |= 3 << 14 | 3 << 7;
706 699 }
707 700  
708   - if (!c->cyclic) {
709   - c->cyclic = true;
  701 + c->cyclic = true;
710 702  
711   - if (__dma_omap15xx(od->plat->dma_attr)) {
712   - uint32_t val;
713   -
714   - val = c->plat->dma_read(CCR, c->dma_ch);
715   - val |= 3 << 8;
716   - c->plat->dma_write(val, CCR, c->dma_ch);
717   - }
718   - }
719   -
720 703 return vchan_tx_prep(&c->vc, &d->vd, flags);
721 704 }
722 705  
... ... @@ -759,14 +742,6 @@
759 742 if (c->cyclic) {
760 743 c->cyclic = false;
761 744 c->paused = false;
762   -
763   - if (__dma_omap15xx(od->plat->dma_attr)) {
764   - uint32_t val;
765   -
766   - val = c->plat->dma_read(CCR, c->dma_ch);
767   - val &= ~(3 << 8);
768   - c->plat->dma_write(val, CCR, c->dma_ch);
769   - }
770 745 }
771 746  
772 747 vchan_get_all_descriptors(&c->vc, &head);