Commit 3f9e92bfefd52ac9888044145604830fe6c5dbc2
Committed by
Tero Kristo
Tero Kristo
1 parent
4db475980d
Exists in
ti-linux-3.14.y
and in
2 other branches
ARM: OMAP2+: pm33xx: Only pass i2c volt scale offsets for DeepSleep
The offsets for i2c voltage scaling sequence were being set directly into IPC register 5 and being passed for all PM operations. This is incorrect as only DeepSleep0 should scale voltage, not standby or cpuidle. Instead we should store the value when it is calculated and only pass for DeepSleep operation, not cpuidle operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Showing 2 changed files with 5 additions and 1 deletions Side-by-side Diff
arch/arm/mach-omap2/pm33xx.c
| ... | ... | @@ -115,6 +115,7 @@ |
| 115 | 115 | am33xx_pm->ipc.reg1 = IPC_CMD_IDLE; |
| 116 | 116 | am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT; |
| 117 | 117 | am33xx_pm->ipc.reg3 = m3_flags; |
| 118 | + am33xx_pm->ipc.reg5 = DS_IPC_DEFAULT; | |
| 118 | 119 | wkup_m3_set_cmd(&am33xx_pm->ipc); |
| 119 | 120 | ret = wkup_m3_ping(); |
| 120 | 121 | if (ret < 0) |
| 121 | 122 | |
| ... | ... | @@ -341,9 +342,11 @@ |
| 341 | 342 | switch (state) { |
| 342 | 343 | case PM_SUSPEND_MEM: |
| 343 | 344 | am33xx_pm->ipc.reg1 = IPC_CMD_DS0; |
| 345 | + am33xx_pm->ipc.reg5 = am33xx_pm->m3_i2c_sequence_offsets; | |
| 344 | 346 | break; |
| 345 | 347 | case PM_SUSPEND_STANDBY: |
| 346 | 348 | am33xx_pm->ipc.reg1 = IPC_CMD_STANDBY; |
| 349 | + am33xx_pm->ipc.reg5 = DS_IPC_DEFAULT; | |
| 347 | 350 | break; |
| 348 | 351 | } |
| 349 | 352 | |
| ... | ... | @@ -422,7 +425,7 @@ |
| 422 | 425 | val = (aux_base + hdr.sleep_offset); |
| 423 | 426 | val |= ((aux_base + hdr.wake_offset) << 16); |
| 424 | 427 | |
| 425 | - am33xx_pm->ipc.reg5 = val; | |
| 428 | + am33xx_pm->m3_i2c_sequence_offsets = val; | |
| 426 | 429 | |
| 427 | 430 | release_sd_fw: |
| 428 | 431 | release_firmware(fw); |