Eric Lee / smarc-ti-linux-kernel

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Commit 45da7b0451b1fe15e882b08c79be58458cbe7a2f

Authored by Russell King
1 parent 5987190270
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

dmaengine: omap-dma: use cached CCR value when enabling DMA 

We don't need to read-modify-write the CCR register; we already know
what value it should contain at this point.  Use the cached CCR value
when setting the enable bit.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 2 additions and 4 deletions Side-by-side Diff

drivers/dma/omap-dma.c
Diff comments   View file @ 45da7b0
... ... @@ -181,7 +181,6 @@
181 181 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
182 182 {
183 183 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
184   - uint32_t val;
185 184  
186 185 if (__dma_omap15xx(od->plat->dma_attr))
187 186 c->plat->dma_write(0, CPC, c->dma_ch);
... ... @@ -193,9 +192,8 @@
193 192 /* Enable interrupts */
194 193 c->plat->dma_write(d->cicr, CICR, c->dma_ch);
195 194  
196   - val = c->plat->dma_read(CCR, c->dma_ch);
197   - val |= CCR_ENABLE;
198   - c->plat->dma_write(val, CCR, c->dma_ch);
  195 + /* Enable channel */
  196 + c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
199 197 }
200 198  
201 199 static void omap_dma_stop(struct omap_chan *c)