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Commit 4f3a8bc7ba6e34403f36e600bc6f54cf0e0041e4

Authored by Paulo Zanoni
Committed by Daniel Vetter
1 parent dc0fa71811
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

drm/i915: rename some HDMI bit definitions 

Bits used only on HDMI mode now have HDMI_ prefix instead of SDVO_.
The COLOR_FORMAT bits now have prefixes (and the 12bpc bit is for HDMI
only).

Notice that this patch uncovers a bug on the SDVO code: the
COLOR_RANGE_16_235 bit can only be used if the port is in TMDS mode,
not SDVO mode. This will have to be fixed in a later patch.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Showing 3 changed files with 13 additions and 9 deletions Side-by-side Diff

drivers/gpu/drm/i915/i915_reg.h
Diff comments   View file @ 4f3a8bc
... ... @@ -1718,19 +1718,19 @@
1718 1718 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
1719 1719  
1720 1720 /* Gen 4 SDVO/HDMI bits: */
1721   -#define COLOR_FORMAT_8bpc (0 << 26)
  1721 +#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
1722 1722 #define SDVO_ENCODING_SDVO (0 << 10)
1723 1723 #define SDVO_ENCODING_HDMI (2 << 10)
1724 1724 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
1725 1725 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1726   -#define SDVO_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
  1726 +#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
1727 1727 #define SDVO_AUDIO_ENABLE (1 << 6)
1728 1728 /* VSYNC/HSYNC bits new with 965, default is to be set */
1729 1729 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1730 1730 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1731 1731  
1732 1732 /* Gen 5 (IBX) SDVO/HDMI bits: */
1733   -#define COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
  1733 +#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
1734 1734 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
1735 1735  
1736 1736 /* Gen 6 (CPT) SDVO/HDMI bits: */
drivers/gpu/drm/i915/intel_hdmi.c
Diff comments   View file @ 4f3a8bc
... ... @@ -609,9 +609,9 @@
609 609 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
610 610  
611 611 if (intel_crtc->bpp > 24)
612   - hdmi_val |= COLOR_FORMAT_12bpc;
  612 + hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
613 613 else
614   - hdmi_val |= COLOR_FORMAT_8bpc;
  614 + hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
615 615  
616 616 /* Required on CPT */
617 617 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
... ... @@ -778,7 +778,7 @@
778 778 /* See CEA-861-E - 5.1 Default Encoding Parameters */
779 779 if (intel_hdmi->has_hdmi_sink &&
780 780 drm_mode_cea_vic(adjusted_mode) > 1)
781   - intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;
  781 + intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
782 782 else
783 783 intel_hdmi->color_range = 0;
784 784 }
... ... @@ -941,7 +941,7 @@
941 941 break;
942 942 case INTEL_BROADCAST_RGB_LIMITED:
943 943 intel_hdmi->color_range_auto = false;
944   - intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;
  944 + intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
945 945 break;
946 946 default:
947 947 return -EINVAL;
drivers/gpu/drm/i915/intel_sdvo.c
Diff comments   View file @ 4f3a8bc
... ... @@ -1076,9 +1076,11 @@
1076 1076  
1077 1077 if (intel_sdvo->color_range_auto) {
1078 1078 /* See CEA-861-E - 5.1 Default Encoding Parameters */
  1079 + /* FIXME: This bit is only valid when using TMDS encoding and 8
  1080 + * bit per color mode. */
1079 1081 if (intel_sdvo->has_hdmi_monitor &&
1080 1082 drm_mode_cea_vic(adjusted_mode) > 1)
1081   - intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  1083 + intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
1082 1084 else
1083 1085 intel_sdvo->color_range = 0;
1084 1086 }
... ... @@ -1926,7 +1928,9 @@
1926 1928 break;
1927 1929 case INTEL_BROADCAST_RGB_LIMITED:
1928 1930 intel_sdvo->color_range_auto = false;
1929   - intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  1931 + /* FIXME: this bit is only valid when using TMDS
  1932 + * encoding and 8 bit per color mode. */
  1933 + intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
1930 1934 break;
1931 1935 default:
1932 1936 return -EINVAL;