Commit 5306c31c5733cb4a79cc002e0c3ad256fd439614

Authored by Andi Kleen
Committed by Ingo Molnar
1 parent 86c269fea3

perf/x86/uncore/hsw-ep: Handle systems with only two SBOXes

There was another report of a boot failure with a #GP fault in the
uncore SBOX initialization. The earlier work around was not enough
for this system.

The boot was failing while trying to initialize the third SBOX.

This patch detects parts with only two SBOXes and limits the number
of SBOX units to two there.

Stable material, as it affects boot problems on 3.18.

Tested-by: Andreas Oehler <andreas@oehler-net.de>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Yan, Zheng <zheng.z.yan@intel.com>
Link: http://lkml.kernel.org/r/1420583675-9163-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

Showing 2 changed files with 18 additions and 1 deletions Side-by-side Diff

arch/x86/kernel/cpu/perf_event_intel_uncore.h
... ... @@ -17,7 +17,7 @@
17 17 #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
18 18 #define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
19 19 #define UNCORE_EXTRA_PCI_DEV 0xff
20   -#define UNCORE_EXTRA_PCI_DEV_MAX 2
  20 +#define UNCORE_EXTRA_PCI_DEV_MAX 3
21 21  
22 22 /* support up to 8 sockets */
23 23 #define UNCORE_SOCKET_MAX 8
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
... ... @@ -891,6 +891,7 @@
891 891 enum {
892 892 SNBEP_PCI_QPI_PORT0_FILTER,
893 893 SNBEP_PCI_QPI_PORT1_FILTER,
  894 + HSWEP_PCI_PCU_3,
894 895 };
895 896  
896 897 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
... ... @@ -2026,6 +2027,17 @@
2026 2027 {
2027 2028 if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2028 2029 hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
  2030 +
  2031 + /* Detect 6-8 core systems with only two SBOXes */
  2032 + if (uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3]) {
  2033 + u32 capid4;
  2034 +
  2035 + pci_read_config_dword(uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3],
  2036 + 0x94, &capid4);
  2037 + if (((capid4 >> 6) & 0x3) == 0)
  2038 + hswep_uncore_sbox.num_boxes = 2;
  2039 + }
  2040 +
2029 2041 uncore_msr_uncores = hswep_msr_uncores;
2030 2042 }
2031 2043  
... ... @@ -2286,6 +2298,11 @@
2286 2298 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
2287 2299 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2288 2300 SNBEP_PCI_QPI_PORT1_FILTER),
  2301 + },
  2302 + { /* PCU.3 (for Capability registers) */
  2303 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0),
  2304 + .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
  2305 + HSWEP_PCI_PCU_3),
2289 2306 },
2290 2307 { /* end: all zeroes */ }
2291 2308 };