Commit 5f407751b0ca9bd876fe8f15ff28153661c6ba0a

Authored by Daniel Vetter
Committed by Jani Nikula
1 parent 3164a80341

drm/i915: Fixup legacy plane->crtc link for initial fb config

This is a very similar bug in the load detect code fixed in

commit 9128b040eb774e04bc23777b005ace2b66ab2a85
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Tue Mar 3 17:31:21 2015 +0100

    drm/i915: Fix modeset state confusion in the load detect code

But this time around it was the initial fb code that forgot to update
the plane->crtc pointer. Otherwise it's the exact same bug, with the
exact same restrains (any set_config call/ioctl that doesn't disable
the pipe papers over the bug for free, so fairly hard to hit in normal
testing). So if you want the full explanation just go read that one
over there - it's rather long ...

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Josh Boyer <jwboyer@fedoraproject.org>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reported-and-tested-by: Josh Boyer <jwboyer@fedoraproject.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[Jani: backported to drm-intel-fixes for v4.0-rc]
Reference: http://mid.gmane.org/CA+5PVA7ChbtJrknqws1qvZcbrg1CW2pQAFkSMURWWgyASRyGXg@mail.gmail.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Showing 1 changed file with 2 additions and 0 deletions Side-by-side Diff

drivers/gpu/drm/i915/intel_display.c
... ... @@ -2442,6 +2442,7 @@
2442 2442 struct drm_plane *primary = intel_crtc->base.primary;
2443 2443  
2444 2444 primary->state->crtc = &intel_crtc->base;
  2445 + primary->crtc = &intel_crtc->base;
2445 2446 update_state_fb(primary);
2446 2447  
2447 2448 return;
... ... @@ -2476,6 +2477,7 @@
2476 2477 drm_framebuffer_reference(c->primary->fb);
2477 2478 primary->fb = c->primary->fb;
2478 2479 primary->state->crtc = &intel_crtc->base;
  2480 + primary->crtc = &intel_crtc->base;
2479 2481 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2480 2482 break;
2481 2483 }