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Commit 609aeacaacd9db3d7abb2eb4d2ff8e62af8ce283

Authored by Ville Syrjälä
Committed by Daniel Vetter
1 parent 92b576e6e9
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

drm/i915: Program VSYNCSHIFT in a more consistent manner 

When interlaced sdvo output is used, vsyncshift should supposedly
be (htotal-1)/2. In reality PIPECONF/TRANSCONF will override it by
using the legacy vsyncshift interlace mode which causes the hardware
to ignore the VSYNCSHIFT register.

The only odd thing here is that on PCH platforms we program the
VSYNCSHIFT on both CPU and PCH, and it's not entirely clear if both
sides have to agree on the value or not. On the CPU side there's no
way to override the value via PIPECONF anymore, so if we want to make
the CPU side agree with the PCH side, we should probably program the
approriate value into VSYNCSHIFT manually. So let's do that, but for
now leave the PCH side to still use the legacy interlace mode in
TRANSCONF.

We can also drop the gen2 check since gen2 doesn't support interlaced
modes at all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Showing 1 changed file with 8 additions and 6 deletions Side-by-side Diff

drivers/gpu/drm/i915/intel_display.c
Diff comments   View file @ 609aeac
... ... @@ -5369,21 +5369,23 @@
5369 5369 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5370 5370 struct drm_display_mode *adjusted_mode =
5371 5371 &intel_crtc->config.adjusted_mode;
5372   - uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  5372 + uint32_t vsyncshift = 0, crtc_vtotal, crtc_vblank_end;
5373 5373  
5374 5374 /* We need to be careful not to changed the adjusted mode, for otherwise
5375 5375 * the hw state checker will get angry at the mismatch. */
5376 5376 crtc_vtotal = adjusted_mode->crtc_vtotal;
5377 5377 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5378 5378  
5379   - if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  5379 + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5380 5380 /* the chip adds 2 halflines automatically */
5381 5381 crtc_vtotal -= 1;
5382 5382 crtc_vblank_end -= 1;
5383   - vsyncshift = adjusted_mode->crtc_hsync_start
5384   - - adjusted_mode->crtc_htotal / 2;
5385   - } else {
5386   - vsyncshift = 0;
  5383 +
  5384 + if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
  5385 + vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
  5386 + else
  5387 + vsyncshift = adjusted_mode->crtc_hsync_start -
  5388 + adjusted_mode->crtc_htotal / 2;
5387 5389 }
5388 5390  
5389 5391 if (INTEL_INFO(dev)->gen > 3)