Commit 68adac5e49436992e9c999fbae879d9ac5b72d4e
Committed by
Dave Airlie
1 parent
15a7df8db8
Exists in
master
and in
20 other branches
drm: move radeon_fixed.h to shared drm_fixed.h header
Will be used by nouveau driver also in the near future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Showing 10 changed files with 447 additions and 447 deletions Side-by-side Diff
- drivers/gpu/drm/radeon/atombios_crtc.c
- drivers/gpu/drm/radeon/r100.c
- drivers/gpu/drm/radeon/radeon_device.c
- drivers/gpu/drm/radeon/radeon_display.c
- drivers/gpu/drm/radeon/radeon_fixed.h
- drivers/gpu/drm/radeon/radeon_legacy_crtc.c
- drivers/gpu/drm/radeon/radeon_mode.h
- drivers/gpu/drm/radeon/rs690.c
- drivers/gpu/drm/radeon/rv515.c
- include/drm/drm_fixed.h
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/r100.c
... | ... | @@ -2686,53 +2686,53 @@ |
2686 | 2686 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
2687 | 2687 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
2688 | 2688 | fixed20_12 memtcas_ff[8] = { |
2689 | - fixed_init(1), | |
2690 | - fixed_init(2), | |
2691 | - fixed_init(3), | |
2692 | - fixed_init(0), | |
2693 | - fixed_init_half(1), | |
2694 | - fixed_init_half(2), | |
2695 | - fixed_init(0), | |
2689 | + dfixed_init(1), | |
2690 | + dfixed_init(2), | |
2691 | + dfixed_init(3), | |
2692 | + dfixed_init(0), | |
2693 | + dfixed_init_half(1), | |
2694 | + dfixed_init_half(2), | |
2695 | + dfixed_init(0), | |
2696 | 2696 | }; |
2697 | 2697 | fixed20_12 memtcas_rs480_ff[8] = { |
2698 | - fixed_init(0), | |
2699 | - fixed_init(1), | |
2700 | - fixed_init(2), | |
2701 | - fixed_init(3), | |
2702 | - fixed_init(0), | |
2703 | - fixed_init_half(1), | |
2704 | - fixed_init_half(2), | |
2705 | - fixed_init_half(3), | |
2698 | + dfixed_init(0), | |
2699 | + dfixed_init(1), | |
2700 | + dfixed_init(2), | |
2701 | + dfixed_init(3), | |
2702 | + dfixed_init(0), | |
2703 | + dfixed_init_half(1), | |
2704 | + dfixed_init_half(2), | |
2705 | + dfixed_init_half(3), | |
2706 | 2706 | }; |
2707 | 2707 | fixed20_12 memtcas2_ff[8] = { |
2708 | - fixed_init(0), | |
2709 | - fixed_init(1), | |
2710 | - fixed_init(2), | |
2711 | - fixed_init(3), | |
2712 | - fixed_init(4), | |
2713 | - fixed_init(5), | |
2714 | - fixed_init(6), | |
2715 | - fixed_init(7), | |
2708 | + dfixed_init(0), | |
2709 | + dfixed_init(1), | |
2710 | + dfixed_init(2), | |
2711 | + dfixed_init(3), | |
2712 | + dfixed_init(4), | |
2713 | + dfixed_init(5), | |
2714 | + dfixed_init(6), | |
2715 | + dfixed_init(7), | |
2716 | 2716 | }; |
2717 | 2717 | fixed20_12 memtrbs[8] = { |
2718 | - fixed_init(1), | |
2719 | - fixed_init_half(1), | |
2720 | - fixed_init(2), | |
2721 | - fixed_init_half(2), | |
2722 | - fixed_init(3), | |
2723 | - fixed_init_half(3), | |
2724 | - fixed_init(4), | |
2725 | - fixed_init_half(4) | |
2718 | + dfixed_init(1), | |
2719 | + dfixed_init_half(1), | |
2720 | + dfixed_init(2), | |
2721 | + dfixed_init_half(2), | |
2722 | + dfixed_init(3), | |
2723 | + dfixed_init_half(3), | |
2724 | + dfixed_init(4), | |
2725 | + dfixed_init_half(4) | |
2726 | 2726 | }; |
2727 | 2727 | fixed20_12 memtrbs_r4xx[8] = { |
2728 | - fixed_init(4), | |
2729 | - fixed_init(5), | |
2730 | - fixed_init(6), | |
2731 | - fixed_init(7), | |
2732 | - fixed_init(8), | |
2733 | - fixed_init(9), | |
2734 | - fixed_init(10), | |
2735 | - fixed_init(11) | |
2728 | + dfixed_init(4), | |
2729 | + dfixed_init(5), | |
2730 | + dfixed_init(6), | |
2731 | + dfixed_init(7), | |
2732 | + dfixed_init(8), | |
2733 | + dfixed_init(9), | |
2734 | + dfixed_init(10), | |
2735 | + dfixed_init(11) | |
2736 | 2736 | }; |
2737 | 2737 | fixed20_12 min_mem_eff; |
2738 | 2738 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
... | ... | @@ -2763,7 +2763,7 @@ |
2763 | 2763 | } |
2764 | 2764 | } |
2765 | 2765 | |
2766 | - min_mem_eff.full = rfixed_const_8(0); | |
2766 | + min_mem_eff.full = dfixed_const_8(0); | |
2767 | 2767 | /* get modes */ |
2768 | 2768 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
2769 | 2769 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
2770 | 2770 | |
2771 | 2771 | |
2772 | 2772 | |
... | ... | @@ -2784,28 +2784,28 @@ |
2784 | 2784 | mclk_ff = rdev->pm.mclk; |
2785 | 2785 | |
2786 | 2786 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
2787 | - temp_ff.full = rfixed_const(temp); | |
2788 | - mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | |
2787 | + temp_ff.full = dfixed_const(temp); | |
2788 | + mem_bw.full = dfixed_mul(mclk_ff, temp_ff); | |
2789 | 2789 | |
2790 | 2790 | pix_clk.full = 0; |
2791 | 2791 | pix_clk2.full = 0; |
2792 | 2792 | peak_disp_bw.full = 0; |
2793 | 2793 | if (mode1) { |
2794 | - temp_ff.full = rfixed_const(1000); | |
2795 | - pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | |
2796 | - pix_clk.full = rfixed_div(pix_clk, temp_ff); | |
2797 | - temp_ff.full = rfixed_const(pixel_bytes1); | |
2798 | - peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | |
2794 | + temp_ff.full = dfixed_const(1000); | |
2795 | + pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ | |
2796 | + pix_clk.full = dfixed_div(pix_clk, temp_ff); | |
2797 | + temp_ff.full = dfixed_const(pixel_bytes1); | |
2798 | + peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); | |
2799 | 2799 | } |
2800 | 2800 | if (mode2) { |
2801 | - temp_ff.full = rfixed_const(1000); | |
2802 | - pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | |
2803 | - pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | |
2804 | - temp_ff.full = rfixed_const(pixel_bytes2); | |
2805 | - peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | |
2801 | + temp_ff.full = dfixed_const(1000); | |
2802 | + pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ | |
2803 | + pix_clk2.full = dfixed_div(pix_clk2, temp_ff); | |
2804 | + temp_ff.full = dfixed_const(pixel_bytes2); | |
2805 | + peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); | |
2806 | 2806 | } |
2807 | 2807 | |
2808 | - mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | |
2808 | + mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); | |
2809 | 2809 | if (peak_disp_bw.full >= mem_bw.full) { |
2810 | 2810 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
2811 | 2811 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
... | ... | @@ -2847,9 +2847,9 @@ |
2847 | 2847 | mem_tras = ((temp >> 12) & 0xf) + 4; |
2848 | 2848 | } |
2849 | 2849 | /* convert to FF */ |
2850 | - trcd_ff.full = rfixed_const(mem_trcd); | |
2851 | - trp_ff.full = rfixed_const(mem_trp); | |
2852 | - tras_ff.full = rfixed_const(mem_tras); | |
2850 | + trcd_ff.full = dfixed_const(mem_trcd); | |
2851 | + trp_ff.full = dfixed_const(mem_trp); | |
2852 | + tras_ff.full = dfixed_const(mem_tras); | |
2853 | 2853 | |
2854 | 2854 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
2855 | 2855 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
... | ... | @@ -2867,7 +2867,7 @@ |
2867 | 2867 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
2868 | 2868 | data = (temp >> 23) & 0x7; |
2869 | 2869 | if (data < 5) |
2870 | - tcas_ff.full += rfixed_const(data); | |
2870 | + tcas_ff.full += dfixed_const(data); | |
2871 | 2871 | } |
2872 | 2872 | |
2873 | 2873 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
2874 | 2874 | |
2875 | 2875 | |
2876 | 2876 | |
2877 | 2877 | |
2878 | 2878 | |
2879 | 2879 | |
2880 | 2880 | |
2881 | 2881 | |
2882 | 2882 | |
2883 | 2883 | |
2884 | 2884 | |
2885 | 2885 | |
2886 | 2886 | |
2887 | 2887 | |
2888 | 2888 | |
... | ... | @@ -2904,72 +2904,72 @@ |
2904 | 2904 | |
2905 | 2905 | if (rdev->flags & RADEON_IS_AGP) { |
2906 | 2906 | fixed20_12 agpmode_ff; |
2907 | - agpmode_ff.full = rfixed_const(radeon_agpmode); | |
2908 | - temp_ff.full = rfixed_const_666(16); | |
2909 | - sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); | |
2907 | + agpmode_ff.full = dfixed_const(radeon_agpmode); | |
2908 | + temp_ff.full = dfixed_const_666(16); | |
2909 | + sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); | |
2910 | 2910 | } |
2911 | 2911 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
2912 | 2912 | |
2913 | 2913 | if (ASIC_IS_R300(rdev)) { |
2914 | - sclk_delay_ff.full = rfixed_const(250); | |
2914 | + sclk_delay_ff.full = dfixed_const(250); | |
2915 | 2915 | } else { |
2916 | 2916 | if ((rdev->family == CHIP_RV100) || |
2917 | 2917 | rdev->flags & RADEON_IS_IGP) { |
2918 | 2918 | if (rdev->mc.vram_is_ddr) |
2919 | - sclk_delay_ff.full = rfixed_const(41); | |
2919 | + sclk_delay_ff.full = dfixed_const(41); | |
2920 | 2920 | else |
2921 | - sclk_delay_ff.full = rfixed_const(33); | |
2921 | + sclk_delay_ff.full = dfixed_const(33); | |
2922 | 2922 | } else { |
2923 | 2923 | if (rdev->mc.vram_width == 128) |
2924 | - sclk_delay_ff.full = rfixed_const(57); | |
2924 | + sclk_delay_ff.full = dfixed_const(57); | |
2925 | 2925 | else |
2926 | - sclk_delay_ff.full = rfixed_const(41); | |
2926 | + sclk_delay_ff.full = dfixed_const(41); | |
2927 | 2927 | } |
2928 | 2928 | } |
2929 | 2929 | |
2930 | - mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); | |
2930 | + mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); | |
2931 | 2931 | |
2932 | 2932 | if (rdev->mc.vram_is_ddr) { |
2933 | 2933 | if (rdev->mc.vram_width == 32) { |
2934 | - k1.full = rfixed_const(40); | |
2934 | + k1.full = dfixed_const(40); | |
2935 | 2935 | c = 3; |
2936 | 2936 | } else { |
2937 | - k1.full = rfixed_const(20); | |
2937 | + k1.full = dfixed_const(20); | |
2938 | 2938 | c = 1; |
2939 | 2939 | } |
2940 | 2940 | } else { |
2941 | - k1.full = rfixed_const(40); | |
2941 | + k1.full = dfixed_const(40); | |
2942 | 2942 | c = 3; |
2943 | 2943 | } |
2944 | 2944 | |
2945 | - temp_ff.full = rfixed_const(2); | |
2946 | - mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); | |
2947 | - temp_ff.full = rfixed_const(c); | |
2948 | - mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); | |
2949 | - temp_ff.full = rfixed_const(4); | |
2950 | - mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); | |
2951 | - mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); | |
2945 | + temp_ff.full = dfixed_const(2); | |
2946 | + mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); | |
2947 | + temp_ff.full = dfixed_const(c); | |
2948 | + mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); | |
2949 | + temp_ff.full = dfixed_const(4); | |
2950 | + mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); | |
2951 | + mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); | |
2952 | 2952 | mc_latency_mclk.full += k1.full; |
2953 | 2953 | |
2954 | - mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); | |
2955 | - mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); | |
2954 | + mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); | |
2955 | + mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); | |
2956 | 2956 | |
2957 | 2957 | /* |
2958 | 2958 | HW cursor time assuming worst case of full size colour cursor. |
2959 | 2959 | */ |
2960 | - temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | |
2960 | + temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | |
2961 | 2961 | temp_ff.full += trcd_ff.full; |
2962 | 2962 | if (temp_ff.full < tras_ff.full) |
2963 | 2963 | temp_ff.full = tras_ff.full; |
2964 | - cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); | |
2964 | + cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); | |
2965 | 2965 | |
2966 | - temp_ff.full = rfixed_const(cur_size); | |
2967 | - cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); | |
2966 | + temp_ff.full = dfixed_const(cur_size); | |
2967 | + cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); | |
2968 | 2968 | /* |
2969 | 2969 | Find the total latency for the display data. |
2970 | 2970 | */ |
2971 | - disp_latency_overhead.full = rfixed_const(8); | |
2972 | - disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); | |
2971 | + disp_latency_overhead.full = dfixed_const(8); | |
2972 | + disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); | |
2973 | 2973 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
2974 | 2974 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
2975 | 2975 | |
2976 | 2976 | |
2977 | 2977 | |
... | ... | @@ -2997,16 +2997,16 @@ |
2997 | 2997 | /* |
2998 | 2998 | Find the drain rate of the display buffer. |
2999 | 2999 | */ |
3000 | - temp_ff.full = rfixed_const((16/pixel_bytes1)); | |
3001 | - disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); | |
3000 | + temp_ff.full = dfixed_const((16/pixel_bytes1)); | |
3001 | + disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); | |
3002 | 3002 | |
3003 | 3003 | /* |
3004 | 3004 | Find the critical point of the display buffer. |
3005 | 3005 | */ |
3006 | - crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); | |
3007 | - crit_point_ff.full += rfixed_const_half(0); | |
3006 | + crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); | |
3007 | + crit_point_ff.full += dfixed_const_half(0); | |
3008 | 3008 | |
3009 | - critical_point = rfixed_trunc(crit_point_ff); | |
3009 | + critical_point = dfixed_trunc(crit_point_ff); | |
3010 | 3010 | |
3011 | 3011 | if (rdev->disp_priority == 2) { |
3012 | 3012 | critical_point = 0; |
... | ... | @@ -3077,8 +3077,8 @@ |
3077 | 3077 | /* |
3078 | 3078 | Find the drain rate of the display buffer. |
3079 | 3079 | */ |
3080 | - temp_ff.full = rfixed_const((16/pixel_bytes2)); | |
3081 | - disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); | |
3080 | + temp_ff.full = dfixed_const((16/pixel_bytes2)); | |
3081 | + disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); | |
3082 | 3082 | |
3083 | 3083 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
3084 | 3084 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
... | ... | @@ -3099,8 +3099,8 @@ |
3099 | 3099 | critical_point2 = 0; |
3100 | 3100 | else { |
3101 | 3101 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
3102 | - temp_ff.full = rfixed_const(temp); | |
3103 | - temp_ff.full = rfixed_mul(mclk_ff, temp_ff); | |
3102 | + temp_ff.full = dfixed_const(temp); | |
3103 | + temp_ff.full = dfixed_mul(mclk_ff, temp_ff); | |
3104 | 3104 | if (sclk_ff.full < temp_ff.full) |
3105 | 3105 | temp_ff.full = sclk_ff.full; |
3106 | 3106 | |
3107 | 3107 | |
3108 | 3108 | |
... | ... | @@ -3108,15 +3108,15 @@ |
3108 | 3108 | |
3109 | 3109 | if (mode1) { |
3110 | 3110 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
3111 | - time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); | |
3111 | + time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); | |
3112 | 3112 | } else { |
3113 | 3113 | time_disp1_drop_priority.full = 0; |
3114 | 3114 | } |
3115 | 3115 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3116 | - crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); | |
3117 | - crit_point_ff.full += rfixed_const_half(0); | |
3116 | + crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); | |
3117 | + crit_point_ff.full += dfixed_const_half(0); | |
3118 | 3118 | |
3119 | - critical_point2 = rfixed_trunc(crit_point_ff); | |
3119 | + critical_point2 = dfixed_trunc(crit_point_ff); | |
3120 | 3120 | |
3121 | 3121 | if (rdev->disp_priority == 2) { |
3122 | 3122 | critical_point2 = 0; |
drivers/gpu/drm/radeon/radeon_device.c
... | ... | @@ -299,24 +299,24 @@ |
299 | 299 | sclk = radeon_get_engine_clock(rdev); |
300 | 300 | mclk = rdev->clock.default_mclk; |
301 | 301 | |
302 | - a.full = rfixed_const(100); | |
303 | - rdev->pm.sclk.full = rfixed_const(sclk); | |
304 | - rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
305 | - rdev->pm.mclk.full = rfixed_const(mclk); | |
306 | - rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | |
302 | + a.full = dfixed_const(100); | |
303 | + rdev->pm.sclk.full = dfixed_const(sclk); | |
304 | + rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
305 | + rdev->pm.mclk.full = dfixed_const(mclk); | |
306 | + rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | |
307 | 307 | |
308 | - a.full = rfixed_const(16); | |
308 | + a.full = dfixed_const(16); | |
309 | 309 | /* core_bandwidth = sclk(Mhz) * 16 */ |
310 | - rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); | |
310 | + rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); | |
311 | 311 | } else { |
312 | 312 | sclk = radeon_get_engine_clock(rdev); |
313 | 313 | mclk = radeon_get_memory_clock(rdev); |
314 | 314 | |
315 | - a.full = rfixed_const(100); | |
316 | - rdev->pm.sclk.full = rfixed_const(sclk); | |
317 | - rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
318 | - rdev->pm.mclk.full = rfixed_const(mclk); | |
319 | - rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | |
315 | + a.full = dfixed_const(100); | |
316 | + rdev->pm.sclk.full = dfixed_const(sclk); | |
317 | + rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
318 | + rdev->pm.mclk.full = dfixed_const(mclk); | |
319 | + rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | |
320 | 320 | } |
321 | 321 | } |
322 | 322 |
drivers/gpu/drm/radeon/radeon_display.c
... | ... | @@ -633,37 +633,37 @@ |
633 | 633 | |
634 | 634 | vco_freq = freq * post_div; |
635 | 635 | /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ |
636 | - a.full = rfixed_const(pll->reference_freq); | |
637 | - feedback_divider.full = rfixed_const(vco_freq); | |
638 | - feedback_divider.full = rfixed_div(feedback_divider, a); | |
639 | - a.full = rfixed_const(ref_div); | |
640 | - feedback_divider.full = rfixed_mul(feedback_divider, a); | |
636 | + a.full = dfixed_const(pll->reference_freq); | |
637 | + feedback_divider.full = dfixed_const(vco_freq); | |
638 | + feedback_divider.full = dfixed_div(feedback_divider, a); | |
639 | + a.full = dfixed_const(ref_div); | |
640 | + feedback_divider.full = dfixed_mul(feedback_divider, a); | |
641 | 641 | |
642 | 642 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
643 | 643 | /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ |
644 | - a.full = rfixed_const(10); | |
645 | - feedback_divider.full = rfixed_mul(feedback_divider, a); | |
646 | - feedback_divider.full += rfixed_const_half(0); | |
647 | - feedback_divider.full = rfixed_floor(feedback_divider); | |
648 | - feedback_divider.full = rfixed_div(feedback_divider, a); | |
644 | + a.full = dfixed_const(10); | |
645 | + feedback_divider.full = dfixed_mul(feedback_divider, a); | |
646 | + feedback_divider.full += dfixed_const_half(0); | |
647 | + feedback_divider.full = dfixed_floor(feedback_divider); | |
648 | + feedback_divider.full = dfixed_div(feedback_divider, a); | |
649 | 649 | |
650 | 650 | /* *fb_div = floor(feedback_divider); */ |
651 | - a.full = rfixed_floor(feedback_divider); | |
652 | - *fb_div = rfixed_trunc(a); | |
651 | + a.full = dfixed_floor(feedback_divider); | |
652 | + *fb_div = dfixed_trunc(a); | |
653 | 653 | /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ |
654 | - a.full = rfixed_const(10); | |
655 | - b.full = rfixed_mul(feedback_divider, a); | |
654 | + a.full = dfixed_const(10); | |
655 | + b.full = dfixed_mul(feedback_divider, a); | |
656 | 656 | |
657 | - feedback_divider.full = rfixed_floor(feedback_divider); | |
658 | - feedback_divider.full = rfixed_mul(feedback_divider, a); | |
657 | + feedback_divider.full = dfixed_floor(feedback_divider); | |
658 | + feedback_divider.full = dfixed_mul(feedback_divider, a); | |
659 | 659 | feedback_divider.full = b.full - feedback_divider.full; |
660 | - *fb_div_frac = rfixed_trunc(feedback_divider); | |
660 | + *fb_div_frac = dfixed_trunc(feedback_divider); | |
661 | 661 | } else { |
662 | 662 | /* *fb_div = floor(feedback_divider + 0.5); */ |
663 | - feedback_divider.full += rfixed_const_half(0); | |
664 | - feedback_divider.full = rfixed_floor(feedback_divider); | |
663 | + feedback_divider.full += dfixed_const_half(0); | |
664 | + feedback_divider.full = dfixed_floor(feedback_divider); | |
665 | 665 | |
666 | - *fb_div = rfixed_trunc(feedback_divider); | |
666 | + *fb_div = dfixed_trunc(feedback_divider); | |
667 | 667 | *fb_div_frac = 0; |
668 | 668 | } |
669 | 669 | |
670 | 670 | |
... | ... | @@ -693,10 +693,10 @@ |
693 | 693 | pll_out_max = pll->pll_out_max; |
694 | 694 | } |
695 | 695 | |
696 | - ffreq.full = rfixed_const(freq); | |
696 | + ffreq.full = dfixed_const(freq); | |
697 | 697 | /* max_error = ffreq * 0.0025; */ |
698 | - a.full = rfixed_const(400); | |
699 | - max_error.full = rfixed_div(ffreq, a); | |
698 | + a.full = dfixed_const(400); | |
699 | + max_error.full = dfixed_div(ffreq, a); | |
700 | 700 | |
701 | 701 | for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { |
702 | 702 | if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { |
... | ... | @@ -707,9 +707,9 @@ |
707 | 707 | continue; |
708 | 708 | |
709 | 709 | /* pll_out = vco / post_div; */ |
710 | - a.full = rfixed_const(post_div); | |
711 | - pll_out.full = rfixed_const(vco); | |
712 | - pll_out.full = rfixed_div(pll_out, a); | |
710 | + a.full = dfixed_const(post_div); | |
711 | + pll_out.full = dfixed_const(vco); | |
712 | + pll_out.full = dfixed_div(pll_out, a); | |
713 | 713 | |
714 | 714 | if (pll_out.full >= ffreq.full) { |
715 | 715 | error.full = pll_out.full - ffreq.full; |
716 | 716 | |
... | ... | @@ -1099,15 +1099,15 @@ |
1099 | 1099 | } |
1100 | 1100 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1101 | 1101 | fixed20_12 a, b; |
1102 | - a.full = rfixed_const(crtc->mode.vdisplay); | |
1103 | - b.full = rfixed_const(radeon_crtc->native_mode.hdisplay); | |
1104 | - radeon_crtc->vsc.full = rfixed_div(a, b); | |
1105 | - a.full = rfixed_const(crtc->mode.hdisplay); | |
1106 | - b.full = rfixed_const(radeon_crtc->native_mode.vdisplay); | |
1107 | - radeon_crtc->hsc.full = rfixed_div(a, b); | |
1102 | + a.full = dfixed_const(crtc->mode.vdisplay); | |
1103 | + b.full = dfixed_const(radeon_crtc->native_mode.hdisplay); | |
1104 | + radeon_crtc->vsc.full = dfixed_div(a, b); | |
1105 | + a.full = dfixed_const(crtc->mode.hdisplay); | |
1106 | + b.full = dfixed_const(radeon_crtc->native_mode.vdisplay); | |
1107 | + radeon_crtc->hsc.full = dfixed_div(a, b); | |
1108 | 1108 | } else { |
1109 | - radeon_crtc->vsc.full = rfixed_const(1); | |
1110 | - radeon_crtc->hsc.full = rfixed_const(1); | |
1109 | + radeon_crtc->vsc.full = dfixed_const(1); | |
1110 | + radeon_crtc->hsc.full = dfixed_const(1); | |
1111 | 1111 | } |
1112 | 1112 | return true; |
1113 | 1113 | } |
drivers/gpu/drm/radeon/radeon_fixed.h
1 | -/* | |
2 | - * Copyright 2009 Red Hat Inc. | |
3 | - * | |
4 | - * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | - * copy of this software and associated documentation files (the "Software"), | |
6 | - * to deal in the Software without restriction, including without limitation | |
7 | - * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | - * and/or sell copies of the Software, and to permit persons to whom the | |
9 | - * Software is furnished to do so, subject to the following conditions: | |
10 | - * | |
11 | - * The above copyright notice and this permission notice shall be included in | |
12 | - * all copies or substantial portions of the Software. | |
13 | - * | |
14 | - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | - * OTHER DEALINGS IN THE SOFTWARE. | |
21 | - * | |
22 | - * Authors: Dave Airlie | |
23 | - */ | |
24 | -#ifndef RADEON_FIXED_H | |
25 | -#define RADEON_FIXED_H | |
26 | - | |
27 | -typedef union rfixed { | |
28 | - u32 full; | |
29 | -} fixed20_12; | |
30 | - | |
31 | - | |
32 | -#define rfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ | |
33 | -#define rfixed_const_half(A) (u32)(((A) << 12) + 2048) | |
34 | -#define rfixed_const_666(A) (u32)(((A) << 12) + 2731) | |
35 | -#define rfixed_const_8(A) (u32)(((A) << 12) + 3277) | |
36 | -#define rfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) | |
37 | -#define fixed_init(A) { .full = rfixed_const((A)) } | |
38 | -#define fixed_init_half(A) { .full = rfixed_const_half((A)) } | |
39 | -#define rfixed_trunc(A) ((A).full >> 12) | |
40 | - | |
41 | -static inline u32 rfixed_floor(fixed20_12 A) | |
42 | -{ | |
43 | - u32 non_frac = rfixed_trunc(A); | |
44 | - | |
45 | - return rfixed_const(non_frac); | |
46 | -} | |
47 | - | |
48 | -static inline u32 rfixed_ceil(fixed20_12 A) | |
49 | -{ | |
50 | - u32 non_frac = rfixed_trunc(A); | |
51 | - | |
52 | - if (A.full > rfixed_const(non_frac)) | |
53 | - return rfixed_const(non_frac + 1); | |
54 | - else | |
55 | - return rfixed_const(non_frac); | |
56 | -} | |
57 | - | |
58 | -static inline u32 rfixed_div(fixed20_12 A, fixed20_12 B) | |
59 | -{ | |
60 | - u64 tmp = ((u64)A.full << 13); | |
61 | - | |
62 | - do_div(tmp, B.full); | |
63 | - tmp += 1; | |
64 | - tmp /= 2; | |
65 | - return lower_32_bits(tmp); | |
66 | -} | |
67 | -#endif |
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
drivers/gpu/drm/radeon/radeon_mode.h
... | ... | @@ -34,10 +34,10 @@ |
34 | 34 | #include <drm_mode.h> |
35 | 35 | #include <drm_edid.h> |
36 | 36 | #include <drm_dp_helper.h> |
37 | +#include <drm_fixed.h> | |
37 | 38 | #include <linux/i2c.h> |
38 | 39 | #include <linux/i2c-id.h> |
39 | 40 | #include <linux/i2c-algo-bit.h> |
40 | -#include "radeon_fixed.h" | |
41 | 41 | |
42 | 42 | struct radeon_bo; |
43 | 43 | struct radeon_device; |
drivers/gpu/drm/radeon/rs690.c
... | ... | @@ -76,59 +76,59 @@ |
76 | 76 | /* Get various system informations from bios */ |
77 | 77 | switch (crev) { |
78 | 78 | case 1: |
79 | - tmp.full = rfixed_const(100); | |
80 | - rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock); | |
81 | - rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
82 | - rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); | |
83 | - rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock)); | |
84 | - rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth); | |
79 | + tmp.full = dfixed_const(100); | |
80 | + rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock); | |
81 | + rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
82 | + rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); | |
83 | + rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); | |
84 | + rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); | |
85 | 85 | break; |
86 | 86 | case 2: |
87 | - tmp.full = rfixed_const(100); | |
88 | - rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock); | |
89 | - rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
90 | - rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock); | |
91 | - rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); | |
92 | - rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq); | |
93 | - rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); | |
94 | - rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); | |
87 | + tmp.full = dfixed_const(100); | |
88 | + rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock); | |
89 | + rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
90 | + rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock); | |
91 | + rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | |
92 | + rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq); | |
93 | + rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); | |
94 | + rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); | |
95 | 95 | break; |
96 | 96 | default: |
97 | - tmp.full = rfixed_const(100); | |
97 | + tmp.full = dfixed_const(100); | |
98 | 98 | /* We assume the slower possible clock ie worst case */ |
99 | 99 | /* DDR 333Mhz */ |
100 | - rdev->pm.igp_sideport_mclk.full = rfixed_const(333); | |
100 | + rdev->pm.igp_sideport_mclk.full = dfixed_const(333); | |
101 | 101 | /* FIXME: system clock ? */ |
102 | - rdev->pm.igp_system_mclk.full = rfixed_const(100); | |
103 | - rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); | |
104 | - rdev->pm.igp_ht_link_clk.full = rfixed_const(200); | |
105 | - rdev->pm.igp_ht_link_width.full = rfixed_const(8); | |
102 | + rdev->pm.igp_system_mclk.full = dfixed_const(100); | |
103 | + rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | |
104 | + rdev->pm.igp_ht_link_clk.full = dfixed_const(200); | |
105 | + rdev->pm.igp_ht_link_width.full = dfixed_const(8); | |
106 | 106 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
107 | 107 | break; |
108 | 108 | } |
109 | 109 | } else { |
110 | - tmp.full = rfixed_const(100); | |
110 | + tmp.full = dfixed_const(100); | |
111 | 111 | /* We assume the slower possible clock ie worst case */ |
112 | 112 | /* DDR 333Mhz */ |
113 | - rdev->pm.igp_sideport_mclk.full = rfixed_const(333); | |
113 | + rdev->pm.igp_sideport_mclk.full = dfixed_const(333); | |
114 | 114 | /* FIXME: system clock ? */ |
115 | - rdev->pm.igp_system_mclk.full = rfixed_const(100); | |
116 | - rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); | |
117 | - rdev->pm.igp_ht_link_clk.full = rfixed_const(200); | |
118 | - rdev->pm.igp_ht_link_width.full = rfixed_const(8); | |
115 | + rdev->pm.igp_system_mclk.full = dfixed_const(100); | |
116 | + rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | |
117 | + rdev->pm.igp_ht_link_clk.full = dfixed_const(200); | |
118 | + rdev->pm.igp_ht_link_width.full = dfixed_const(8); | |
119 | 119 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
120 | 120 | } |
121 | 121 | /* Compute various bandwidth */ |
122 | 122 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
123 | - tmp.full = rfixed_const(4); | |
124 | - rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); | |
123 | + tmp.full = dfixed_const(4); | |
124 | + rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); | |
125 | 125 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
126 | 126 | * = ht_clk * ht_width / 5 |
127 | 127 | */ |
128 | - tmp.full = rfixed_const(5); | |
129 | - rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, | |
128 | + tmp.full = dfixed_const(5); | |
129 | + rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, | |
130 | 130 | rdev->pm.igp_ht_link_width); |
131 | - rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); | |
131 | + rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); | |
132 | 132 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
133 | 133 | /* HT link is a limiting factor */ |
134 | 134 | rdev->pm.max_bandwidth.full = tmp.full; |
... | ... | @@ -136,10 +136,10 @@ |
136 | 136 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
137 | 137 | * = (sideport_clk * 14) / 10 |
138 | 138 | */ |
139 | - tmp.full = rfixed_const(14); | |
140 | - rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); | |
141 | - tmp.full = rfixed_const(10); | |
142 | - rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); | |
139 | + tmp.full = dfixed_const(14); | |
140 | + rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); | |
141 | + tmp.full = dfixed_const(10); | |
142 | + rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); | |
143 | 143 | } |
144 | 144 | |
145 | 145 | void rs690_mc_init(struct radeon_device *rdev) |
146 | 146 | |
147 | 147 | |
148 | 148 | |
... | ... | @@ -239,20 +239,20 @@ |
239 | 239 | return; |
240 | 240 | } |
241 | 241 | |
242 | - if (crtc->vsc.full > rfixed_const(2)) | |
243 | - wm->num_line_pair.full = rfixed_const(2); | |
242 | + if (crtc->vsc.full > dfixed_const(2)) | |
243 | + wm->num_line_pair.full = dfixed_const(2); | |
244 | 244 | else |
245 | - wm->num_line_pair.full = rfixed_const(1); | |
245 | + wm->num_line_pair.full = dfixed_const(1); | |
246 | 246 | |
247 | - b.full = rfixed_const(mode->crtc_hdisplay); | |
248 | - c.full = rfixed_const(256); | |
249 | - a.full = rfixed_div(b, c); | |
250 | - request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); | |
251 | - request_fifo_depth.full = rfixed_ceil(request_fifo_depth); | |
252 | - if (a.full < rfixed_const(4)) { | |
247 | + b.full = dfixed_const(mode->crtc_hdisplay); | |
248 | + c.full = dfixed_const(256); | |
249 | + a.full = dfixed_div(b, c); | |
250 | + request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); | |
251 | + request_fifo_depth.full = dfixed_ceil(request_fifo_depth); | |
252 | + if (a.full < dfixed_const(4)) { | |
253 | 253 | wm->lb_request_fifo_depth = 4; |
254 | 254 | } else { |
255 | - wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | |
255 | + wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); | |
256 | 256 | } |
257 | 257 | |
258 | 258 | /* Determine consumption rate |
259 | 259 | |
260 | 260 | |
261 | 261 | |
... | ... | @@ -261,23 +261,23 @@ |
261 | 261 | * vsc = vertical scaling ratio, defined as source/destination |
262 | 262 | * hsc = horizontal scaling ration, defined as source/destination |
263 | 263 | */ |
264 | - a.full = rfixed_const(mode->clock); | |
265 | - b.full = rfixed_const(1000); | |
266 | - a.full = rfixed_div(a, b); | |
267 | - pclk.full = rfixed_div(b, a); | |
264 | + a.full = dfixed_const(mode->clock); | |
265 | + b.full = dfixed_const(1000); | |
266 | + a.full = dfixed_div(a, b); | |
267 | + pclk.full = dfixed_div(b, a); | |
268 | 268 | if (crtc->rmx_type != RMX_OFF) { |
269 | - b.full = rfixed_const(2); | |
269 | + b.full = dfixed_const(2); | |
270 | 270 | if (crtc->vsc.full > b.full) |
271 | 271 | b.full = crtc->vsc.full; |
272 | - b.full = rfixed_mul(b, crtc->hsc); | |
273 | - c.full = rfixed_const(2); | |
274 | - b.full = rfixed_div(b, c); | |
275 | - consumption_time.full = rfixed_div(pclk, b); | |
272 | + b.full = dfixed_mul(b, crtc->hsc); | |
273 | + c.full = dfixed_const(2); | |
274 | + b.full = dfixed_div(b, c); | |
275 | + consumption_time.full = dfixed_div(pclk, b); | |
276 | 276 | } else { |
277 | 277 | consumption_time.full = pclk.full; |
278 | 278 | } |
279 | - a.full = rfixed_const(1); | |
280 | - wm->consumption_rate.full = rfixed_div(a, consumption_time); | |
279 | + a.full = dfixed_const(1); | |
280 | + wm->consumption_rate.full = dfixed_div(a, consumption_time); | |
281 | 281 | |
282 | 282 | |
283 | 283 | /* Determine line time |
284 | 284 | |
... | ... | @@ -285,18 +285,18 @@ |
285 | 285 | * LineTime = total number of horizontal pixels |
286 | 286 | * pclk = pixel clock period(ns) |
287 | 287 | */ |
288 | - a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
289 | - line_time.full = rfixed_mul(a, pclk); | |
288 | + a.full = dfixed_const(crtc->base.mode.crtc_htotal); | |
289 | + line_time.full = dfixed_mul(a, pclk); | |
290 | 290 | |
291 | 291 | /* Determine active time |
292 | 292 | * ActiveTime = time of active region of display within one line, |
293 | 293 | * hactive = total number of horizontal active pixels |
294 | 294 | * htotal = total number of horizontal pixels |
295 | 295 | */ |
296 | - a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
297 | - b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
298 | - wm->active_time.full = rfixed_mul(line_time, b); | |
299 | - wm->active_time.full = rfixed_div(wm->active_time, a); | |
296 | + a.full = dfixed_const(crtc->base.mode.crtc_htotal); | |
297 | + b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
298 | + wm->active_time.full = dfixed_mul(line_time, b); | |
299 | + wm->active_time.full = dfixed_div(wm->active_time, a); | |
300 | 300 | |
301 | 301 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
302 | 302 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
... | ... | @@ -304,8 +304,8 @@ |
304 | 304 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
305 | 305 | rdev->pm.sideport_bandwidth.full) |
306 | 306 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
307 | - read_delay_latency.full = rfixed_const(370 * 800 * 1000); | |
308 | - read_delay_latency.full = rfixed_div(read_delay_latency, | |
307 | + read_delay_latency.full = dfixed_const(370 * 800 * 1000); | |
308 | + read_delay_latency.full = dfixed_div(read_delay_latency, | |
309 | 309 | rdev->pm.igp_sideport_mclk); |
310 | 310 | } else { |
311 | 311 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
312 | 312 | |
313 | 313 | |
... | ... | @@ -314,23 +314,23 @@ |
314 | 314 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
315 | 315 | rdev->pm.ht_bandwidth.full) |
316 | 316 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
317 | - read_delay_latency.full = rfixed_const(5000); | |
317 | + read_delay_latency.full = dfixed_const(5000); | |
318 | 318 | } |
319 | 319 | |
320 | 320 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
321 | - a.full = rfixed_const(16); | |
322 | - rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); | |
323 | - a.full = rfixed_const(1000); | |
324 | - rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); | |
321 | + a.full = dfixed_const(16); | |
322 | + rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); | |
323 | + a.full = dfixed_const(1000); | |
324 | + rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); | |
325 | 325 | /* Determine chunk time |
326 | 326 | * ChunkTime = the time it takes the DCP to send one chunk of data |
327 | 327 | * to the LB which consists of pipeline delay and inter chunk gap |
328 | 328 | * sclk = system clock(ns) |
329 | 329 | */ |
330 | - a.full = rfixed_const(256 * 13); | |
331 | - chunk_time.full = rfixed_mul(rdev->pm.sclk, a); | |
332 | - a.full = rfixed_const(10); | |
333 | - chunk_time.full = rfixed_div(chunk_time, a); | |
330 | + a.full = dfixed_const(256 * 13); | |
331 | + chunk_time.full = dfixed_mul(rdev->pm.sclk, a); | |
332 | + a.full = dfixed_const(10); | |
333 | + chunk_time.full = dfixed_div(chunk_time, a); | |
334 | 334 | |
335 | 335 | /* Determine the worst case latency |
336 | 336 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
337 | 337 | |
... | ... | @@ -340,13 +340,13 @@ |
340 | 340 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
341 | 341 | * which consists of pipeline delay and inter chunk gap |
342 | 342 | */ |
343 | - if (rfixed_trunc(wm->num_line_pair) > 1) { | |
344 | - a.full = rfixed_const(3); | |
345 | - wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | |
343 | + if (dfixed_trunc(wm->num_line_pair) > 1) { | |
344 | + a.full = dfixed_const(3); | |
345 | + wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
346 | 346 | wm->worst_case_latency.full += read_delay_latency.full; |
347 | 347 | } else { |
348 | - a.full = rfixed_const(2); | |
349 | - wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | |
348 | + a.full = dfixed_const(2); | |
349 | + wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
350 | 350 | wm->worst_case_latency.full += read_delay_latency.full; |
351 | 351 | } |
352 | 352 | |
353 | 353 | |
354 | 354 | |
355 | 355 | |
356 | 356 | |
357 | 357 | |
358 | 358 | |
... | ... | @@ -360,34 +360,34 @@ |
360 | 360 | * of data to the LB which consists of |
361 | 361 | * pipeline delay and inter chunk gap |
362 | 362 | */ |
363 | - if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | |
363 | + if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { | |
364 | 364 | tolerable_latency.full = line_time.full; |
365 | 365 | } else { |
366 | - tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | |
366 | + tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); | |
367 | 367 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
368 | - tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | |
368 | + tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); | |
369 | 369 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
370 | 370 | } |
371 | 371 | /* We assume worst case 32bits (4 bytes) */ |
372 | - wm->dbpp.full = rfixed_const(4 * 8); | |
372 | + wm->dbpp.full = dfixed_const(4 * 8); | |
373 | 373 | |
374 | 374 | /* Determine the maximum priority mark |
375 | 375 | * width = viewport width in pixels |
376 | 376 | */ |
377 | - a.full = rfixed_const(16); | |
378 | - wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
379 | - wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | |
380 | - wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); | |
377 | + a.full = dfixed_const(16); | |
378 | + wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
379 | + wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); | |
380 | + wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); | |
381 | 381 | |
382 | 382 | /* Determine estimated width */ |
383 | 383 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
384 | - estimated_width.full = rfixed_div(estimated_width, consumption_time); | |
385 | - if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
386 | - wm->priority_mark.full = rfixed_const(10); | |
384 | + estimated_width.full = dfixed_div(estimated_width, consumption_time); | |
385 | + if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
386 | + wm->priority_mark.full = dfixed_const(10); | |
387 | 387 | } else { |
388 | - a.full = rfixed_const(16); | |
389 | - wm->priority_mark.full = rfixed_div(estimated_width, a); | |
390 | - wm->priority_mark.full = rfixed_ceil(wm->priority_mark); | |
388 | + a.full = dfixed_const(16); | |
389 | + wm->priority_mark.full = dfixed_div(estimated_width, a); | |
390 | + wm->priority_mark.full = dfixed_ceil(wm->priority_mark); | |
391 | 391 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
392 | 392 | } |
393 | 393 | } |
394 | 394 | |
395 | 395 | |
396 | 396 | |
397 | 397 | |
398 | 398 | |
399 | 399 | |
400 | 400 | |
401 | 401 | |
402 | 402 | |
403 | 403 | |
404 | 404 | |
405 | 405 | |
406 | 406 | |
... | ... | @@ -439,58 +439,58 @@ |
439 | 439 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
440 | 440 | |
441 | 441 | if (mode0 && mode1) { |
442 | - if (rfixed_trunc(wm0.dbpp) > 64) | |
443 | - a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
442 | + if (dfixed_trunc(wm0.dbpp) > 64) | |
443 | + a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
444 | 444 | else |
445 | 445 | a.full = wm0.num_line_pair.full; |
446 | - if (rfixed_trunc(wm1.dbpp) > 64) | |
447 | - b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
446 | + if (dfixed_trunc(wm1.dbpp) > 64) | |
447 | + b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
448 | 448 | else |
449 | 449 | b.full = wm1.num_line_pair.full; |
450 | 450 | a.full += b.full; |
451 | - fill_rate.full = rfixed_div(wm0.sclk, a); | |
451 | + fill_rate.full = dfixed_div(wm0.sclk, a); | |
452 | 452 | if (wm0.consumption_rate.full > fill_rate.full) { |
453 | 453 | b.full = wm0.consumption_rate.full - fill_rate.full; |
454 | - b.full = rfixed_mul(b, wm0.active_time); | |
455 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
454 | + b.full = dfixed_mul(b, wm0.active_time); | |
455 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
456 | 456 | wm0.consumption_rate); |
457 | 457 | a.full = a.full + b.full; |
458 | - b.full = rfixed_const(16 * 1000); | |
459 | - priority_mark02.full = rfixed_div(a, b); | |
458 | + b.full = dfixed_const(16 * 1000); | |
459 | + priority_mark02.full = dfixed_div(a, b); | |
460 | 460 | } else { |
461 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
461 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
462 | 462 | wm0.consumption_rate); |
463 | - b.full = rfixed_const(16 * 1000); | |
464 | - priority_mark02.full = rfixed_div(a, b); | |
463 | + b.full = dfixed_const(16 * 1000); | |
464 | + priority_mark02.full = dfixed_div(a, b); | |
465 | 465 | } |
466 | 466 | if (wm1.consumption_rate.full > fill_rate.full) { |
467 | 467 | b.full = wm1.consumption_rate.full - fill_rate.full; |
468 | - b.full = rfixed_mul(b, wm1.active_time); | |
469 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
468 | + b.full = dfixed_mul(b, wm1.active_time); | |
469 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
470 | 470 | wm1.consumption_rate); |
471 | 471 | a.full = a.full + b.full; |
472 | - b.full = rfixed_const(16 * 1000); | |
473 | - priority_mark12.full = rfixed_div(a, b); | |
472 | + b.full = dfixed_const(16 * 1000); | |
473 | + priority_mark12.full = dfixed_div(a, b); | |
474 | 474 | } else { |
475 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
475 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
476 | 476 | wm1.consumption_rate); |
477 | - b.full = rfixed_const(16 * 1000); | |
478 | - priority_mark12.full = rfixed_div(a, b); | |
477 | + b.full = dfixed_const(16 * 1000); | |
478 | + priority_mark12.full = dfixed_div(a, b); | |
479 | 479 | } |
480 | 480 | if (wm0.priority_mark.full > priority_mark02.full) |
481 | 481 | priority_mark02.full = wm0.priority_mark.full; |
482 | - if (rfixed_trunc(priority_mark02) < 0) | |
482 | + if (dfixed_trunc(priority_mark02) < 0) | |
483 | 483 | priority_mark02.full = 0; |
484 | 484 | if (wm0.priority_mark_max.full > priority_mark02.full) |
485 | 485 | priority_mark02.full = wm0.priority_mark_max.full; |
486 | 486 | if (wm1.priority_mark.full > priority_mark12.full) |
487 | 487 | priority_mark12.full = wm1.priority_mark.full; |
488 | - if (rfixed_trunc(priority_mark12) < 0) | |
488 | + if (dfixed_trunc(priority_mark12) < 0) | |
489 | 489 | priority_mark12.full = 0; |
490 | 490 | if (wm1.priority_mark_max.full > priority_mark12.full) |
491 | 491 | priority_mark12.full = wm1.priority_mark_max.full; |
492 | - d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); | |
493 | - d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); | |
492 | + d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
493 | + d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
494 | 494 | if (rdev->disp_priority == 2) { |
495 | 495 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
496 | 496 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
497 | 497 | |
498 | 498 | |
499 | 499 | |
500 | 500 | |
501 | 501 | |
502 | 502 | |
503 | 503 | |
... | ... | @@ -500,32 +500,32 @@ |
500 | 500 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
501 | 501 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
502 | 502 | } else if (mode0) { |
503 | - if (rfixed_trunc(wm0.dbpp) > 64) | |
504 | - a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
503 | + if (dfixed_trunc(wm0.dbpp) > 64) | |
504 | + a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
505 | 505 | else |
506 | 506 | a.full = wm0.num_line_pair.full; |
507 | - fill_rate.full = rfixed_div(wm0.sclk, a); | |
507 | + fill_rate.full = dfixed_div(wm0.sclk, a); | |
508 | 508 | if (wm0.consumption_rate.full > fill_rate.full) { |
509 | 509 | b.full = wm0.consumption_rate.full - fill_rate.full; |
510 | - b.full = rfixed_mul(b, wm0.active_time); | |
511 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
510 | + b.full = dfixed_mul(b, wm0.active_time); | |
511 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
512 | 512 | wm0.consumption_rate); |
513 | 513 | a.full = a.full + b.full; |
514 | - b.full = rfixed_const(16 * 1000); | |
515 | - priority_mark02.full = rfixed_div(a, b); | |
514 | + b.full = dfixed_const(16 * 1000); | |
515 | + priority_mark02.full = dfixed_div(a, b); | |
516 | 516 | } else { |
517 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
517 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
518 | 518 | wm0.consumption_rate); |
519 | - b.full = rfixed_const(16 * 1000); | |
520 | - priority_mark02.full = rfixed_div(a, b); | |
519 | + b.full = dfixed_const(16 * 1000); | |
520 | + priority_mark02.full = dfixed_div(a, b); | |
521 | 521 | } |
522 | 522 | if (wm0.priority_mark.full > priority_mark02.full) |
523 | 523 | priority_mark02.full = wm0.priority_mark.full; |
524 | - if (rfixed_trunc(priority_mark02) < 0) | |
524 | + if (dfixed_trunc(priority_mark02) < 0) | |
525 | 525 | priority_mark02.full = 0; |
526 | 526 | if (wm0.priority_mark_max.full > priority_mark02.full) |
527 | 527 | priority_mark02.full = wm0.priority_mark_max.full; |
528 | - d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); | |
528 | + d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
529 | 529 | if (rdev->disp_priority == 2) |
530 | 530 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
531 | 531 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
532 | 532 | |
533 | 533 | |
534 | 534 | |
535 | 535 | |
536 | 536 | |
537 | 537 | |
538 | 538 | |
... | ... | @@ -535,32 +535,32 @@ |
535 | 535 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, |
536 | 536 | S_006D4C_D2MODE_PRIORITY_B_OFF(1)); |
537 | 537 | } else { |
538 | - if (rfixed_trunc(wm1.dbpp) > 64) | |
539 | - a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
538 | + if (dfixed_trunc(wm1.dbpp) > 64) | |
539 | + a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
540 | 540 | else |
541 | 541 | a.full = wm1.num_line_pair.full; |
542 | - fill_rate.full = rfixed_div(wm1.sclk, a); | |
542 | + fill_rate.full = dfixed_div(wm1.sclk, a); | |
543 | 543 | if (wm1.consumption_rate.full > fill_rate.full) { |
544 | 544 | b.full = wm1.consumption_rate.full - fill_rate.full; |
545 | - b.full = rfixed_mul(b, wm1.active_time); | |
546 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
545 | + b.full = dfixed_mul(b, wm1.active_time); | |
546 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
547 | 547 | wm1.consumption_rate); |
548 | 548 | a.full = a.full + b.full; |
549 | - b.full = rfixed_const(16 * 1000); | |
550 | - priority_mark12.full = rfixed_div(a, b); | |
549 | + b.full = dfixed_const(16 * 1000); | |
550 | + priority_mark12.full = dfixed_div(a, b); | |
551 | 551 | } else { |
552 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
552 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
553 | 553 | wm1.consumption_rate); |
554 | - b.full = rfixed_const(16 * 1000); | |
555 | - priority_mark12.full = rfixed_div(a, b); | |
554 | + b.full = dfixed_const(16 * 1000); | |
555 | + priority_mark12.full = dfixed_div(a, b); | |
556 | 556 | } |
557 | 557 | if (wm1.priority_mark.full > priority_mark12.full) |
558 | 558 | priority_mark12.full = wm1.priority_mark.full; |
559 | - if (rfixed_trunc(priority_mark12) < 0) | |
559 | + if (dfixed_trunc(priority_mark12) < 0) | |
560 | 560 | priority_mark12.full = 0; |
561 | 561 | if (wm1.priority_mark_max.full > priority_mark12.full) |
562 | 562 | priority_mark12.full = wm1.priority_mark_max.full; |
563 | - d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); | |
563 | + d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
564 | 564 | if (rdev->disp_priority == 2) |
565 | 565 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
566 | 566 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, |
drivers/gpu/drm/radeon/rv515.c
... | ... | @@ -795,20 +795,20 @@ |
795 | 795 | return; |
796 | 796 | } |
797 | 797 | |
798 | - if (crtc->vsc.full > rfixed_const(2)) | |
799 | - wm->num_line_pair.full = rfixed_const(2); | |
798 | + if (crtc->vsc.full > dfixed_const(2)) | |
799 | + wm->num_line_pair.full = dfixed_const(2); | |
800 | 800 | else |
801 | - wm->num_line_pair.full = rfixed_const(1); | |
801 | + wm->num_line_pair.full = dfixed_const(1); | |
802 | 802 | |
803 | - b.full = rfixed_const(mode->crtc_hdisplay); | |
804 | - c.full = rfixed_const(256); | |
805 | - a.full = rfixed_div(b, c); | |
806 | - request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); | |
807 | - request_fifo_depth.full = rfixed_ceil(request_fifo_depth); | |
808 | - if (a.full < rfixed_const(4)) { | |
803 | + b.full = dfixed_const(mode->crtc_hdisplay); | |
804 | + c.full = dfixed_const(256); | |
805 | + a.full = dfixed_div(b, c); | |
806 | + request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); | |
807 | + request_fifo_depth.full = dfixed_ceil(request_fifo_depth); | |
808 | + if (a.full < dfixed_const(4)) { | |
809 | 809 | wm->lb_request_fifo_depth = 4; |
810 | 810 | } else { |
811 | - wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | |
811 | + wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); | |
812 | 812 | } |
813 | 813 | |
814 | 814 | /* Determine consumption rate |
815 | 815 | |
816 | 816 | |
817 | 817 | |
... | ... | @@ -817,23 +817,23 @@ |
817 | 817 | * vsc = vertical scaling ratio, defined as source/destination |
818 | 818 | * hsc = horizontal scaling ration, defined as source/destination |
819 | 819 | */ |
820 | - a.full = rfixed_const(mode->clock); | |
821 | - b.full = rfixed_const(1000); | |
822 | - a.full = rfixed_div(a, b); | |
823 | - pclk.full = rfixed_div(b, a); | |
820 | + a.full = dfixed_const(mode->clock); | |
821 | + b.full = dfixed_const(1000); | |
822 | + a.full = dfixed_div(a, b); | |
823 | + pclk.full = dfixed_div(b, a); | |
824 | 824 | if (crtc->rmx_type != RMX_OFF) { |
825 | - b.full = rfixed_const(2); | |
825 | + b.full = dfixed_const(2); | |
826 | 826 | if (crtc->vsc.full > b.full) |
827 | 827 | b.full = crtc->vsc.full; |
828 | - b.full = rfixed_mul(b, crtc->hsc); | |
829 | - c.full = rfixed_const(2); | |
830 | - b.full = rfixed_div(b, c); | |
831 | - consumption_time.full = rfixed_div(pclk, b); | |
828 | + b.full = dfixed_mul(b, crtc->hsc); | |
829 | + c.full = dfixed_const(2); | |
830 | + b.full = dfixed_div(b, c); | |
831 | + consumption_time.full = dfixed_div(pclk, b); | |
832 | 832 | } else { |
833 | 833 | consumption_time.full = pclk.full; |
834 | 834 | } |
835 | - a.full = rfixed_const(1); | |
836 | - wm->consumption_rate.full = rfixed_div(a, consumption_time); | |
835 | + a.full = dfixed_const(1); | |
836 | + wm->consumption_rate.full = dfixed_div(a, consumption_time); | |
837 | 837 | |
838 | 838 | |
839 | 839 | /* Determine line time |
840 | 840 | |
841 | 841 | |
... | ... | @@ -841,27 +841,27 @@ |
841 | 841 | * LineTime = total number of horizontal pixels |
842 | 842 | * pclk = pixel clock period(ns) |
843 | 843 | */ |
844 | - a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
845 | - line_time.full = rfixed_mul(a, pclk); | |
844 | + a.full = dfixed_const(crtc->base.mode.crtc_htotal); | |
845 | + line_time.full = dfixed_mul(a, pclk); | |
846 | 846 | |
847 | 847 | /* Determine active time |
848 | 848 | * ActiveTime = time of active region of display within one line, |
849 | 849 | * hactive = total number of horizontal active pixels |
850 | 850 | * htotal = total number of horizontal pixels |
851 | 851 | */ |
852 | - a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
853 | - b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
854 | - wm->active_time.full = rfixed_mul(line_time, b); | |
855 | - wm->active_time.full = rfixed_div(wm->active_time, a); | |
852 | + a.full = dfixed_const(crtc->base.mode.crtc_htotal); | |
853 | + b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
854 | + wm->active_time.full = dfixed_mul(line_time, b); | |
855 | + wm->active_time.full = dfixed_div(wm->active_time, a); | |
856 | 856 | |
857 | 857 | /* Determine chunk time |
858 | 858 | * ChunkTime = the time it takes the DCP to send one chunk of data |
859 | 859 | * to the LB which consists of pipeline delay and inter chunk gap |
860 | 860 | * sclk = system clock(Mhz) |
861 | 861 | */ |
862 | - a.full = rfixed_const(600 * 1000); | |
863 | - chunk_time.full = rfixed_div(a, rdev->pm.sclk); | |
864 | - read_delay_latency.full = rfixed_const(1000); | |
862 | + a.full = dfixed_const(600 * 1000); | |
863 | + chunk_time.full = dfixed_div(a, rdev->pm.sclk); | |
864 | + read_delay_latency.full = dfixed_const(1000); | |
865 | 865 | |
866 | 866 | /* Determine the worst case latency |
867 | 867 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
... | ... | @@ -871,9 +871,9 @@ |
871 | 871 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
872 | 872 | * which consists of pipeline delay and inter chunk gap |
873 | 873 | */ |
874 | - if (rfixed_trunc(wm->num_line_pair) > 1) { | |
875 | - a.full = rfixed_const(3); | |
876 | - wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | |
874 | + if (dfixed_trunc(wm->num_line_pair) > 1) { | |
875 | + a.full = dfixed_const(3); | |
876 | + wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
877 | 877 | wm->worst_case_latency.full += read_delay_latency.full; |
878 | 878 | } else { |
879 | 879 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
880 | 880 | |
881 | 881 | |
882 | 882 | |
883 | 883 | |
884 | 884 | |
885 | 885 | |
... | ... | @@ -889,34 +889,34 @@ |
889 | 889 | * of data to the LB which consists of |
890 | 890 | * pipeline delay and inter chunk gap |
891 | 891 | */ |
892 | - if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | |
892 | + if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { | |
893 | 893 | tolerable_latency.full = line_time.full; |
894 | 894 | } else { |
895 | - tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | |
895 | + tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); | |
896 | 896 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
897 | - tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | |
897 | + tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); | |
898 | 898 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
899 | 899 | } |
900 | 900 | /* We assume worst case 32bits (4 bytes) */ |
901 | - wm->dbpp.full = rfixed_const(2 * 16); | |
901 | + wm->dbpp.full = dfixed_const(2 * 16); | |
902 | 902 | |
903 | 903 | /* Determine the maximum priority mark |
904 | 904 | * width = viewport width in pixels |
905 | 905 | */ |
906 | - a.full = rfixed_const(16); | |
907 | - wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
908 | - wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | |
909 | - wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); | |
906 | + a.full = dfixed_const(16); | |
907 | + wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
908 | + wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); | |
909 | + wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); | |
910 | 910 | |
911 | 911 | /* Determine estimated width */ |
912 | 912 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
913 | - estimated_width.full = rfixed_div(estimated_width, consumption_time); | |
914 | - if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
913 | + estimated_width.full = dfixed_div(estimated_width, consumption_time); | |
914 | + if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
915 | 915 | wm->priority_mark.full = wm->priority_mark_max.full; |
916 | 916 | } else { |
917 | - a.full = rfixed_const(16); | |
918 | - wm->priority_mark.full = rfixed_div(estimated_width, a); | |
919 | - wm->priority_mark.full = rfixed_ceil(wm->priority_mark); | |
917 | + a.full = dfixed_const(16); | |
918 | + wm->priority_mark.full = dfixed_div(estimated_width, a); | |
919 | + wm->priority_mark.full = dfixed_ceil(wm->priority_mark); | |
920 | 920 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
921 | 921 | } |
922 | 922 | } |
923 | 923 | |
924 | 924 | |
925 | 925 | |
926 | 926 | |
927 | 927 | |
928 | 928 | |
929 | 929 | |
930 | 930 | |
931 | 931 | |
932 | 932 | |
933 | 933 | |
... | ... | @@ -945,58 +945,58 @@ |
945 | 945 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
946 | 946 | |
947 | 947 | if (mode0 && mode1) { |
948 | - if (rfixed_trunc(wm0.dbpp) > 64) | |
949 | - a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
948 | + if (dfixed_trunc(wm0.dbpp) > 64) | |
949 | + a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | |
950 | 950 | else |
951 | 951 | a.full = wm0.num_line_pair.full; |
952 | - if (rfixed_trunc(wm1.dbpp) > 64) | |
953 | - b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
952 | + if (dfixed_trunc(wm1.dbpp) > 64) | |
953 | + b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | |
954 | 954 | else |
955 | 955 | b.full = wm1.num_line_pair.full; |
956 | 956 | a.full += b.full; |
957 | - fill_rate.full = rfixed_div(wm0.sclk, a); | |
957 | + fill_rate.full = dfixed_div(wm0.sclk, a); | |
958 | 958 | if (wm0.consumption_rate.full > fill_rate.full) { |
959 | 959 | b.full = wm0.consumption_rate.full - fill_rate.full; |
960 | - b.full = rfixed_mul(b, wm0.active_time); | |
961 | - a.full = rfixed_const(16); | |
962 | - b.full = rfixed_div(b, a); | |
963 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
960 | + b.full = dfixed_mul(b, wm0.active_time); | |
961 | + a.full = dfixed_const(16); | |
962 | + b.full = dfixed_div(b, a); | |
963 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
964 | 964 | wm0.consumption_rate); |
965 | 965 | priority_mark02.full = a.full + b.full; |
966 | 966 | } else { |
967 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
967 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
968 | 968 | wm0.consumption_rate); |
969 | - b.full = rfixed_const(16 * 1000); | |
970 | - priority_mark02.full = rfixed_div(a, b); | |
969 | + b.full = dfixed_const(16 * 1000); | |
970 | + priority_mark02.full = dfixed_div(a, b); | |
971 | 971 | } |
972 | 972 | if (wm1.consumption_rate.full > fill_rate.full) { |
973 | 973 | b.full = wm1.consumption_rate.full - fill_rate.full; |
974 | - b.full = rfixed_mul(b, wm1.active_time); | |
975 | - a.full = rfixed_const(16); | |
976 | - b.full = rfixed_div(b, a); | |
977 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
974 | + b.full = dfixed_mul(b, wm1.active_time); | |
975 | + a.full = dfixed_const(16); | |
976 | + b.full = dfixed_div(b, a); | |
977 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
978 | 978 | wm1.consumption_rate); |
979 | 979 | priority_mark12.full = a.full + b.full; |
980 | 980 | } else { |
981 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
981 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
982 | 982 | wm1.consumption_rate); |
983 | - b.full = rfixed_const(16 * 1000); | |
984 | - priority_mark12.full = rfixed_div(a, b); | |
983 | + b.full = dfixed_const(16 * 1000); | |
984 | + priority_mark12.full = dfixed_div(a, b); | |
985 | 985 | } |
986 | 986 | if (wm0.priority_mark.full > priority_mark02.full) |
987 | 987 | priority_mark02.full = wm0.priority_mark.full; |
988 | - if (rfixed_trunc(priority_mark02) < 0) | |
988 | + if (dfixed_trunc(priority_mark02) < 0) | |
989 | 989 | priority_mark02.full = 0; |
990 | 990 | if (wm0.priority_mark_max.full > priority_mark02.full) |
991 | 991 | priority_mark02.full = wm0.priority_mark_max.full; |
992 | 992 | if (wm1.priority_mark.full > priority_mark12.full) |
993 | 993 | priority_mark12.full = wm1.priority_mark.full; |
994 | - if (rfixed_trunc(priority_mark12) < 0) | |
994 | + if (dfixed_trunc(priority_mark12) < 0) | |
995 | 995 | priority_mark12.full = 0; |
996 | 996 | if (wm1.priority_mark_max.full > priority_mark12.full) |
997 | 997 | priority_mark12.full = wm1.priority_mark_max.full; |
998 | - d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); | |
999 | - d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); | |
998 | + d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
999 | + d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
1000 | 1000 | if (rdev->disp_priority == 2) { |
1001 | 1001 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1002 | 1002 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1003 | 1003 | |
1004 | 1004 | |
1005 | 1005 | |
1006 | 1006 | |
1007 | 1007 | |
1008 | 1008 | |
... | ... | @@ -1006,32 +1006,32 @@ |
1006 | 1006 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1007 | 1007 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
1008 | 1008 | } else if (mode0) { |
1009 | - if (rfixed_trunc(wm0.dbpp) > 64) | |
1010 | - a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
1009 | + if (dfixed_trunc(wm0.dbpp) > 64) | |
1010 | + a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | |
1011 | 1011 | else |
1012 | 1012 | a.full = wm0.num_line_pair.full; |
1013 | - fill_rate.full = rfixed_div(wm0.sclk, a); | |
1013 | + fill_rate.full = dfixed_div(wm0.sclk, a); | |
1014 | 1014 | if (wm0.consumption_rate.full > fill_rate.full) { |
1015 | 1015 | b.full = wm0.consumption_rate.full - fill_rate.full; |
1016 | - b.full = rfixed_mul(b, wm0.active_time); | |
1017 | - a.full = rfixed_const(16); | |
1018 | - b.full = rfixed_div(b, a); | |
1019 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
1016 | + b.full = dfixed_mul(b, wm0.active_time); | |
1017 | + a.full = dfixed_const(16); | |
1018 | + b.full = dfixed_div(b, a); | |
1019 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
1020 | 1020 | wm0.consumption_rate); |
1021 | 1021 | priority_mark02.full = a.full + b.full; |
1022 | 1022 | } else { |
1023 | - a.full = rfixed_mul(wm0.worst_case_latency, | |
1023 | + a.full = dfixed_mul(wm0.worst_case_latency, | |
1024 | 1024 | wm0.consumption_rate); |
1025 | - b.full = rfixed_const(16); | |
1026 | - priority_mark02.full = rfixed_div(a, b); | |
1025 | + b.full = dfixed_const(16); | |
1026 | + priority_mark02.full = dfixed_div(a, b); | |
1027 | 1027 | } |
1028 | 1028 | if (wm0.priority_mark.full > priority_mark02.full) |
1029 | 1029 | priority_mark02.full = wm0.priority_mark.full; |
1030 | - if (rfixed_trunc(priority_mark02) < 0) | |
1030 | + if (dfixed_trunc(priority_mark02) < 0) | |
1031 | 1031 | priority_mark02.full = 0; |
1032 | 1032 | if (wm0.priority_mark_max.full > priority_mark02.full) |
1033 | 1033 | priority_mark02.full = wm0.priority_mark_max.full; |
1034 | - d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); | |
1034 | + d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
1035 | 1035 | if (rdev->disp_priority == 2) |
1036 | 1036 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1037 | 1037 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
1038 | 1038 | |
1039 | 1039 | |
1040 | 1040 | |
1041 | 1041 | |
1042 | 1042 | |
1043 | 1043 | |
... | ... | @@ -1039,32 +1039,32 @@ |
1039 | 1039 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
1040 | 1040 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
1041 | 1041 | } else { |
1042 | - if (rfixed_trunc(wm1.dbpp) > 64) | |
1043 | - a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
1042 | + if (dfixed_trunc(wm1.dbpp) > 64) | |
1043 | + a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | |
1044 | 1044 | else |
1045 | 1045 | a.full = wm1.num_line_pair.full; |
1046 | - fill_rate.full = rfixed_div(wm1.sclk, a); | |
1046 | + fill_rate.full = dfixed_div(wm1.sclk, a); | |
1047 | 1047 | if (wm1.consumption_rate.full > fill_rate.full) { |
1048 | 1048 | b.full = wm1.consumption_rate.full - fill_rate.full; |
1049 | - b.full = rfixed_mul(b, wm1.active_time); | |
1050 | - a.full = rfixed_const(16); | |
1051 | - b.full = rfixed_div(b, a); | |
1052 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
1049 | + b.full = dfixed_mul(b, wm1.active_time); | |
1050 | + a.full = dfixed_const(16); | |
1051 | + b.full = dfixed_div(b, a); | |
1052 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
1053 | 1053 | wm1.consumption_rate); |
1054 | 1054 | priority_mark12.full = a.full + b.full; |
1055 | 1055 | } else { |
1056 | - a.full = rfixed_mul(wm1.worst_case_latency, | |
1056 | + a.full = dfixed_mul(wm1.worst_case_latency, | |
1057 | 1057 | wm1.consumption_rate); |
1058 | - b.full = rfixed_const(16 * 1000); | |
1059 | - priority_mark12.full = rfixed_div(a, b); | |
1058 | + b.full = dfixed_const(16 * 1000); | |
1059 | + priority_mark12.full = dfixed_div(a, b); | |
1060 | 1060 | } |
1061 | 1061 | if (wm1.priority_mark.full > priority_mark12.full) |
1062 | 1062 | priority_mark12.full = wm1.priority_mark.full; |
1063 | - if (rfixed_trunc(priority_mark12) < 0) | |
1063 | + if (dfixed_trunc(priority_mark12) < 0) | |
1064 | 1064 | priority_mark12.full = 0; |
1065 | 1065 | if (wm1.priority_mark_max.full > priority_mark12.full) |
1066 | 1066 | priority_mark12.full = wm1.priority_mark_max.full; |
1067 | - d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); | |
1067 | + d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
1068 | 1068 | if (rdev->disp_priority == 2) |
1069 | 1069 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1070 | 1070 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
include/drm/drm_fixed.h
1 | +/* | |
2 | + * Copyright 2009 Red Hat Inc. | |
3 | + * | |
4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | + * copy of this software and associated documentation files (the "Software"), | |
6 | + * to deal in the Software without restriction, including without limitation | |
7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
9 | + * Software is furnished to do so, subject to the following conditions: | |
10 | + * | |
11 | + * The above copyright notice and this permission notice shall be included in | |
12 | + * all copies or substantial portions of the Software. | |
13 | + * | |
14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
21 | + * | |
22 | + * Authors: Dave Airlie | |
23 | + */ | |
24 | +#ifndef DRM_FIXED_H | |
25 | +#define DRM_FIXED_H | |
26 | + | |
27 | +typedef union dfixed { | |
28 | + u32 full; | |
29 | +} fixed20_12; | |
30 | + | |
31 | + | |
32 | +#define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ | |
33 | +#define dfixed_const_half(A) (u32)(((A) << 12) + 2048) | |
34 | +#define dfixed_const_666(A) (u32)(((A) << 12) + 2731) | |
35 | +#define dfixed_const_8(A) (u32)(((A) << 12) + 3277) | |
36 | +#define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) | |
37 | +#define dfixed_init(A) { .full = dfixed_const((A)) } | |
38 | +#define dfixed_init_half(A) { .full = dfixed_const_half((A)) } | |
39 | +#define dfixed_trunc(A) ((A).full >> 12) | |
40 | + | |
41 | +static inline u32 dfixed_floor(fixed20_12 A) | |
42 | +{ | |
43 | + u32 non_frac = dfixed_trunc(A); | |
44 | + | |
45 | + return dfixed_const(non_frac); | |
46 | +} | |
47 | + | |
48 | +static inline u32 dfixed_ceil(fixed20_12 A) | |
49 | +{ | |
50 | + u32 non_frac = dfixed_trunc(A); | |
51 | + | |
52 | + if (A.full > dfixed_const(non_frac)) | |
53 | + return dfixed_const(non_frac + 1); | |
54 | + else | |
55 | + return dfixed_const(non_frac); | |
56 | +} | |
57 | + | |
58 | +static inline u32 dfixed_div(fixed20_12 A, fixed20_12 B) | |
59 | +{ | |
60 | + u64 tmp = ((u64)A.full << 13); | |
61 | + | |
62 | + do_div(tmp, B.full); | |
63 | + tmp += 1; | |
64 | + tmp /= 2; | |
65 | + return lower_32_bits(tmp); | |
66 | +} | |
67 | +#endif |